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   1 /*
   2  * ipg.c: Device Driver for the IP1000 Gigabit Ethernet Adapter
   3  *
   4  * Copyright (C) 2003, 2007  IC Plus Corp
   5  *
   6  * Original Author:
   7  *
   8  *   Craig Rich
   9  *   Sundance Technology, Inc.
  10  *   www.sundanceti.com
  11  *   craig_rich@sundanceti.com
  12  *
  13  * Current Maintainer:
  14  *
  15  *   Sorbica Shieh.
  16  *   http://www.icplus.com.tw
  17  *   sorbica@icplus.com.tw
  18  *
  19  *   Jesse Huang
  20  *   http://www.icplus.com.tw
  21  *   jesse@icplus.com.tw
  22  */
  23 #include <linux/crc32.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mii.h>
  26 #include <linux/mutex.h>
  27
  28 #include <asm/div64.h>
  29
  30 #define IPG_RX_RING_BYTES       (sizeof(struct ipg_rx) * IPG_RFDLIST_LENGTH)
  31 #define IPG_TX_RING_BYTES       (sizeof(struct ipg_tx) * IPG_TFDLIST_LENGTH)
  32 #define IPG_RESET_MASK \
  33         (IPG_AC_GLOBAL_RESET | IPG_AC_RX_RESET | IPG_AC_TX_RESET | \
  34          IPG_AC_DMA | IPG_AC_FIFO | IPG_AC_NETWORK | IPG_AC_HOST | \
  35          IPG_AC_AUTO_INIT)
  36
  37 #define ipg_w32(val32, reg)     iowrite32((val32), ioaddr + (reg))
  38 #define ipg_w16(val16, reg)     iowrite16((val16), ioaddr + (reg))
  39 #define ipg_w8(val8, reg)       iowrite8((val8), ioaddr + (reg))
  40
  41 #define ipg_r32(reg)            ioread32(ioaddr + (reg))
  42 #define ipg_r16(reg)            ioread16(ioaddr + (reg))
  43 #define ipg_r8(reg)             ioread8(ioaddr + (reg))
  44
  45 #define JUMBO_FRAME_4k_ONLY
  46 enum {
  47         netdev_io_size = 128
  48 };
  49
  50 #include "ipg.h"
  51 #define DRV_NAME        "ipg"
  52
  53 MODULE_AUTHOR("IC Plus Corp. 2003");
  54 MODULE_DESCRIPTION("IC Plus IP1000 Gigabit Ethernet Adapter Linux Driver");
  55 MODULE_LICENSE("GPL");
  56
  57 /*
  58  * Variable record -- index by leading revision/length
  59  * Revision/Length(=N*4), Address1, Data1, Address2, Data2,...,AddressN,DataN
  60  */
  61 static unsigned short DefaultPhyParam[] = {
  62         /* 11/12/03 IP1000A v1-3 rev=0x40 */
  63         /*--------------------------------------------------------------------------
  64         (0x4000|(15*4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 22, 0x85bd, 24, 0xfff2,
  65                                  27, 0x0c10, 28, 0x0c10, 29, 0x2c10, 31, 0x0003, 23, 0x92f6,
  66                                  31, 0x0000, 23, 0x003d, 30, 0x00de, 20, 0x20e7,  9, 0x0700,
  67           --------------------------------------------------------------------------*/
  68         /* 12/17/03 IP1000A v1-4 rev=0x40 */
  69         (0x4000 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
  70             0x0000,
  71         30, 0x005e, 9, 0x0700,
  72         /* 01/09/04 IP1000A v1-5 rev=0x41 */
  73         (0x4100 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
  74             0x0000,
  75         30, 0x005e, 9, 0x0700,
  76         0x0000
  77 };
  78
  79 static const char *ipg_brand_name[] = {
  80         "IC PLUS IP1000 1000/100/10 based NIC",
  81         "Sundance Technology ST2021 based NIC",
  82         "Tamarack Microelectronics TC9020/9021 based NIC",
  83         "Tamarack Microelectronics TC9020/9021 based NIC",
  84         "D-Link NIC",
  85         "D-Link NIC IP1000A"
  86 };
  87
  88 static struct pci_device_id ipg_pci_tbl[] __devinitdata = {
  89         { PCI_VDEVICE(SUNDANCE, 0x1023), 0 },
  90         { PCI_VDEVICE(SUNDANCE, 0x2021), 1 },
  91         { PCI_VDEVICE(SUNDANCE, 0x1021), 2 },
  92         { PCI_VDEVICE(DLINK,    0x9021), 3 },
  93         { PCI_VDEVICE(DLINK,    0x4000), 4 },
  94         { PCI_VDEVICE(DLINK,    0x4020), 5 },
  95         { 0, }
  96 };
  97
  98 MODULE_DEVICE_TABLE(pci, ipg_pci_tbl);
  99
 100 static inline void __iomem *ipg_ioaddr(struct net_device *dev)
 101 {
 102         struct ipg_nic_private *sp = netdev_priv(dev);
 103         return sp->ioaddr;
 104 }
 105
 106 #ifdef IPG_DEBUG
 107 static void ipg_dump_rfdlist(struct net_device *dev)
 108 {
 109         struct ipg_nic_private *sp = netdev_priv(dev);
 110         void __iomem *ioaddr = sp->ioaddr;
 111         unsigned int i;
 112         u32 offset;
 113
 114         IPG_DEBUG_MSG("_dump_rfdlist\n");
 115
 116         printk(KERN_INFO "rx_current = %2.2x\n", sp->rx_current);
 117         printk(KERN_INFO "rx_dirty   = %2.2x\n", sp->rx_dirty);
 118         printk(KERN_INFO "RFDList start address = %16.16lx\n",
 119                (unsigned long) sp->rxd_map);
 120         printk(KERN_INFO "RFDListPtr register   = %8.8x%8.8x\n",
 121                ipg_r32(IPG_RFDLISTPTR1), ipg_r32(IPG_RFDLISTPTR0));
 122
 123         for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
 124                 offset = (u32) &sp->rxd[i].next_desc - (u32) sp->rxd;
 125                 printk(KERN_INFO "%2.2x %4.4x RFDNextPtr = %16.16lx\n", i,
 126                        offset, (unsigned long) sp->rxd[i].next_desc);
 127                 offset = (u32) &sp->rxd[i].rfs - (u32) sp->rxd;
 128                 printk(KERN_INFO "%2.2x %4.4x RFS        = %16.16lx\n", i,
 129                        offset, (unsigned long) sp->rxd[i].rfs);
 130                 offset = (u32) &sp->rxd[i].frag_info - (u32) sp->rxd;
 131                 printk(KERN_INFO "%2.2x %4.4x frag_info   = %16.16lx\n", i,
 132                        offset, (unsigned long) sp->rxd[i].frag_info);
 133         }
 134 }
 135
 136 static void ipg_dump_tfdlist(struct net_device *dev)
 137 {
 138         struct ipg_nic_private *sp = netdev_priv(dev);
 139         void __iomem *ioaddr = sp->ioaddr;
 140         unsigned int i;
 141         u32 offset;
 142
 143         IPG_DEBUG_MSG("_dump_tfdlist\n");
 144
 145         printk(KERN_INFO "tx_current         = %2.2x\n", sp->tx_current);
 146         printk(KERN_INFO "tx_dirty = %2.2x\n", sp->tx_dirty);
 147         printk(KERN_INFO "TFDList start address = %16.16lx\n",
 148                (unsigned long) sp->txd_map);
 149         printk(KERN_INFO "TFDListPtr register   = %8.8x%8.8x\n",
 150                ipg_r32(IPG_TFDLISTPTR1), ipg_r32(IPG_TFDLISTPTR0));
 151
 152         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
 153                 offset = (u32) &sp->txd[i].next_desc - (u32) sp->txd;
 154                 printk(KERN_INFO "%2.2x %4.4x TFDNextPtr = %16.16lx\n", i,
 155                        offset, (unsigned long) sp->txd[i].next_desc);
 156
 157                 offset = (u32) &sp->txd[i].tfc - (u32) sp->txd;
 158                 printk(KERN_INFO "%2.2x %4.4x TFC        = %16.16lx\n", i,
 159                        offset, (unsigned long) sp->txd[i].tfc);
 160                 offset = (u32) &sp->txd[i].frag_info - (u32) sp->txd;
 161                 printk(KERN_INFO "%2.2x %4.4x frag_info   = %16.16lx\n", i,
 162                        offset, (unsigned long) sp->txd[i].frag_info);
 163         }
 164 }
 165 #endif
 166
 167 static void ipg_write_phy_ctl(void __iomem *ioaddr, u8 data)
 168 {
 169         ipg_w8(IPG_PC_RSVD_MASK & data, PHY_CTRL);
 170         ndelay(IPG_PC_PHYCTRLWAIT_NS);
 171 }
 172
 173 static void ipg_drive_phy_ctl_low_high(void __iomem *ioaddr, u8 data)
 174 {
 175         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | data);
 176         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | data);
 177 }
 178
 179 static void send_three_state(void __iomem *ioaddr, u8 phyctrlpolarity)
 180 {
 181         phyctrlpolarity |= (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR;
 182
 183         ipg_drive_phy_ctl_low_high(ioaddr, phyctrlpolarity);
 184 }
 185
 186 static void send_end(void __iomem *ioaddr, u8 phyctrlpolarity)
 187 {
 188         ipg_w8((IPG_PC_MGMTCLK_LO | (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR |
 189                 phyctrlpolarity) & IPG_PC_RSVD_MASK, PHY_CTRL);
 190 }
 191
 192 static u16 read_phy_bit(void __iomem *ioaddr, u8 phyctrlpolarity)
 193 {
 194         u16 bit_data;
 195
 196         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | phyctrlpolarity);
 197
 198         bit_data = ((ipg_r8(PHY_CTRL) & IPG_PC_MGMTDATA) >> 1) & 1;
 199
 200         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | phyctrlpolarity);
 201
 202         return bit_data;
 203 }
 204
 205 /*
 206  * Read a register from the Physical Layer device located
 207  * on the IPG NIC, using the IPG PHYCTRL register.
 208  */
 209 static int mdio_read(struct net_device *dev, int phy_id, int phy_reg)
 210 {
 211         void __iomem *ioaddr = ipg_ioaddr(dev);
 212         /*
 213          * The GMII mangement frame structure for a read is as follows:
 214          *
 215          * |Preamble|st|op|phyad|regad|ta|      data      |idle|
 216          * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z   |
 217          *
 218          * <32 1s> = 32 consecutive logic 1 values
 219          * A = bit of Physical Layer device address (MSB first)
 220          * R = bit of register address (MSB first)
 221          * z = High impedance state
 222          * D = bit of read data (MSB first)
 223          *
 224          * Transmission order is 'Preamble' field first, bits transmitted
 225          * left to right (first to last).
 226          */
 227         struct {
 228                 u32 field;
 229                 unsigned int len;
 230         } p[] = {
 231                 { GMII_PREAMBLE,        32 },   /* Preamble */
 232                 { GMII_ST,              2  },   /* ST */
 233                 { GMII_READ,            2  },   /* OP */
 234                 { phy_id,               5  },   /* PHYAD */
 235                 { phy_reg,              5  },   /* REGAD */
 236                 { 0x0000,               2  },   /* TA */
 237                 { 0x0000,               16 },   /* DATA */
 238                 { 0x0000,               1  }    /* IDLE */
 239         };
 240         unsigned int i, j;
 241         u8 polarity, data;
 242
 243         polarity  = ipg_r8(PHY_CTRL);
 244         polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
 245
 246         /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
 247         for (j = 0; j < 5; j++) {
 248                 for (i = 0; i < p[j].len; i++) {
 249                         /* For each variable length field, the MSB must be
 250                          * transmitted first. Rotate through the field bits,
 251                          * starting with the MSB, and move each bit into the
 252                          * the 1st (2^1) bit position (this is the bit position
 253                          * corresponding to the MgmtData bit of the PhyCtrl
 254                          * register for the IPG).
 255                          *
 256                          * Example: ST = 01;
 257                          *
 258                          *          First write a '0' to bit 1 of the PhyCtrl
 259                          *          register, then write a '1' to bit 1 of the
 260                          *          PhyCtrl register.
 261                          *
 262                          * To do this, right shift the MSB of ST by the value:
 263                          * [field length - 1 - #ST bits already written]
 264                          * then left shift this result by 1.
 265                          */
 266                         data  = (p[j].field >> (p[j].len - 1 - i)) << 1;
 267                         data &= IPG_PC_MGMTDATA;
 268                         data |= polarity | IPG_PC_MGMTDIR;
 269
 270                         ipg_drive_phy_ctl_low_high(ioaddr, data);
 271                 }
 272         }
 273
 274         send_three_state(ioaddr, polarity);
 275
 276         read_phy_bit(ioaddr, polarity);
 277
 278         /*
 279          * For a read cycle, the bits for the next two fields (TA and
 280          * DATA) are driven by the PHY (the IPG reads these bits).
 281          */
 282         for (i = 0; i < p[6].len; i++) {
 283                 p[6].field |=
 284                     (read_phy_bit(ioaddr, polarity) << (p[6].len - 1 - i));
 285         }
 286
 287         send_three_state(ioaddr, polarity);
 288         send_three_state(ioaddr, polarity);
 289         send_three_state(ioaddr, polarity);
 290         send_end(ioaddr, polarity);
 291
 292         /* Return the value of the DATA field. */
 293         return p[6].field;
 294 }
 295
 296 /*
 297  * Write to a register from the Physical Layer device located
 298  * on the IPG NIC, using the IPG PHYCTRL register.
 299  */
 300 static void mdio_write(struct net_device *dev, int phy_id, int phy_reg, int val)
 301 {
 302         void __iomem *ioaddr = ipg_ioaddr(dev);
 303         /*
 304          * The GMII mangement frame structure for a read is as follows:
 305          *
 306          * |Preamble|st|op|phyad|regad|ta|      data      |idle|
 307          * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z   |
 308          *
 309          * <32 1s> = 32 consecutive logic 1 values
 310          * A = bit of Physical Layer device address (MSB first)
 311          * R = bit of register address (MSB first)
 312          * z = High impedance state
 313          * D = bit of write data (MSB first)
 314          *
 315          * Transmission order is 'Preamble' field first, bits transmitted
 316          * left to right (first to last).
 317          */
 318         struct {
 319                 u32 field;
 320                 unsigned int len;
 321         } p[] = {
 322                 { GMII_PREAMBLE,        32 },   /* Preamble */
 323                 { GMII_ST,              2  },   /* ST */
 324                 { GMII_WRITE,           2  },   /* OP */
 325                 { phy_id,               5  },   /* PHYAD */
 326                 { phy_reg,              5  },   /* REGAD */
 327                 { 0x0002,               2  },   /* TA */
 328                 { val & 0xffff,         16 },   /* DATA */
 329                 { 0x0000,               1  }    /* IDLE */
 330         };
 331         unsigned int i, j;
 332         u8 polarity, data;
 333
 334         polarity  = ipg_r8(PHY_CTRL);
 335         polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
 336
 337         /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
 338         for (j = 0; j < 7; j++) {
 339                 for (i = 0; i < p[j].len; i++) {
 340                         /* For each variable length field, the MSB must be
 341                          * transmitted first. Rotate through the field bits,
 342                          * starting with the MSB, and move each bit into the
 343                          * the 1st (2^1) bit position (this is the bit position
 344                          * corresponding to the MgmtData bit of the PhyCtrl
 345                          * register for the IPG).
 346                          *
 347                          * Example: ST = 01;
 348                          *
 349                          *          First write a '0' to bit 1 of the PhyCtrl
 350                          *          register, then write a '1' to bit 1 of the
 351                          *          PhyCtrl register.
 352                          *
 353                          * To do this, right shift the MSB of ST by the value:
 354                          * [field length - 1 - #ST bits already written]
 355                          * then left shift this result by 1.
 356                          */
 357                         data  = (p[j].field >> (p[j].len - 1 - i)) << 1;
 358                         data &= IPG_PC_MGMTDATA;
 359                         data |= polarity | IPG_PC_MGMTDIR;
 360
 361                         ipg_drive_phy_ctl_low_high(ioaddr, data);
 362                 }
 363         }
 364
 365         /* The last cycle is a tri-state, so read from the PHY. */
 366         for (j = 7; j < 8; j++) {
 367                 for (i = 0; i < p[j].len; i++) {
 368                         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | polarity);
 369
 370                         p[j].field |= ((ipg_r8(PHY_CTRL) &
 371                                 IPG_PC_MGMTDATA) >> 1) << (p[j].len - 1 - i);
 372
 373                         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | polarity);
 374                 }
 375         }
 376 }
 377
 378 static void ipg_set_led_mode(struct net_device *dev)
 379 {
 380         struct ipg_nic_private *sp = netdev_priv(dev);
 381         void __iomem *ioaddr = sp->ioaddr;
 382         u32 mode;
 383
 384         mode = ipg_r32(ASIC_CTRL);
 385         mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
 386
 387         if ((sp->led_mode & 0x03) > 1)
 388                 mode |= IPG_AC_LED_MODE_BIT_1;  /* Write Asic Control Bit 29 */
 389
 390         if ((sp->led_mode & 0x01) == 1)
 391                 mode |= IPG_AC_LED_MODE;        /* Write Asic Control Bit 14 */
 392
 393         if ((sp->led_mode & 0x08) == 8)
 394                 mode |= IPG_AC_LED_SPEED;       /* Write Asic Control Bit 27 */
 395
 396         ipg_w32(mode, ASIC_CTRL);
 397 }
 398
 399 static void ipg_set_phy_set(struct net_device *dev)
 400 {
 401         struct ipg_nic_private *sp = netdev_priv(dev);
 402         void __iomem *ioaddr = sp->ioaddr;
 403         int physet;
 404
 405         physet = ipg_r8(PHY_SET);
 406         physet &= ~(IPG_PS_MEM_LENB9B | IPG_PS_MEM_LEN9 | IPG_PS_NON_COMPDET);
 407         physet |= ((sp->led_mode & 0x70) >> 4);
 408         ipg_w8(physet, PHY_SET);
 409 }
 410
 411 static int ipg_reset(struct net_device *dev, u32 resetflags)
 412 {
 413         /* Assert functional resets via the IPG AsicCtrl
 414          * register as specified by the 'resetflags' input
 415          * parameter.
 416          */
 417         void __iomem *ioaddr = ipg_ioaddr(dev);
 418         unsigned int timeout_count = 0;
 419
 420         IPG_DEBUG_MSG("_reset\n");
 421
 422         ipg_w32(ipg_r32(ASIC_CTRL) | resetflags, ASIC_CTRL);
 423
 424         /* Delay added to account for problem with 10Mbps reset. */
 425         mdelay(IPG_AC_RESETWAIT);
 426
 427         while (IPG_AC_RESET_BUSY & ipg_r32(ASIC_CTRL)) {
 428                 mdelay(IPG_AC_RESETWAIT);
 429                 if (++timeout_count > IPG_AC_RESET_TIMEOUT)
 430                         return -ETIME;
 431         }
 432         /* Set LED Mode in Asic Control */
 433         ipg_set_led_mode(dev);
 434
 435         /* Set PHYSet Register Value */
 436         ipg_set_phy_set(dev);
 437         return 0;
 438 }
 439
 440 /* Find the GMII PHY address. */
 441 static int ipg_find_phyaddr(struct net_device *dev)
 442 {
 443         unsigned int phyaddr, i;
 444
 445         for (i = 0; i < 32; i++) {
 446                 u32 status;
 447
 448                 /* Search for the correct PHY address among 32 possible. */
 449                 phyaddr = (IPG_NIC_PHY_ADDRESS + i) % 32;
 450
 451                 /* 10/22/03 Grace change verify from GMII_PHY_STATUS to
 452                    GMII_PHY_ID1
 453                  */
 454
 455                 status = mdio_read(dev, phyaddr, MII_BMSR);
 456
 457                 if ((status != 0xFFFF) && (status != 0))
 458                         return phyaddr;
 459         }
 460
 461         return 0x1f;
 462 }
 463
 464 /*
 465  * Configure IPG based on result of IEEE 802.3 PHY
 466  * auto-negotiation.
 467  */
 468 static int ipg_config_autoneg(struct net_device *dev)
 469 {
 470         struct ipg_nic_private *sp = netdev_priv(dev);
 471         void __iomem *ioaddr = sp->ioaddr;
 472         unsigned int txflowcontrol;
 473         unsigned int rxflowcontrol;
 474         unsigned int fullduplex;
 475         u32 mac_ctrl_val;
 476         u32 asicctrl;
 477         u8 phyctrl;
 478
 479         IPG_DEBUG_MSG("_config_autoneg\n");
 480
 481         asicctrl = ipg_r32(ASIC_CTRL);
 482         phyctrl = ipg_r8(PHY_CTRL);
 483         mac_ctrl_val = ipg_r32(MAC_CTRL);
 484
 485         /* Set flags for use in resolving auto-negotation, assuming
 486          * non-1000Mbps, half duplex, no flow control.
 487          */
 488         fullduplex = 0;
 489         txflowcontrol = 0;
 490         rxflowcontrol = 0;
 491
 492         /* To accomodate a problem in 10Mbps operation,
 493          * set a global flag if PHY running in 10Mbps mode.
 494          */
 495         sp->tenmbpsmode = 0;
 496
 497         printk(KERN_INFO "%s: Link speed = ", dev->name);
 498
 499         /* Determine actual speed of operation. */
 500         switch (phyctrl & IPG_PC_LINK_SPEED) {
 501         case IPG_PC_LINK_SPEED_10MBPS:
 502                 printk("10Mbps.\n");
 503                 printk(KERN_INFO "%s: 10Mbps operational mode enabled.\n",
 504                        dev->name);
 505                 sp->tenmbpsmode = 1;
 506                 break;
 507         case IPG_PC_LINK_SPEED_100MBPS:
 508                 printk("100Mbps.\n");
 509                 break;
 510         case IPG_PC_LINK_SPEED_1000MBPS:
 511                 printk("1000Mbps.\n");
 512                 break;
 513         default:
 514                 printk("undefined!\n");
 515                 return 0;
 516         }
 517
 518         if (phyctrl & IPG_PC_DUPLEX_STATUS) {
 519                 fullduplex = 1;
 520                 txflowcontrol = 1;
 521                 rxflowcontrol = 1;
 522         }
 523
 524         /* Configure full duplex, and flow control. */
 525         if (fullduplex == 1) {
 526                 /* Configure IPG for full duplex operation. */
 527                 printk(KERN_INFO "%s: setting full duplex, ", dev->name);
 528
 529                 mac_ctrl_val |= IPG_MC_DUPLEX_SELECT_FD;
 530
 531                 if (txflowcontrol == 1) {
 532                         printk("TX flow control");
 533                         mac_ctrl_val |= IPG_MC_TX_FLOW_CONTROL_ENABLE;
 534                 } else {
 535                         printk("no TX flow control");
 536                         mac_ctrl_val &= ~IPG_MC_TX_FLOW_CONTROL_ENABLE;
 537                 }
 538
 539                 if (rxflowcontrol == 1) {
 540                         printk(", RX flow control.");
 541                         mac_ctrl_val |= IPG_MC_RX_FLOW_CONTROL_ENABLE;
 542                 } else {
 543                         printk(", no RX flow control.");
 544                         mac_ctrl_val &= ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
 545                 }
 546
 547                 printk("\n");
 548         } else {
 549                 /* Configure IPG for half duplex operation. */
 550                 printk(KERN_INFO "%s: setting half duplex, "
 551                        "no TX flow control, no RX flow control.\n", dev->name);
 552
 553                 mac_ctrl_val &= ~IPG_MC_DUPLEX_SELECT_FD &
 554                         ~IPG_MC_TX_FLOW_CONTROL_ENABLE &
 555                         ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
 556         }
 557         ipg_w32(mac_ctrl_val, MAC_CTRL);
 558         return 0;
 559 }
 560
 561 /* Determine and configure multicast operation and set
 562  * receive mode for IPG.
 563  */
 564 static void ipg_nic_set_multicast_list(struct net_device *dev)
 565 {
 566         void __iomem *ioaddr = ipg_ioaddr(dev);
 567         struct dev_mc_list *mc_list_ptr;
 568         unsigned int hashindex;
 569         u32 hashtable[2];
 570         u8 receivemode;
 571
 572         IPG_DEBUG_MSG("_nic_set_multicast_list\n");
 573
 574         receivemode = IPG_RM_RECEIVEUNICAST | IPG_RM_RECEIVEBROADCAST;
 575
 576         if (dev->flags & IFF_PROMISC) {
 577                 /* NIC to be configured in promiscuous mode. */
 578                 receivemode = IPG_RM_RECEIVEALLFRAMES;
 579         } else if ((dev->flags & IFF_ALLMULTI) ||
 580                    ((dev->flags & IFF_MULTICAST) &&
 581                     (dev->mc_count > IPG_MULTICAST_HASHTABLE_SIZE))) {
 582                 /* NIC to be configured to receive all multicast
 583                  * frames. */
 584                 receivemode |= IPG_RM_RECEIVEMULTICAST;
 585         } else if ((dev->flags & IFF_MULTICAST) && (dev->mc_count > 0)) {
 586                 /* NIC to be configured to receive selected
 587                  * multicast addresses. */
 588                 receivemode |= IPG_RM_RECEIVEMULTICASTHASH;
 589         }
 590
 591         /* Calculate the bits to set for the 64 bit, IPG HASHTABLE.
 592          * The IPG applies a cyclic-redundancy-check (the same CRC
 593          * used to calculate the frame data FCS) to the destination
 594          * address all incoming multicast frames whose destination
 595          * address has the multicast bit set. The least significant
 596          * 6 bits of the CRC result are used as an addressing index
 597          * into the hash table. If the value of the bit addressed by
 598          * this index is a 1, the frame is passed to the host system.
 599          */
 600
 601         /* Clear hashtable. */
 602         hashtable[0] = 0x00000000;
 603         hashtable[1] = 0x00000000;
 604
 605         /* Cycle through all multicast addresses to filter. */
 606         for (mc_list_ptr = dev->mc_list;
 607              mc_list_ptr != NULL; mc_list_ptr = mc_list_ptr->next) {
 608                 /* Calculate CRC result for each multicast address. */
 609                 hashindex = crc32_le(0xffffffff, mc_list_ptr->dmi_addr,
 610                                      ETH_ALEN);
 611
 612                 /* Use only the least significant 6 bits. */
 613                 hashindex = hashindex & 0x3F;
 614
 615                 /* Within "hashtable", set bit number "hashindex"
 616                  * to a logic 1.
 617                  */
 618                 set_bit(hashindex, (void *)hashtable);
 619         }
 620
 621         /* Write the value of the hashtable, to the 4, 16 bit
 622          * HASHTABLE IPG registers.
 623          */
 624         ipg_w32(hashtable[0], HASHTABLE_0);
 625         ipg_w32(hashtable[1], HASHTABLE_1);
 626
 627         ipg_w8(IPG_RM_RSVD_MASK & receivemode, RECEIVE_MODE);
 628
 629         IPG_DEBUG_MSG("ReceiveMode = %x\n", ipg_r8(RECEIVE_MODE));
 630 }
 631
 632 static int ipg_io_config(struct net_device *dev)
 633 {
 634         void __iomem *ioaddr = ipg_ioaddr(dev);
 635         u32 origmacctrl;
 636         u32 restoremacctrl;
 637
 638         IPG_DEBUG_MSG("_io_config\n");
 639
 640         origmacctrl = ipg_r32(MAC_CTRL);
 641
 642         restoremacctrl = origmacctrl | IPG_MC_STATISTICS_ENABLE;
 643
 644         /* Based on compilation option, determine if FCS is to be
 645          * stripped on receive frames by IPG.
 646          */
 647         if (!IPG_STRIP_FCS_ON_RX)
 648                 restoremacctrl |= IPG_MC_RCV_FCS;
 649
 650         /* Determine if transmitter and/or receiver are
 651          * enabled so we may restore MACCTRL correctly.
 652          */
 653         if (origmacctrl & IPG_MC_TX_ENABLED)
 654                 restoremacctrl |= IPG_MC_TX_ENABLE;
 655
 656         if (origmacctrl & IPG_MC_RX_ENABLED)
 657                 restoremacctrl |= IPG_MC_RX_ENABLE;
 658
 659         /* Transmitter and receiver must be disabled before setting
 660          * IFSSelect.
 661          */
 662         ipg_w32((origmacctrl & (IPG_MC_RX_DISABLE | IPG_MC_TX_DISABLE)) &
 663                 IPG_MC_RSVD_MASK, MAC_CTRL);
 664
 665         /* Now that transmitter and receiver are disabled, write
 666          * to IFSSelect.
 667          */
 668         ipg_w32((origmacctrl & IPG_MC_IFS_96BIT) & IPG_MC_RSVD_MASK, MAC_CTRL);
 669
 670         /* Set RECEIVEMODE register. */
 671         ipg_nic_set_multicast_list(dev);
 672
 673         ipg_w16(IPG_MAX_RXFRAME_SIZE, MAX_FRAME_SIZE);
 674
 675         ipg_w8(IPG_RXDMAPOLLPERIOD_VALUE,   RX_DMA_POLL_PERIOD);
 676         ipg_w8(IPG_RXDMAURGENTTHRESH_VALUE, RX_DMA_URGENT_THRESH);
 677         ipg_w8(IPG_RXDMABURSTTHRESH_VALUE,  RX_DMA_BURST_THRESH);
 678         ipg_w8(IPG_TXDMAPOLLPERIOD_VALUE,   TX_DMA_POLL_PERIOD);
 679         ipg_w8(IPG_TXDMAURGENTTHRESH_VALUE, TX_DMA_URGENT_THRESH);
 680         ipg_w8(IPG_TXDMABURSTTHRESH_VALUE,  TX_DMA_BURST_THRESH);
 681         ipg_w16((IPG_IE_HOST_ERROR | IPG_IE_TX_DMA_COMPLETE |
 682                  IPG_IE_TX_COMPLETE | IPG_IE_INT_REQUESTED |
 683                  IPG_IE_UPDATE_STATS | IPG_IE_LINK_EVENT |
 684                  IPG_IE_RX_DMA_COMPLETE | IPG_IE_RX_DMA_PRIORITY), INT_ENABLE);
 685         ipg_w16(IPG_FLOWONTHRESH_VALUE,  FLOW_ON_THRESH);
 686         ipg_w16(IPG_FLOWOFFTHRESH_VALUE, FLOW_OFF_THRESH);
 687
 688         /* IPG multi-frag frame bug workaround.
 689          * Per silicon revision B3 eratta.
 690          */
 691         ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0200, DEBUG_CTRL);
 692
 693         /* IPG TX poll now bug workaround.
 694          * Per silicon revision B3 eratta.
 695          */
 696         ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0010, DEBUG_CTRL);
 697
 698         /* IPG RX poll now bug workaround.
 699          * Per silicon revision B3 eratta.
 700          */
 701         ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0020, DEBUG_CTRL);
 702
 703         /* Now restore MACCTRL to original setting. */
 704         ipg_w32(IPG_MC_RSVD_MASK & restoremacctrl, MAC_CTRL);
 705
 706         /* Disable unused RMON statistics. */
 707         ipg_w32(IPG_RZ_ALL, RMON_STATISTICS_MASK);
 708
 709         /* Disable unused MIB statistics. */
 710         ipg_w32(IPG_SM_MACCONTROLFRAMESXMTD | IPG_SM_MACCONTROLFRAMESRCVD |
 711                 IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK | IPG_SM_TXJUMBOFRAMES |
 712                 IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK | IPG_SM_RXJUMBOFRAMES |
 713                 IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK |
 714                 IPG_SM_UDPCHECKSUMERRORS | IPG_SM_TCPCHECKSUMERRORS |
 715                 IPG_SM_IPCHECKSUMERRORS, STATISTICS_MASK);
 716
 717         return 0;
 718 }
 719
 720 /*
 721  * Create a receive buffer within system memory and update
 722  * NIC private structure appropriately.
 723  */
 724 static int ipg_get_rxbuff(struct net_device *dev, int entry)
 725 {
 726         struct ipg_nic_private *sp = netdev_priv(dev);
 727         struct ipg_rx *rxfd = sp->rxd + entry;
 728         struct sk_buff *skb;
 729         u64 rxfragsize;
 730
 731         IPG_DEBUG_MSG("_get_rxbuff\n");
 732
 733         skb = netdev_alloc_skb(dev, IPG_RXSUPPORT_SIZE + NET_IP_ALIGN);
 734         if (!skb) {
 735                 sp->rx_buff[entry] = NULL;
 736                 return -ENOMEM;
 737         }
 738
 739         /* Adjust the data start location within the buffer to
 740          * align IP address field to a 16 byte boundary.
 741          */
 742         skb_reserve(skb, NET_IP_ALIGN);
 743
 744         /* Associate the receive buffer with the IPG NIC. */
 745         skb->dev = dev;
 746
 747         /* Save the address of the sk_buff structure. */
 748         sp->rx_buff[entry] = skb;
 749
 750         rxfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
 751                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE));
 752
 753         /* Set the RFD fragment length. */
 754         rxfragsize = sp->rxfrag_size;
 755         rxfd->frag_info |= cpu_to_le64((rxfragsize << 48) & IPG_RFI_FRAGLEN);
 756
 757         return 0;
 758 }
 759
 760 static int init_rfdlist(struct net_device *dev)
 761 {
 762         struct ipg_nic_private *sp = netdev_priv(dev);
 763         void __iomem *ioaddr = sp->ioaddr;
 764         unsigned int i;
 765
 766         IPG_DEBUG_MSG("_init_rfdlist\n");
 767
 768         for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
 769                 struct ipg_rx *rxfd = sp->rxd + i;
 770
 771                 if (sp->rx_buff[i]) {
 772                         pci_unmap_single(sp->pdev,
 773                                 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
 774                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
 775                         dev_kfree_skb_irq(sp->rx_buff[i]);
 776                         sp->rx_buff[i] = NULL;
 777                 }
 778
 779                 /* Clear out the RFS field. */
 780                 rxfd->rfs = 0x0000000000000000;
 781
 782                 if (ipg_get_rxbuff(dev, i) < 0) {
 783                         /*
 784                          * A receive buffer was not ready, break the
 785                          * RFD list here.
 786                          */
 787                         IPG_DEBUG_MSG("Cannot allocate Rx buffer.\n");
 788
 789                         /* Just in case we cannot allocate a single RFD.
 790                          * Should not occur.
 791                          */
 792                         if (i == 0) {
 793                                 printk(KERN_ERR "%s: No memory available"
 794                                         " for RFD list.\n", dev->name);
 795                                 return -ENOMEM;
 796                         }
 797                 }
 798
 799                 rxfd->next_desc = cpu_to_le64(sp->rxd_map +
 800                         sizeof(struct ipg_rx)*(i + 1));
 801         }
 802         sp->rxd[i - 1].next_desc = cpu_to_le64(sp->rxd_map);
 803
 804         sp->rx_current = 0;
 805         sp->rx_dirty = 0;
 806
 807         /* Write the location of the RFDList to the IPG. */
 808         ipg_w32((u32) sp->rxd_map, RFD_LIST_PTR_0);
 809         ipg_w32(0x00000000, RFD_LIST_PTR_1);
 810
 811         return 0;
 812 }
 813
 814 static void init_tfdlist(struct net_device *dev)
 815 {
 816         struct ipg_nic_private *sp = netdev_priv(dev);
 817         void __iomem *ioaddr = sp->ioaddr;
 818         unsigned int i;
 819
 820         IPG_DEBUG_MSG("_init_tfdlist\n");
 821
 822         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
 823                 struct ipg_tx *txfd = sp->txd + i;
 824
 825                 txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
 826
 827                 if (sp->tx_buff[i]) {
 828                         dev_kfree_skb_irq(sp->tx_buff[i]);
 829                         sp->tx_buff[i] = NULL;
 830                 }
 831
 832                 txfd->next_desc = cpu_to_le64(sp->txd_map +
 833                         sizeof(struct ipg_tx)*(i + 1));
 834         }
 835         sp->txd[i - 1].next_desc = cpu_to_le64(sp->txd_map);
 836
 837         sp->tx_current = 0;
 838         sp->tx_dirty = 0;
 839
 840         /* Write the location of the TFDList to the IPG. */
 841         IPG_DDEBUG_MSG("Starting TFDListPtr = %8.8x\n",
 842                        (u32) sp->txd_map);
 843         ipg_w32((u32) sp->txd_map, TFD_LIST_PTR_0);
 844         ipg_w32(0x00000000, TFD_LIST_PTR_1);
 845
 846         sp->reset_current_tfd = 1;
 847 }
 848
 849 /*
 850  * Free all transmit buffers which have already been transfered
 851  * via DMA to the IPG.
 852  */
 853 static void ipg_nic_txfree(struct net_device *dev)
 854 {
 855         struct ipg_nic_private *sp = netdev_priv(dev);
 856         unsigned int released, pending, dirty;
 857
 858         IPG_DEBUG_MSG("_nic_txfree\n");
 859
 860         pending = sp->tx_current - sp->tx_dirty;
 861         dirty = sp->tx_dirty % IPG_TFDLIST_LENGTH;
 862
 863         for (released = 0; released < pending; released++) {
 864                 struct sk_buff *skb = sp->tx_buff[dirty];
 865                 struct ipg_tx *txfd = sp->txd + dirty;
 866
 867                 IPG_DEBUG_MSG("TFC = %16.16lx\n", (unsigned long) txfd->tfc);
 868
 869                 /* Look at each TFD's TFC field beginning
 870                  * at the last freed TFD up to the current TFD.
 871                  * If the TFDDone bit is set, free the associated
 872                  * buffer.
 873                  */
 874                 if (!(txfd->tfc & cpu_to_le64(IPG_TFC_TFDDONE)))
 875                         break;
 876
 877                 /* Free the transmit buffer. */
 878                 if (skb) {
 879                         pci_unmap_single(sp->pdev,
 880                                 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
 881                                 skb->len, PCI_DMA_TODEVICE);
 882
 883                         dev_kfree_skb_irq(skb);
 884
 885                         sp->tx_buff[dirty] = NULL;
 886                 }
 887                 dirty = (dirty + 1) % IPG_TFDLIST_LENGTH;
 888         }
 889
 890         sp->tx_dirty += released;
 891
 892         if (netif_queue_stopped(dev) &&
 893             (sp->tx_current != (sp->tx_dirty + IPG_TFDLIST_LENGTH))) {
 894                 netif_wake_queue(dev);
 895         }
 896 }
 897
 898 static void ipg_tx_timeout(struct net_device *dev)
 899 {
 900         struct ipg_nic_private *sp = netdev_priv(dev);
 901         void __iomem *ioaddr = sp->ioaddr;
 902
 903         ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA | IPG_AC_NETWORK |
 904                   IPG_AC_FIFO);
 905
 906         spin_lock_irq(&sp->lock);
 907
 908         /* Re-configure after DMA reset. */
 909         if (ipg_io_config(dev) < 0) {
 910                 printk(KERN_INFO "%s: Error during re-configuration.\n",
 911                        dev->name);
 912         }
 913
 914         init_tfdlist(dev);
 915
 916         spin_unlock_irq(&sp->lock);
 917
 918         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) & IPG_MC_RSVD_MASK,
 919                 MAC_CTRL);
 920 }
 921
 922 /*
 923  * For TxComplete interrupts, free all transmit
 924  * buffers which have already been transfered via DMA
 925  * to the IPG.
 926  */
 927 static void ipg_nic_txcleanup(struct net_device *dev)
 928 {
 929         struct ipg_nic_private *sp = netdev_priv(dev);
 930         void __iomem *ioaddr = sp->ioaddr;
 931         unsigned int i;
 932
 933         IPG_DEBUG_MSG("_nic_txcleanup\n");
 934
 935         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
 936                 /* Reading the TXSTATUS register clears the
 937                  * TX_COMPLETE interrupt.
 938                  */
 939                 u32 txstatusdword = ipg_r32(TX_STATUS);
 940
 941                 IPG_DEBUG_MSG("TxStatus = %8.8x\n", txstatusdword);
 942
 943                 /* Check for Transmit errors. Error bits only valid if
 944                  * TX_COMPLETE bit in the TXSTATUS register is a 1.
 945                  */
 946                 if (!(txstatusdword & IPG_TS_TX_COMPLETE))
 947                         break;
 948
 949                 /* If in 10Mbps mode, indicate transmit is ready. */
 950                 if (sp->tenmbpsmode) {
 951                         netif_wake_queue(dev);
 952                 }
 953
 954                 /* Transmit error, increment stat counters. */
 955                 if (txstatusdword & IPG_TS_TX_ERROR) {
 956                         IPG_DEBUG_MSG("Transmit error.\n");
 957                         sp->stats.tx_errors++;
 958                 }
 959
 960                 /* Late collision, re-enable transmitter. */
 961                 if (txstatusdword & IPG_TS_LATE_COLLISION) {
 962                         IPG_DEBUG_MSG("Late collision on transmit.\n");
 963                         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
 964                                 IPG_MC_RSVD_MASK, MAC_CTRL);
 965                 }
 966
 967                 /* Maximum collisions, re-enable transmitter. */
 968                 if (txstatusdword & IPG_TS_TX_MAX_COLL) {
 969                         IPG_DEBUG_MSG("Maximum collisions on transmit.\n");
 970                         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
 971                                 IPG_MC_RSVD_MASK, MAC_CTRL);
 972                 }
 973
 974                 /* Transmit underrun, reset and re-enable
 975                  * transmitter.
 976                  */
 977                 if (txstatusdword & IPG_TS_TX_UNDERRUN) {
 978                         IPG_DEBUG_MSG("Transmitter underrun.\n");
 979                         sp->stats.tx_fifo_errors++;
 980                         ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA |
 981                                   IPG_AC_NETWORK | IPG_AC_FIFO);
 982
 983                         /* Re-configure after DMA reset. */
 984                         if (ipg_io_config(dev) < 0) {
 985                                 printk(KERN_INFO
 986                                        "%s: Error during re-configuration.\n",
 987                                        dev->name);
 988                         }
 989                         init_tfdlist(dev);
 990
 991                         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
 992                                 IPG_MC_RSVD_MASK, MAC_CTRL);
 993                 }
 994         }
 995
 996         ipg_nic_txfree(dev);
 997 }
 998
 999 /* Provides statistical information about the IPG NIC. */
1000 static struct net_device_stats *ipg_nic_get_stats(struct net_device *dev)
1001 {
1002         struct ipg_nic_private *sp = netdev_priv(dev);
1003         void __iomem *ioaddr = sp->ioaddr;
1004         u16 temp1;
1005         u16 temp2;
1006
1007         IPG_DEBUG_MSG("_nic_get_stats\n");
1008
1009         /* Check to see if the NIC has been initialized via nic_open,
1010          * before trying to read statistic registers.
1011          */
1012         if (!test_bit(__LINK_STATE_START, &dev->state))
1013                 return &sp->stats;
1014
1015         sp->stats.rx_packets += ipg_r32(IPG_FRAMESRCVDOK);
1016         sp->stats.tx_packets += ipg_r32(IPG_FRAMESXMTDOK);
1017         sp->stats.rx_bytes += ipg_r32(IPG_OCTETRCVOK);
1018         sp->stats.tx_bytes += ipg_r32(IPG_OCTETXMTOK);
1019         temp1 = ipg_r16(IPG_FRAMESLOSTRXERRORS);
1020         sp->stats.rx_errors += temp1;
1021         sp->stats.rx_missed_errors += temp1;
1022         temp1 = ipg_r32(IPG_SINGLECOLFRAMES) + ipg_r32(IPG_MULTICOLFRAMES) +
1023                 ipg_r32(IPG_LATECOLLISIONS);
1024         temp2 = ipg_r16(IPG_CARRIERSENSEERRORS);
1025         sp->stats.collisions += temp1;
1026         sp->stats.tx_dropped += ipg_r16(IPG_FRAMESABORTXSCOLLS);
1027         sp->stats.tx_errors += ipg_r16(IPG_FRAMESWEXDEFERRAL) +
1028                 ipg_r32(IPG_FRAMESWDEFERREDXMT) + temp1 + temp2;
1029         sp->stats.multicast += ipg_r32(IPG_MCSTOCTETRCVDOK);
1030
1031         /* detailed tx_errors */
1032         sp->stats.tx_carrier_errors += temp2;
1033
1034         /* detailed rx_errors */
1035         sp->stats.rx_length_errors += ipg_r16(IPG_INRANGELENGTHERRORS) +
1036                 ipg_r16(IPG_FRAMETOOLONGERRRORS);
1037         sp->stats.rx_crc_errors += ipg_r16(IPG_FRAMECHECKSEQERRORS);
1038
1039         /* Unutilized IPG statistic registers. */
1040         ipg_r32(IPG_MCSTFRAMESRCVDOK);
1041
1042         return &sp->stats;
1043 }
1044
1045 /* Restore used receive buffers. */
1046 static int ipg_nic_rxrestore(struct net_device *dev)
1047 {
1048         struct ipg_nic_private *sp = netdev_priv(dev);
1049         const unsigned int curr = sp->rx_current;
1050         unsigned int dirty = sp->rx_dirty;
1051
1052         IPG_DEBUG_MSG("_nic_rxrestore\n");
1053
1054         for (dirty = sp->rx_dirty; curr - dirty > 0; dirty++) {
1055                 unsigned int entry = dirty % IPG_RFDLIST_LENGTH;
1056
1057                 /* rx_copybreak may poke hole here and there. */
1058                 if (sp->rx_buff[entry])
1059                         continue;
1060
1061                 /* Generate a new receive buffer to replace the
1062                  * current buffer (which will be released by the
1063                  * Linux system).
1064                  */
1065                 if (ipg_get_rxbuff(dev, entry) < 0) {
1066                         IPG_DEBUG_MSG("Cannot allocate new Rx buffer.\n");
1067
1068                         break;
1069                 }
1070
1071                 /* Reset the RFS field. */
1072                 sp->rxd[entry].rfs = 0x0000000000000000;
1073         }
1074         sp->rx_dirty = dirty;
1075
1076         return 0;
1077 }
1078
1079 /* use jumboindex and jumbosize to control jumbo frame status
1080  * initial status is jumboindex=-1 and jumbosize=0
1081  * 1. jumboindex = -1 and jumbosize=0 : previous jumbo frame has been done.
1082  * 2. jumboindex != -1 and jumbosize != 0 : jumbo frame is not over size and receiving
1083  * 3. jumboindex = -1 and jumbosize != 0 : jumbo frame is over size, already dump
1084  *               previous receiving and need to continue dumping the current one
1085  */
1086 enum {
1087         NORMAL_PACKET,
1088         ERROR_PACKET
1089 };
1090
1091 enum {
1092         FRAME_NO_START_NO_END   = 0,
1093         FRAME_WITH_START                = 1,
1094         FRAME_WITH_END          = 10,
1095         FRAME_WITH_START_WITH_END = 11
1096 };
1097
1098 static void ipg_nic_rx_free_skb(struct net_device *dev)
1099 {
1100         struct ipg_nic_private *sp = netdev_priv(dev);
1101         unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1102
1103         if (sp->rx_buff[entry]) {
1104                 struct ipg_rx *rxfd = sp->rxd + entry;
1105
1106                 pci_unmap_single(sp->pdev,
1107                         le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1108                         sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1109                 dev_kfree_skb_irq(sp->rx_buff[entry]);
1110                 sp->rx_buff[entry] = NULL;
1111         }
1112 }
1113
1114 static int ipg_nic_rx_check_frame_type(struct net_device *dev)
1115 {
1116         struct ipg_nic_private *sp = netdev_priv(dev);
1117         struct ipg_rx *rxfd = sp->rxd + (sp->rx_current % IPG_RFDLIST_LENGTH);
1118         int type = FRAME_NO_START_NO_END;
1119
1120         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART)
1121                 type += FRAME_WITH_START;
1122         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND)
1123                 type += FRAME_WITH_END;
1124         return type;
1125 }
1126
1127 static int ipg_nic_rx_check_error(struct net_device *dev)
1128 {
1129         struct ipg_nic_private *sp = netdev_priv(dev);
1130         unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1131         struct ipg_rx *rxfd = sp->rxd + entry;
1132
1133         if (IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1134              (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1135               IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
1136               IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR))) {
1137                 IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1138                               (unsigned long) rxfd->rfs);
1139
1140                 /* Increment general receive error statistic. */
1141                 sp->stats.rx_errors++;
1142
1143                 /* Increment detailed receive error statistics. */
1144                 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1145                         IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1146
1147                         sp->stats.rx_fifo_errors++;
1148                 }
1149
1150                 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1151                         IPG_DEBUG_MSG("RX runt occured.\n");
1152                         sp->stats.rx_length_errors++;
1153                 }
1154
1155                 /* Do nothing for IPG_RFS_RXOVERSIZEDFRAME,
1156                  * error count handled by a IPG statistic register.
1157                  */
1158
1159                 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1160                         IPG_DEBUG_MSG("RX alignment error occured.\n");
1161                         sp->stats.rx_frame_errors++;
1162                 }
1163
1164                 /* Do nothing for IPG_RFS_RXFCSERROR, error count
1165                  * handled by a IPG statistic register.
1166                  */
1167
1168                 /* Free the memory associated with the RX
1169                  * buffer since it is erroneous and we will
1170                  * not pass it to higher layer processes.
1171                  */
1172                 if (sp->rx_buff[entry]) {
1173                         pci_unmap_single(sp->pdev,
1174                                 le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1175                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1176
1177                         dev_kfree_skb_irq(sp->rx_buff[entry]);
1178                         sp->rx_buff[entry] = NULL;
1179                 }
1180                 return ERROR_PACKET;
1181         }
1182         return NORMAL_PACKET;
1183 }
1184
1185 static void ipg_nic_rx_with_start_and_end(struct net_device *dev,
1186                                           struct ipg_nic_private *sp,
1187                                           struct ipg_rx *rxfd, unsigned entry)
1188 {
1189         struct ipg_jumbo *jumbo = &sp->jumbo;
1190         struct sk_buff *skb;
1191         int framelen;
1192
1193         if (jumbo->found_start) {
1194                 dev_kfree_skb_irq(jumbo->skb);
1195                 jumbo->found_start = 0;
1196                 jumbo->current_size = 0;
1197                 jumbo->skb = NULL;
1198         }
1199
1200         /* 1: found error, 0 no error */
1201         if (ipg_nic_rx_check_error(dev) != NORMAL_PACKET)
1202                 return;
1203
1204         skb = sp->rx_buff[entry];
1205         if (!skb)
1206                 return;
1207
1208         /* accept this frame and send to upper layer */
1209         framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1210         if (framelen > sp->rxfrag_size)
1211                 framelen = sp->rxfrag_size;
1212
1213         skb_put(skb, framelen);
1214         skb->protocol = eth_type_trans(skb, dev);
1215         skb->ip_summed = CHECKSUM_NONE;
1216         netif_rx(skb);
1217         dev->last_rx = jiffies;
1218         sp->rx_buff[entry] = NULL;
1219 }
1220
1221 static void ipg_nic_rx_with_start(struct net_device *dev,
1222                                   struct ipg_nic_private *sp,
1223                                   struct ipg_rx *rxfd, unsigned entry)
1224 {
1225         struct ipg_jumbo *jumbo = &sp->jumbo;
1226         struct pci_dev *pdev = sp->pdev;
1227         struct sk_buff *skb;
1228
1229         /* 1: found error, 0 no error */
1230         if (ipg_nic_rx_check_error(dev) != NORMAL_PACKET)
1231                 return;
1232
1233         /* accept this frame and send to upper layer */
1234         skb = sp->rx_buff[entry];
1235         if (!skb)
1236                 return;
1237
1238         if (jumbo->found_start)
1239                 dev_kfree_skb_irq(jumbo->skb);
1240
1241         pci_unmap_single(pdev, le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1242                          sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1243
1244         skb_put(skb, sp->rxfrag_size);
1245
1246         jumbo->found_start = 1;
1247         jumbo->current_size = sp->rxfrag_size;
1248         jumbo->skb = skb;
1249
1250         sp->rx_buff[entry] = NULL;
1251         dev->last_rx = jiffies;
1252 }
1253
1254 static void ipg_nic_rx_with_end(struct net_device *dev,
1255                                 struct ipg_nic_private *sp,
1256                                 struct ipg_rx *rxfd, unsigned entry)
1257 {
1258         struct ipg_jumbo *jumbo = &sp->jumbo;
1259
1260         /* 1: found error, 0 no error */
1261         if (ipg_nic_rx_check_error(dev) == NORMAL_PACKET) {
1262                 struct sk_buff *skb = sp->rx_buff[entry];
1263
1264                 if (!skb)
1265                         return;
1266
1267                 if (jumbo->found_start) {
1268                         int framelen, endframelen;
1269
1270                         framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1271
1272                         endframelen = framelen - jumbo->current_size;
1273                         if (framelen > IPG_RXSUPPORT_SIZE)
1274                                 dev_kfree_skb_irq(jumbo->skb);
1275                         else {
1276                                 memcpy(skb_put(jumbo->skb, endframelen),
1277                                        skb->data, endframelen);
1278
1279                                 jumbo->skb->protocol =
1280                                     eth_type_trans(jumbo->skb, dev);
1281
1282                                 jumbo->skb->ip_summed = CHECKSUM_NONE;
1283                                 netif_rx(jumbo->skb);
1284                         }
1285                 }
1286
1287                 dev->last_rx = jiffies;
1288                 jumbo->found_start = 0;
1289                 jumbo->current_size = 0;
1290                 jumbo->skb = NULL;
1291
1292                 ipg_nic_rx_free_skb(dev);
1293         } else {
1294                 dev_kfree_skb_irq(jumbo->skb);
1295                 jumbo->found_start = 0;
1296                 jumbo->current_size = 0;
1297                 jumbo->skb = NULL;
1298         }
1299 }
1300
1301 static void ipg_nic_rx_no_start_no_end(struct net_device *dev,
1302                                        struct ipg_nic_private *sp,
1303                                        struct ipg_rx *rxfd, unsigned entry)
1304 {
1305         struct ipg_jumbo *jumbo = &sp->jumbo;
1306
1307         /* 1: found error, 0 no error */
1308         if (ipg_nic_rx_check_error(dev) == NORMAL_PACKET) {
1309                 struct sk_buff *skb = sp->rx_buff[entry];
1310
1311                 if (skb) {
1312                         if (jumbo->found_start) {
1313                                 jumbo->current_size += sp->rxfrag_size;
1314                                 if (jumbo->current_size <= IPG_RXSUPPORT_SIZE) {
1315                                         memcpy(skb_put(jumbo->skb,
1316                                                        sp->rxfrag_size),
1317                                                skb->data, sp->rxfrag_size);
1318                                 }
1319                         }
1320                         dev->last_rx = jiffies;
1321                         ipg_nic_rx_free_skb(dev);
1322                 }
1323         } else {
1324                 dev_kfree_skb_irq(jumbo->skb);
1325                 jumbo->found_start = 0;
1326                 jumbo->current_size = 0;
1327                 jumbo->skb = NULL;
1328         }
1329 }
1330
1331 static int ipg_nic_rx_jumbo(struct net_device *dev)
1332 {
1333         struct ipg_nic_private *sp = netdev_priv(dev);
1334         unsigned int curr = sp->rx_current;
1335         void __iomem *ioaddr = sp->ioaddr;
1336         unsigned int i;
1337
1338         IPG_DEBUG_MSG("_nic_rx\n");
1339
1340         for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1341                 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1342                 struct ipg_rx *rxfd = sp->rxd + entry;
1343
1344                 if (!(rxfd->rfs & le64_to_cpu(IPG_RFS_RFDDONE)))
1345                         break;
1346
1347                 switch (ipg_nic_rx_check_frame_type(dev)) {
1348                 case FRAME_WITH_START_WITH_END:
1349                         ipg_nic_rx_with_start_and_end(dev, sp, rxfd, entry);
1350                         break;
1351                 case FRAME_WITH_START:
1352                         ipg_nic_rx_with_start(dev, sp, rxfd, entry);
1353                         break;
1354                 case FRAME_WITH_END:
1355                         ipg_nic_rx_with_end(dev, sp, rxfd, entry);
1356                         break;
1357                 case FRAME_NO_START_NO_END:
1358                         ipg_nic_rx_no_start_no_end(dev, sp, rxfd, entry);
1359                         break;
1360                 }
1361         }
1362
1363         sp->rx_current = curr;
1364
1365         if (i == IPG_MAXRFDPROCESS_COUNT) {
1366                 /* There are more RFDs to process, however the
1367                  * allocated amount of RFD processing time has
1368                  * expired. Assert Interrupt Requested to make
1369                  * sure we come back to process the remaining RFDs.
1370                  */
1371                 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1372         }
1373
1374         ipg_nic_rxrestore(dev);
1375
1376         return 0;
1377 }
1378
1379 static int ipg_nic_rx(struct net_device *dev)
1380 {
1381         /* Transfer received Ethernet frames to higher network layers. */
1382         struct ipg_nic_private *sp = netdev_priv(dev);
1383         unsigned int curr = sp->rx_current;
1384         void __iomem *ioaddr = sp->ioaddr;
1385         struct ipg_rx *rxfd;
1386         unsigned int i;
1387
1388         IPG_DEBUG_MSG("_nic_rx\n");
1389
1390 #define __RFS_MASK \
1391         cpu_to_le64(IPG_RFS_RFDDONE | IPG_RFS_FRAMESTART | IPG_RFS_FRAMEEND)
1392
1393         for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1394                 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1395                 struct sk_buff *skb = sp->rx_buff[entry];
1396                 unsigned int framelen;
1397
1398                 rxfd = sp->rxd + entry;
1399
1400                 if (((rxfd->rfs & __RFS_MASK) != __RFS_MASK) || !skb)
1401                         break;
1402
1403                 /* Get received frame length. */
1404                 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1405
1406                 /* Check for jumbo frame arrival with too small
1407                  * RXFRAG_SIZE.
1408                  */
1409                 if (framelen > sp->rxfrag_size) {
1410                         IPG_DEBUG_MSG
1411                             ("RFS FrameLen > allocated fragment size.\n");
1412
1413                         framelen = sp->rxfrag_size;
1414                 }
1415
1416                 if ((IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1417                        (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1418                         IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
1419                         IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR)))) {
1420
1421                         IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1422                                       (unsigned long int) rxfd->rfs);
1423
1424                         /* Increment general receive error statistic. */
1425                         sp->stats.rx_errors++;
1426
1427                         /* Increment detailed receive error statistics. */
1428                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1429                                 IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1430                                 sp->stats.rx_fifo_errors++;
1431                         }
1432
1433                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1434                                 IPG_DEBUG_MSG("RX runt occured.\n");
1435                                 sp->stats.rx_length_errors++;
1436                         }
1437
1438                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXOVERSIZEDFRAME) ;
1439                         /* Do nothing, error count handled by a IPG
1440                          * statistic register.
1441                          */
1442
1443                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1444                                 IPG_DEBUG_MSG("RX alignment error occured.\n");
1445                                 sp->stats.rx_frame_errors++;
1446                         }
1447
1448                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFCSERROR) ;
1449                         /* Do nothing, error count handled by a IPG
1450                          * statistic register.
1451                          */
1452
1453                         /* Free the memory associated with the RX
1454                          * buffer since it is erroneous and we will
1455                          * not pass it to higher layer processes.
1456                          */
1457                         if (skb) {
1458                                 __le64 info = rxfd->frag_info;
1459
1460                                 pci_unmap_single(sp->pdev,
1461                                         le64_to_cpu(info) & ~IPG_RFI_FRAGLEN,
1462                                         sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1463
1464                                 dev_kfree_skb_irq(skb);
1465                         }
1466                 } else {
1467
1468                         /* Adjust the new buffer length to accomodate the size
1469                          * of the received frame.
1470                          */
1471                         skb_put(skb, framelen);
1472
1473                         /* Set the buffer's protocol field to Ethernet. */
1474                         skb->protocol = eth_type_trans(skb, dev);
1475
1476                         /* The IPG encountered an error with (or
1477                          * there were no) IP/TCP/UDP checksums.
1478                          * This may or may not indicate an invalid
1479                          * IP/TCP/UDP frame was received. Let the
1480                          * upper layer decide.
1481                          */
1482                         skb->ip_summed = CHECKSUM_NONE;
1483
1484                         /* Hand off frame for higher layer processing.
1485                          * The function netif_rx() releases the sk_buff
1486                          * when processing completes.
1487                          */
1488                         netif_rx(skb);
1489
1490                         /* Record frame receive time (jiffies = Linux
1491                          * kernel current time stamp).
1492                          */
1493                         dev->last_rx = jiffies;
1494                 }
1495
1496                 /* Assure RX buffer is not reused by IPG. */
1497                 sp->rx_buff[entry] = NULL;
1498         }
1499
1500         /*
1501          * If there are more RFDs to proces and the allocated amount of RFD
1502          * processing time has expired, assert Interrupt Requested to make
1503          * sure we come back to process the remaining RFDs.
1504          */
1505         if (i == IPG_MAXRFDPROCESS_COUNT)
1506                 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1507
1508 #ifdef IPG_DEBUG
1509         /* Check if the RFD list contained no receive frame data. */
1510         if (!i)
1511                 sp->EmptyRFDListCount++;
1512 #endif
1513         while ((le64_to_cpu(rxfd->rfs) & IPG_RFS_RFDDONE) &&
1514                !((le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART) &&
1515                  (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND))) {
1516                 unsigned int entry = curr++ % IPG_RFDLIST_LENGTH;
1517
1518                 rxfd = sp->rxd + entry;
1519
1520                 IPG_DEBUG_MSG("Frame requires multiple RFDs.\n");
1521
1522                 /* An unexpected event, additional code needed to handle
1523                  * properly. So for the time being, just disregard the
1524                  * frame.
1525                  */
1526
1527                 /* Free the memory associated with the RX
1528                  * buffer since it is erroneous and we will
1529                  * not pass it to higher layer processes.
1530                  */
1531                 if (sp->rx_buff[entry]) {
1532                         pci_unmap_single(sp->pdev,
1533                                 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1534                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1535                         dev_kfree_skb_irq(sp->rx_buff[entry]);
1536                 }
1537
1538                 /* Assure RX buffer is not reused by IPG. */
1539                 sp->rx_buff[entry] = NULL;
1540         }
1541
1542         sp->rx_current = curr;
1543
1544         /* Check to see if there are a minimum number of used
1545          * RFDs before restoring any (should improve performance.)
1546          */
1547         if ((curr - sp->rx_dirty) >= IPG_MINUSEDRFDSTOFREE)
1548                 ipg_nic_rxrestore(dev);
1549
1550         return 0;
1551 }
1552
1553 static void ipg_reset_after_host_error(struct work_struct *work)
1554 {
1555         struct ipg_nic_private *sp =
1556                 container_of(work, struct ipg_nic_private, task.work);
1557         struct net_device *dev = sp->dev;
1558
1559         IPG_DDEBUG_MSG("DMACtrl = %8.8x\n", ioread32(sp->ioaddr + IPG_DMACTRL));
1560
1561         /*
1562          * Acknowledge HostError interrupt by resetting
1563          * IPG DMA and HOST.
1564          */
1565         ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1566
1567         init_rfdlist(dev);
1568         init_tfdlist(dev);
1569
1570         if (ipg_io_config(dev) < 0) {
1571                 printk(KERN_INFO "%s: Cannot recover from PCI error.\n",
1572                        dev->name);
1573                 schedule_delayed_work(&sp->task, HZ);
1574         }
1575 }
1576
1577 static irqreturn_t ipg_interrupt_handler(int irq, void *dev_inst)
1578 {
1579         struct net_device *dev = dev_inst;
1580         struct ipg_nic_private *sp = netdev_priv(dev);
1581         void __iomem *ioaddr = sp->ioaddr;
1582         unsigned int handled = 0;
1583         u16 status;
1584
1585         IPG_DEBUG_MSG("_interrupt_handler\n");
1586
1587         if (sp->is_jumbo)
1588                 ipg_nic_rxrestore(dev);
1589
1590         spin_lock(&sp->lock);
1591
1592         /* Get interrupt source information, and acknowledge
1593          * some (i.e. TxDMAComplete, RxDMAComplete, RxEarly,
1594          * IntRequested, MacControlFrame, LinkEvent) interrupts
1595          * if issued. Also, all IPG interrupts are disabled by
1596          * reading IntStatusAck.
1597          */
1598         status = ipg_r16(INT_STATUS_ACK);
1599
1600         IPG_DEBUG_MSG("IntStatusAck = %4.4x\n", status);
1601
1602         /* Shared IRQ of remove event. */
1603         if (!(status & IPG_IS_RSVD_MASK))
1604                 goto out_enable;
1605
1606         handled = 1;
1607
1608         if (unlikely(!netif_running(dev)))
1609                 goto out_unlock;
1610
1611         /* If RFDListEnd interrupt, restore all used RFDs. */
1612         if (status & IPG_IS_RFD_LIST_END) {
1613                 IPG_DEBUG_MSG("RFDListEnd Interrupt.\n");
1614
1615                 /* The RFD list end indicates an RFD was encountered
1616                  * with a 0 NextPtr, or with an RFDDone bit set to 1
1617                  * (indicating the RFD is not read for use by the
1618                  * IPG.) Try to restore all RFDs.
1619                  */
1620                 ipg_nic_rxrestore(dev);
1621
1622 #ifdef IPG_DEBUG
1623                 /* Increment the RFDlistendCount counter. */
1624                 sp->RFDlistendCount++;
1625 #endif
1626         }
1627
1628         /* If RFDListEnd, RxDMAPriority, RxDMAComplete, or
1629          * IntRequested interrupt, process received frames. */
1630         if ((status & IPG_IS_RX_DMA_PRIORITY) ||
1631             (status & IPG_IS_RFD_LIST_END) ||
1632             (status & IPG_IS_RX_DMA_COMPLETE) ||
1633             (status & IPG_IS_INT_REQUESTED)) {
1634 #ifdef IPG_DEBUG
1635                 /* Increment the RFD list checked counter if interrupted
1636                  * only to check the RFD list. */
1637                 if (status & (~(IPG_IS_RX_DMA_PRIORITY | IPG_IS_RFD_LIST_END |
1638                                 IPG_IS_RX_DMA_COMPLETE | IPG_IS_INT_REQUESTED) &
1639                                (IPG_IS_HOST_ERROR | IPG_IS_TX_DMA_COMPLETE |
1640                                 IPG_IS_LINK_EVENT | IPG_IS_TX_COMPLETE |
1641                                 IPG_IS_UPDATE_STATS)))
1642                         sp->RFDListCheckedCount++;
1643 #endif
1644
1645                 if (sp->is_jumbo)
1646                         ipg_nic_rx_jumbo(dev);
1647                 else
1648                         ipg_nic_rx(dev);
1649         }
1650
1651         /* If TxDMAComplete interrupt, free used TFDs. */
1652         if (status & IPG_IS_TX_DMA_COMPLETE)
1653                 ipg_nic_txfree(dev);
1654
1655         /* TxComplete interrupts indicate one of numerous actions.
1656          * Determine what action to take based on TXSTATUS register.
1657          */
1658         if (status & IPG_IS_TX_COMPLETE)
1659                 ipg_nic_txcleanup(dev);
1660
1661         /* If UpdateStats interrupt, update Linux Ethernet statistics */
1662         if (status & IPG_IS_UPDATE_STATS)
1663                 ipg_nic_get_stats(dev);
1664
1665         /* If HostError interrupt, reset IPG. */
1666         if (status & IPG_IS_HOST_ERROR) {
1667                 IPG_DDEBUG_MSG("HostError Interrupt\n");
1668
1669                 schedule_delayed_work(&sp->task, 0);
1670         }
1671
1672         /* If LinkEvent interrupt, resolve autonegotiation. */
1673         if (status & IPG_IS_LINK_EVENT) {
1674                 if (ipg_config_autoneg(dev) < 0)
1675                         printk(KERN_INFO "%s: Auto-negotiation error.\n",
1676                                dev->name);
1677         }
1678
1679         /* If MACCtrlFrame interrupt, do nothing. */
1680         if (status & IPG_IS_MAC_CTRL_FRAME)
1681                 IPG_DEBUG_MSG("MACCtrlFrame interrupt.\n");
1682
1683         /* If RxComplete interrupt, do nothing. */
1684         if (status & IPG_IS_RX_COMPLETE)
1685                 IPG_DEBUG_MSG("RxComplete interrupt.\n");
1686
1687         /* If RxEarly interrupt, do nothing. */
1688         if (status & IPG_IS_RX_EARLY)
1689                 IPG_DEBUG_MSG("RxEarly interrupt.\n");
1690
1691 out_enable:
1692         /* Re-enable IPG interrupts. */
1693         ipg_w16(IPG_IE_TX_DMA_COMPLETE | IPG_IE_RX_DMA_COMPLETE |
1694                 IPG_IE_HOST_ERROR | IPG_IE_INT_REQUESTED | IPG_IE_TX_COMPLETE |
1695                 IPG_IE_LINK_EVENT | IPG_IE_UPDATE_STATS, INT_ENABLE);
1696 out_unlock:
1697         spin_unlock(&sp->lock);
1698
1699         return IRQ_RETVAL(handled);
1700 }
1701
1702 static void ipg_rx_clear(struct ipg_nic_private *sp)
1703 {
1704         unsigned int i;
1705
1706         for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
1707                 if (sp->rx_buff[i]) {
1708                         struct ipg_rx *rxfd = sp->rxd + i;
1709
1710                         dev_kfree_skb_irq(sp->rx_buff[i]);
1711                         sp->rx_buff[i] = NULL;
1712                         pci_unmap_single(sp->pdev,
1713                                 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1714                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1715                 }
1716         }
1717 }
1718
1719 static void ipg_tx_clear(struct ipg_nic_private *sp)
1720 {
1721         unsigned int i;
1722
1723         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
1724                 if (sp->tx_buff[i]) {
1725                         struct ipg_tx *txfd = sp->txd + i;
1726
1727                         pci_unmap_single(sp->pdev,
1728                                 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
1729                                 sp->tx_buff[i]->len, PCI_DMA_TODEVICE);
1730
1731                         dev_kfree_skb_irq(sp->tx_buff[i]);
1732
1733                         sp->tx_buff[i] = NULL;
1734                 }
1735         }
1736 }
1737
1738 static int ipg_nic_open(struct net_device *dev)
1739 {
1740         struct ipg_nic_private *sp = netdev_priv(dev);
1741         void __iomem *ioaddr = sp->ioaddr;
1742         struct pci_dev *pdev = sp->pdev;
1743         int rc;
1744
1745         IPG_DEBUG_MSG("_nic_open\n");
1746
1747         sp->rx_buf_sz = IPG_RXSUPPORT_SIZE;
1748
1749         /* Check for interrupt line conflicts, and request interrupt
1750          * line for IPG.
1751          *
1752          * IMPORTANT: Disable IPG interrupts prior to registering
1753          *            IRQ.
1754          */
1755         ipg_w16(0x0000, INT_ENABLE);
1756
1757         /* Register the interrupt line to be used by the IPG within
1758          * the Linux system.
1759          */
1760         rc = request_irq(pdev->irq, &ipg_interrupt_handler, IRQF_SHARED,
1761                          dev->name, dev);
1762         if (rc < 0) {
1763                 printk(KERN_INFO "%s: Error when requesting interrupt.\n",
1764                        dev->name);
1765                 goto out;
1766         }
1767
1768         dev->irq = pdev->irq;
1769
1770         rc = -ENOMEM;
1771
1772         sp->rxd = dma_alloc_coherent(&pdev->dev, IPG_RX_RING_BYTES,
1773                                      &sp->rxd_map, GFP_KERNEL);
1774         if (!sp->rxd)
1775                 goto err_free_irq_0;
1776
1777         sp->txd = dma_alloc_coherent(&pdev->dev, IPG_TX_RING_BYTES,
1778                                      &sp->txd_map, GFP_KERNEL);
1779         if (!sp->txd)
1780                 goto err_free_rx_1;
1781
1782         rc = init_rfdlist(dev);
1783         if (rc < 0) {
1784                 printk(KERN_INFO "%s: Error during configuration.\n",
1785                        dev->name);
1786                 goto err_free_tx_2;
1787         }
1788
1789         init_tfdlist(dev);
1790
1791         rc = ipg_io_config(dev);
1792         if (rc < 0) {
1793                 printk(KERN_INFO "%s: Error during configuration.\n",
1794                        dev->name);
1795                 goto err_release_tfdlist_3;
1796         }
1797
1798         /* Resolve autonegotiation. */
1799         if (ipg_config_autoneg(dev) < 0)
1800                 printk(KERN_INFO "%s: Auto-negotiation error.\n", dev->name);
1801
1802         /* initialize JUMBO Frame control variable */
1803         sp->jumbo.found_start = 0;
1804         sp->jumbo.current_size = 0;
1805         sp->jumbo.skb = NULL;
1806
1807         if (IPG_TXFRAG_SIZE)
1808                 dev->mtu = IPG_TXFRAG_SIZE;
1809
1810         /* Enable transmit and receive operation of the IPG. */
1811         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_RX_ENABLE | IPG_MC_TX_ENABLE) &
1812                  IPG_MC_RSVD_MASK, MAC_CTRL);
1813
1814         netif_start_queue(dev);
1815 out:
1816         return rc;
1817
1818 err_release_tfdlist_3:
1819         ipg_tx_clear(sp);
1820         ipg_rx_clear(sp);
1821 err_free_tx_2:
1822         dma_free_coherent(&pdev->dev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1823 err_free_rx_1:
1824         dma_free_coherent(&pdev->dev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1825 err_free_irq_0:
1826         free_irq(pdev->irq, dev);
1827         goto out;
1828 }
1829
1830 static int ipg_nic_stop(struct net_device *dev)
1831 {
1832         struct ipg_nic_private *sp = netdev_priv(dev);
1833         void __iomem *ioaddr = sp->ioaddr;
1834         struct pci_dev *pdev = sp->pdev;
1835
1836         IPG_DEBUG_MSG("_nic_stop\n");
1837
1838         netif_stop_queue(dev);
1839
1840         IPG_DDEBUG_MSG("RFDlistendCount = %i\n", sp->RFDlistendCount);
1841         IPG_DDEBUG_MSG("RFDListCheckedCount = %i\n", sp->rxdCheckedCount);
1842         IPG_DDEBUG_MSG("EmptyRFDListCount = %i\n", sp->EmptyRFDListCount);
1843         IPG_DUMPTFDLIST(dev);
1844
1845         do {
1846                 (void) ipg_r16(INT_STATUS_ACK);
1847
1848                 ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1849
1850                 synchronize_irq(pdev->irq);
1851         } while (ipg_r16(INT_ENABLE) & IPG_IE_RSVD_MASK);
1852
1853         ipg_rx_clear(sp);
1854
1855         ipg_tx_clear(sp);
1856
1857         pci_free_consistent(pdev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1858         pci_free_consistent(pdev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1859
1860         free_irq(pdev->irq, dev);
1861
1862         return 0;
1863 }
1864
1865 static int ipg_nic_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1866 {
1867         struct ipg_nic_private *sp = netdev_priv(dev);
1868         void __iomem *ioaddr = sp->ioaddr;
1869         unsigned int entry = sp->tx_current % IPG_TFDLIST_LENGTH;
1870         unsigned long flags;
1871         struct ipg_tx *txfd;
1872
1873         IPG_DDEBUG_MSG("_nic_hard_start_xmit\n");
1874
1875         /* If in 10Mbps mode, stop the transmit queue so
1876          * no more transmit frames are accepted.
1877          */
1878         if (sp->tenmbpsmode)
1879                 netif_stop_queue(dev);
1880
1881         if (sp->reset_current_tfd) {
1882                 sp->reset_current_tfd = 0;
1883                 entry = 0;
1884         }
1885
1886         txfd = sp->txd + entry;
1887
1888         sp->tx_buff[entry] = skb;
1889
1890         /* Clear all TFC fields, except TFDDONE. */
1891         txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
1892
1893         /* Specify the TFC field within the TFD. */
1894         txfd->tfc |= cpu_to_le64(IPG_TFC_WORDALIGNDISABLED |
1895                 (IPG_TFC_FRAMEID & sp->tx_current) |
1896                 (IPG_TFC_FRAGCOUNT & (1 << 24)));
1897         /*
1898          * 16--17 (WordAlign) <- 3 (disable),
1899          * 0--15 (FrameId) <- sp->tx_current,
1900          * 24--27 (FragCount) <- 1
1901          */
1902
1903         /* Request TxComplete interrupts at an interval defined
1904          * by the constant IPG_FRAMESBETWEENTXCOMPLETES.
1905          * Request TxComplete interrupt for every frame
1906          * if in 10Mbps mode to accomodate problem with 10Mbps
1907          * processing.
1908          */
1909         if (sp->tenmbpsmode)
1910                 txfd->tfc |= cpu_to_le64(IPG_TFC_TXINDICATE);
1911         txfd->tfc |= cpu_to_le64(IPG_TFC_TXDMAINDICATE);
1912         /* Based on compilation option, determine if FCS is to be
1913          * appended to transmit frame by IPG.
1914          */
1915         if (!(IPG_APPEND_FCS_ON_TX))
1916                 txfd->tfc |= cpu_to_le64(IPG_TFC_FCSAPPENDDISABLE);
1917
1918         /* Based on compilation option, determine if IP, TCP and/or
1919          * UDP checksums are to be added to transmit frame by IPG.
1920          */
1921         if (IPG_ADD_IPCHECKSUM_ON_TX)
1922                 txfd->tfc |= cpu_to_le64(IPG_TFC_IPCHECKSUMENABLE);
1923
1924         if (IPG_ADD_TCPCHECKSUM_ON_TX)
1925                 txfd->tfc |= cpu_to_le64(IPG_TFC_TCPCHECKSUMENABLE);
1926
1927         if (IPG_ADD_UDPCHECKSUM_ON_TX)
1928                 txfd->tfc |= cpu_to_le64(IPG_TFC_UDPCHECKSUMENABLE);
1929
1930         /* Based on compilation option, determine if VLAN tag info is to be
1931          * inserted into transmit frame by IPG.
1932          */
1933         if (IPG_INSERT_MANUAL_VLAN_TAG) {
1934                 txfd->tfc |= cpu_to_le64(IPG_TFC_VLANTAGINSERT |
1935                         ((u64) IPG_MANUAL_VLAN_VID << 32) |
1936                         ((u64) IPG_MANUAL_VLAN_CFI << 44) |
1937                         ((u64) IPG_MANUAL_VLAN_USERPRIORITY << 45));
1938         }
1939
1940         /* The fragment start location within system memory is defined
1941          * by the sk_buff structure's data field. The physical address
1942          * of this location within the system's virtual memory space
1943          * is determined using the IPG_HOST2BUS_MAP function.
1944          */
1945         txfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
1946                 skb->len, PCI_DMA_TODEVICE));
1947
1948         /* The length of the fragment within system memory is defined by
1949          * the sk_buff structure's len field.
1950          */
1951         txfd->frag_info |= cpu_to_le64(IPG_TFI_FRAGLEN &
1952                 ((u64) (skb->len & 0xffff) << 48));
1953
1954         /* Clear the TFDDone bit last to indicate the TFD is ready
1955          * for transfer to the IPG.
1956          */
1957         txfd->tfc &= cpu_to_le64(~IPG_TFC_TFDDONE);
1958
1959         spin_lock_irqsave(&sp->lock, flags);
1960
1961         sp->tx_current++;
1962
1963         mmiowb();
1964
1965         ipg_w32(IPG_DC_TX_DMA_POLL_NOW, DMA_CTRL);
1966
1967         if (sp->tx_current == (sp->tx_dirty + IPG_TFDLIST_LENGTH))
1968                 netif_stop_queue(dev);
1969
1970         spin_unlock_irqrestore(&sp->lock, flags);
1971
1972         return NETDEV_TX_OK;
1973 }
1974
1975 static void ipg_set_phy_default_param(unsigned char rev,
1976                                       struct net_device *dev, int phy_address)
1977 {
1978         unsigned short length;
1979         unsigned char revision;
1980         unsigned short *phy_param;
1981         unsigned short address, value;
1982
1983         phy_param = &DefaultPhyParam[0];
1984         length = *phy_param & 0x00FF;
1985         revision = (unsigned char)((*phy_param) >> 8);
1986         phy_param++;
1987         while (length != 0) {
1988                 if (rev == revision) {
1989                         while (length > 1) {
1990                                 address = *phy_param;
1991                                 value = *(phy_param + 1);
1992                                 phy_param += 2;
1993                                 mdio_write(dev, phy_address, address, value);
1994                                 length -= 4;
1995                         }
1996                         break;
1997                 } else {
1998                         phy_param += length / 2;
1999                         length = *phy_param & 0x00FF;
2000                         revision = (unsigned char)((*phy_param) >> 8);
2001                         phy_param++;
2002                 }
2003         }
2004 }
2005
2006 static int read_eeprom(struct net_device *dev, int eep_addr)
2007 {
2008         void __iomem *ioaddr = ipg_ioaddr(dev);
2009         unsigned int i;
2010         int ret = 0;
2011         u16 value;
2012
2013         value = IPG_EC_EEPROM_READOPCODE | (eep_addr & 0xff);
2014         ipg_w16(value, EEPROM_CTRL);
2015
2016         for (i = 0; i < 1000; i++) {
2017                 u16 data;
2018
2019                 mdelay(10);
2020                 data = ipg_r16(EEPROM_CTRL);
2021                 if (!(data & IPG_EC_EEPROM_BUSY)) {
2022                         ret = ipg_r16(EEPROM_DATA);
2023                         break;
2024                 }
2025         }
2026         return ret;
2027 }
2028
2029 static void ipg_init_mii(struct net_device *dev)
2030 {
2031         struct ipg_nic_private *sp = netdev_priv(dev);
2032         struct mii_if_info *mii_if = &sp->mii_if;
2033         int phyaddr;
2034
2035         mii_if->dev          = dev;
2036         mii_if->mdio_read    = mdio_read;
2037         mii_if->mdio_write   = mdio_write;
2038         mii_if->phy_id_mask  = 0x1f;
2039         mii_if->reg_num_mask = 0x1f;
2040
2041         mii_if->phy_id = phyaddr = ipg_find_phyaddr(dev);
2042
2043         if (phyaddr != 0x1f) {
2044                 u16 mii_phyctrl, mii_1000cr;
2045                 u8 revisionid = 0;
2046
2047                 mii_1000cr  = mdio_read(dev, phyaddr, MII_CTRL1000);
2048                 mii_1000cr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF |
2049                         GMII_PHY_1000BASETCONTROL_PreferMaster;
2050                 mdio_write(dev, phyaddr, MII_CTRL1000, mii_1000cr);
2051
2052                 mii_phyctrl = mdio_read(dev, phyaddr, MII_BMCR);
2053
2054                 /* Set default phyparam */
2055                 pci_read_config_byte(sp->pdev, PCI_REVISION_ID, &revisionid);
2056                 ipg_set_phy_default_param(revisionid, dev, phyaddr);
2057
2058                 /* Reset PHY */
2059                 mii_phyctrl |= BMCR_RESET | BMCR_ANRESTART;
2060                 mdio_write(dev, phyaddr, MII_BMCR, mii_phyctrl);
2061
2062         }
2063 }
2064
2065 static int ipg_hw_init(struct net_device *dev)
2066 {
2067         struct ipg_nic_private *sp = netdev_priv(dev);
2068         void __iomem *ioaddr = sp->ioaddr;
2069         unsigned int i;
2070         int rc;
2071
2072         /* Read/Write and Reset EEPROM Value */
2073         /* Read LED Mode Configuration from EEPROM */
2074         sp->led_mode = read_eeprom(dev, 6);
2075
2076         /* Reset all functions within the IPG. Do not assert
2077          * RST_OUT as not compatible with some PHYs.
2078          */
2079         rc = ipg_reset(dev, IPG_RESET_MASK);
2080         if (rc < 0)
2081                 goto out;
2082
2083         ipg_init_mii(dev);
2084
2085         /* Read MAC Address from EEPROM */
2086         for (i = 0; i < 3; i++)
2087                 sp->station_addr[i] = read_eeprom(dev, 16 + i);
2088
2089         for (i = 0; i < 3; i++)
2090                 ipg_w16(sp->station_addr[i], STATION_ADDRESS_0 + 2*i);
2091
2092         /* Set station address in ethernet_device structure. */
2093         dev->dev_addr[0] =  ipg_r16(STATION_ADDRESS_0) & 0x00ff;
2094         dev->dev_addr[1] = (ipg_r16(STATION_ADDRESS_0) & 0xff00) >> 8;
2095         dev->dev_addr[2] =  ipg_r16(STATION_ADDRESS_1) & 0x00ff;
2096         dev->dev_addr[3] = (ipg_r16(STATION_ADDRESS_1) & 0xff00) >> 8;
2097         dev->dev_addr[4] =  ipg_r16(STATION_ADDRESS_2) & 0x00ff;
2098         dev->dev_addr[5] = (ipg_r16(STATION_ADDRESS_2) & 0xff00) >> 8;
2099 out:
2100         return rc;
2101 }
2102
2103 static int ipg_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2104 {
2105         struct ipg_nic_private *sp = netdev_priv(dev);
2106         int rc;
2107
2108         mutex_lock(&sp->mii_mutex);
2109         rc = generic_mii_ioctl(&sp->mii_if, if_mii(ifr), cmd, NULL);
2110         mutex_unlock(&sp->mii_mutex);
2111
2112         return rc;
2113 }
2114
2115 static int ipg_nic_change_mtu(struct net_device *dev, int new_mtu)
2116 {
2117         /* Function to accomodate changes to Maximum Transfer Unit
2118          * (or MTU) of IPG NIC. Cannot use default function since
2119          * the default will not allow for MTU > 1500 bytes.
2120          */
2121
2122         IPG_DEBUG_MSG("_nic_change_mtu\n");
2123
2124         /* Check that the new MTU value is between 68 (14 byte header, 46
2125          * byte payload, 4 byte FCS) and IPG_MAX_RXFRAME_SIZE, which
2126          * corresponds to the MAXFRAMESIZE register in the IPG.
2127          */
2128         if ((new_mtu < 68) || (new_mtu > IPG_MAX_RXFRAME_SIZE))
2129                 return -EINVAL;
2130
2131         dev->mtu = new_mtu;
2132
2133         return 0;
2134 }
2135
2136 static int ipg_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2137 {
2138         struct ipg_nic_private *sp = netdev_priv(dev);
2139         int rc;
2140
2141         mutex_lock(&sp->mii_mutex);
2142         rc = mii_ethtool_gset(&sp->mii_if, cmd);
2143         mutex_unlock(&sp->mii_mutex);
2144
2145         return rc;
2146 }
2147
2148 static int ipg_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2149 {
2150         struct ipg_nic_private *sp = netdev_priv(dev);
2151         int rc;
2152
2153         mutex_lock(&sp->mii_mutex);
2154         rc = mii_ethtool_sset(&sp->mii_if, cmd);
2155         mutex_unlock(&sp->mii_mutex);
2156
2157         return rc;
2158 }
2159
2160 static int ipg_nway_reset(struct net_device *dev)
2161 {
2162         struct ipg_nic_private *sp = netdev_priv(dev);
2163         int rc;
2164
2165         mutex_lock(&sp->mii_mutex);
2166         rc = mii_nway_restart(&sp->mii_if);
2167         mutex_unlock(&sp->mii_mutex);
2168
2169         return rc;
2170 }
2171
2172 static struct ethtool_ops ipg_ethtool_ops = {
2173         .get_settings = ipg_get_settings,
2174         .set_settings = ipg_set_settings,
2175         .nway_reset   = ipg_nway_reset,
2176 };
2177
2178 static void __devexit ipg_remove(struct pci_dev *pdev)
2179 {
2180         struct net_device *dev = pci_get_drvdata(pdev);
2181         struct ipg_nic_private *sp = netdev_priv(dev);
2182
2183         IPG_DEBUG_MSG("_remove\n");
2184
2185         /* Un-register Ethernet device. */
2186         unregister_netdev(dev);
2187
2188         pci_iounmap(pdev, sp->ioaddr);
2189
2190         pci_release_regions(pdev);
2191
2192         free_netdev(dev);
2193         pci_disable_device(pdev);
2194         pci_set_drvdata(pdev, NULL);
2195 }
2196
2197 static int __devinit ipg_probe(struct pci_dev *pdev,
2198                                const struct pci_device_id *id)
2199 {
2200         unsigned int i = id->driver_data;
2201         struct ipg_nic_private *sp;
2202         struct net_device *dev;
2203         void __iomem *ioaddr;
2204         int rc;
2205
2206         rc = pci_enable_device(pdev);
2207         if (rc < 0)
2208                 goto out;
2209
2210         printk(KERN_INFO "%s: %s\n", pci_name(pdev), ipg_brand_name[i]);
2211
2212         pci_set_master(pdev);
2213
2214         rc = pci_set_dma_mask(pdev, DMA_40BIT_MASK);
2215         if (rc < 0) {
2216                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2217                 if (rc < 0) {
2218                         printk(KERN_ERR "%s: DMA config failed.\n",
2219                                pci_name(pdev));
2220                         goto err_disable_0;
2221                 }
2222         }
2223
2224         /*
2225          * Initialize net device.
2226          */
2227         dev = alloc_etherdev(sizeof(struct ipg_nic_private));
2228         if (!dev) {
2229                 printk(KERN_ERR "%s: alloc_etherdev failed\n", pci_name(pdev));
2230                 rc = -ENOMEM;
2231                 goto err_disable_0;
2232         }
2233
2234         sp = netdev_priv(dev);
2235         spin_lock_init(&sp->lock);
2236         mutex_init(&sp->mii_mutex);
2237
2238         sp->is_jumbo = IPG_JUMBO;
2239         sp->rxfrag_size = IPG_RXFRAG_SIZE;
2240
2241         /* Declare IPG NIC functions for Ethernet device methods.
2242          */
2243         dev->open = &ipg_nic_open;
2244         dev->stop = &ipg_nic_stop;
2245         dev->hard_start_xmit = &ipg_nic_hard_start_xmit;
2246         dev->get_stats = &ipg_nic_get_stats;
2247         dev->set_multicast_list = &ipg_nic_set_multicast_list;
2248         dev->do_ioctl = ipg_ioctl;
2249         dev->tx_timeout = ipg_tx_timeout;
2250         dev->change_mtu = &ipg_nic_change_mtu;
2251
2252         SET_NETDEV_DEV(dev, &pdev->dev);
2253         SET_ETHTOOL_OPS(dev, &ipg_ethtool_ops);
2254
2255         rc = pci_request_regions(pdev, DRV_NAME);
2256         if (rc)
2257                 goto err_free_dev_1;
2258
2259         ioaddr = pci_iomap(pdev, 1, pci_resource_len(pdev, 1));
2260         if (!ioaddr) {
2261                 printk(KERN_ERR "%s cannot map MMIO\n", pci_name(pdev));
2262                 rc = -EIO;
2263                 goto err_release_regions_2;
2264         }
2265
2266         /* Save the pointer to the PCI device information. */
2267         sp->ioaddr = ioaddr;
2268         sp->pdev = pdev;
2269         sp->dev = dev;
2270
2271         INIT_DELAYED_WORK(&sp->task, ipg_reset_after_host_error);
2272
2273         pci_set_drvdata(pdev, dev);
2274
2275         rc = ipg_hw_init(dev);
2276         if (rc < 0)
2277                 goto err_unmap_3;
2278
2279         rc = register_netdev(dev);
2280         if (rc < 0)
2281                 goto err_unmap_3;
2282
2283         printk(KERN_INFO "Ethernet device registered as: %s\n", dev->name);
2284 out:
2285         return rc;
2286
2287 err_unmap_3:
2288         pci_iounmap(pdev, ioaddr);
2289 err_release_regions_2:
2290         pci_release_regions(pdev);
2291 err_free_dev_1:
2292         free_netdev(dev);
2293 err_disable_0:
2294         pci_disable_device(pdev);
2295         goto out;
2296 }
2297
2298 static struct pci_driver ipg_pci_driver = {
2299         .name           = IPG_DRIVER_NAME,
2300         .id_table       = ipg_pci_tbl,
2301         .probe          = ipg_probe,
2302         .remove         = __devexit_p(ipg_remove),
2303 };
2304
2305 static int __init ipg_init_module(void)
2306 {
2307         return pci_register_driver(&ipg_pci_driver);
2308 }
2309
2310 static void __exit ipg_exit_module(void)
2311 {
2312         pci_unregister_driver(&ipg_pci_driver);
2313 }
2314
2315 module_init(ipg_init_module);
2316 module_exit(ipg_exit_module);