git.oblomov.eu Git - linux-2.6/blob - drivers/media/video/cx18/cx18-firmware.c

   1 /*
   2  *  cx18 firmware functions
   3  *
   4  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  19  *  02111-1307  USA
  20  */
  21
  22 #include "cx18-driver.h"
  23 #include "cx18-io.h"
  24 #include "cx18-scb.h"
  25 #include "cx18-irq.h"
  26 #include "cx18-firmware.h"
  27 #include "cx18-cards.h"
  28 #include <linux/firmware.h>
  29
  30 #define CX18_PROC_SOFT_RESET            0xc70010
  31 #define CX18_DDR_SOFT_RESET             0xc70014
  32 #define CX18_CLOCK_SELECT1              0xc71000
  33 #define CX18_CLOCK_SELECT2              0xc71004
  34 #define CX18_HALF_CLOCK_SELECT1         0xc71008
  35 #define CX18_HALF_CLOCK_SELECT2         0xc7100C
  36 #define CX18_CLOCK_POLARITY1            0xc71010
  37 #define CX18_CLOCK_POLARITY2            0xc71014
  38 #define CX18_ADD_DELAY_ENABLE1          0xc71018
  39 #define CX18_ADD_DELAY_ENABLE2          0xc7101C
  40 #define CX18_CLOCK_ENABLE1              0xc71020
  41 #define CX18_CLOCK_ENABLE2              0xc71024
  42
  43 #define CX18_REG_BUS_TIMEOUT_EN         0xc72024
  44
  45 #define CX18_FAST_CLOCK_PLL_INT         0xc78000
  46 #define CX18_FAST_CLOCK_PLL_FRAC        0xc78004
  47 #define CX18_FAST_CLOCK_PLL_POST        0xc78008
  48 #define CX18_FAST_CLOCK_PLL_PRESCALE    0xc7800C
  49 #define CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH 0xc78010
  50
  51 #define CX18_SLOW_CLOCK_PLL_INT         0xc78014
  52 #define CX18_SLOW_CLOCK_PLL_FRAC        0xc78018
  53 #define CX18_SLOW_CLOCK_PLL_POST        0xc7801C
  54 #define CX18_MPEG_CLOCK_PLL_INT         0xc78040
  55 #define CX18_MPEG_CLOCK_PLL_FRAC        0xc78044
  56 #define CX18_MPEG_CLOCK_PLL_POST        0xc78048
  57 #define CX18_PLL_POWER_DOWN             0xc78088
  58 #define CX18_SW1_INT_STATUS             0xc73104
  59 #define CX18_SW1_INT_ENABLE_PCI         0xc7311C
  60 #define CX18_SW2_INT_SET                0xc73140
  61 #define CX18_SW2_INT_STATUS             0xc73144
  62 #define CX18_ADEC_CONTROL               0xc78120
  63
  64 #define CX18_DDR_REQUEST_ENABLE         0xc80000
  65 #define CX18_DDR_CHIP_CONFIG            0xc80004
  66 #define CX18_DDR_REFRESH                0xc80008
  67 #define CX18_DDR_TIMING1                0xc8000C
  68 #define CX18_DDR_TIMING2                0xc80010
  69 #define CX18_DDR_POWER_REG              0xc8001C
  70
  71 #define CX18_DDR_TUNE_LANE              0xc80048
  72 #define CX18_DDR_INITIAL_EMRS           0xc80054
  73 #define CX18_DDR_MB_PER_ROW_7           0xc8009C
  74 #define CX18_DDR_BASE_63_ADDR           0xc804FC
  75
  76 #define CX18_WMB_CLIENT02               0xc90108
  77 #define CX18_WMB_CLIENT05               0xc90114
  78 #define CX18_WMB_CLIENT06               0xc90118
  79 #define CX18_WMB_CLIENT07               0xc9011C
  80 #define CX18_WMB_CLIENT08               0xc90120
  81 #define CX18_WMB_CLIENT09               0xc90124
  82 #define CX18_WMB_CLIENT10               0xc90128
  83 #define CX18_WMB_CLIENT11               0xc9012C
  84 #define CX18_WMB_CLIENT12               0xc90130
  85 #define CX18_WMB_CLIENT13               0xc90134
  86 #define CX18_WMB_CLIENT14               0xc90138
  87
  88 #define CX18_DSP0_INTERRUPT_MASK        0xd0004C
  89
  90 #define APU_ROM_SYNC1 0x6D676553 /* "mgeS" */
  91 #define APU_ROM_SYNC2 0x72646548 /* "rdeH" */
  92
  93 struct cx18_apu_rom_seghdr {
  94         u32 sync1;
  95         u32 sync2;
  96         u32 addr;
  97         u32 size;
  98 };
  99
 100 static int load_cpu_fw_direct(const char *fn, u8 __iomem *mem, struct cx18 *cx)
 101 {
 102         const struct firmware *fw = NULL;
 103         int i, j;
 104         unsigned size;
 105         u32 __iomem *dst = (u32 __iomem *)mem;
 106         const u32 *src;
 107
 108         if (request_firmware(&fw, fn, &cx->dev->dev)) {
 109                 CX18_ERR("Unable to open firmware %s\n", fn);
 110                 CX18_ERR("Did you put the firmware in the hotplug firmware directory?\n");
 111                 return -ENOMEM;
 112         }
 113
 114         src = (const u32 *)fw->data;
 115
 116         for (i = 0; i < fw->size; i += 4096) {
 117                 cx18_setup_page(cx, i);
 118                 for (j = i; j < fw->size && j < i + 4096; j += 4) {
 119                         /* no need for endianness conversion on the ppc */
 120                         cx18_raw_writel(cx, *src, dst);
 121                         if (cx18_raw_readl(cx, dst) != *src) {
 122                                 CX18_ERR("Mismatch at offset %x\n", i);
 123                                 release_firmware(fw);
 124                                 cx18_setup_page(cx, 0);
 125                                 return -EIO;
 126                         }
 127                         dst++;
 128                         src++;
 129                 }
 130         }
 131         if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))
 132                 CX18_INFO("loaded %s firmware (%zd bytes)\n", fn, fw->size);
 133         size = fw->size;
 134         release_firmware(fw);
 135         cx18_setup_page(cx, SCB_OFFSET);
 136         return size;
 137 }
 138
 139 static int load_apu_fw_direct(const char *fn, u8 __iomem *dst, struct cx18 *cx,
 140                                 u32 *entry_addr)
 141 {
 142         const struct firmware *fw = NULL;
 143         int i, j;
 144         unsigned size;
 145         const u32 *src;
 146         struct cx18_apu_rom_seghdr seghdr;
 147         const u8 *vers;
 148         u32 offset = 0;
 149         u32 apu_version = 0;
 150         int sz;
 151
 152         if (request_firmware(&fw, fn, &cx->dev->dev)) {
 153                 CX18_ERR("unable to open firmware %s\n", fn);
 154                 CX18_ERR("did you put the firmware in the hotplug firmware directory?\n");
 155                 cx18_setup_page(cx, 0);
 156                 return -ENOMEM;
 157         }
 158
 159         *entry_addr = 0;
 160         src = (const u32 *)fw->data;
 161         vers = fw->data + sizeof(seghdr);
 162         sz = fw->size;
 163
 164         apu_version = (vers[0] << 24) | (vers[4] << 16) | vers[32];
 165         while (offset + sizeof(seghdr) < fw->size) {
 166                 /* TODO: byteswapping */
 167                 memcpy(&seghdr, src + offset / 4, sizeof(seghdr));
 168                 offset += sizeof(seghdr);
 169                 if (seghdr.sync1 != APU_ROM_SYNC1 ||
 170                     seghdr.sync2 != APU_ROM_SYNC2) {
 171                         offset += seghdr.size;
 172                         continue;
 173                 }
 174                 CX18_DEBUG_INFO("load segment %x-%x\n", seghdr.addr,
 175                                 seghdr.addr + seghdr.size - 1);
 176                 if (*entry_addr == 0)
 177                         *entry_addr = seghdr.addr;
 178                 if (offset + seghdr.size > sz)
 179                         break;
 180                 for (i = 0; i < seghdr.size; i += 4096) {
 181                         cx18_setup_page(cx, seghdr.addr + i);
 182                         for (j = i; j < seghdr.size && j < i + 4096; j += 4) {
 183                                 /* no need for endianness conversion on the ppc */
 184                                 cx18_raw_writel(cx, src[(offset + j) / 4],
 185                                                 dst + seghdr.addr + j);
 186                                 if (cx18_raw_readl(cx, dst + seghdr.addr + j)
 187                                     != src[(offset + j) / 4]) {
 188                                         CX18_ERR("Mismatch at offset %x\n",
 189                                                  offset + j);
 190                                         release_firmware(fw);
 191                                         cx18_setup_page(cx, 0);
 192                                         return -EIO;
 193                                 }
 194                         }
 195                 }
 196                 offset += seghdr.size;
 197         }
 198         if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))
 199                 CX18_INFO("loaded %s firmware V%08x (%zd bytes)\n",
 200                                 fn, apu_version, fw->size);
 201         size = fw->size;
 202         release_firmware(fw);
 203         cx18_setup_page(cx, 0);
 204         return size;
 205 }
 206
 207 void cx18_halt_firmware(struct cx18 *cx)
 208 {
 209         CX18_DEBUG_INFO("Preparing for firmware halt.\n");
 210         cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET,
 211                                   0x0000000F, 0x000F000F);
 212         cx18_write_reg_expect(cx, 0x00020002, CX18_ADEC_CONTROL,
 213                                   0x00000002, 0x00020002);
 214 }
 215
 216 void cx18_init_power(struct cx18 *cx, int lowpwr)
 217 {
 218         /* power-down Spare and AOM PLLs */
 219         /* power-up fast, slow and mpeg PLLs */
 220         cx18_write_reg(cx, 0x00000008, CX18_PLL_POWER_DOWN);
 221
 222         /* ADEC out of sleep */
 223         cx18_write_reg_expect(cx, 0x00020000, CX18_ADEC_CONTROL,
 224                                   0x00000000, 0x00020002);
 225
 226         /* The fast clock is at 200/245 MHz */
 227         cx18_write_reg(cx, lowpwr ? 0xD : 0x11, CX18_FAST_CLOCK_PLL_INT);
 228         cx18_write_reg(cx, lowpwr ? 0x1EFBF37 : 0x038E3D7,
 229                                                 CX18_FAST_CLOCK_PLL_FRAC);
 230
 231         cx18_write_reg(cx, 2, CX18_FAST_CLOCK_PLL_POST);
 232         cx18_write_reg(cx, 1, CX18_FAST_CLOCK_PLL_PRESCALE);
 233         cx18_write_reg(cx, 4, CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH);
 234
 235         /* set slow clock to 125/120 MHz */
 236         cx18_write_reg(cx, lowpwr ? 0x11 : 0x10, CX18_SLOW_CLOCK_PLL_INT);
 237         cx18_write_reg(cx, lowpwr ? 0xEBAF05 : 0x18618A8,
 238                                                 CX18_SLOW_CLOCK_PLL_FRAC);
 239         cx18_write_reg(cx, 4, CX18_SLOW_CLOCK_PLL_POST);
 240
 241         /* mpeg clock pll 54MHz */
 242         cx18_write_reg(cx, 0xF, CX18_MPEG_CLOCK_PLL_INT);
 243         cx18_write_reg(cx, 0x2BCFEF, CX18_MPEG_CLOCK_PLL_FRAC);
 244         cx18_write_reg(cx, 8, CX18_MPEG_CLOCK_PLL_POST);
 245
 246         /* Defaults */
 247         /* APU = SC or SC/2 = 125/62.5 */
 248         /* EPU = SC = 125 */
 249         /* DDR = FC = 180 */
 250         /* ENC = SC = 125 */
 251         /* AI1 = SC = 125 */
 252         /* VIM2 = disabled */
 253         /* PCI = FC/2 = 90 */
 254         /* AI2 = disabled */
 255         /* DEMUX = disabled */
 256         /* AO = SC/2 = 62.5 */
 257         /* SER = 54MHz */
 258         /* VFC = disabled */
 259         /* USB = disabled */
 260
 261         if (lowpwr) {
 262                 cx18_write_reg_expect(cx, 0xFFFF0020, CX18_CLOCK_SELECT1,
 263                                           0x00000020, 0xFFFFFFFF);
 264                 cx18_write_reg_expect(cx, 0xFFFF0004, CX18_CLOCK_SELECT2,
 265                                           0x00000004, 0xFFFFFFFF);
 266         } else {
 267                 /* This doesn't explicitly set every clock select */
 268                 cx18_write_reg_expect(cx, 0x00060004, CX18_CLOCK_SELECT1,
 269                                           0x00000004, 0x00060006);
 270                 cx18_write_reg_expect(cx, 0x00060006, CX18_CLOCK_SELECT2,
 271                                           0x00000006, 0x00060006);
 272         }
 273
 274         cx18_write_reg_expect(cx, 0xFFFF0002, CX18_HALF_CLOCK_SELECT1,
 275                                   0x00000002, 0xFFFFFFFF);
 276         cx18_write_reg_expect(cx, 0xFFFF0104, CX18_HALF_CLOCK_SELECT2,
 277                                   0x00000104, 0xFFFFFFFF);
 278         cx18_write_reg_expect(cx, 0xFFFF9026, CX18_CLOCK_ENABLE1,
 279                                   0x00009026, 0xFFFFFFFF);
 280         cx18_write_reg_expect(cx, 0xFFFF3105, CX18_CLOCK_ENABLE2,
 281                                   0x00003105, 0xFFFFFFFF);
 282 }
 283
 284 void cx18_init_memory(struct cx18 *cx)
 285 {
 286         cx18_msleep_timeout(10, 0);
 287         cx18_write_reg_expect(cx, 0x00010000, CX18_DDR_SOFT_RESET,
 288                                   0x00000000, 0x00010001);
 289         cx18_msleep_timeout(10, 0);
 290
 291         cx18_write_reg(cx, cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG);
 292
 293         cx18_msleep_timeout(10, 0);
 294
 295         cx18_write_reg(cx, cx->card->ddr.refresh, CX18_DDR_REFRESH);
 296         cx18_write_reg(cx, cx->card->ddr.timing1, CX18_DDR_TIMING1);
 297         cx18_write_reg(cx, cx->card->ddr.timing2, CX18_DDR_TIMING2);
 298
 299         cx18_msleep_timeout(10, 0);
 300
 301         /* Initialize DQS pad time */
 302         cx18_write_reg(cx, cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE);
 303         cx18_write_reg(cx, cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS);
 304
 305         cx18_msleep_timeout(10, 0);
 306
 307         cx18_write_reg_expect(cx, 0x00020000, CX18_DDR_SOFT_RESET,
 308                                   0x00000000, 0x00020002);
 309         cx18_msleep_timeout(10, 0);
 310
 311         /* use power-down mode when idle */
 312         cx18_write_reg(cx, 0x00000010, CX18_DDR_POWER_REG);
 313
 314         cx18_write_reg_expect(cx, 0x00010001, CX18_REG_BUS_TIMEOUT_EN,
 315                                   0x00000001, 0x00010001);
 316
 317         cx18_write_reg(cx, 0x48, CX18_DDR_MB_PER_ROW_7);
 318         cx18_write_reg(cx, 0xE0000, CX18_DDR_BASE_63_ADDR);
 319
 320         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT02);  /* AO */
 321         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT09);  /* AI2 */
 322         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT05);  /* VIM1 */
 323         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT06);  /* AI1 */
 324         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT07);  /* 3D comb */
 325         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT10);  /* ME */
 326         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT12);  /* ENC */
 327         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT13);  /* PK */
 328         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT11);  /* RC */
 329         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT14);  /* AVO */
 330 }
 331
 332 int cx18_firmware_init(struct cx18 *cx)
 333 {
 334         /* Allow chip to control CLKRUN */
 335         cx18_write_reg(cx, 0x5, CX18_DSP0_INTERRUPT_MASK);
 336
 337         /* Stop the firmware */
 338         cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET,
 339                                   0x0000000F, 0x000F000F);
 340
 341         cx18_msleep_timeout(1, 0);
 342
 343         cx18_sw1_irq_enable(cx, IRQ_CPU_TO_EPU | IRQ_APU_TO_EPU);
 344         cx18_sw2_irq_enable(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK);
 345
 346         /* Only if the processor is not running */
 347         if (cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 8) {
 348                 u32 fw_entry_addr = 0;
 349                 int sz = load_apu_fw_direct("v4l-cx23418-apu.fw",
 350                                cx->enc_mem, cx, &fw_entry_addr);
 351
 352                 if (sz <= 0)
 353                         return sz;
 354
 355                 /* Clear bit0 for APU to start from 0 */
 356                 cx18_write_reg(cx, cx18_read_reg(cx, 0xc72030) & ~1, 0xc72030);
 357
 358                 cx18_write_enc(cx, 0xE51FF004, 0);    /* ldr pc, [pc, #-4] */
 359                 cx18_write_enc(cx, fw_entry_addr, 4);
 360
 361                 /* Start APU */
 362                 cx18_write_reg_expect(cx, 0x00010000, CX18_PROC_SOFT_RESET,
 363                                           0x00000000, 0x00010001);
 364                 cx18_msleep_timeout(500, 0);
 365
 366                 sz = sz <= 0 ? sz : load_cpu_fw_direct("v4l-cx23418-cpu.fw",
 367                                         cx->enc_mem, cx);
 368
 369                 if (sz > 0) {
 370                         int retries = 0;
 371
 372                         /* start the CPU */
 373                         cx18_write_reg_expect(cx,
 374                                               0x00080000, CX18_PROC_SOFT_RESET,
 375                                               0x00000000, 0x00080008);
 376                         while (retries++ < 50) { /* Loop for max 500mS */
 377                                 if ((cx18_read_reg(cx, CX18_PROC_SOFT_RESET)
 378                                      & 1) == 0)
 379                                         break;
 380                                 cx18_msleep_timeout(10, 0);
 381                         }
 382                         cx18_msleep_timeout(200, 0);
 383                         if (retries == 51) {
 384                                 CX18_ERR("Could not start the CPU\n");
 385                                 return -EIO;
 386                         }
 387                 }
 388                 if (sz <= 0)
 389                         return -EIO;
 390         }
 391
 392         /*
 393          * The CPU firmware apparently sets up to receive an interrupt for it's
 394          * outgoing IRQ_CPU_TO_EPU_ACK to us (*boggle*).  We get an interrupt
 395          * when it sends us an ack, but by the time we process it, that flag in
 396          * the SW2 status register has been cleared by the CPU firmware.
 397          * We'll prevent that not so useful behavior by clearing the CPU's
 398          * interrupt enables for Ack IRQ's we want to process.
 399          */
 400         cx18_sw2_irq_disable_cpu(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK);
 401
 402         /* initialize GPIO */
 403         cx18_write_reg_expect(cx, 0x14001400, 0xc78110, 0x00001400, 0x14001400);
 404         return 0;
 405 }