git.oblomov.eu Git - linux-2.6/blob - arch/ppc/syslib/mv64x60.c

   1 /*
   2  * arch/ppc/syslib/mv64x60.c
   3  *
   4  * Common routines for the Marvell/Galileo Discovery line of host bridges
   5  * (gt64260, mv64360, mv64460, ...).
   6  *
   7  * Author: Mark A. Greer <mgreer@mvista.com>
   8  *
   9  * 2004 (c) MontaVista, Software, Inc.  This file is licensed under
  10  * the terms of the GNU General Public License version 2.  This program
  11  * is licensed "as is" without any warranty of any kind, whether express
  12  * or implied.
  13  */
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/pci.h>
  17 #include <linux/slab.h>
  18 #include <linux/module.h>
  19 #include <linux/string.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/mv643xx.h>
  22 #include <linux/platform_device.h>
  23
  24 #include <asm/byteorder.h>
  25 #include <asm/io.h>
  26 #include <asm/irq.h>
  27 #include <asm/uaccess.h>
  28 #include <asm/machdep.h>
  29 #include <asm/pci-bridge.h>
  30 #include <asm/delay.h>
  31 #include <asm/mv64x60.h>
  32
  33
  34 u8 mv64x60_pci_exclude_bridge = 1;
  35 DEFINE_SPINLOCK(mv64x60_lock);
  36
  37 static phys_addr_t      mv64x60_bridge_pbase;
  38 static void             __iomem *mv64x60_bridge_vbase;
  39 static u32              mv64x60_bridge_type = MV64x60_TYPE_INVALID;
  40 static u32              mv64x60_bridge_rev;
  41 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
  42 static struct pci_controller    sysfs_hose_a;
  43 #endif
  44
  45 static u32 gt64260_translate_size(u32 base, u32 size, u32 num_bits);
  46 static u32 gt64260_untranslate_size(u32 base, u32 size, u32 num_bits);
  47 static void gt64260_set_pci2mem_window(struct pci_controller *hose, u32 bus,
  48         u32 window, u32 base);
  49 static void gt64260_set_pci2regs_window(struct mv64x60_handle *bh,
  50         struct pci_controller *hose, u32 bus, u32 base);
  51 static u32 gt64260_is_enabled_32bit(struct mv64x60_handle *bh, u32 window);
  52 static void gt64260_enable_window_32bit(struct mv64x60_handle *bh, u32 window);
  53 static void gt64260_disable_window_32bit(struct mv64x60_handle *bh, u32 window);
  54 static void gt64260_enable_window_64bit(struct mv64x60_handle *bh, u32 window);
  55 static void gt64260_disable_window_64bit(struct mv64x60_handle *bh, u32 window);
  56 static void gt64260_disable_all_windows(struct mv64x60_handle *bh,
  57         struct mv64x60_setup_info *si);
  58 static void gt64260a_chip_specific_init(struct mv64x60_handle *bh,
  59         struct mv64x60_setup_info *si);
  60 static void gt64260b_chip_specific_init(struct mv64x60_handle *bh,
  61         struct mv64x60_setup_info *si);
  62
  63 static u32 mv64360_translate_size(u32 base, u32 size, u32 num_bits);
  64 static u32 mv64360_untranslate_size(u32 base, u32 size, u32 num_bits);
  65 static void mv64360_set_pci2mem_window(struct pci_controller *hose, u32 bus,
  66         u32 window, u32 base);
  67 static void mv64360_set_pci2regs_window(struct mv64x60_handle *bh,
  68         struct pci_controller *hose, u32 bus, u32 base);
  69 static u32 mv64360_is_enabled_32bit(struct mv64x60_handle *bh, u32 window);
  70 static void mv64360_enable_window_32bit(struct mv64x60_handle *bh, u32 window);
  71 static void mv64360_disable_window_32bit(struct mv64x60_handle *bh, u32 window);
  72 static void mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window);
  73 static void mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window);
  74 static void mv64360_disable_all_windows(struct mv64x60_handle *bh,
  75         struct mv64x60_setup_info *si);
  76 static void mv64360_config_io2mem_windows(struct mv64x60_handle *bh,
  77         struct mv64x60_setup_info *si,
  78         u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
  79 static void mv64360_set_mpsc2regs_window(struct mv64x60_handle *bh, u32 base);
  80 static void mv64360_chip_specific_init(struct mv64x60_handle *bh,
  81         struct mv64x60_setup_info *si);
  82 static void mv64460_chip_specific_init(struct mv64x60_handle *bh,
  83         struct mv64x60_setup_info *si);
  84
  85
  86 /*
  87  * Define tables that have the chip-specific info for each type of
  88  * Marvell bridge chip.
  89  */
  90 static struct mv64x60_chip_info gt64260a_ci __initdata = { /* GT64260A */
  91         .translate_size         = gt64260_translate_size,
  92         .untranslate_size       = gt64260_untranslate_size,
  93         .set_pci2mem_window     = gt64260_set_pci2mem_window,
  94         .set_pci2regs_window    = gt64260_set_pci2regs_window,
  95         .is_enabled_32bit       = gt64260_is_enabled_32bit,
  96         .enable_window_32bit    = gt64260_enable_window_32bit,
  97         .disable_window_32bit   = gt64260_disable_window_32bit,
  98         .enable_window_64bit    = gt64260_enable_window_64bit,
  99         .disable_window_64bit   = gt64260_disable_window_64bit,
 100         .disable_all_windows    = gt64260_disable_all_windows,
 101         .chip_specific_init     = gt64260a_chip_specific_init,
 102         .window_tab_32bit       = gt64260_32bit_windows,
 103         .window_tab_64bit       = gt64260_64bit_windows,
 104 };
 105
 106 static struct mv64x60_chip_info gt64260b_ci __initdata = { /* GT64260B */
 107         .translate_size         = gt64260_translate_size,
 108         .untranslate_size       = gt64260_untranslate_size,
 109         .set_pci2mem_window     = gt64260_set_pci2mem_window,
 110         .set_pci2regs_window    = gt64260_set_pci2regs_window,
 111         .is_enabled_32bit       = gt64260_is_enabled_32bit,
 112         .enable_window_32bit    = gt64260_enable_window_32bit,
 113         .disable_window_32bit   = gt64260_disable_window_32bit,
 114         .enable_window_64bit    = gt64260_enable_window_64bit,
 115         .disable_window_64bit   = gt64260_disable_window_64bit,
 116         .disable_all_windows    = gt64260_disable_all_windows,
 117         .chip_specific_init     = gt64260b_chip_specific_init,
 118         .window_tab_32bit       = gt64260_32bit_windows,
 119         .window_tab_64bit       = gt64260_64bit_windows,
 120 };
 121
 122 static struct mv64x60_chip_info mv64360_ci __initdata = { /* MV64360 */
 123         .translate_size         = mv64360_translate_size,
 124         .untranslate_size       = mv64360_untranslate_size,
 125         .set_pci2mem_window     = mv64360_set_pci2mem_window,
 126         .set_pci2regs_window    = mv64360_set_pci2regs_window,
 127         .is_enabled_32bit       = mv64360_is_enabled_32bit,
 128         .enable_window_32bit    = mv64360_enable_window_32bit,
 129         .disable_window_32bit   = mv64360_disable_window_32bit,
 130         .enable_window_64bit    = mv64360_enable_window_64bit,
 131         .disable_window_64bit   = mv64360_disable_window_64bit,
 132         .disable_all_windows    = mv64360_disable_all_windows,
 133         .config_io2mem_windows  = mv64360_config_io2mem_windows,
 134         .set_mpsc2regs_window   = mv64360_set_mpsc2regs_window,
 135         .chip_specific_init     = mv64360_chip_specific_init,
 136         .window_tab_32bit       = mv64360_32bit_windows,
 137         .window_tab_64bit       = mv64360_64bit_windows,
 138 };
 139
 140 static struct mv64x60_chip_info mv64460_ci __initdata = { /* MV64460 */
 141         .translate_size         = mv64360_translate_size,
 142         .untranslate_size       = mv64360_untranslate_size,
 143         .set_pci2mem_window     = mv64360_set_pci2mem_window,
 144         .set_pci2regs_window    = mv64360_set_pci2regs_window,
 145         .is_enabled_32bit       = mv64360_is_enabled_32bit,
 146         .enable_window_32bit    = mv64360_enable_window_32bit,
 147         .disable_window_32bit   = mv64360_disable_window_32bit,
 148         .enable_window_64bit    = mv64360_enable_window_64bit,
 149         .disable_window_64bit   = mv64360_disable_window_64bit,
 150         .disable_all_windows    = mv64360_disable_all_windows,
 151         .config_io2mem_windows  = mv64360_config_io2mem_windows,
 152         .set_mpsc2regs_window   = mv64360_set_mpsc2regs_window,
 153         .chip_specific_init     = mv64460_chip_specific_init,
 154         .window_tab_32bit       = mv64360_32bit_windows,
 155         .window_tab_64bit       = mv64360_64bit_windows,
 156 };
 157
 158 /*
 159  *****************************************************************************
 160  *
 161  *      Platform Device Definitions
 162  *
 163  *****************************************************************************
 164  */
 165 #ifdef CONFIG_SERIAL_MPSC
 166 static struct mpsc_shared_pdata mv64x60_mpsc_shared_pdata = {
 167         .mrr_val                = 0x3ffffe38,
 168         .rcrr_val               = 0,
 169         .tcrr_val               = 0,
 170         .intr_cause_val         = 0,
 171         .intr_mask_val          = 0,
 172 };
 173
 174 static struct resource mv64x60_mpsc_shared_resources[] = {
 175         /* Do not change the order of the IORESOURCE_MEM resources */
 176         [0] = {
 177                 .name   = "mpsc routing base",
 178                 .start  = MV64x60_MPSC_ROUTING_OFFSET,
 179                 .end    = MV64x60_MPSC_ROUTING_OFFSET +
 180                         MPSC_ROUTING_REG_BLOCK_SIZE - 1,
 181                 .flags  = IORESOURCE_MEM,
 182         },
 183         [1] = {
 184                 .name   = "sdma intr base",
 185                 .start  = MV64x60_SDMA_INTR_OFFSET,
 186                 .end    = MV64x60_SDMA_INTR_OFFSET +
 187                         MPSC_SDMA_INTR_REG_BLOCK_SIZE - 1,
 188                 .flags  = IORESOURCE_MEM,
 189         },
 190 };
 191
 192 static struct platform_device mpsc_shared_device = { /* Shared device */
 193         .name           = MPSC_SHARED_NAME,
 194         .id             = 0,
 195         .num_resources  = ARRAY_SIZE(mv64x60_mpsc_shared_resources),
 196         .resource       = mv64x60_mpsc_shared_resources,
 197         .dev = {
 198                 .platform_data = &mv64x60_mpsc_shared_pdata,
 199         },
 200 };
 201
 202 static struct mpsc_pdata mv64x60_mpsc0_pdata = {
 203         .mirror_regs            = 0,
 204         .cache_mgmt             = 0,
 205         .max_idle               = 0,
 206         .default_baud           = 9600,
 207         .default_bits           = 8,
 208         .default_parity         = 'n',
 209         .default_flow           = 'n',
 210         .chr_1_val              = 0x00000000,
 211         .chr_2_val              = 0x00000000,
 212         .chr_10_val             = 0x00000003,
 213         .mpcr_val               = 0,
 214         .bcr_val                = 0,
 215         .brg_can_tune           = 0,
 216         .brg_clk_src            = 8,            /* Default to TCLK */
 217         .brg_clk_freq           = 100000000,    /* Default to 100 MHz */
 218 };
 219
 220 static struct resource mv64x60_mpsc0_resources[] = {
 221         /* Do not change the order of the IORESOURCE_MEM resources */
 222         [0] = {
 223                 .name   = "mpsc 0 base",
 224                 .start  = MV64x60_MPSC_0_OFFSET,
 225                 .end    = MV64x60_MPSC_0_OFFSET + MPSC_REG_BLOCK_SIZE - 1,
 226                 .flags  = IORESOURCE_MEM,
 227         },
 228         [1] = {
 229                 .name   = "sdma 0 base",
 230                 .start  = MV64x60_SDMA_0_OFFSET,
 231                 .end    = MV64x60_SDMA_0_OFFSET + MPSC_SDMA_REG_BLOCK_SIZE - 1,
 232                 .flags  = IORESOURCE_MEM,
 233         },
 234         [2] = {
 235                 .name   = "brg 0 base",
 236                 .start  = MV64x60_BRG_0_OFFSET,
 237                 .end    = MV64x60_BRG_0_OFFSET + MPSC_BRG_REG_BLOCK_SIZE - 1,
 238                 .flags  = IORESOURCE_MEM,
 239         },
 240         [3] = {
 241                 .name   = "sdma 0 irq",
 242                 .start  = MV64x60_IRQ_SDMA_0,
 243                 .end    = MV64x60_IRQ_SDMA_0,
 244                 .flags  = IORESOURCE_IRQ,
 245         },
 246 };
 247
 248 static struct platform_device mpsc0_device = {
 249         .name           = MPSC_CTLR_NAME,
 250         .id             = 0,
 251         .num_resources  = ARRAY_SIZE(mv64x60_mpsc0_resources),
 252         .resource       = mv64x60_mpsc0_resources,
 253         .dev = {
 254                 .platform_data = &mv64x60_mpsc0_pdata,
 255         },
 256 };
 257
 258 static struct mpsc_pdata mv64x60_mpsc1_pdata = {
 259         .mirror_regs            = 0,
 260         .cache_mgmt             = 0,
 261         .max_idle               = 0,
 262         .default_baud           = 9600,
 263         .default_bits           = 8,
 264         .default_parity         = 'n',
 265         .default_flow           = 'n',
 266         .chr_1_val              = 0x00000000,
 267         .chr_1_val              = 0x00000000,
 268         .chr_2_val              = 0x00000000,
 269         .chr_10_val             = 0x00000003,
 270         .mpcr_val               = 0,
 271         .bcr_val                = 0,
 272         .brg_can_tune           = 0,
 273         .brg_clk_src            = 8,            /* Default to TCLK */
 274         .brg_clk_freq           = 100000000,    /* Default to 100 MHz */
 275 };
 276
 277 static struct resource mv64x60_mpsc1_resources[] = {
 278         /* Do not change the order of the IORESOURCE_MEM resources */
 279         [0] = {
 280                 .name   = "mpsc 1 base",
 281                 .start  = MV64x60_MPSC_1_OFFSET,
 282                 .end    = MV64x60_MPSC_1_OFFSET + MPSC_REG_BLOCK_SIZE - 1,
 283                 .flags  = IORESOURCE_MEM,
 284         },
 285         [1] = {
 286                 .name   = "sdma 1 base",
 287                 .start  = MV64x60_SDMA_1_OFFSET,
 288                 .end    = MV64x60_SDMA_1_OFFSET + MPSC_SDMA_REG_BLOCK_SIZE - 1,
 289                 .flags  = IORESOURCE_MEM,
 290         },
 291         [2] = {
 292                 .name   = "brg 1 base",
 293                 .start  = MV64x60_BRG_1_OFFSET,
 294                 .end    = MV64x60_BRG_1_OFFSET + MPSC_BRG_REG_BLOCK_SIZE - 1,
 295                 .flags  = IORESOURCE_MEM,
 296         },
 297         [3] = {
 298                 .name   = "sdma 1 irq",
 299                 .start  = MV64360_IRQ_SDMA_1,
 300                 .end    = MV64360_IRQ_SDMA_1,
 301                 .flags  = IORESOURCE_IRQ,
 302         },
 303 };
 304
 305 static struct platform_device mpsc1_device = {
 306         .name           = MPSC_CTLR_NAME,
 307         .id             = 1,
 308         .num_resources  = ARRAY_SIZE(mv64x60_mpsc1_resources),
 309         .resource       = mv64x60_mpsc1_resources,
 310         .dev = {
 311                 .platform_data = &mv64x60_mpsc1_pdata,
 312         },
 313 };
 314 #endif
 315
 316 #ifdef CONFIG_MV643XX_ETH
 317 static struct resource mv64x60_eth_shared_resources[] = {
 318         [0] = {
 319                 .name   = "ethernet shared base",
 320                 .start  = MV643XX_ETH_SHARED_REGS,
 321                 .end    = MV643XX_ETH_SHARED_REGS +
 322                                         MV643XX_ETH_SHARED_REGS_SIZE - 1,
 323                 .flags  = IORESOURCE_MEM,
 324         },
 325 };
 326
 327 static struct platform_device mv64x60_eth_shared_device = {
 328         .name           = MV643XX_ETH_SHARED_NAME,
 329         .id             = 0,
 330         .num_resources  = ARRAY_SIZE(mv64x60_eth_shared_resources),
 331         .resource       = mv64x60_eth_shared_resources,
 332 };
 333
 334 #ifdef CONFIG_MV643XX_ETH_0
 335 static struct resource mv64x60_eth0_resources[] = {
 336         [0] = {
 337                 .name   = "eth0 irq",
 338                 .start  = MV64x60_IRQ_ETH_0,
 339                 .end    = MV64x60_IRQ_ETH_0,
 340                 .flags  = IORESOURCE_IRQ,
 341         },
 342 };
 343
 344 static struct mv643xx_eth_platform_data eth0_pd;
 345
 346 static struct platform_device eth0_device = {
 347         .name           = MV643XX_ETH_NAME,
 348         .id             = 0,
 349         .num_resources  = ARRAY_SIZE(mv64x60_eth0_resources),
 350         .resource       = mv64x60_eth0_resources,
 351         .dev = {
 352                 .platform_data = &eth0_pd,
 353         },
 354 };
 355 #endif
 356
 357 #ifdef CONFIG_MV643XX_ETH_1
 358 static struct resource mv64x60_eth1_resources[] = {
 359         [0] = {
 360                 .name   = "eth1 irq",
 361                 .start  = MV64x60_IRQ_ETH_1,
 362                 .end    = MV64x60_IRQ_ETH_1,
 363                 .flags  = IORESOURCE_IRQ,
 364         },
 365 };
 366
 367 static struct mv643xx_eth_platform_data eth1_pd;
 368
 369 static struct platform_device eth1_device = {
 370         .name           = MV643XX_ETH_NAME,
 371         .id             = 1,
 372         .num_resources  = ARRAY_SIZE(mv64x60_eth1_resources),
 373         .resource       = mv64x60_eth1_resources,
 374         .dev = {
 375                 .platform_data = &eth1_pd,
 376         },
 377 };
 378 #endif
 379
 380 #ifdef CONFIG_MV643XX_ETH_2
 381 static struct resource mv64x60_eth2_resources[] = {
 382         [0] = {
 383                 .name   = "eth2 irq",
 384                 .start  = MV64x60_IRQ_ETH_2,
 385                 .end    = MV64x60_IRQ_ETH_2,
 386                 .flags  = IORESOURCE_IRQ,
 387         },
 388 };
 389
 390 static struct mv643xx_eth_platform_data eth2_pd;
 391
 392 static struct platform_device eth2_device = {
 393         .name           = MV643XX_ETH_NAME,
 394         .id             = 2,
 395         .num_resources  = ARRAY_SIZE(mv64x60_eth2_resources),
 396         .resource       = mv64x60_eth2_resources,
 397         .dev = {
 398                 .platform_data = &eth2_pd,
 399         },
 400 };
 401 #endif
 402 #endif
 403
 404 #ifdef  CONFIG_I2C_MV64XXX
 405 static struct mv64xxx_i2c_pdata mv64xxx_i2c_pdata = {
 406         .freq_m                 = 8,
 407         .freq_n                 = 3,
 408         .timeout                = 1000, /* Default timeout of 1 second */
 409         .retries                = 1,
 410 };
 411
 412 static struct resource mv64xxx_i2c_resources[] = {
 413         /* Do not change the order of the IORESOURCE_MEM resources */
 414         [0] = {
 415                 .name   = "mv64xxx i2c base",
 416                 .start  = MV64XXX_I2C_OFFSET,
 417                 .end    = MV64XXX_I2C_OFFSET + MV64XXX_I2C_REG_BLOCK_SIZE - 1,
 418                 .flags  = IORESOURCE_MEM,
 419         },
 420         [1] = {
 421                 .name   = "mv64xxx i2c irq",
 422                 .start  = MV64x60_IRQ_I2C,
 423                 .end    = MV64x60_IRQ_I2C,
 424                 .flags  = IORESOURCE_IRQ,
 425         },
 426 };
 427
 428 static struct platform_device i2c_device = {
 429         .name           = MV64XXX_I2C_CTLR_NAME,
 430         .id             = 0,
 431         .num_resources  = ARRAY_SIZE(mv64xxx_i2c_resources),
 432         .resource       = mv64xxx_i2c_resources,
 433         .dev = {
 434                 .platform_data = &mv64xxx_i2c_pdata,
 435         },
 436 };
 437 #endif
 438
 439 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
 440 static struct mv64xxx_pdata mv64xxx_pdata = {
 441         .hs_reg_valid   = 0,
 442 };
 443
 444 static struct platform_device mv64xxx_device = { /* general mv64x60 stuff */
 445         .name   = MV64XXX_DEV_NAME,
 446         .id     = 0,
 447         .dev = {
 448                 .platform_data = &mv64xxx_pdata,
 449         },
 450 };
 451 #endif
 452
 453 static struct platform_device *mv64x60_pd_devs[] __initdata = {
 454 #ifdef CONFIG_SERIAL_MPSC
 455         &mpsc_shared_device,
 456         &mpsc0_device,
 457         &mpsc1_device,
 458 #endif
 459 #ifdef CONFIG_MV643XX_ETH
 460         &mv64x60_eth_shared_device,
 461 #endif
 462 #ifdef CONFIG_MV643XX_ETH_0
 463         &eth0_device,
 464 #endif
 465 #ifdef CONFIG_MV643XX_ETH_1
 466         &eth1_device,
 467 #endif
 468 #ifdef CONFIG_MV643XX_ETH_2
 469         &eth2_device,
 470 #endif
 471 #ifdef  CONFIG_I2C_MV64XXX
 472         &i2c_device,
 473 #endif
 474 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
 475         &mv64xxx_device,
 476 #endif
 477 };
 478
 479 /*
 480  *****************************************************************************
 481  *
 482  *      Bridge Initialization Routines
 483  *
 484  *****************************************************************************
 485  */
 486 /*
 487  * mv64x60_init()
 488  *
 489  * Initialze the bridge based on setting passed in via 'si'.  The bridge
 490  * handle, 'bh', will be set so that it can be used to make subsequent
 491  * calls to routines in this file.
 492  */
 493 int __init
 494 mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si)
 495 {
 496         u32     mem_windows[MV64x60_CPU2MEM_WINDOWS][2];
 497
 498         if (ppc_md.progress)
 499                 ppc_md.progress("mv64x60 initialization", 0x0);
 500
 501         spin_lock_init(&mv64x60_lock);
 502         mv64x60_early_init(bh, si);
 503
 504         if (mv64x60_get_type(bh) || mv64x60_setup_for_chip(bh)) {
 505                 iounmap(bh->v_base);
 506                 bh->v_base = 0;
 507                 if (ppc_md.progress)
 508                         ppc_md.progress("mv64x60_init: Can't determine chip",0);
 509                 return -1;
 510         }
 511
 512         bh->ci->disable_all_windows(bh, si);
 513         mv64x60_get_mem_windows(bh, mem_windows);
 514         mv64x60_config_cpu2mem_windows(bh, si, mem_windows);
 515
 516         if (bh->ci->config_io2mem_windows)
 517                 bh->ci->config_io2mem_windows(bh, si, mem_windows);
 518         if (bh->ci->set_mpsc2regs_window)
 519                 bh->ci->set_mpsc2regs_window(bh, si->phys_reg_base);
 520
 521         if (si->pci_1.enable_bus) {
 522                 bh->io_base_b = (u32)ioremap(si->pci_1.pci_io.cpu_base,
 523                         si->pci_1.pci_io.size);
 524                 isa_io_base = bh->io_base_b;
 525         }
 526
 527         if (si->pci_0.enable_bus) {
 528                 bh->io_base_a = (u32)ioremap(si->pci_0.pci_io.cpu_base,
 529                         si->pci_0.pci_io.size);
 530                 isa_io_base = bh->io_base_a;
 531
 532                 mv64x60_alloc_hose(bh, MV64x60_PCI0_CONFIG_ADDR,
 533                         MV64x60_PCI0_CONFIG_DATA, &bh->hose_a);
 534                 mv64x60_config_resources(bh->hose_a, &si->pci_0, bh->io_base_a);
 535                 mv64x60_config_pci_params(bh->hose_a, &si->pci_0);
 536
 537                 mv64x60_config_cpu2pci_windows(bh, &si->pci_0, 0);
 538                 mv64x60_config_pci2mem_windows(bh, bh->hose_a, &si->pci_0, 0,
 539                         mem_windows);
 540                 bh->ci->set_pci2regs_window(bh, bh->hose_a, 0,
 541                         si->phys_reg_base);
 542         }
 543
 544         if (si->pci_1.enable_bus) {
 545                 mv64x60_alloc_hose(bh, MV64x60_PCI1_CONFIG_ADDR,
 546                         MV64x60_PCI1_CONFIG_DATA, &bh->hose_b);
 547                 mv64x60_config_resources(bh->hose_b, &si->pci_1, bh->io_base_b);
 548                 mv64x60_config_pci_params(bh->hose_b, &si->pci_1);
 549
 550                 mv64x60_config_cpu2pci_windows(bh, &si->pci_1, 1);
 551                 mv64x60_config_pci2mem_windows(bh, bh->hose_b, &si->pci_1, 1,
 552                         mem_windows);
 553                 bh->ci->set_pci2regs_window(bh, bh->hose_b, 1,
 554                         si->phys_reg_base);
 555         }
 556
 557         bh->ci->chip_specific_init(bh, si);
 558         mv64x60_pd_fixup(bh, mv64x60_pd_devs, ARRAY_SIZE(mv64x60_pd_devs));
 559
 560         return 0;
 561 }
 562
 563 /*
 564  * mv64x60_early_init()
 565  *
 566  * Do some bridge work that must take place before we start messing with
 567  * the bridge for real.
 568  */
 569 void __init
 570 mv64x60_early_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si)
 571 {
 572         struct pci_controller   hose_a, hose_b;
 573
 574         memset(bh, 0, sizeof(*bh));
 575
 576         bh->p_base = si->phys_reg_base;
 577         bh->v_base = ioremap(bh->p_base, MV64x60_INTERNAL_SPACE_SIZE);
 578
 579         mv64x60_bridge_pbase = bh->p_base;
 580         mv64x60_bridge_vbase = bh->v_base;
 581
 582         /* Assuming pci mode [reserved] bits 4:5 on 64260 are 0 */
 583         bh->pci_mode_a = mv64x60_read(bh, MV64x60_PCI0_MODE) &
 584                 MV64x60_PCIMODE_MASK;
 585         bh->pci_mode_b = mv64x60_read(bh, MV64x60_PCI1_MODE) &
 586                 MV64x60_PCIMODE_MASK;
 587
 588         /* Need temporary hose structs to call mv64x60_set_bus() */
 589         memset(&hose_a, 0, sizeof(hose_a));
 590         memset(&hose_b, 0, sizeof(hose_b));
 591         setup_indirect_pci_nomap(&hose_a, bh->v_base + MV64x60_PCI0_CONFIG_ADDR,
 592                 bh->v_base + MV64x60_PCI0_CONFIG_DATA);
 593         setup_indirect_pci_nomap(&hose_b, bh->v_base + MV64x60_PCI1_CONFIG_ADDR,
 594                 bh->v_base + MV64x60_PCI1_CONFIG_DATA);
 595         bh->hose_a = &hose_a;
 596         bh->hose_b = &hose_b;
 597
 598 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
 599         /* Save a copy of hose_a for sysfs functions -- hack */
 600         memcpy(&sysfs_hose_a, &hose_a, sizeof(hose_a));
 601 #endif
 602
 603         mv64x60_set_bus(bh, 0, 0);
 604         mv64x60_set_bus(bh, 1, 0);
 605
 606         bh->hose_a = NULL;
 607         bh->hose_b = NULL;
 608
 609         /* Clear bit 0 of PCI addr decode control so PCI->CPU remap 1:1 */
 610         mv64x60_clr_bits(bh, MV64x60_PCI0_PCI_DECODE_CNTL, 0x00000001);
 611         mv64x60_clr_bits(bh, MV64x60_PCI1_PCI_DECODE_CNTL, 0x00000001);
 612
 613         /* Bit 12 MUST be 0; set bit 27--don't auto-update cpu remap regs */
 614         mv64x60_clr_bits(bh, MV64x60_CPU_CONFIG, (1<<12));
 615         mv64x60_set_bits(bh, MV64x60_CPU_CONFIG, (1<<27));
 616
 617         mv64x60_set_bits(bh, MV64x60_PCI0_TO_RETRY, 0xffff);
 618         mv64x60_set_bits(bh, MV64x60_PCI1_TO_RETRY, 0xffff);
 619 }
 620
 621 /*
 622  *****************************************************************************
 623  *
 624  *      Window Config Routines
 625  *
 626  *****************************************************************************
 627  */
 628 /*
 629  * mv64x60_get_32bit_window()
 630  *
 631  * Determine the base address and size of a 32-bit window on the bridge.
 632  */
 633 void __init
 634 mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window,
 635         u32 *base, u32 *size)
 636 {
 637         u32     val, base_reg, size_reg, base_bits, size_bits;
 638         u32     (*get_from_field)(u32 val, u32 num_bits);
 639
 640         base_reg = bh->ci->window_tab_32bit[window].base_reg;
 641
 642         if (base_reg != 0) {
 643                 size_reg  = bh->ci->window_tab_32bit[window].size_reg;
 644                 base_bits = bh->ci->window_tab_32bit[window].base_bits;
 645                 size_bits = bh->ci->window_tab_32bit[window].size_bits;
 646                 get_from_field= bh->ci->window_tab_32bit[window].get_from_field;
 647
 648                 val = mv64x60_read(bh, base_reg);
 649                 *base = get_from_field(val, base_bits);
 650
 651                 if (size_reg != 0) {
 652                         val = mv64x60_read(bh, size_reg);
 653                         val = get_from_field(val, size_bits);
 654                         *size = bh->ci->untranslate_size(*base, val, size_bits);
 655                 } else
 656                         *size = 0;
 657         } else {
 658                 *base = 0;
 659                 *size = 0;
 660         }
 661
 662         pr_debug("get 32bit window: %d, base: 0x%x, size: 0x%x\n",
 663                 window, *base, *size);
 664 }
 665
 666 /*
 667  * mv64x60_set_32bit_window()
 668  *
 669  * Set the base address and size of a 32-bit window on the bridge.
 670  */
 671 void __init
 672 mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window,
 673         u32 base, u32 size, u32 other_bits)
 674 {
 675         u32     val, base_reg, size_reg, base_bits, size_bits;
 676         u32     (*map_to_field)(u32 val, u32 num_bits);
 677
 678         pr_debug("set 32bit window: %d, base: 0x%x, size: 0x%x, other: 0x%x\n",
 679                 window, base, size, other_bits);
 680
 681         base_reg = bh->ci->window_tab_32bit[window].base_reg;
 682
 683         if (base_reg != 0) {
 684                 size_reg  = bh->ci->window_tab_32bit[window].size_reg;
 685                 base_bits = bh->ci->window_tab_32bit[window].base_bits;
 686                 size_bits = bh->ci->window_tab_32bit[window].size_bits;
 687                 map_to_field = bh->ci->window_tab_32bit[window].map_to_field;
 688
 689                 val = map_to_field(base, base_bits) | other_bits;
 690                 mv64x60_write(bh, base_reg, val);
 691
 692                 if (size_reg != 0) {
 693                         val = bh->ci->translate_size(base, size, size_bits);
 694                         val = map_to_field(val, size_bits);
 695                         mv64x60_write(bh, size_reg, val);
 696                 }
 697
 698                 (void)mv64x60_read(bh, base_reg); /* Flush FIFO */
 699         }
 700 }
 701
 702 /*
 703  * mv64x60_get_64bit_window()
 704  *
 705  * Determine the base address and size of a 64-bit window on the bridge.
 706  */
 707 void __init
 708 mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window,
 709         u32 *base_hi, u32 *base_lo, u32 *size)
 710 {
 711         u32     val, base_lo_reg, size_reg, base_lo_bits, size_bits;
 712         u32     (*get_from_field)(u32 val, u32 num_bits);
 713
 714         base_lo_reg = bh->ci->window_tab_64bit[window].base_lo_reg;
 715
 716         if (base_lo_reg != 0) {
 717                 size_reg = bh->ci->window_tab_64bit[window].size_reg;
 718                 base_lo_bits = bh->ci->window_tab_64bit[window].base_lo_bits;
 719                 size_bits = bh->ci->window_tab_64bit[window].size_bits;
 720                 get_from_field= bh->ci->window_tab_64bit[window].get_from_field;
 721
 722                 *base_hi = mv64x60_read(bh,
 723                         bh->ci->window_tab_64bit[window].base_hi_reg);
 724
 725                 val = mv64x60_read(bh, base_lo_reg);
 726                 *base_lo = get_from_field(val, base_lo_bits);
 727
 728                 if (size_reg != 0) {
 729                         val = mv64x60_read(bh, size_reg);
 730                         val = get_from_field(val, size_bits);
 731                         *size = bh->ci->untranslate_size(*base_lo, val,
 732                                                                 size_bits);
 733                 } else
 734                         *size = 0;
 735         } else {
 736                 *base_hi = 0;
 737                 *base_lo = 0;
 738                 *size = 0;
 739         }
 740
 741         pr_debug("get 64bit window: %d, base hi: 0x%x, base lo: 0x%x, "
 742                 "size: 0x%x\n", window, *base_hi, *base_lo, *size);
 743 }
 744
 745 /*
 746  * mv64x60_set_64bit_window()
 747  *
 748  * Set the base address and size of a 64-bit window on the bridge.
 749  */
 750 void __init
 751 mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window,
 752         u32 base_hi, u32 base_lo, u32 size, u32 other_bits)
 753 {
 754         u32     val, base_lo_reg, size_reg, base_lo_bits, size_bits;
 755         u32     (*map_to_field)(u32 val, u32 num_bits);
 756
 757         pr_debug("set 64bit window: %d, base hi: 0x%x, base lo: 0x%x, "
 758                 "size: 0x%x, other: 0x%x\n",
 759                 window, base_hi, base_lo, size, other_bits);
 760
 761         base_lo_reg = bh->ci->window_tab_64bit[window].base_lo_reg;
 762
 763         if (base_lo_reg != 0) {
 764                 size_reg = bh->ci->window_tab_64bit[window].size_reg;
 765                 base_lo_bits = bh->ci->window_tab_64bit[window].base_lo_bits;
 766                 size_bits = bh->ci->window_tab_64bit[window].size_bits;
 767                 map_to_field = bh->ci->window_tab_64bit[window].map_to_field;
 768
 769                 mv64x60_write(bh, bh->ci->window_tab_64bit[window].base_hi_reg,
 770                         base_hi);
 771
 772                 val = map_to_field(base_lo, base_lo_bits) | other_bits;
 773                 mv64x60_write(bh, base_lo_reg, val);
 774
 775                 if (size_reg != 0) {
 776                         val = bh->ci->translate_size(base_lo, size, size_bits);
 777                         val = map_to_field(val, size_bits);
 778                         mv64x60_write(bh, size_reg, val);
 779                 }
 780
 781                 (void)mv64x60_read(bh, base_lo_reg); /* Flush FIFO */
 782         }
 783 }
 784
 785 /*
 786  * mv64x60_mask()
 787  *
 788  * Take the high-order 'num_bits' of 'val' & mask off low bits.
 789  */
 790 u32 __init
 791 mv64x60_mask(u32 val, u32 num_bits)
 792 {
 793         return val & (0xffffffff << (32 - num_bits));
 794 }
 795
 796 /*
 797  * mv64x60_shift_left()
 798  *
 799  * Take the low-order 'num_bits' of 'val', shift left to align at bit 31 (MSB).
 800  */
 801 u32 __init
 802 mv64x60_shift_left(u32 val, u32 num_bits)
 803 {
 804         return val << (32 - num_bits);
 805 }
 806
 807 /*
 808  * mv64x60_shift_right()
 809  *
 810  * Take the high-order 'num_bits' of 'val', shift right to align at bit 0 (LSB).
 811  */
 812 u32 __init
 813 mv64x60_shift_right(u32 val, u32 num_bits)
 814 {
 815         return val >> (32 - num_bits);
 816 }
 817
 818 /*
 819  *****************************************************************************
 820  *
 821  *      Chip Identification Routines
 822  *
 823  *****************************************************************************
 824  */
 825 /*
 826  * mv64x60_get_type()
 827  *
 828  * Determine the type of bridge chip we have.
 829  */
 830 int __init
 831 mv64x60_get_type(struct mv64x60_handle *bh)
 832 {
 833         struct pci_controller hose;
 834         u16     val;
 835         u8      save_exclude;
 836
 837         memset(&hose, 0, sizeof(hose));
 838         setup_indirect_pci_nomap(&hose, bh->v_base + MV64x60_PCI0_CONFIG_ADDR,
 839                 bh->v_base + MV64x60_PCI0_CONFIG_DATA);
 840
 841         save_exclude = mv64x60_pci_exclude_bridge;
 842         mv64x60_pci_exclude_bridge = 0;
 843         /* Sanity check of bridge's Vendor ID */
 844         early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val);
 845
 846         if (val != PCI_VENDOR_ID_MARVELL) {
 847                 mv64x60_pci_exclude_bridge = save_exclude;
 848                 return -1;
 849         }
 850
 851         /* Get the revision of the chip */
 852         early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_CLASS_REVISION,
 853                 &val);
 854         bh->rev = (u32)(val & 0xff);
 855
 856         /* Figure out the type of Marvell bridge it is */
 857         early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &val);
 858         mv64x60_pci_exclude_bridge = save_exclude;
 859
 860         switch (val) {
 861         case PCI_DEVICE_ID_MARVELL_GT64260:
 862                 switch (bh->rev) {
 863                 case GT64260_REV_A:
 864                         bh->type = MV64x60_TYPE_GT64260A;
 865                         break;
 866
 867                 default:
 868                         printk(KERN_WARNING "Unsupported GT64260 rev %04x\n",
 869                                 bh->rev);
 870                         /* Assume its similar to a 'B' rev and fallthru */
 871                 case GT64260_REV_B:
 872                         bh->type = MV64x60_TYPE_GT64260B;
 873                         break;
 874                 }
 875                 break;
 876
 877         case PCI_DEVICE_ID_MARVELL_MV64360:
 878                 /* Marvell won't tell me how to distinguish a 64361 & 64362 */
 879                 bh->type = MV64x60_TYPE_MV64360;
 880                 break;
 881
 882         case PCI_DEVICE_ID_MARVELL_MV64460:
 883                 bh->type = MV64x60_TYPE_MV64460;
 884                 break;
 885
 886         default:
 887                 printk(KERN_ERR "Unknown Marvell bridge type %04x\n", val);
 888                 return -1;
 889         }
 890
 891         /* Hang onto bridge type & rev for PIC code */
 892         mv64x60_bridge_type = bh->type;
 893         mv64x60_bridge_rev = bh->rev;
 894
 895         return 0;
 896 }
 897
 898 /*
 899  * mv64x60_setup_for_chip()
 900  *
 901  * Set 'bh' to use the proper set of routine for the bridge chip that we have.
 902  */
 903 int __init
 904 mv64x60_setup_for_chip(struct mv64x60_handle *bh)
 905 {
 906         int     rc = 0;
 907
 908         /* Set up chip-specific info based on the chip/bridge type */
 909         switch(bh->type) {
 910         case MV64x60_TYPE_GT64260A:
 911                 bh->ci = &gt64260a_ci;
 912                 break;
 913
 914         case MV64x60_TYPE_GT64260B:
 915                 bh->ci = &gt64260b_ci;
 916                 break;
 917
 918         case MV64x60_TYPE_MV64360:
 919                 bh->ci = &mv64360_ci;
 920                 break;
 921
 922         case MV64x60_TYPE_MV64460:
 923                 bh->ci = &mv64460_ci;
 924                 break;
 925
 926         case MV64x60_TYPE_INVALID:
 927         default:
 928                 if (ppc_md.progress)
 929                         ppc_md.progress("mv64x60: Unsupported bridge", 0x0);
 930                 printk(KERN_ERR "mv64x60: Unsupported bridge\n");
 931                 rc = -1;
 932         }
 933
 934         return rc;
 935 }
 936
 937 /*
 938  * mv64x60_get_bridge_vbase()
 939  *
 940  * Return the virtual address of the bridge's registers.
 941  */
 942 void __iomem *
 943 mv64x60_get_bridge_vbase(void)
 944 {
 945         return mv64x60_bridge_vbase;
 946 }
 947
 948 /*
 949  * mv64x60_get_bridge_type()
 950  *
 951  * Return the type of bridge on the platform.
 952  */
 953 u32
 954 mv64x60_get_bridge_type(void)
 955 {
 956         return mv64x60_bridge_type;
 957 }
 958
 959 /*
 960  * mv64x60_get_bridge_rev()
 961  *
 962  * Return the revision of the bridge on the platform.
 963  */
 964 u32
 965 mv64x60_get_bridge_rev(void)
 966 {
 967         return mv64x60_bridge_rev;
 968 }
 969
 970 /*
 971  *****************************************************************************
 972  *
 973  *      System Memory Window Related Routines
 974  *
 975  *****************************************************************************
 976  */
 977 /*
 978  * mv64x60_get_mem_size()
 979  *
 980  * Calculate the amount of memory that the memory controller is set up for.
 981  * This should only be used by board-specific code if there is no other
 982  * way to determine the amount of memory in the system.
 983  */
 984 u32 __init
 985 mv64x60_get_mem_size(u32 bridge_base, u32 chip_type)
 986 {
 987         struct mv64x60_handle   bh;
 988         u32     mem_windows[MV64x60_CPU2MEM_WINDOWS][2];
 989         u32     rc = 0;
 990
 991         memset(&bh, 0, sizeof(bh));
 992
 993         bh.type = chip_type;
 994         bh.v_base = (void *)bridge_base;
 995
 996         if (!mv64x60_setup_for_chip(&bh)) {
 997                 mv64x60_get_mem_windows(&bh, mem_windows);
 998                 rc = mv64x60_calc_mem_size(&bh, mem_windows);
 999         }
1000
1001         return rc;
1002 }
1003
1004 /*
1005  * mv64x60_get_mem_windows()
1006  *
1007  * Get the values in the memory controller & return in the 'mem_windows' array.
1008  */
1009 void __init
1010 mv64x60_get_mem_windows(struct mv64x60_handle *bh,
1011         u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1012 {
1013         u32     i, win;
1014
1015         for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
1016                 if (bh->ci->is_enabled_32bit(bh, win))
1017                         mv64x60_get_32bit_window(bh, win,
1018                                 &mem_windows[i][0], &mem_windows[i][1]);
1019                 else {
1020                         mem_windows[i][0] = 0;
1021                         mem_windows[i][1] = 0;
1022                 }
1023 }
1024
1025 /*
1026  * mv64x60_calc_mem_size()
1027  *
1028  * Using the memory controller register values in 'mem_windows', determine
1029  * how much memory it is set up for.
1030  */
1031 u32 __init
1032 mv64x60_calc_mem_size(struct mv64x60_handle *bh,
1033         u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1034 {
1035         u32     i, total = 0;
1036
1037         for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++)
1038                 total += mem_windows[i][1];
1039
1040         return total;
1041 }
1042
1043 /*
1044  *****************************************************************************
1045  *
1046  *      CPU->System MEM, PCI Config Routines
1047  *
1048  *****************************************************************************
1049  */
1050 /*
1051  * mv64x60_config_cpu2mem_windows()
1052  *
1053  * Configure CPU->Memory windows on the bridge.
1054  */
1055 static u32 prot_tab[] __initdata = {
1056         MV64x60_CPU_PROT_0_WIN, MV64x60_CPU_PROT_1_WIN,
1057         MV64x60_CPU_PROT_2_WIN, MV64x60_CPU_PROT_3_WIN
1058 };
1059
1060 static u32 cpu_snoop_tab[] __initdata = {
1061         MV64x60_CPU_SNOOP_0_WIN, MV64x60_CPU_SNOOP_1_WIN,
1062         MV64x60_CPU_SNOOP_2_WIN, MV64x60_CPU_SNOOP_3_WIN
1063 };
1064
1065 void __init
1066 mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh,
1067         struct mv64x60_setup_info *si,
1068         u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1069 {
1070         u32     i, win;
1071
1072         /* Set CPU protection & snoop windows */
1073         for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
1074                 if (bh->ci->is_enabled_32bit(bh, win)) {
1075                         mv64x60_set_32bit_window(bh, prot_tab[i],
1076                                 mem_windows[i][0], mem_windows[i][1],
1077                                 si->cpu_prot_options[i]);
1078                         bh->ci->enable_window_32bit(bh, prot_tab[i]);
1079
1080                         if (bh->ci->window_tab_32bit[cpu_snoop_tab[i]].
1081                                                                 base_reg != 0) {
1082                                 mv64x60_set_32bit_window(bh, cpu_snoop_tab[i],
1083                                         mem_windows[i][0], mem_windows[i][1],
1084                                         si->cpu_snoop_options[i]);
1085                                 bh->ci->enable_window_32bit(bh,
1086                                         cpu_snoop_tab[i]);
1087                         }
1088
1089                 }
1090 }
1091
1092 /*
1093  * mv64x60_config_cpu2pci_windows()
1094  *
1095  * Configure the CPU->PCI windows for one of the PCI buses.
1096  */
1097 static u32 win_tab[2][4] __initdata = {
1098         { MV64x60_CPU2PCI0_IO_WIN, MV64x60_CPU2PCI0_MEM_0_WIN,
1099           MV64x60_CPU2PCI0_MEM_1_WIN, MV64x60_CPU2PCI0_MEM_2_WIN },
1100         { MV64x60_CPU2PCI1_IO_WIN, MV64x60_CPU2PCI1_MEM_0_WIN,
1101           MV64x60_CPU2PCI1_MEM_1_WIN, MV64x60_CPU2PCI1_MEM_2_WIN },
1102 };
1103
1104 static u32 remap_tab[2][4] __initdata = {
1105         { MV64x60_CPU2PCI0_IO_REMAP_WIN, MV64x60_CPU2PCI0_MEM_0_REMAP_WIN,
1106           MV64x60_CPU2PCI0_MEM_1_REMAP_WIN, MV64x60_CPU2PCI0_MEM_2_REMAP_WIN },
1107         { MV64x60_CPU2PCI1_IO_REMAP_WIN, MV64x60_CPU2PCI1_MEM_0_REMAP_WIN,
1108           MV64x60_CPU2PCI1_MEM_1_REMAP_WIN, MV64x60_CPU2PCI1_MEM_2_REMAP_WIN }
1109 };
1110
1111 void __init
1112 mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh,
1113         struct mv64x60_pci_info *pi, u32 bus)
1114 {
1115         int     i;
1116
1117         if (pi->pci_io.size > 0) {
1118                 mv64x60_set_32bit_window(bh, win_tab[bus][0],
1119                         pi->pci_io.cpu_base, pi->pci_io.size, pi->pci_io.swap);
1120                 mv64x60_set_32bit_window(bh, remap_tab[bus][0],
1121                         pi->pci_io.pci_base_lo, 0, 0);
1122                 bh->ci->enable_window_32bit(bh, win_tab[bus][0]);
1123         } else /* Actually, the window should already be disabled */
1124                 bh->ci->disable_window_32bit(bh, win_tab[bus][0]);
1125
1126         for (i=0; i<3; i++)
1127                 if (pi->pci_mem[i].size > 0) {
1128                         mv64x60_set_32bit_window(bh, win_tab[bus][i+1],
1129                                 pi->pci_mem[i].cpu_base, pi->pci_mem[i].size,
1130                                 pi->pci_mem[i].swap);
1131                         mv64x60_set_64bit_window(bh, remap_tab[bus][i+1],
1132                                 pi->pci_mem[i].pci_base_hi,
1133                                 pi->pci_mem[i].pci_base_lo, 0, 0);
1134                         bh->ci->enable_window_32bit(bh, win_tab[bus][i+1]);
1135                 } else /* Actually, the window should already be disabled */
1136                         bh->ci->disable_window_32bit(bh, win_tab[bus][i+1]);
1137 }
1138
1139 /*
1140  *****************************************************************************
1141  *
1142  *      PCI->System MEM Config Routines
1143  *
1144  *****************************************************************************
1145  */
1146 /*
1147  * mv64x60_config_pci2mem_windows()
1148  *
1149  * Configure the PCI->Memory windows on the bridge.
1150  */
1151 static u32 pci_acc_tab[2][4] __initdata = {
1152         { MV64x60_PCI02MEM_ACC_CNTL_0_WIN, MV64x60_PCI02MEM_ACC_CNTL_1_WIN,
1153           MV64x60_PCI02MEM_ACC_CNTL_2_WIN, MV64x60_PCI02MEM_ACC_CNTL_3_WIN },
1154         { MV64x60_PCI12MEM_ACC_CNTL_0_WIN, MV64x60_PCI12MEM_ACC_CNTL_1_WIN,
1155           MV64x60_PCI12MEM_ACC_CNTL_2_WIN, MV64x60_PCI12MEM_ACC_CNTL_3_WIN }
1156 };
1157
1158 static u32 pci_snoop_tab[2][4] __initdata = {
1159         { MV64x60_PCI02MEM_SNOOP_0_WIN, MV64x60_PCI02MEM_SNOOP_1_WIN,
1160           MV64x60_PCI02MEM_SNOOP_2_WIN, MV64x60_PCI02MEM_SNOOP_3_WIN },
1161         { MV64x60_PCI12MEM_SNOOP_0_WIN, MV64x60_PCI12MEM_SNOOP_1_WIN,
1162           MV64x60_PCI12MEM_SNOOP_2_WIN, MV64x60_PCI12MEM_SNOOP_3_WIN }
1163 };
1164
1165 static u32 pci_size_tab[2][4] __initdata = {
1166         { MV64x60_PCI0_MEM_0_SIZE, MV64x60_PCI0_MEM_1_SIZE,
1167           MV64x60_PCI0_MEM_2_SIZE, MV64x60_PCI0_MEM_3_SIZE },
1168         { MV64x60_PCI1_MEM_0_SIZE, MV64x60_PCI1_MEM_1_SIZE,
1169           MV64x60_PCI1_MEM_2_SIZE, MV64x60_PCI1_MEM_3_SIZE }
1170 };
1171
1172 void __init
1173 mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh,
1174         struct pci_controller *hose, struct mv64x60_pci_info *pi,
1175         u32 bus, u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1176 {
1177         u32     i, win;
1178
1179         /*
1180          * Set the access control, snoop, BAR size, and window base addresses.
1181          * PCI->MEM windows base addresses will match exactly what the
1182          * CPU->MEM windows are.
1183          */
1184         for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
1185                 if (bh->ci->is_enabled_32bit(bh, win)) {
1186                         mv64x60_set_64bit_window(bh,
1187                                 pci_acc_tab[bus][i], 0,
1188                                 mem_windows[i][0], mem_windows[i][1],
1189                                 pi->acc_cntl_options[i]);
1190                         bh->ci->enable_window_64bit(bh, pci_acc_tab[bus][i]);
1191
1192                         if (bh->ci->window_tab_64bit[
1193                                 pci_snoop_tab[bus][i]].base_lo_reg != 0) {
1194
1195                                 mv64x60_set_64bit_window(bh,
1196                                         pci_snoop_tab[bus][i], 0,
1197                                         mem_windows[i][0], mem_windows[i][1],
1198                                         pi->snoop_options[i]);
1199                                 bh->ci->enable_window_64bit(bh,
1200                                         pci_snoop_tab[bus][i]);
1201                         }
1202
1203                         bh->ci->set_pci2mem_window(hose, bus, i,
1204                                 mem_windows[i][0]);
1205                         mv64x60_write(bh, pci_size_tab[bus][i],
1206                                 mv64x60_mask(mem_windows[i][1] - 1, 20));
1207
1208                         /* Enable the window */
1209                         mv64x60_clr_bits(bh, ((bus == 0) ?
1210                                 MV64x60_PCI0_BAR_ENABLE :
1211                                 MV64x60_PCI1_BAR_ENABLE), (1 << i));
1212                 }
1213 }
1214
1215 /*
1216  *****************************************************************************
1217  *
1218  *      Hose & Resource Alloc/Init Routines
1219  *
1220  *****************************************************************************
1221  */
1222 /*
1223  * mv64x60_alloc_hoses()
1224  *
1225  * Allocate the PCI hose structures for the bridge's PCI buses.
1226  */
1227 void __init
1228 mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr, u32 cfg_data,
1229         struct pci_controller **hose)
1230 {
1231         *hose = pcibios_alloc_controller();
1232         setup_indirect_pci_nomap(*hose, bh->v_base + cfg_addr,
1233                 bh->v_base + cfg_data);
1234 }
1235
1236 /*
1237  * mv64x60_config_resources()
1238  *
1239  * Calculate the offsets, etc. for the hose structures to reflect all of
1240  * the address remapping that happens as you go from CPU->PCI and PCI->MEM.
1241  */
1242 void __init
1243 mv64x60_config_resources(struct pci_controller *hose,
1244         struct mv64x60_pci_info *pi, u32 io_base)
1245 {
1246         int             i;
1247         /* 2 hoses; 4 resources/hose; string <= 64 bytes */
1248         static char     s[2][4][64];
1249
1250         if (pi->pci_io.size != 0) {
1251                 sprintf(s[hose->index][0], "PCI hose %d I/O Space",
1252                         hose->index);
1253                 pci_init_resource(&hose->io_resource, io_base - isa_io_base,
1254                         io_base - isa_io_base + pi->pci_io.size - 1,
1255                         IORESOURCE_IO, s[hose->index][0]);
1256                 hose->io_space.start = pi->pci_io.pci_base_lo;
1257                 hose->io_space.end = pi->pci_io.pci_base_lo + pi->pci_io.size-1;
1258                 hose->io_base_phys = pi->pci_io.cpu_base;
1259                 hose->io_base_virt = (void *)isa_io_base;
1260         }
1261
1262         for (i=0; i<3; i++)
1263                 if (pi->pci_mem[i].size != 0) {
1264                         sprintf(s[hose->index][i+1], "PCI hose %d MEM Space %d",
1265                                 hose->index, i);
1266                         pci_init_resource(&hose->mem_resources[i],
1267                                 pi->pci_mem[i].cpu_base,
1268                                 pi->pci_mem[i].cpu_base + pi->pci_mem[i].size-1,
1269                                 IORESOURCE_MEM, s[hose->index][i+1]);
1270                 }
1271
1272         hose->mem_space.end = pi->pci_mem[0].pci_base_lo +
1273                                                 pi->pci_mem[0].size - 1;
1274         hose->pci_mem_offset = pi->pci_mem[0].cpu_base -
1275                                                 pi->pci_mem[0].pci_base_lo;
1276 }
1277
1278 /*
1279  * mv64x60_config_pci_params()
1280  *
1281  * Configure a hose's PCI config space parameters.
1282  */
1283 void __init
1284 mv64x60_config_pci_params(struct pci_controller *hose,
1285         struct mv64x60_pci_info *pi)
1286 {
1287         u32     devfn;
1288         u16     u16_val;
1289         u8      save_exclude;
1290
1291         devfn = PCI_DEVFN(0,0);
1292
1293         save_exclude = mv64x60_pci_exclude_bridge;
1294         mv64x60_pci_exclude_bridge = 0;
1295
1296         /* Set class code to indicate host bridge */
1297         u16_val = PCI_CLASS_BRIDGE_HOST; /* 0x0600 (host bridge) */
1298         early_write_config_word(hose, 0, devfn, PCI_CLASS_DEVICE, u16_val);
1299
1300         /* Enable bridge to be PCI master & respond to PCI MEM cycles */
1301         early_read_config_word(hose, 0, devfn, PCI_COMMAND, &u16_val);
1302         u16_val &= ~(PCI_COMMAND_IO | PCI_COMMAND_INVALIDATE |
1303                 PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
1304         u16_val |= pi->pci_cmd_bits | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
1305         early_write_config_word(hose, 0, devfn, PCI_COMMAND, u16_val);
1306
1307         /* Set latency timer, cache line size, clear BIST */
1308         u16_val = (pi->latency_timer << 8) | (L1_CACHE_BYTES >> 2);
1309         early_write_config_word(hose, 0, devfn, PCI_CACHE_LINE_SIZE, u16_val);
1310
1311         mv64x60_pci_exclude_bridge = save_exclude;
1312 }
1313
1314 /*
1315  *****************************************************************************
1316  *
1317  *      PCI Related Routine
1318  *
1319  *****************************************************************************
1320  */
1321 /*
1322  * mv64x60_set_bus()
1323  *
1324  * Set the bus number for the hose directly under the bridge.
1325  */
1326 void __init
1327 mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus)
1328 {
1329         struct pci_controller   *hose;
1330         u32     pci_mode, p2p_cfg, pci_cfg_offset, val;
1331         u8      save_exclude;
1332
1333         if (bus == 0) {
1334                 pci_mode = bh->pci_mode_a;
1335                 p2p_cfg = MV64x60_PCI0_P2P_CONFIG;
1336                 pci_cfg_offset = 0x64;
1337                 hose = bh->hose_a;
1338         } else {
1339                 pci_mode = bh->pci_mode_b;
1340                 p2p_cfg = MV64x60_PCI1_P2P_CONFIG;
1341                 pci_cfg_offset = 0xe4;
1342                 hose = bh->hose_b;
1343         }
1344
1345         child_bus &= 0xff;
1346         val = mv64x60_read(bh, p2p_cfg);
1347
1348         if (pci_mode == MV64x60_PCIMODE_CONVENTIONAL) {
1349                 val &= 0xe0000000; /* Force dev num to 0, turn off P2P bridge */
1350                 val |= (child_bus << 16) | 0xff;
1351                 mv64x60_write(bh, p2p_cfg, val);
1352                 (void)mv64x60_read(bh, p2p_cfg); /* Flush FIFO */
1353         } else { /* PCI-X */
1354                 /*
1355                  * Need to use the current bus/dev number (that's in the
1356                  * P2P CONFIG reg) to access the bridge's pci config space.
1357                  */
1358                 save_exclude = mv64x60_pci_exclude_bridge;
1359                 mv64x60_pci_exclude_bridge = 0;
1360                 early_write_config_dword(hose, (val & 0x00ff0000) >> 16,
1361                         PCI_DEVFN(((val & 0x1f000000) >> 24), 0),
1362                         pci_cfg_offset, child_bus << 8);
1363                 mv64x60_pci_exclude_bridge = save_exclude;
1364         }
1365 }
1366
1367 /*
1368  * mv64x60_pci_exclude_device()
1369  *
1370  * This routine is used to make the bridge not appear when the
1371  * PCI subsystem is accessing PCI devices (in PCI config space).
1372  */
1373 int
1374 mv64x60_pci_exclude_device(u8 bus, u8 devfn)
1375 {
1376         struct pci_controller   *hose;
1377
1378         hose = pci_bus_to_hose(bus);
1379
1380         /* Skip slot 0 on both hoses */
1381         if ((mv64x60_pci_exclude_bridge == 1) && (PCI_SLOT(devfn) == 0) &&
1382                 (hose->first_busno == bus))
1383
1384                 return PCIBIOS_DEVICE_NOT_FOUND;
1385         else
1386                 return PCIBIOS_SUCCESSFUL;
1387 } /* mv64x60_pci_exclude_device() */
1388
1389 /*
1390  *****************************************************************************
1391  *
1392  *      Platform Device Routines
1393  *
1394  *****************************************************************************
1395  */
1396
1397 /*
1398  * mv64x60_pd_fixup()
1399  *
1400  * Need to add the base addr of where the bridge's regs are mapped in the
1401  * physical addr space so drivers can ioremap() them.
1402  */
1403 void __init
1404 mv64x60_pd_fixup(struct mv64x60_handle *bh, struct platform_device *pd_devs[],
1405         u32 entries)
1406 {
1407         struct resource *r;
1408         u32             i, j;
1409
1410         for (i=0; i<entries; i++) {
1411                 j = 0;
1412
1413                 while ((r = platform_get_resource(pd_devs[i],IORESOURCE_MEM,j))
1414                         != NULL) {
1415
1416                         r->start += bh->p_base;
1417                         r->end += bh->p_base;
1418                         j++;
1419                 }
1420         }
1421 }
1422
1423 /*
1424  * mv64x60_add_pds()
1425  *
1426  * Add the mv64x60 platform devices to the list of platform devices.
1427  */
1428 static int __init
1429 mv64x60_add_pds(void)
1430 {
1431         return platform_add_devices(mv64x60_pd_devs,
1432                 ARRAY_SIZE(mv64x60_pd_devs));
1433 }
1434 arch_initcall(mv64x60_add_pds);
1435
1436 /*
1437  *****************************************************************************
1438  *
1439  *      GT64260-Specific Routines
1440  *
1441  *****************************************************************************
1442  */
1443 /*
1444  * gt64260_translate_size()
1445  *
1446  * On the GT64260, the size register is really the "top" address of the window.
1447  */
1448 static u32 __init
1449 gt64260_translate_size(u32 base, u32 size, u32 num_bits)
1450 {
1451         return base + mv64x60_mask(size - 1, num_bits);
1452 }
1453
1454 /*
1455  * gt64260_untranslate_size()
1456  *
1457  * Translate the top address of a window into a window size.
1458  */
1459 static u32 __init
1460 gt64260_untranslate_size(u32 base, u32 size, u32 num_bits)
1461 {
1462         if (size >= base)
1463                 size = size - base + (1 << (32 - num_bits));
1464         else
1465                 size = 0;
1466
1467         return size;
1468 }
1469
1470 /*
1471  * gt64260_set_pci2mem_window()
1472  *
1473  * The PCI->MEM window registers are actually in PCI config space so need
1474  * to set them by setting the correct config space BARs.
1475  */
1476 static u32 gt64260_reg_addrs[2][4] __initdata = {
1477         { 0x10, 0x14, 0x18, 0x1c }, { 0x90, 0x94, 0x98, 0x9c }
1478 };
1479
1480 static void __init
1481 gt64260_set_pci2mem_window(struct pci_controller *hose, u32 bus, u32 window,
1482         u32 base)
1483 {
1484         u8      save_exclude;
1485
1486         pr_debug("set pci->mem window: %d, hose: %d, base: 0x%x\n", window,
1487                 hose->index, base);
1488
1489         save_exclude = mv64x60_pci_exclude_bridge;
1490         mv64x60_pci_exclude_bridge = 0;
1491         early_write_config_dword(hose, 0, PCI_DEVFN(0, 0),
1492                 gt64260_reg_addrs[bus][window], mv64x60_mask(base, 20) | 0x8);
1493         mv64x60_pci_exclude_bridge = save_exclude;
1494 }
1495
1496 /*
1497  * gt64260_set_pci2regs_window()
1498  *
1499  * Set where the bridge's registers appear in PCI MEM space.
1500  */
1501 static u32 gt64260_offset[2] __initdata = {0x20, 0xa0};
1502
1503 static void __init
1504 gt64260_set_pci2regs_window(struct mv64x60_handle *bh,
1505         struct pci_controller *hose, u32 bus, u32 base)
1506 {
1507         u8      save_exclude;
1508
1509         pr_debug("set pci->internal regs hose: %d, base: 0x%x\n", hose->index,
1510                 base);
1511
1512         save_exclude = mv64x60_pci_exclude_bridge;
1513         mv64x60_pci_exclude_bridge = 0;
1514         early_write_config_dword(hose, 0, PCI_DEVFN(0,0), gt64260_offset[bus],
1515                 (base << 16));
1516         mv64x60_pci_exclude_bridge = save_exclude;
1517 }
1518
1519 /*
1520  * gt64260_is_enabled_32bit()
1521  *
1522  * On a GT64260, a window is enabled iff its top address is >= to its base
1523  * address.
1524  */
1525 static u32 __init
1526 gt64260_is_enabled_32bit(struct mv64x60_handle *bh, u32 window)
1527 {
1528         u32     rc = 0;
1529
1530         if ((gt64260_32bit_windows[window].base_reg != 0) &&
1531                 (gt64260_32bit_windows[window].size_reg != 0) &&
1532                 ((mv64x60_read(bh, gt64260_32bit_windows[window].size_reg) &
1533                         ((1 << gt64260_32bit_windows[window].size_bits) - 1)) >=
1534                  (mv64x60_read(bh, gt64260_32bit_windows[window].base_reg) &
1535                         ((1 << gt64260_32bit_windows[window].base_bits) - 1))))
1536
1537                 rc = 1;
1538
1539         return rc;
1540 }
1541
1542 /*
1543  * gt64260_enable_window_32bit()
1544  *
1545  * On the GT64260, a window is enabled iff the top address is >= to the base
1546  * address of the window.  Since the window has already been configured by
1547  * the time this routine is called, we have nothing to do here.
1548  */
1549 static void __init
1550 gt64260_enable_window_32bit(struct mv64x60_handle *bh, u32 window)
1551 {
1552         pr_debug("enable 32bit window: %d\n", window);
1553 }
1554
1555 /*
1556  * gt64260_disable_window_32bit()
1557  *
1558  * On a GT64260, you disable a window by setting its top address to be less
1559  * than its base address.
1560  */
1561 static void __init
1562 gt64260_disable_window_32bit(struct mv64x60_handle *bh, u32 window)
1563 {
1564         pr_debug("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
1565                 window, gt64260_32bit_windows[window].base_reg,
1566                 gt64260_32bit_windows[window].size_reg);
1567
1568         if ((gt64260_32bit_windows[window].base_reg != 0) &&
1569                 (gt64260_32bit_windows[window].size_reg != 0)) {
1570
1571                 /* To disable, make bottom reg higher than top reg */
1572                 mv64x60_write(bh, gt64260_32bit_windows[window].base_reg,0xfff);
1573                 mv64x60_write(bh, gt64260_32bit_windows[window].size_reg, 0);
1574         }
1575 }
1576
1577 /*
1578  * gt64260_enable_window_64bit()
1579  *
1580  * On the GT64260, a window is enabled iff the top address is >= to the base
1581  * address of the window.  Since the window has already been configured by
1582  * the time this routine is called, we have nothing to do here.
1583  */
1584 static void __init
1585 gt64260_enable_window_64bit(struct mv64x60_handle *bh, u32 window)
1586 {
1587         pr_debug("enable 64bit window: %d\n", window);
1588 }
1589
1590 /*
1591  * gt64260_disable_window_64bit()
1592  *
1593  * On a GT64260, you disable a window by setting its top address to be less
1594  * than its base address.
1595  */
1596 static void __init
1597 gt64260_disable_window_64bit(struct mv64x60_handle *bh, u32 window)
1598 {
1599         pr_debug("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
1600                 window, gt64260_64bit_windows[window].base_lo_reg,
1601                 gt64260_64bit_windows[window].size_reg);
1602
1603         if ((gt64260_64bit_windows[window].base_lo_reg != 0) &&
1604                 (gt64260_64bit_windows[window].size_reg != 0)) {
1605
1606                 /* To disable, make bottom reg higher than top reg */
1607                 mv64x60_write(bh, gt64260_64bit_windows[window].base_lo_reg,
1608                                                                         0xfff);
1609                 mv64x60_write(bh, gt64260_64bit_windows[window].base_hi_reg, 0);
1610                 mv64x60_write(bh, gt64260_64bit_windows[window].size_reg, 0);
1611         }
1612 }
1613
1614 /*
1615  * gt64260_disable_all_windows()
1616  *
1617  * The GT64260 has several windows that aren't represented in the table of
1618  * windows at the top of this file.  This routine turns all of them off
1619  * except for the memory controller windows, of course.
1620  */
1621 static void __init
1622 gt64260_disable_all_windows(struct mv64x60_handle *bh,
1623         struct mv64x60_setup_info *si)
1624 {
1625         u32     i, preserve;
1626
1627         /* Disable 32bit windows (don't disable cpu->mem windows) */
1628         for (i=MV64x60_CPU2DEV_0_WIN; i<MV64x60_32BIT_WIN_COUNT; i++) {
1629                 if (i < 32)
1630                         preserve = si->window_preserve_mask_32_lo & (1 << i);
1631                 else
1632                         preserve = si->window_preserve_mask_32_hi & (1<<(i-32));
1633
1634                 if (!preserve)
1635                         gt64260_disable_window_32bit(bh, i);
1636         }
1637
1638         /* Disable 64bit windows */
1639         for (i=0; i<MV64x60_64BIT_WIN_COUNT; i++)
1640                 if (!(si->window_preserve_mask_64 & (1<<i)))
1641                         gt64260_disable_window_64bit(bh, i);
1642
1643         /* Turn off cpu protection windows not in gt64260_32bit_windows[] */
1644         mv64x60_write(bh, GT64260_CPU_PROT_BASE_4, 0xfff);
1645         mv64x60_write(bh, GT64260_CPU_PROT_SIZE_4, 0);
1646         mv64x60_write(bh, GT64260_CPU_PROT_BASE_5, 0xfff);
1647         mv64x60_write(bh, GT64260_CPU_PROT_SIZE_5, 0);
1648         mv64x60_write(bh, GT64260_CPU_PROT_BASE_6, 0xfff);
1649         mv64x60_write(bh, GT64260_CPU_PROT_SIZE_6, 0);
1650         mv64x60_write(bh, GT64260_CPU_PROT_BASE_7, 0xfff);
1651         mv64x60_write(bh, GT64260_CPU_PROT_SIZE_7, 0);
1652
1653         /* Turn off PCI->MEM access cntl wins not in gt64260_64bit_windows[] */
1654         mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_LO, 0xfff);
1655         mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_HI, 0);
1656         mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_SIZE, 0);
1657         mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_LO, 0xfff);
1658         mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_HI, 0);
1659         mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_SIZE, 0);
1660         mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_BASE_LO, 0xfff);
1661         mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_BASE_HI, 0);
1662         mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_SIZE, 0);
1663         mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_BASE_LO, 0xfff);
1664         mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_BASE_HI, 0);
1665         mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_SIZE, 0);
1666
1667         mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_LO, 0xfff);
1668         mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_HI, 0);
1669         mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_SIZE, 0);
1670         mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_LO, 0xfff);
1671         mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_HI, 0);
1672         mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_SIZE, 0);
1673         mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_BASE_LO, 0xfff);
1674         mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_BASE_HI, 0);
1675         mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_SIZE, 0);
1676         mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_BASE_LO, 0xfff);
1677         mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_BASE_HI, 0);
1678         mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_SIZE, 0);
1679
1680         /* Disable all PCI-><whatever> windows */
1681         mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x07fffdff);
1682         mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x07fffdff);
1683
1684         /*
1685          * Some firmwares enable a bunch of intr sources
1686          * for the PCI INT output pins.
1687          */
1688         mv64x60_write(bh, GT64260_IC_CPU_INTR_MASK_LO, 0);
1689         mv64x60_write(bh, GT64260_IC_CPU_INTR_MASK_HI, 0);
1690         mv64x60_write(bh, GT64260_IC_PCI0_INTR_MASK_LO, 0);
1691         mv64x60_write(bh, GT64260_IC_PCI0_INTR_MASK_HI, 0);
1692         mv64x60_write(bh, GT64260_IC_PCI1_INTR_MASK_LO, 0);
1693         mv64x60_write(bh, GT64260_IC_PCI1_INTR_MASK_HI, 0);
1694         mv64x60_write(bh, GT64260_IC_CPU_INT_0_MASK, 0);
1695         mv64x60_write(bh, GT64260_IC_CPU_INT_1_MASK, 0);
1696         mv64x60_write(bh, GT64260_IC_CPU_INT_2_MASK, 0);
1697         mv64x60_write(bh, GT64260_IC_CPU_INT_3_MASK, 0);
1698 }
1699
1700 /*
1701  * gt64260a_chip_specific_init()
1702  *
1703  * Implement errata work arounds for the GT64260A.
1704  */
1705 static void __init
1706 gt64260a_chip_specific_init(struct mv64x60_handle *bh,
1707         struct mv64x60_setup_info *si)
1708 {
1709 #ifdef CONFIG_SERIAL_MPSC
1710         struct resource *r;
1711 #endif
1712 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1713         u32     val;
1714         u8      save_exclude;
1715 #endif
1716
1717         if (si->pci_0.enable_bus)
1718                 mv64x60_set_bits(bh, MV64x60_PCI0_CMD,
1719                         ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1720
1721         if (si->pci_1.enable_bus)
1722                 mv64x60_set_bits(bh, MV64x60_PCI1_CMD,
1723                         ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1724
1725         /*
1726          * Dave Wilhardt found that bit 4 in the PCI Command registers must
1727          * be set if you are using cache coherency.
1728          */
1729 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1730         /* Res #MEM-4 -- cpu read buffer to buffer 1 */
1731         if ((mv64x60_read(bh, MV64x60_CPU_MODE) & 0xf0) == 0x40)
1732                 mv64x60_set_bits(bh, GT64260_SDRAM_CONFIG, (1<<26));
1733
1734         save_exclude = mv64x60_pci_exclude_bridge;
1735         mv64x60_pci_exclude_bridge = 0;
1736         if (si->pci_0.enable_bus) {
1737                 early_read_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1738                         PCI_COMMAND, &val);
1739                 val |= PCI_COMMAND_INVALIDATE;
1740                 early_write_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1741                         PCI_COMMAND, val);
1742         }
1743
1744         if (si->pci_1.enable_bus) {
1745                 early_read_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1746                         PCI_COMMAND, &val);
1747                 val |= PCI_COMMAND_INVALIDATE;
1748                 early_write_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1749                         PCI_COMMAND, val);
1750         }
1751         mv64x60_pci_exclude_bridge = save_exclude;
1752 #endif
1753
1754         /* Disable buffer/descriptor snooping */
1755         mv64x60_clr_bits(bh, 0xf280, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1756         mv64x60_clr_bits(bh, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1757
1758 #ifdef CONFIG_SERIAL_MPSC
1759         mv64x60_mpsc0_pdata.mirror_regs = 1;
1760         mv64x60_mpsc0_pdata.cache_mgmt = 1;
1761         mv64x60_mpsc1_pdata.mirror_regs = 1;
1762         mv64x60_mpsc1_pdata.cache_mgmt = 1;
1763
1764         if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0))
1765                         != NULL) {
1766                 r->start = MV64x60_IRQ_SDMA_0;
1767                 r->end = MV64x60_IRQ_SDMA_0;
1768         }
1769 #endif
1770 }
1771
1772 /*
1773  * gt64260b_chip_specific_init()
1774  *
1775  * Implement errata work arounds for the GT64260B.
1776  */
1777 static void __init
1778 gt64260b_chip_specific_init(struct mv64x60_handle *bh,
1779         struct mv64x60_setup_info *si)
1780 {
1781 #ifdef CONFIG_SERIAL_MPSC
1782         struct resource *r;
1783 #endif
1784 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1785         u32     val;
1786         u8      save_exclude;
1787 #endif
1788
1789         if (si->pci_0.enable_bus)
1790                 mv64x60_set_bits(bh, MV64x60_PCI0_CMD,
1791                         ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1792
1793         if (si->pci_1.enable_bus)
1794                 mv64x60_set_bits(bh, MV64x60_PCI1_CMD,
1795                         ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1796
1797         /*
1798          * Dave Wilhardt found that bit 4 in the PCI Command registers must
1799          * be set if you are using cache coherency.
1800          */
1801 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1802         mv64x60_set_bits(bh, GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH, 0xf);
1803
1804         /* Res #MEM-4 -- cpu read buffer to buffer 1 */
1805         if ((mv64x60_read(bh, MV64x60_CPU_MODE) & 0xf0) == 0x40)
1806                 mv64x60_set_bits(bh, GT64260_SDRAM_CONFIG, (1<<26));
1807
1808         save_exclude = mv64x60_pci_exclude_bridge;
1809         mv64x60_pci_exclude_bridge = 0;
1810         if (si->pci_0.enable_bus) {
1811                 early_read_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1812                         PCI_COMMAND, &val);
1813                 val |= PCI_COMMAND_INVALIDATE;
1814                 early_write_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1815                         PCI_COMMAND, val);
1816         }
1817
1818         if (si->pci_1.enable_bus) {
1819                 early_read_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1820                         PCI_COMMAND, &val);
1821                 val |= PCI_COMMAND_INVALIDATE;
1822                 early_write_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1823                         PCI_COMMAND, val);
1824         }
1825         mv64x60_pci_exclude_bridge = save_exclude;
1826 #endif
1827
1828         /* Disable buffer/descriptor snooping */
1829         mv64x60_clr_bits(bh, 0xf280, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1830         mv64x60_clr_bits(bh, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1831
1832 #ifdef CONFIG_SERIAL_MPSC
1833         /*
1834          * The 64260B is not supposed to have the bug where the MPSC & ENET
1835          * can't access cache coherent regions.  However, testing has shown
1836          * that the MPSC, at least, still has this bug.
1837          */
1838         mv64x60_mpsc0_pdata.cache_mgmt = 1;
1839         mv64x60_mpsc1_pdata.cache_mgmt = 1;
1840
1841         if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0))
1842                         != NULL) {
1843                 r->start = MV64x60_IRQ_SDMA_0;
1844                 r->end = MV64x60_IRQ_SDMA_0;
1845         }
1846 #endif
1847 }
1848
1849 /*
1850  *****************************************************************************
1851  *
1852  *      MV64360-Specific Routines
1853  *
1854  *****************************************************************************
1855  */
1856 /*
1857  * mv64360_translate_size()
1858  *
1859  * On the MV64360, the size register is set similar to the size you get
1860  * from a pci config space BAR register.  That is, programmed from LSB to MSB
1861  * as a sequence of 1's followed by a sequence of 0's. IOW, "size -1" with the
1862  * assumption that the size is a power of 2.
1863  */
1864 static u32 __init
1865 mv64360_translate_size(u32 base_addr, u32 size, u32 num_bits)
1866 {
1867         return mv64x60_mask(size - 1, num_bits);
1868 }
1869
1870 /*
1871  * mv64360_untranslate_size()
1872  *
1873  * Translate the size register value of a window into a window size.
1874  */
1875 static u32 __init
1876 mv64360_untranslate_size(u32 base_addr, u32 size, u32 num_bits)
1877 {
1878         if (size > 0) {
1879                 size >>= (32 - num_bits);
1880                 size++;
1881                 size <<= (32 - num_bits);
1882         }
1883
1884         return size;
1885 }
1886
1887 /*
1888  * mv64360_set_pci2mem_window()
1889  *
1890  * The PCI->MEM window registers are actually in PCI config space so need
1891  * to set them by setting the correct config space BARs.
1892  */
1893 struct {
1894         u32     fcn;
1895         u32     base_hi_bar;
1896         u32     base_lo_bar;
1897 } static mv64360_reg_addrs[2][4] __initdata = {
1898         {{ 0, 0x14, 0x10 }, { 0, 0x1c, 0x18 },
1899          { 1, 0x14, 0x10 }, { 1, 0x1c, 0x18 }},
1900         {{ 0, 0x94, 0x90 }, { 0, 0x9c, 0x98 },
1901          { 1, 0x94, 0x90 }, { 1, 0x9c, 0x98 }}
1902 };
1903
1904 static void __init
1905 mv64360_set_pci2mem_window(struct pci_controller *hose, u32 bus, u32 window,
1906         u32 base)
1907 {
1908         u8 save_exclude;
1909
1910         pr_debug("set pci->mem window: %d, hose: %d, base: 0x%x\n", window,
1911                 hose->index, base);
1912
1913         save_exclude = mv64x60_pci_exclude_bridge;
1914         mv64x60_pci_exclude_bridge = 0;
1915         early_write_config_dword(hose, 0,
1916                 PCI_DEVFN(0, mv64360_reg_addrs[bus][window].fcn),
1917                 mv64360_reg_addrs[bus][window].base_hi_bar, 0);
1918         early_write_config_dword(hose, 0,
1919                 PCI_DEVFN(0, mv64360_reg_addrs[bus][window].fcn),
1920                 mv64360_reg_addrs[bus][window].base_lo_bar,
1921                 mv64x60_mask(base,20) | 0xc);
1922         mv64x60_pci_exclude_bridge = save_exclude;
1923 }
1924
1925 /*
1926  * mv64360_set_pci2regs_window()
1927  *
1928  * Set where the bridge's registers appear in PCI MEM space.
1929  */
1930 static u32 mv64360_offset[2][2] __initdata = {{0x20, 0x24}, {0xa0, 0xa4}};
1931
1932 static void __init
1933 mv64360_set_pci2regs_window(struct mv64x60_handle *bh,
1934         struct pci_controller *hose, u32 bus, u32 base)
1935 {
1936         u8      save_exclude;
1937
1938         pr_debug("set pci->internal regs hose: %d, base: 0x%x\n", hose->index,
1939                 base);
1940
1941         save_exclude = mv64x60_pci_exclude_bridge;
1942         mv64x60_pci_exclude_bridge = 0;
1943         early_write_config_dword(hose, 0, PCI_DEVFN(0,0),
1944                 mv64360_offset[bus][0], (base << 16));
1945         early_write_config_dword(hose, 0, PCI_DEVFN(0,0),
1946                 mv64360_offset[bus][1], 0);
1947         mv64x60_pci_exclude_bridge = save_exclude;
1948 }
1949
1950 /*
1951  * mv64360_is_enabled_32bit()
1952  *
1953  * On a MV64360, a window is enabled by either clearing a bit in the
1954  * CPU BAR Enable reg or setting a bit in the window's base reg.
1955  * Note that this doesn't work for windows on the PCI slave side but we don't
1956  * check those so its okay.
1957  */
1958 static u32 __init
1959 mv64360_is_enabled_32bit(struct mv64x60_handle *bh, u32 window)
1960 {
1961         u32     extra, rc = 0;
1962
1963         if (((mv64360_32bit_windows[window].base_reg != 0) &&
1964                 (mv64360_32bit_windows[window].size_reg != 0)) ||
1965                 (window == MV64x60_CPU2SRAM_WIN)) {
1966
1967                 extra = mv64360_32bit_windows[window].extra;
1968
1969                 switch (extra & MV64x60_EXTRA_MASK) {
1970                 case MV64x60_EXTRA_CPUWIN_ENAB:
1971                         rc = (mv64x60_read(bh, MV64360_CPU_BAR_ENABLE) &
1972                                 (1 << (extra & 0x1f))) == 0;
1973                         break;
1974
1975                 case MV64x60_EXTRA_CPUPROT_ENAB:
1976                         rc = (mv64x60_read(bh,
1977                                 mv64360_32bit_windows[window].base_reg) &
1978                                         (1 << (extra & 0x1f))) != 0;
1979                         break;
1980
1981                 case MV64x60_EXTRA_ENET_ENAB:
1982                         rc = (mv64x60_read(bh, MV64360_ENET2MEM_BAR_ENABLE) &
1983                                 (1 << (extra & 0x7))) == 0;
1984                         break;
1985
1986                 case MV64x60_EXTRA_MPSC_ENAB:
1987                         rc = (mv64x60_read(bh, MV64360_MPSC2MEM_BAR_ENABLE) &
1988                                 (1 << (extra & 0x3))) == 0;
1989                         break;
1990
1991                 case MV64x60_EXTRA_IDMA_ENAB:
1992                         rc = (mv64x60_read(bh, MV64360_IDMA2MEM_BAR_ENABLE) &
1993                                 (1 << (extra & 0x7))) == 0;
1994                         break;
1995
1996                 default:
1997                         printk(KERN_ERR "mv64360_is_enabled: %s\n",
1998                                 "32bit table corrupted");
1999                 }
2000         }
2001
2002         return rc;
2003 }
2004
2005 /*
2006  * mv64360_enable_window_32bit()
2007  *
2008  * On a MV64360, a window is enabled by either clearing a bit in the
2009  * CPU BAR Enable reg or setting a bit in the window's base reg.
2010  */
2011 static void __init
2012 mv64360_enable_window_32bit(struct mv64x60_handle *bh, u32 window)
2013 {
2014         u32     extra;
2015
2016         pr_debug("enable 32bit window: %d\n", window);
2017
2018         if (((mv64360_32bit_windows[window].base_reg != 0) &&
2019                 (mv64360_32bit_windows[window].size_reg != 0)) ||
2020                 (window == MV64x60_CPU2SRAM_WIN)) {
2021
2022                 extra = mv64360_32bit_windows[window].extra;
2023
2024                 switch (extra & MV64x60_EXTRA_MASK) {
2025                 case MV64x60_EXTRA_CPUWIN_ENAB:
2026                         mv64x60_clr_bits(bh, MV64360_CPU_BAR_ENABLE,
2027                                 (1 << (extra & 0x1f)));
2028                         break;
2029
2030                 case MV64x60_EXTRA_CPUPROT_ENAB:
2031                         mv64x60_set_bits(bh,
2032                                 mv64360_32bit_windows[window].base_reg,
2033                                 (1 << (extra & 0x1f)));
2034                         break;
2035
2036                 case MV64x60_EXTRA_ENET_ENAB:
2037                         mv64x60_clr_bits(bh, MV64360_ENET2MEM_BAR_ENABLE,
2038                                 (1 << (extra & 0x7)));
2039                         break;
2040
2041                 case MV64x60_EXTRA_MPSC_ENAB:
2042                         mv64x60_clr_bits(bh, MV64360_MPSC2MEM_BAR_ENABLE,
2043                                 (1 << (extra & 0x3)));
2044                         break;
2045
2046                 case MV64x60_EXTRA_IDMA_ENAB:
2047                         mv64x60_clr_bits(bh, MV64360_IDMA2MEM_BAR_ENABLE,
2048                                 (1 << (extra & 0x7)));
2049                         break;
2050
2051                 default:
2052                         printk(KERN_ERR "mv64360_enable: %s\n",
2053                                 "32bit table corrupted");
2054                 }
2055         }
2056 }
2057
2058 /*
2059  * mv64360_disable_window_32bit()
2060  *
2061  * On a MV64360, a window is disabled by either setting a bit in the
2062  * CPU BAR Enable reg or clearing a bit in the window's base reg.
2063  */
2064 static void __init
2065 mv64360_disable_window_32bit(struct mv64x60_handle *bh, u32 window)
2066 {
2067         u32     extra;
2068
2069         pr_debug("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
2070                 window, mv64360_32bit_windows[window].base_reg,
2071                 mv64360_32bit_windows[window].size_reg);
2072
2073         if (((mv64360_32bit_windows[window].base_reg != 0) &&
2074                 (mv64360_32bit_windows[window].size_reg != 0)) ||
2075                 (window == MV64x60_CPU2SRAM_WIN)) {
2076
2077                 extra = mv64360_32bit_windows[window].extra;
2078
2079                 switch (extra & MV64x60_EXTRA_MASK) {
2080                 case MV64x60_EXTRA_CPUWIN_ENAB:
2081                         mv64x60_set_bits(bh, MV64360_CPU_BAR_ENABLE,
2082                                 (1 << (extra & 0x1f)));
2083                         break;
2084
2085                 case MV64x60_EXTRA_CPUPROT_ENAB:
2086                         mv64x60_clr_bits(bh,
2087                                 mv64360_32bit_windows[window].base_reg,
2088                                 (1 << (extra & 0x1f)));
2089                         break;
2090
2091                 case MV64x60_EXTRA_ENET_ENAB:
2092                         mv64x60_set_bits(bh, MV64360_ENET2MEM_BAR_ENABLE,
2093                                 (1 << (extra & 0x7)));
2094                         break;
2095
2096                 case MV64x60_EXTRA_MPSC_ENAB:
2097                         mv64x60_set_bits(bh, MV64360_MPSC2MEM_BAR_ENABLE,
2098                                 (1 << (extra & 0x3)));
2099                         break;
2100
2101                 case MV64x60_EXTRA_IDMA_ENAB:
2102                         mv64x60_set_bits(bh, MV64360_IDMA2MEM_BAR_ENABLE,
2103                                 (1 << (extra & 0x7)));
2104                         break;
2105
2106                 default:
2107                         printk(KERN_ERR "mv64360_disable: %s\n",
2108                                 "32bit table corrupted");
2109                 }
2110         }
2111 }
2112
2113 /*
2114  * mv64360_enable_window_64bit()
2115  *
2116  * On the MV64360, a 64-bit window is enabled by setting a bit in the window's
2117  * base reg.
2118  */
2119 static void __init
2120 mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window)
2121 {
2122         pr_debug("enable 64bit window: %d\n", window);
2123
2124         if ((mv64360_64bit_windows[window].base_lo_reg!= 0) &&
2125                 (mv64360_64bit_windows[window].size_reg != 0)) {
2126
2127                 if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK)
2128                                 == MV64x60_EXTRA_PCIACC_ENAB)
2129                         mv64x60_set_bits(bh,
2130                                 mv64360_64bit_windows[window].base_lo_reg,
2131                                 (1 << (mv64360_64bit_windows[window].extra &
2132                                                                         0x1f)));
2133                 else
2134                         printk(KERN_ERR "mv64360_enable: %s\n",
2135                                 "64bit table corrupted");
2136         }
2137 }
2138
2139 /*
2140  * mv64360_disable_window_64bit()
2141  *
2142  * On a MV64360, a 64-bit window is disabled by clearing a bit in the window's
2143  * base reg.
2144  */
2145 static void __init
2146 mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window)
2147 {
2148         pr_debug("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
2149                 window, mv64360_64bit_windows[window].base_lo_reg,
2150                 mv64360_64bit_windows[window].size_reg);
2151
2152         if ((mv64360_64bit_windows[window].base_lo_reg != 0) &&
2153                         (mv64360_64bit_windows[window].size_reg != 0)) {
2154                 if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK)
2155                                 == MV64x60_EXTRA_PCIACC_ENAB)
2156                         mv64x60_clr_bits(bh,
2157                                 mv64360_64bit_windows[window].base_lo_reg,
2158                                 (1 << (mv64360_64bit_windows[window].extra &
2159                                                                         0x1f)));
2160                 else
2161                         printk(KERN_ERR "mv64360_disable: %s\n",
2162                                 "64bit table corrupted");
2163         }
2164 }
2165
2166 /*
2167  * mv64360_disable_all_windows()
2168  *
2169  * The MV64360 has a few windows that aren't represented in the table of
2170  * windows at the top of this file.  This routine turns all of them off
2171  * except for the memory controller windows, of course.
2172  */
2173 static void __init
2174 mv64360_disable_all_windows(struct mv64x60_handle *bh,
2175         struct mv64x60_setup_info *si)
2176 {
2177         u32     preserve, i;
2178
2179         /* Disable 32bit windows (don't disable cpu->mem windows) */
2180         for (i=MV64x60_CPU2DEV_0_WIN; i<MV64x60_32BIT_WIN_COUNT; i++) {
2181                 if (i < 32)
2182                         preserve = si->window_preserve_mask_32_lo & (1 << i);
2183                 else
2184                         preserve = si->window_preserve_mask_32_hi & (1<<(i-32));
2185
2186                 if (!preserve)
2187                         mv64360_disable_window_32bit(bh, i);
2188         }
2189
2190         /* Disable 64bit windows */
2191         for (i=0; i<MV64x60_64BIT_WIN_COUNT; i++)
2192                 if (!(si->window_preserve_mask_64 & (1<<i)))
2193                         mv64360_disable_window_64bit(bh, i);
2194
2195         /* Turn off PCI->MEM access cntl wins not in mv64360_64bit_windows[] */
2196         mv64x60_clr_bits(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_LO, 0);
2197         mv64x60_clr_bits(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_LO, 0);
2198         mv64x60_clr_bits(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_LO, 0);
2199         mv64x60_clr_bits(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_LO, 0);
2200
2201         /* Disable all PCI-><whatever> windows */
2202         mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x0000f9ff);
2203         mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x0000f9ff);
2204 }
2205
2206 /*
2207  * mv64360_config_io2mem_windows()
2208  *
2209  * ENET, MPSC, and IDMA ctlrs on the MV64[34]60 have separate windows that
2210  * must be set up so that the respective ctlr can access system memory.
2211  */
2212 static u32 enet_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = {
2213         MV64x60_ENET2MEM_0_WIN, MV64x60_ENET2MEM_1_WIN,
2214         MV64x60_ENET2MEM_2_WIN, MV64x60_ENET2MEM_3_WIN,
2215 };
2216
2217 static u32 mpsc_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = {
2218         MV64x60_MPSC2MEM_0_WIN, MV64x60_MPSC2MEM_1_WIN,
2219         MV64x60_MPSC2MEM_2_WIN, MV64x60_MPSC2MEM_3_WIN,
2220 };
2221
2222 static u32 idma_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = {
2223         MV64x60_IDMA2MEM_0_WIN, MV64x60_IDMA2MEM_1_WIN,
2224         MV64x60_IDMA2MEM_2_WIN, MV64x60_IDMA2MEM_3_WIN,
2225 };
2226
2227 static u32 dram_selects[MV64x60_CPU2MEM_WINDOWS] __initdata =
2228         { 0xe, 0xd, 0xb, 0x7 };
2229
2230 static void __init
2231 mv64360_config_io2mem_windows(struct mv64x60_handle *bh,
2232         struct mv64x60_setup_info *si,
2233         u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
2234 {
2235         u32     i, win;
2236
2237         pr_debug("config_io2regs_windows: enet, mpsc, idma -> bridge regs\n");
2238
2239         mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_0, 0);
2240         mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_1, 0);
2241         mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_2, 0);
2242
2243         mv64x60_write(bh, MV64360_MPSC2MEM_ACC_PROT_0, 0);
2244         mv64x60_write(bh, MV64360_MPSC2MEM_ACC_PROT_1, 0);
2245
2246         mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_0, 0);
2247         mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_1, 0);
2248         mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_2, 0);
2249         mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_3, 0);
2250
2251         /* Assume that mem ctlr has no more windows than embedded I/O ctlr */
2252         for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
2253                 if (bh->ci->is_enabled_32bit(bh, win)) {
2254                         mv64x60_set_32bit_window(bh, enet_tab[i],
2255                                 mem_windows[i][0], mem_windows[i][1],
2256                                 (dram_selects[i] << 8) |
2257                                 (si->enet_options[i] & 0x3000));
2258                         bh->ci->enable_window_32bit(bh, enet_tab[i]);
2259
2260                         /* Give enet r/w access to memory region */
2261                         mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_0,
2262                                 (0x3 << (i << 1)));
2263                         mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_1,
2264                                 (0x3 << (i << 1)));
2265                         mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_2,
2266                                 (0x3 << (i << 1)));
2267
2268                         mv64x60_set_32bit_window(bh, mpsc_tab[i],
2269                                 mem_windows[i][0], mem_windows[i][1],
2270                                 (dram_selects[i] << 8) |
2271                                 (si->mpsc_options[i] & 0x3000));
2272                         bh->ci->enable_window_32bit(bh, mpsc_tab[i]);
2273
2274                         /* Give mpsc r/w access to memory region */
2275                         mv64x60_set_bits(bh, MV64360_MPSC2MEM_ACC_PROT_0,
2276                                 (0x3 << (i << 1)));
2277                         mv64x60_set_bits(bh, MV64360_MPSC2MEM_ACC_PROT_1,
2278                                 (0x3 << (i << 1)));
2279
2280                         mv64x60_set_32bit_window(bh, idma_tab[i],
2281                                 mem_windows[i][0], mem_windows[i][1],
2282                                 (dram_selects[i] << 8) |
2283                                 (si->idma_options[i] & 0x3000));
2284                         bh->ci->enable_window_32bit(bh, idma_tab[i]);
2285
2286                         /* Give idma r/w access to memory region */
2287                         mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_0,
2288                                 (0x3 << (i << 1)));
2289                         mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_1,
2290                                 (0x3 << (i << 1)));
2291                         mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_2,
2292                                 (0x3 << (i << 1)));
2293                         mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_3,
2294                                 (0x3 << (i << 1)));
2295                 }
2296 }
2297
2298 /*
2299  * mv64360_set_mpsc2regs_window()
2300  *
2301  * MPSC has a window to the bridge's internal registers.  Call this routine
2302  * to change that window so it doesn't conflict with the windows mapping the
2303  * mpsc to system memory.
2304  */
2305 static void __init
2306 mv64360_set_mpsc2regs_window(struct mv64x60_handle *bh, u32 base)
2307 {
2308         pr_debug("set mpsc->internal regs, base: 0x%x\n", base);
2309         mv64x60_write(bh, MV64360_MPSC2REGS_BASE, base & 0xffff0000);
2310 }
2311
2312 /*
2313  * mv64360_chip_specific_init()
2314  *
2315  * Implement errata work arounds for the MV64360.
2316  */
2317 static void __init
2318 mv64360_chip_specific_init(struct mv64x60_handle *bh,
2319         struct mv64x60_setup_info *si)
2320 {
2321 #if !defined(CONFIG_NOT_COHERENT_CACHE)
2322         mv64x60_set_bits(bh, MV64360_D_UNIT_CONTROL_HIGH, (1<<24));
2323 #endif
2324 #ifdef CONFIG_SERIAL_MPSC
2325         mv64x60_mpsc0_pdata.brg_can_tune = 1;
2326         mv64x60_mpsc0_pdata.cache_mgmt = 1;
2327         mv64x60_mpsc1_pdata.brg_can_tune = 1;
2328         mv64x60_mpsc1_pdata.cache_mgmt = 1;
2329 #endif
2330 }
2331
2332 /*
2333  * mv64460_chip_specific_init()
2334  *
2335  * Implement errata work arounds for the MV64460.
2336  */
2337 static void __init
2338 mv64460_chip_specific_init(struct mv64x60_handle *bh,
2339         struct mv64x60_setup_info *si)
2340 {
2341 #if !defined(CONFIG_NOT_COHERENT_CACHE)
2342         mv64x60_set_bits(bh, MV64360_D_UNIT_CONTROL_HIGH, (1<<24) | (1<<25));
2343         mv64x60_set_bits(bh, MV64460_D_UNIT_MMASK, (1<<1) | (1<<4));
2344 #endif
2345 #ifdef CONFIG_SERIAL_MPSC
2346         mv64x60_mpsc0_pdata.brg_can_tune = 1;
2347         mv64x60_mpsc0_pdata.cache_mgmt = 1;
2348         mv64x60_mpsc1_pdata.brg_can_tune = 1;
2349         mv64x60_mpsc1_pdata.cache_mgmt = 1;
2350 #endif
2351 }
2352
2353
2354 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
2355 /* Export the hotswap register via sysfs for enum event monitoring */
2356 #define VAL_LEN_MAX     11 /* 32-bit hex or dec stringified number + '\n' */
2357
2358 DECLARE_MUTEX(mv64xxx_hs_lock);
2359
2360 static ssize_t
2361 mv64xxx_hs_reg_read(struct kobject *kobj, char *buf, loff_t off, size_t count)
2362 {
2363         u32     v;
2364         u8      save_exclude;
2365
2366         if (off > 0)
2367                 return 0;
2368         if (count < VAL_LEN_MAX)
2369                 return -EINVAL;
2370
2371         if (down_interruptible(&mv64xxx_hs_lock))
2372                 return -ERESTARTSYS;
2373         save_exclude = mv64x60_pci_exclude_bridge;
2374         mv64x60_pci_exclude_bridge = 0;
2375         early_read_config_dword(&sysfs_hose_a, 0, PCI_DEVFN(0, 0),
2376                         MV64360_PCICFG_CPCI_HOTSWAP, &v);
2377         mv64x60_pci_exclude_bridge = save_exclude;
2378         up(&mv64xxx_hs_lock);
2379
2380         return sprintf(buf, "0x%08x\n", v);
2381 }
2382
2383 static ssize_t
2384 mv64xxx_hs_reg_write(struct kobject *kobj, char *buf, loff_t off, size_t count)
2385 {
2386         u32     v;
2387         u8      save_exclude;
2388
2389         if (off > 0)
2390                 return 0;
2391         if (count <= 0)
2392                 return -EINVAL;
2393
2394         if (sscanf(buf, "%i", &v) == 1) {
2395                 if (down_interruptible(&mv64xxx_hs_lock))
2396                         return -ERESTARTSYS;
2397                 save_exclude = mv64x60_pci_exclude_bridge;
2398                 mv64x60_pci_exclude_bridge = 0;
2399                 early_write_config_dword(&sysfs_hose_a, 0, PCI_DEVFN(0, 0),
2400                                 MV64360_PCICFG_CPCI_HOTSWAP, v);
2401                 mv64x60_pci_exclude_bridge = save_exclude;
2402                 up(&mv64xxx_hs_lock);
2403         }
2404         else
2405                 count = -EINVAL;
2406
2407         return count;
2408 }
2409
2410 static struct bin_attribute mv64xxx_hs_reg_attr = { /* Hotswap register */
2411         .attr = {
2412                 .name = "hs_reg",
2413                 .mode = S_IRUGO | S_IWUSR,
2414                 .owner = THIS_MODULE,
2415         },
2416         .size  = VAL_LEN_MAX,
2417         .read  = mv64xxx_hs_reg_read,
2418         .write = mv64xxx_hs_reg_write,
2419 };
2420
2421 /* Provide sysfs file indicating if this platform supports the hs_reg */
2422 static ssize_t
2423 mv64xxx_hs_reg_valid_show(struct device *dev, struct device_attribute *attr,
2424                 char *buf)
2425 {
2426         struct platform_device  *pdev;
2427         struct mv64xxx_pdata    *pdp;
2428         u32                     v;
2429
2430         pdev = container_of(dev, struct platform_device, dev);
2431         pdp = (struct mv64xxx_pdata *)pdev->dev.platform_data;
2432
2433         if (down_interruptible(&mv64xxx_hs_lock))
2434                 return -ERESTARTSYS;
2435         v = pdp->hs_reg_valid;
2436         up(&mv64xxx_hs_lock);
2437
2438         return sprintf(buf, "%i\n", v);
2439 }
2440 static DEVICE_ATTR(hs_reg_valid, S_IRUGO, mv64xxx_hs_reg_valid_show, NULL);
2441
2442 static int __init
2443 mv64xxx_sysfs_init(void)
2444 {
2445         sysfs_create_bin_file(&mv64xxx_device.dev.kobj, &mv64xxx_hs_reg_attr);
2446         sysfs_create_file(&mv64xxx_device.dev.kobj,&dev_attr_hs_reg_valid.attr);
2447         return 0;
2448 }
2449 subsys_initcall(mv64xxx_sysfs_init);
2450 #endif