git.oblomov.eu Git - linux-2.6/blob - drivers/net/s2io.c

   1 /************************************************************************
   2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3  * Copyright(c) 2002-2005 Neterion Inc.
   4
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  *
  13  * Credits:
  14  * Jeff Garzik          : For pointing out the improper error condition
  15  *                        check in the s2io_xmit routine and also some
  16  *                        issues in the Tx watch dog function. Also for
  17  *                        patiently answering all those innumerable
  18  *                        questions regaring the 2.6 porting issues.
  19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
  20  *                        macros available only in 2.6 Kernel.
  21  * Francois Romieu      : For pointing out all code part that were
  22  *                        deprecated and also styling related comments.
  23  * Grant Grundler       : For helping me get rid of some Architecture
  24  *                        dependent code.
  25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
  26  *
  27  * The module loadable parameters that are supported by the driver and a brief
  28  * explaination of all the variables.
  29  * rx_ring_num : This can be used to program the number of receive rings used
  30  * in the driver.
  31  * rx_ring_sz: This defines the number of descriptors each ring can have. This
  32  * is also an array of size 8.
  33  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
  34  *              values are 1, 2 and 3.
  35  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
  36  * tx_fifo_len: This too is an array of 8. Each element defines the number of
  37  * Tx descriptors that can be associated with each corresponding FIFO.
  38  ************************************************************************/
  39
  40 #include <linux/config.h>
  41 #include <linux/module.h>
  42 #include <linux/types.h>
  43 #include <linux/errno.h>
  44 #include <linux/ioport.h>
  45 #include <linux/pci.h>
  46 #include <linux/dma-mapping.h>
  47 #include <linux/kernel.h>
  48 #include <linux/netdevice.h>
  49 #include <linux/etherdevice.h>
  50 #include <linux/skbuff.h>
  51 #include <linux/init.h>
  52 #include <linux/delay.h>
  53 #include <linux/stddef.h>
  54 #include <linux/ioctl.h>
  55 #include <linux/timex.h>
  56 #include <linux/sched.h>
  57 #include <linux/ethtool.h>
  58 #include <linux/version.h>
  59 #include <linux/workqueue.h>
  60 #include <linux/if_vlan.h>
  61
  62 #include <asm/system.h>
  63 #include <asm/uaccess.h>
  64 #include <asm/io.h>
  65
  66 /* local include */
  67 #include "s2io.h"
  68 #include "s2io-regs.h"
  69
  70 #define DRV_VERSION "Version 2.0.9.3"
  71
  72 /* S2io Driver name & version. */
  73 static char s2io_driver_name[] = "Neterion";
  74 static char s2io_driver_version[] = DRV_VERSION;
  75
  76 int rxd_size[4] = {32,48,48,64};
  77 int rxd_count[4] = {127,85,85,63};
  78
  79 static inline int RXD_IS_UP2DT(RxD_t *rxdp)
  80 {
  81         int ret;
  82
  83         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
  84                 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
  85
  86         return ret;
  87 }
  88
  89 /*
  90  * Cards with following subsystem_id have a link state indication
  91  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
  92  * macro below identifies these cards given the subsystem_id.
  93  */
  94 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
  95         (dev_type == XFRAME_I_DEVICE) ?                 \
  96                 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
  97                  ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
  98
  99 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
 100                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
 101 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
 102 #define PANIC   1
 103 #define LOW     2
 104 static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
 105 {
 106         int level = 0;
 107         mac_info_t *mac_control;
 108
 109         mac_control = &sp->mac_control;
 110         if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16) {
 111                 level = LOW;
 112                 if (rxb_size <= rxd_count[sp->rxd_mode]) {
 113                         level = PANIC;
 114                 }
 115         }
 116
 117         return level;
 118 }
 119
 120 /* Ethtool related variables and Macros. */
 121 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
 122         "Register test\t(offline)",
 123         "Eeprom test\t(offline)",
 124         "Link test\t(online)",
 125         "RLDRAM test\t(offline)",
 126         "BIST Test\t(offline)"
 127 };
 128
 129 static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
 130         {"tmac_frms"},
 131         {"tmac_data_octets"},
 132         {"tmac_drop_frms"},
 133         {"tmac_mcst_frms"},
 134         {"tmac_bcst_frms"},
 135         {"tmac_pause_ctrl_frms"},
 136         {"tmac_any_err_frms"},
 137         {"tmac_vld_ip_octets"},
 138         {"tmac_vld_ip"},
 139         {"tmac_drop_ip"},
 140         {"tmac_icmp"},
 141         {"tmac_rst_tcp"},
 142         {"tmac_tcp"},
 143         {"tmac_udp"},
 144         {"rmac_vld_frms"},
 145         {"rmac_data_octets"},
 146         {"rmac_fcs_err_frms"},
 147         {"rmac_drop_frms"},
 148         {"rmac_vld_mcst_frms"},
 149         {"rmac_vld_bcst_frms"},
 150         {"rmac_in_rng_len_err_frms"},
 151         {"rmac_long_frms"},
 152         {"rmac_pause_ctrl_frms"},
 153         {"rmac_discarded_frms"},
 154         {"rmac_usized_frms"},
 155         {"rmac_osized_frms"},
 156         {"rmac_frag_frms"},
 157         {"rmac_jabber_frms"},
 158         {"rmac_ip"},
 159         {"rmac_ip_octets"},
 160         {"rmac_hdr_err_ip"},
 161         {"rmac_drop_ip"},
 162         {"rmac_icmp"},
 163         {"rmac_tcp"},
 164         {"rmac_udp"},
 165         {"rmac_err_drp_udp"},
 166         {"rmac_pause_cnt"},
 167         {"rmac_accepted_ip"},
 168         {"rmac_err_tcp"},
 169         {"\n DRIVER STATISTICS"},
 170         {"single_bit_ecc_errs"},
 171         {"double_bit_ecc_errs"},
 172 };
 173
 174 #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
 175 #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
 176
 177 #define S2IO_TEST_LEN   sizeof(s2io_gstrings) / ETH_GSTRING_LEN
 178 #define S2IO_STRINGS_LEN        S2IO_TEST_LEN * ETH_GSTRING_LEN
 179
 180 #define S2IO_TIMER_CONF(timer, handle, arg, exp)                \
 181                         init_timer(&timer);                     \
 182                         timer.function = handle;                \
 183                         timer.data = (unsigned long) arg;       \
 184                         mod_timer(&timer, (jiffies + exp))      \
 185
 186 /* Add the vlan */
 187 static void s2io_vlan_rx_register(struct net_device *dev,
 188                                         struct vlan_group *grp)
 189 {
 190         nic_t *nic = dev->priv;
 191         unsigned long flags;
 192
 193         spin_lock_irqsave(&nic->tx_lock, flags);
 194         nic->vlgrp = grp;
 195         spin_unlock_irqrestore(&nic->tx_lock, flags);
 196 }
 197
 198 /* Unregister the vlan */
 199 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
 200 {
 201         nic_t *nic = dev->priv;
 202         unsigned long flags;
 203
 204         spin_lock_irqsave(&nic->tx_lock, flags);
 205         if (nic->vlgrp)
 206                 nic->vlgrp->vlan_devices[vid] = NULL;
 207         spin_unlock_irqrestore(&nic->tx_lock, flags);
 208 }
 209
 210 /*
 211  * Constants to be programmed into the Xena's registers, to configure
 212  * the XAUI.
 213  */
 214
 215 #define SWITCH_SIGN     0xA5A5A5A5A5A5A5A5ULL
 216 #define END_SIGN        0x0
 217
 218 static u64 herc_act_dtx_cfg[] = {
 219         /* Set address */
 220         0x8000051536750000ULL, 0x80000515367500E0ULL,
 221         /* Write data */
 222         0x8000051536750004ULL, 0x80000515367500E4ULL,
 223         /* Set address */
 224         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
 225         /* Write data */
 226         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
 227         /* Set address */
 228         0x801205150D440000ULL, 0x801205150D4400E0ULL,
 229         /* Write data */
 230         0x801205150D440004ULL, 0x801205150D4400E4ULL,
 231         /* Set address */
 232         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
 233         /* Write data */
 234         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 235         /* Done */
 236         END_SIGN
 237 };
 238
 239 static u64 xena_mdio_cfg[] = {
 240         /* Reset PMA PLL */
 241         0xC001010000000000ULL, 0xC0010100000000E0ULL,
 242         0xC0010100008000E4ULL,
 243         /* Remove Reset from PMA PLL */
 244         0xC001010000000000ULL, 0xC0010100000000E0ULL,
 245         0xC0010100000000E4ULL,
 246         END_SIGN
 247 };
 248
 249 static u64 xena_dtx_cfg[] = {
 250         0x8000051500000000ULL, 0x80000515000000E0ULL,
 251         0x80000515D93500E4ULL, 0x8001051500000000ULL,
 252         0x80010515000000E0ULL, 0x80010515001E00E4ULL,
 253         0x8002051500000000ULL, 0x80020515000000E0ULL,
 254         0x80020515F21000E4ULL,
 255         /* Set PADLOOPBACKN */
 256         0x8002051500000000ULL, 0x80020515000000E0ULL,
 257         0x80020515B20000E4ULL, 0x8003051500000000ULL,
 258         0x80030515000000E0ULL, 0x80030515B20000E4ULL,
 259         0x8004051500000000ULL, 0x80040515000000E0ULL,
 260         0x80040515B20000E4ULL, 0x8005051500000000ULL,
 261         0x80050515000000E0ULL, 0x80050515B20000E4ULL,
 262         SWITCH_SIGN,
 263         /* Remove PADLOOPBACKN */
 264         0x8002051500000000ULL, 0x80020515000000E0ULL,
 265         0x80020515F20000E4ULL, 0x8003051500000000ULL,
 266         0x80030515000000E0ULL, 0x80030515F20000E4ULL,
 267         0x8004051500000000ULL, 0x80040515000000E0ULL,
 268         0x80040515F20000E4ULL, 0x8005051500000000ULL,
 269         0x80050515000000E0ULL, 0x80050515F20000E4ULL,
 270         END_SIGN
 271 };
 272
 273 /*
 274  * Constants for Fixing the MacAddress problem seen mostly on
 275  * Alpha machines.
 276  */
 277 static u64 fix_mac[] = {
 278         0x0060000000000000ULL, 0x0060600000000000ULL,
 279         0x0040600000000000ULL, 0x0000600000000000ULL,
 280         0x0020600000000000ULL, 0x0060600000000000ULL,
 281         0x0020600000000000ULL, 0x0060600000000000ULL,
 282         0x0020600000000000ULL, 0x0060600000000000ULL,
 283         0x0020600000000000ULL, 0x0060600000000000ULL,
 284         0x0020600000000000ULL, 0x0060600000000000ULL,
 285         0x0020600000000000ULL, 0x0060600000000000ULL,
 286         0x0020600000000000ULL, 0x0060600000000000ULL,
 287         0x0020600000000000ULL, 0x0060600000000000ULL,
 288         0x0020600000000000ULL, 0x0060600000000000ULL,
 289         0x0020600000000000ULL, 0x0060600000000000ULL,
 290         0x0020600000000000ULL, 0x0000600000000000ULL,
 291         0x0040600000000000ULL, 0x0060600000000000ULL,
 292         END_SIGN
 293 };
 294
 295 /* Module Loadable parameters. */
 296 static unsigned int tx_fifo_num = 1;
 297 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
 298     {[0 ...(MAX_TX_FIFOS - 1)] = 0 };
 299 static unsigned int rx_ring_num = 1;
 300 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
 301     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
 302 static unsigned int rts_frm_len[MAX_RX_RINGS] =
 303     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
 304 static unsigned int rx_ring_mode = 1;
 305 static unsigned int use_continuous_tx_intrs = 1;
 306 static unsigned int rmac_pause_time = 65535;
 307 static unsigned int mc_pause_threshold_q0q3 = 187;
 308 static unsigned int mc_pause_threshold_q4q7 = 187;
 309 static unsigned int shared_splits;
 310 static unsigned int tmac_util_period = 5;
 311 static unsigned int rmac_util_period = 5;
 312 static unsigned int bimodal = 0;
 313 static unsigned int l3l4hdr_size = 128;
 314 #ifndef CONFIG_S2IO_NAPI
 315 static unsigned int indicate_max_pkts;
 316 #endif
 317 /* Frequency of Rx desc syncs expressed as power of 2 */
 318 static unsigned int rxsync_frequency = 3;
 319 /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
 320 static unsigned int intr_type = 0;
 321
 322 /*
 323  * S2IO device table.
 324  * This table lists all the devices that this driver supports.
 325  */
 326 static struct pci_device_id s2io_tbl[] __devinitdata = {
 327         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
 328          PCI_ANY_ID, PCI_ANY_ID},
 329         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
 330          PCI_ANY_ID, PCI_ANY_ID},
 331         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
 332          PCI_ANY_ID, PCI_ANY_ID},
 333         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
 334          PCI_ANY_ID, PCI_ANY_ID},
 335         {0,}
 336 };
 337
 338 MODULE_DEVICE_TABLE(pci, s2io_tbl);
 339
 340 static struct pci_driver s2io_driver = {
 341       .name = "S2IO",
 342       .id_table = s2io_tbl,
 343       .probe = s2io_init_nic,
 344       .remove = __devexit_p(s2io_rem_nic),
 345 };
 346
 347 /* A simplifier macro used both by init and free shared_mem Fns(). */
 348 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
 349
 350 /**
 351  * init_shared_mem - Allocation and Initialization of Memory
 352  * @nic: Device private variable.
 353  * Description: The function allocates all the memory areas shared
 354  * between the NIC and the driver. This includes Tx descriptors,
 355  * Rx descriptors and the statistics block.
 356  */
 357
 358 static int init_shared_mem(struct s2io_nic *nic)
 359 {
 360         u32 size;
 361         void *tmp_v_addr, *tmp_v_addr_next;
 362         dma_addr_t tmp_p_addr, tmp_p_addr_next;
 363         RxD_block_t *pre_rxd_blk = NULL;
 364         int i, j, blk_cnt, rx_sz, tx_sz;
 365         int lst_size, lst_per_page;
 366         struct net_device *dev = nic->dev;
 367         unsigned long tmp;
 368         buffAdd_t *ba;
 369
 370         mac_info_t *mac_control;
 371         struct config_param *config;
 372
 373         mac_control = &nic->mac_control;
 374         config = &nic->config;
 375
 376
 377         /* Allocation and initialization of TXDLs in FIOFs */
 378         size = 0;
 379         for (i = 0; i < config->tx_fifo_num; i++) {
 380                 size += config->tx_cfg[i].fifo_len;
 381         }
 382         if (size > MAX_AVAILABLE_TXDS) {
 383                 DBG_PRINT(ERR_DBG, "%s: Requested TxDs too high, ",
 384                           __FUNCTION__);
 385                 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
 386                 return FAILURE;
 387         }
 388
 389         lst_size = (sizeof(TxD_t) * config->max_txds);
 390         tx_sz = lst_size * size;
 391         lst_per_page = PAGE_SIZE / lst_size;
 392
 393         for (i = 0; i < config->tx_fifo_num; i++) {
 394                 int fifo_len = config->tx_cfg[i].fifo_len;
 395                 int list_holder_size = fifo_len * sizeof(list_info_hold_t);
 396                 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
 397                                                           GFP_KERNEL);
 398                 if (!mac_control->fifos[i].list_info) {
 399                         DBG_PRINT(ERR_DBG,
 400                                   "Malloc failed for list_info\n");
 401                         return -ENOMEM;
 402                 }
 403                 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
 404         }
 405         for (i = 0; i < config->tx_fifo_num; i++) {
 406                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 407                                                 lst_per_page);
 408                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
 409                 mac_control->fifos[i].tx_curr_put_info.fifo_len =
 410                     config->tx_cfg[i].fifo_len - 1;
 411                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
 412                 mac_control->fifos[i].tx_curr_get_info.fifo_len =
 413                     config->tx_cfg[i].fifo_len - 1;
 414                 mac_control->fifos[i].fifo_no = i;
 415                 mac_control->fifos[i].nic = nic;
 416                 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 1;
 417
 418                 for (j = 0; j < page_num; j++) {
 419                         int k = 0;
 420                         dma_addr_t tmp_p;
 421                         void *tmp_v;
 422                         tmp_v = pci_alloc_consistent(nic->pdev,
 423                                                      PAGE_SIZE, &tmp_p);
 424                         if (!tmp_v) {
 425                                 DBG_PRINT(ERR_DBG,
 426                                           "pci_alloc_consistent ");
 427                                 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
 428                                 return -ENOMEM;
 429                         }
 430                         /* If we got a zero DMA address(can happen on
 431                          * certain platforms like PPC), reallocate.
 432                          * Store virtual address of page we don't want,
 433                          * to be freed later.
 434                          */
 435                         if (!tmp_p) {
 436                                 mac_control->zerodma_virt_addr = tmp_v;
 437                                 DBG_PRINT(INIT_DBG,
 438                                 "%s: Zero DMA address for TxDL. ", dev->name);
 439                                 DBG_PRINT(INIT_DBG,
 440                                 "Virtual address %p\n", tmp_v);
 441                                 tmp_v = pci_alloc_consistent(nic->pdev,
 442                                                      PAGE_SIZE, &tmp_p);
 443                                 if (!tmp_v) {
 444                                         DBG_PRINT(ERR_DBG,
 445                                           "pci_alloc_consistent ");
 446                                         DBG_PRINT(ERR_DBG, "failed for TxDL\n");
 447                                         return -ENOMEM;
 448                                 }
 449                         }
 450                         while (k < lst_per_page) {
 451                                 int l = (j * lst_per_page) + k;
 452                                 if (l == config->tx_cfg[i].fifo_len)
 453                                         break;
 454                                 mac_control->fifos[i].list_info[l].list_virt_addr =
 455                                     tmp_v + (k * lst_size);
 456                                 mac_control->fifos[i].list_info[l].list_phy_addr =
 457                                     tmp_p + (k * lst_size);
 458                                 k++;
 459                         }
 460                 }
 461         }
 462
 463         /* Allocation and initialization of RXDs in Rings */
 464         size = 0;
 465         for (i = 0; i < config->rx_ring_num; i++) {
 466                 if (config->rx_cfg[i].num_rxd %
 467                     (rxd_count[nic->rxd_mode] + 1)) {
 468                         DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
 469                         DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
 470                                   i);
 471                         DBG_PRINT(ERR_DBG, "RxDs per Block");
 472                         return FAILURE;
 473                 }
 474                 size += config->rx_cfg[i].num_rxd;
 475                 mac_control->rings[i].block_count =
 476                         config->rx_cfg[i].num_rxd /
 477                         (rxd_count[nic->rxd_mode] + 1 );
 478                 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
 479                         mac_control->rings[i].block_count;
 480         }
 481         if (nic->rxd_mode == RXD_MODE_1)
 482                 size = (size * (sizeof(RxD1_t)));
 483         else
 484                 size = (size * (sizeof(RxD3_t)));
 485         rx_sz = size;
 486
 487         for (i = 0; i < config->rx_ring_num; i++) {
 488                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
 489                 mac_control->rings[i].rx_curr_get_info.offset = 0;
 490                 mac_control->rings[i].rx_curr_get_info.ring_len =
 491                     config->rx_cfg[i].num_rxd - 1;
 492                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
 493                 mac_control->rings[i].rx_curr_put_info.offset = 0;
 494                 mac_control->rings[i].rx_curr_put_info.ring_len =
 495                     config->rx_cfg[i].num_rxd - 1;
 496                 mac_control->rings[i].nic = nic;
 497                 mac_control->rings[i].ring_no = i;
 498
 499                 blk_cnt = config->rx_cfg[i].num_rxd /
 500                                 (rxd_count[nic->rxd_mode] + 1);
 501                 /*  Allocating all the Rx blocks */
 502                 for (j = 0; j < blk_cnt; j++) {
 503                         rx_block_info_t *rx_blocks;
 504                         int l;
 505
 506                         rx_blocks = &mac_control->rings[i].rx_blocks[j];
 507                         size = SIZE_OF_BLOCK; //size is always page size
 508                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
 509                                                           &tmp_p_addr);
 510                         if (tmp_v_addr == NULL) {
 511                                 /*
 512                                  * In case of failure, free_shared_mem()
 513                                  * is called, which should free any
 514                                  * memory that was alloced till the
 515                                  * failure happened.
 516                                  */
 517                                 rx_blocks->block_virt_addr = tmp_v_addr;
 518                                 return -ENOMEM;
 519                         }
 520                         memset(tmp_v_addr, 0, size);
 521                         rx_blocks->block_virt_addr = tmp_v_addr;
 522                         rx_blocks->block_dma_addr = tmp_p_addr;
 523                         rx_blocks->rxds = kmalloc(sizeof(rxd_info_t)*
 524                                                   rxd_count[nic->rxd_mode],
 525                                                   GFP_KERNEL);
 526                         for (l=0; l<rxd_count[nic->rxd_mode];l++) {
 527                                 rx_blocks->rxds[l].virt_addr =
 528                                         rx_blocks->block_virt_addr +
 529                                         (rxd_size[nic->rxd_mode] * l);
 530                                 rx_blocks->rxds[l].dma_addr =
 531                                         rx_blocks->block_dma_addr +
 532                                         (rxd_size[nic->rxd_mode] * l);
 533                         }
 534
 535                         mac_control->rings[i].rx_blocks[j].block_virt_addr =
 536                                 tmp_v_addr;
 537                         mac_control->rings[i].rx_blocks[j].block_dma_addr =
 538                                 tmp_p_addr;
 539                 }
 540                 /* Interlinking all Rx Blocks */
 541                 for (j = 0; j < blk_cnt; j++) {
 542                         tmp_v_addr =
 543                                 mac_control->rings[i].rx_blocks[j].block_virt_addr;
 544                         tmp_v_addr_next =
 545                                 mac_control->rings[i].rx_blocks[(j + 1) %
 546                                               blk_cnt].block_virt_addr;
 547                         tmp_p_addr =
 548                                 mac_control->rings[i].rx_blocks[j].block_dma_addr;
 549                         tmp_p_addr_next =
 550                                 mac_control->rings[i].rx_blocks[(j + 1) %
 551                                               blk_cnt].block_dma_addr;
 552
 553                         pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
 554                         pre_rxd_blk->reserved_2_pNext_RxD_block =
 555                             (unsigned long) tmp_v_addr_next;
 556                         pre_rxd_blk->pNext_RxD_Blk_physical =
 557                             (u64) tmp_p_addr_next;
 558                 }
 559         }
 560         if (nic->rxd_mode >= RXD_MODE_3A) {
 561                 /*
 562                  * Allocation of Storages for buffer addresses in 2BUFF mode
 563                  * and the buffers as well.
 564                  */
 565                 for (i = 0; i < config->rx_ring_num; i++) {
 566                         blk_cnt = config->rx_cfg[i].num_rxd /
 567                            (rxd_count[nic->rxd_mode]+ 1);
 568                         mac_control->rings[i].ba =
 569                                 kmalloc((sizeof(buffAdd_t *) * blk_cnt),
 570                                      GFP_KERNEL);
 571                         if (!mac_control->rings[i].ba)
 572                                 return -ENOMEM;
 573                         for (j = 0; j < blk_cnt; j++) {
 574                                 int k = 0;
 575                                 mac_control->rings[i].ba[j] =
 576                                         kmalloc((sizeof(buffAdd_t) *
 577                                                 (rxd_count[nic->rxd_mode] + 1)),
 578                                                 GFP_KERNEL);
 579                                 if (!mac_control->rings[i].ba[j])
 580                                         return -ENOMEM;
 581                                 while (k != rxd_count[nic->rxd_mode]) {
 582                                         ba = &mac_control->rings[i].ba[j][k];
 583
 584                                         ba->ba_0_org = (void *) kmalloc
 585                                             (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
 586                                         if (!ba->ba_0_org)
 587                                                 return -ENOMEM;
 588                                         tmp = (unsigned long)ba->ba_0_org;
 589                                         tmp += ALIGN_SIZE;
 590                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 591                                         ba->ba_0 = (void *) tmp;
 592
 593                                         ba->ba_1_org = (void *) kmalloc
 594                                             (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
 595                                         if (!ba->ba_1_org)
 596                                                 return -ENOMEM;
 597                                         tmp = (unsigned long) ba->ba_1_org;
 598                                         tmp += ALIGN_SIZE;
 599                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 600                                         ba->ba_1 = (void *) tmp;
 601                                         k++;
 602                                 }
 603                         }
 604                 }
 605         }
 606
 607         /* Allocation and initialization of Statistics block */
 608         size = sizeof(StatInfo_t);
 609         mac_control->stats_mem = pci_alloc_consistent
 610             (nic->pdev, size, &mac_control->stats_mem_phy);
 611
 612         if (!mac_control->stats_mem) {
 613                 /*
 614                  * In case of failure, free_shared_mem() is called, which
 615                  * should free any memory that was alloced till the
 616                  * failure happened.
 617                  */
 618                 return -ENOMEM;
 619         }
 620         mac_control->stats_mem_sz = size;
 621
 622         tmp_v_addr = mac_control->stats_mem;
 623         mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
 624         memset(tmp_v_addr, 0, size);
 625         DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
 626                   (unsigned long long) tmp_p_addr);
 627
 628         return SUCCESS;
 629 }
 630
 631 /**
 632  * free_shared_mem - Free the allocated Memory
 633  * @nic:  Device private variable.
 634  * Description: This function is to free all memory locations allocated by
 635  * the init_shared_mem() function and return it to the kernel.
 636  */
 637
 638 static void free_shared_mem(struct s2io_nic *nic)
 639 {
 640         int i, j, blk_cnt, size;
 641         void *tmp_v_addr;
 642         dma_addr_t tmp_p_addr;
 643         mac_info_t *mac_control;
 644         struct config_param *config;
 645         int lst_size, lst_per_page;
 646         struct net_device *dev = nic->dev;
 647
 648         if (!nic)
 649                 return;
 650
 651         mac_control = &nic->mac_control;
 652         config = &nic->config;
 653
 654         lst_size = (sizeof(TxD_t) * config->max_txds);
 655         lst_per_page = PAGE_SIZE / lst_size;
 656
 657         for (i = 0; i < config->tx_fifo_num; i++) {
 658                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 659                                                 lst_per_page);
 660                 for (j = 0; j < page_num; j++) {
 661                         int mem_blks = (j * lst_per_page);
 662                         if (!mac_control->fifos[i].list_info)
 663                                 return;
 664                         if (!mac_control->fifos[i].list_info[mem_blks].
 665                                  list_virt_addr)
 666                                 break;
 667                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 668                                             mac_control->fifos[i].
 669                                             list_info[mem_blks].
 670                                             list_virt_addr,
 671                                             mac_control->fifos[i].
 672                                             list_info[mem_blks].
 673                                             list_phy_addr);
 674                 }
 675                 /* If we got a zero DMA address during allocation,
 676                  * free the page now
 677                  */
 678                 if (mac_control->zerodma_virt_addr) {
 679                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 680                                             mac_control->zerodma_virt_addr,
 681                                             (dma_addr_t)0);
 682                         DBG_PRINT(INIT_DBG,
 683                                 "%s: Freeing TxDL with zero DMA addr. ",
 684                                 dev->name);
 685                         DBG_PRINT(INIT_DBG, "Virtual address %p\n",
 686                                 mac_control->zerodma_virt_addr);
 687                 }
 688                 kfree(mac_control->fifos[i].list_info);
 689         }
 690
 691         size = SIZE_OF_BLOCK;
 692         for (i = 0; i < config->rx_ring_num; i++) {
 693                 blk_cnt = mac_control->rings[i].block_count;
 694                 for (j = 0; j < blk_cnt; j++) {
 695                         tmp_v_addr = mac_control->rings[i].rx_blocks[j].
 696                                 block_virt_addr;
 697                         tmp_p_addr = mac_control->rings[i].rx_blocks[j].
 698                                 block_dma_addr;
 699                         if (tmp_v_addr == NULL)
 700                                 break;
 701                         pci_free_consistent(nic->pdev, size,
 702                                             tmp_v_addr, tmp_p_addr);
 703                         kfree(mac_control->rings[i].rx_blocks[j].rxds);
 704                 }
 705         }
 706
 707         if (nic->rxd_mode >= RXD_MODE_3A) {
 708                 /* Freeing buffer storage addresses in 2BUFF mode. */
 709                 for (i = 0; i < config->rx_ring_num; i++) {
 710                         blk_cnt = config->rx_cfg[i].num_rxd /
 711                             (rxd_count[nic->rxd_mode] + 1);
 712                         for (j = 0; j < blk_cnt; j++) {
 713                                 int k = 0;
 714                                 if (!mac_control->rings[i].ba[j])
 715                                         continue;
 716                                 while (k != rxd_count[nic->rxd_mode]) {
 717                                         buffAdd_t *ba =
 718                                                 &mac_control->rings[i].ba[j][k];
 719                                         kfree(ba->ba_0_org);
 720                                         kfree(ba->ba_1_org);
 721                                         k++;
 722                                 }
 723                                 kfree(mac_control->rings[i].ba[j]);
 724                         }
 725                         kfree(mac_control->rings[i].ba);
 726                 }
 727         }
 728
 729         if (mac_control->stats_mem) {
 730                 pci_free_consistent(nic->pdev,
 731                                     mac_control->stats_mem_sz,
 732                                     mac_control->stats_mem,
 733                                     mac_control->stats_mem_phy);
 734         }
 735 }
 736
 737 /**
 738  * s2io_verify_pci_mode -
 739  */
 740
 741 static int s2io_verify_pci_mode(nic_t *nic)
 742 {
 743         XENA_dev_config_t __iomem *bar0 = nic->bar0;
 744         register u64 val64 = 0;
 745         int     mode;
 746
 747         val64 = readq(&bar0->pci_mode);
 748         mode = (u8)GET_PCI_MODE(val64);
 749
 750         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 751                 return -1;      /* Unknown PCI mode */
 752         return mode;
 753 }
 754
 755
 756 /**
 757  * s2io_print_pci_mode -
 758  */
 759 static int s2io_print_pci_mode(nic_t *nic)
 760 {
 761         XENA_dev_config_t __iomem *bar0 = nic->bar0;
 762         register u64 val64 = 0;
 763         int     mode;
 764         struct config_param *config = &nic->config;
 765
 766         val64 = readq(&bar0->pci_mode);
 767         mode = (u8)GET_PCI_MODE(val64);
 768
 769         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 770                 return -1;      /* Unknown PCI mode */
 771
 772         if (val64 & PCI_MODE_32_BITS) {
 773                 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
 774         } else {
 775                 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
 776         }
 777
 778         switch(mode) {
 779                 case PCI_MODE_PCI_33:
 780                         DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
 781                         config->bus_speed = 33;
 782                         break;
 783                 case PCI_MODE_PCI_66:
 784                         DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
 785                         config->bus_speed = 133;
 786                         break;
 787                 case PCI_MODE_PCIX_M1_66:
 788                         DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
 789                         config->bus_speed = 133; /* Herc doubles the clock rate */
 790                         break;
 791                 case PCI_MODE_PCIX_M1_100:
 792                         DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
 793                         config->bus_speed = 200;
 794                         break;
 795                 case PCI_MODE_PCIX_M1_133:
 796                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
 797                         config->bus_speed = 266;
 798                         break;
 799                 case PCI_MODE_PCIX_M2_66:
 800                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
 801                         config->bus_speed = 133;
 802                         break;
 803                 case PCI_MODE_PCIX_M2_100:
 804                         DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
 805                         config->bus_speed = 200;
 806                         break;
 807                 case PCI_MODE_PCIX_M2_133:
 808                         DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
 809                         config->bus_speed = 266;
 810                         break;
 811                 default:
 812                         return -1;      /* Unsupported bus speed */
 813         }
 814
 815         return mode;
 816 }
 817
 818 /**
 819  *  init_nic - Initialization of hardware
 820  *  @nic: device peivate variable
 821  *  Description: The function sequentially configures every block
 822  *  of the H/W from their reset values.
 823  *  Return Value:  SUCCESS on success and
 824  *  '-1' on failure (endian settings incorrect).
 825  */
 826
 827 static int init_nic(struct s2io_nic *nic)
 828 {
 829         XENA_dev_config_t __iomem *bar0 = nic->bar0;
 830         struct net_device *dev = nic->dev;
 831         register u64 val64 = 0;
 832         void __iomem *add;
 833         u32 time;
 834         int i, j;
 835         mac_info_t *mac_control;
 836         struct config_param *config;
 837         int mdio_cnt = 0, dtx_cnt = 0;
 838         unsigned long long mem_share;
 839         int mem_size;
 840
 841         mac_control = &nic->mac_control;
 842         config = &nic->config;
 843
 844         /* to set the swapper controle on the card */
 845         if(s2io_set_swapper(nic)) {
 846                 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
 847                 return -1;
 848         }
 849
 850         /*
 851          * Herc requires EOI to be removed from reset before XGXS, so..
 852          */
 853         if (nic->device_type & XFRAME_II_DEVICE) {
 854                 val64 = 0xA500000000ULL;
 855                 writeq(val64, &bar0->sw_reset);
 856                 msleep(500);
 857                 val64 = readq(&bar0->sw_reset);
 858         }
 859
 860         /* Remove XGXS from reset state */
 861         val64 = 0;
 862         writeq(val64, &bar0->sw_reset);
 863         msleep(500);
 864         val64 = readq(&bar0->sw_reset);
 865
 866         /*  Enable Receiving broadcasts */
 867         add = &bar0->mac_cfg;
 868         val64 = readq(&bar0->mac_cfg);
 869         val64 |= MAC_RMAC_BCAST_ENABLE;
 870         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
 871         writel((u32) val64, add);
 872         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
 873         writel((u32) (val64 >> 32), (add + 4));
 874
 875         /* Read registers in all blocks */
 876         val64 = readq(&bar0->mac_int_mask);
 877         val64 = readq(&bar0->mc_int_mask);
 878         val64 = readq(&bar0->xgxs_int_mask);
 879
 880         /*  Set MTU */
 881         val64 = dev->mtu;
 882         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
 883
 884         /*
 885          * Configuring the XAUI Interface of Xena.
 886          * ***************************************
 887          * To Configure the Xena's XAUI, one has to write a series
 888          * of 64 bit values into two registers in a particular
 889          * sequence. Hence a macro 'SWITCH_SIGN' has been defined
 890          * which will be defined in the array of configuration values
 891          * (xena_dtx_cfg & xena_mdio_cfg) at appropriate places
 892          * to switch writing from one regsiter to another. We continue
 893          * writing these values until we encounter the 'END_SIGN' macro.
 894          * For example, After making a series of 21 writes into
 895          * dtx_control register the 'SWITCH_SIGN' appears and hence we
 896          * start writing into mdio_control until we encounter END_SIGN.
 897          */
 898         if (nic->device_type & XFRAME_II_DEVICE) {
 899                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
 900                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
 901                                           &bar0->dtx_control, UF);
 902                         if (dtx_cnt & 0x1)
 903                                 msleep(1); /* Necessary!! */
 904                         dtx_cnt++;
 905                 }
 906         } else {
 907                 while (1) {
 908                       dtx_cfg:
 909                         while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
 910                                 if (xena_dtx_cfg[dtx_cnt] == SWITCH_SIGN) {
 911                                         dtx_cnt++;
 912                                         goto mdio_cfg;
 913                                 }
 914                                 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
 915                                                   &bar0->dtx_control, UF);
 916                                 val64 = readq(&bar0->dtx_control);
 917                                 dtx_cnt++;
 918                         }
 919                       mdio_cfg:
 920                         while (xena_mdio_cfg[mdio_cnt] != END_SIGN) {
 921                                 if (xena_mdio_cfg[mdio_cnt] == SWITCH_SIGN) {
 922                                         mdio_cnt++;
 923                                         goto dtx_cfg;
 924                                 }
 925                                 SPECIAL_REG_WRITE(xena_mdio_cfg[mdio_cnt],
 926                                                   &bar0->mdio_control, UF);
 927                                 val64 = readq(&bar0->mdio_control);
 928                                 mdio_cnt++;
 929                         }
 930                         if ((xena_dtx_cfg[dtx_cnt] == END_SIGN) &&
 931                             (xena_mdio_cfg[mdio_cnt] == END_SIGN)) {
 932                                 break;
 933                         } else {
 934                                 goto dtx_cfg;
 935                         }
 936                 }
 937         }
 938
 939         /*  Tx DMA Initialization */
 940         val64 = 0;
 941         writeq(val64, &bar0->tx_fifo_partition_0);
 942         writeq(val64, &bar0->tx_fifo_partition_1);
 943         writeq(val64, &bar0->tx_fifo_partition_2);
 944         writeq(val64, &bar0->tx_fifo_partition_3);
 945
 946
 947         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
 948                 val64 |=
 949                     vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
 950                          13) | vBIT(config->tx_cfg[i].fifo_priority,
 951                                     ((i * 32) + 5), 3);
 952
 953                 if (i == (config->tx_fifo_num - 1)) {
 954                         if (i % 2 == 0)
 955                                 i++;
 956                 }
 957
 958                 switch (i) {
 959                 case 1:
 960                         writeq(val64, &bar0->tx_fifo_partition_0);
 961                         val64 = 0;
 962                         break;
 963                 case 3:
 964                         writeq(val64, &bar0->tx_fifo_partition_1);
 965                         val64 = 0;
 966                         break;
 967                 case 5:
 968                         writeq(val64, &bar0->tx_fifo_partition_2);
 969                         val64 = 0;
 970                         break;
 971                 case 7:
 972                         writeq(val64, &bar0->tx_fifo_partition_3);
 973                         break;
 974                 }
 975         }
 976
 977         /* Enable Tx FIFO partition 0. */
 978         val64 = readq(&bar0->tx_fifo_partition_0);
 979         val64 |= BIT(0);        /* To enable the FIFO partition. */
 980         writeq(val64, &bar0->tx_fifo_partition_0);
 981
 982         /*
 983          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
 984          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
 985          */
 986         if ((nic->device_type == XFRAME_I_DEVICE) &&
 987                 (get_xena_rev_id(nic->pdev) < 4))
 988                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
 989
 990         val64 = readq(&bar0->tx_fifo_partition_0);
 991         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
 992                   &bar0->tx_fifo_partition_0, (unsigned long long) val64);
 993
 994         /*
 995          * Initialization of Tx_PA_CONFIG register to ignore packet
 996          * integrity checking.
 997          */
 998         val64 = readq(&bar0->tx_pa_cfg);
 999         val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1000             TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1001         writeq(val64, &bar0->tx_pa_cfg);
1002
1003         /* Rx DMA intialization. */
1004         val64 = 0;
1005         for (i = 0; i < config->rx_ring_num; i++) {
1006                 val64 |=
1007                     vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1008                          3);
1009         }
1010         writeq(val64, &bar0->rx_queue_priority);
1011
1012         /*
1013          * Allocating equal share of memory to all the
1014          * configured Rings.
1015          */
1016         val64 = 0;
1017         if (nic->device_type & XFRAME_II_DEVICE)
1018                 mem_size = 32;
1019         else
1020                 mem_size = 64;
1021
1022         for (i = 0; i < config->rx_ring_num; i++) {
1023                 switch (i) {
1024                 case 0:
1025                         mem_share = (mem_size / config->rx_ring_num +
1026                                      mem_size % config->rx_ring_num);
1027                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1028                         continue;
1029                 case 1:
1030                         mem_share = (mem_size / config->rx_ring_num);
1031                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1032                         continue;
1033                 case 2:
1034                         mem_share = (mem_size / config->rx_ring_num);
1035                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1036                         continue;
1037                 case 3:
1038                         mem_share = (mem_size / config->rx_ring_num);
1039                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1040                         continue;
1041                 case 4:
1042                         mem_share = (mem_size / config->rx_ring_num);
1043                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1044                         continue;
1045                 case 5:
1046                         mem_share = (mem_size / config->rx_ring_num);
1047                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1048                         continue;
1049                 case 6:
1050                         mem_share = (mem_size / config->rx_ring_num);
1051                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1052                         continue;
1053                 case 7:
1054                         mem_share = (mem_size / config->rx_ring_num);
1055                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1056                         continue;
1057                 }
1058         }
1059         writeq(val64, &bar0->rx_queue_cfg);
1060
1061         /*
1062          * Filling Tx round robin registers
1063          * as per the number of FIFOs
1064          */
1065         switch (config->tx_fifo_num) {
1066         case 1:
1067                 val64 = 0x0000000000000000ULL;
1068                 writeq(val64, &bar0->tx_w_round_robin_0);
1069                 writeq(val64, &bar0->tx_w_round_robin_1);
1070                 writeq(val64, &bar0->tx_w_round_robin_2);
1071                 writeq(val64, &bar0->tx_w_round_robin_3);
1072                 writeq(val64, &bar0->tx_w_round_robin_4);
1073                 break;
1074         case 2:
1075                 val64 = 0x0000010000010000ULL;
1076                 writeq(val64, &bar0->tx_w_round_robin_0);
1077                 val64 = 0x0100000100000100ULL;
1078                 writeq(val64, &bar0->tx_w_round_robin_1);
1079                 val64 = 0x0001000001000001ULL;
1080                 writeq(val64, &bar0->tx_w_round_robin_2);
1081                 val64 = 0x0000010000010000ULL;
1082                 writeq(val64, &bar0->tx_w_round_robin_3);
1083                 val64 = 0x0100000000000000ULL;
1084                 writeq(val64, &bar0->tx_w_round_robin_4);
1085                 break;
1086         case 3:
1087                 val64 = 0x0001000102000001ULL;
1088                 writeq(val64, &bar0->tx_w_round_robin_0);
1089                 val64 = 0x0001020000010001ULL;
1090                 writeq(val64, &bar0->tx_w_round_robin_1);
1091                 val64 = 0x0200000100010200ULL;
1092                 writeq(val64, &bar0->tx_w_round_robin_2);
1093                 val64 = 0x0001000102000001ULL;
1094                 writeq(val64, &bar0->tx_w_round_robin_3);
1095                 val64 = 0x0001020000000000ULL;
1096                 writeq(val64, &bar0->tx_w_round_robin_4);
1097                 break;
1098         case 4:
1099                 val64 = 0x0001020300010200ULL;
1100                 writeq(val64, &bar0->tx_w_round_robin_0);
1101                 val64 = 0x0100000102030001ULL;
1102                 writeq(val64, &bar0->tx_w_round_robin_1);
1103                 val64 = 0x0200010000010203ULL;
1104                 writeq(val64, &bar0->tx_w_round_robin_2);
1105                 val64 = 0x0001020001000001ULL;
1106                 writeq(val64, &bar0->tx_w_round_robin_3);
1107                 val64 = 0x0203000100000000ULL;
1108                 writeq(val64, &bar0->tx_w_round_robin_4);
1109                 break;
1110         case 5:
1111                 val64 = 0x0001000203000102ULL;
1112                 writeq(val64, &bar0->tx_w_round_robin_0);
1113                 val64 = 0x0001020001030004ULL;
1114                 writeq(val64, &bar0->tx_w_round_robin_1);
1115                 val64 = 0x0001000203000102ULL;
1116                 writeq(val64, &bar0->tx_w_round_robin_2);
1117                 val64 = 0x0001020001030004ULL;
1118                 writeq(val64, &bar0->tx_w_round_robin_3);
1119                 val64 = 0x0001000000000000ULL;
1120                 writeq(val64, &bar0->tx_w_round_robin_4);
1121                 break;
1122         case 6:
1123                 val64 = 0x0001020304000102ULL;
1124                 writeq(val64, &bar0->tx_w_round_robin_0);
1125                 val64 = 0x0304050001020001ULL;
1126                 writeq(val64, &bar0->tx_w_round_robin_1);
1127                 val64 = 0x0203000100000102ULL;
1128                 writeq(val64, &bar0->tx_w_round_robin_2);
1129                 val64 = 0x0304000102030405ULL;
1130                 writeq(val64, &bar0->tx_w_round_robin_3);
1131                 val64 = 0x0001000200000000ULL;
1132                 writeq(val64, &bar0->tx_w_round_robin_4);
1133                 break;
1134         case 7:
1135                 val64 = 0x0001020001020300ULL;
1136                 writeq(val64, &bar0->tx_w_round_robin_0);
1137                 val64 = 0x0102030400010203ULL;
1138                 writeq(val64, &bar0->tx_w_round_robin_1);
1139                 val64 = 0x0405060001020001ULL;
1140                 writeq(val64, &bar0->tx_w_round_robin_2);
1141                 val64 = 0x0304050000010200ULL;
1142                 writeq(val64, &bar0->tx_w_round_robin_3);
1143                 val64 = 0x0102030000000000ULL;
1144                 writeq(val64, &bar0->tx_w_round_robin_4);
1145                 break;
1146         case 8:
1147                 val64 = 0x0001020300040105ULL;
1148                 writeq(val64, &bar0->tx_w_round_robin_0);
1149                 val64 = 0x0200030106000204ULL;
1150                 writeq(val64, &bar0->tx_w_round_robin_1);
1151                 val64 = 0x0103000502010007ULL;
1152                 writeq(val64, &bar0->tx_w_round_robin_2);
1153                 val64 = 0x0304010002060500ULL;
1154                 writeq(val64, &bar0->tx_w_round_robin_3);
1155                 val64 = 0x0103020400000000ULL;
1156                 writeq(val64, &bar0->tx_w_round_robin_4);
1157                 break;
1158         }
1159
1160         /* Filling the Rx round robin registers as per the
1161          * number of Rings and steering based on QoS.
1162          */
1163         switch (config->rx_ring_num) {
1164         case 1:
1165                 val64 = 0x8080808080808080ULL;
1166                 writeq(val64, &bar0->rts_qos_steering);
1167                 break;
1168         case 2:
1169                 val64 = 0x0000010000010000ULL;
1170                 writeq(val64, &bar0->rx_w_round_robin_0);
1171                 val64 = 0x0100000100000100ULL;
1172                 writeq(val64, &bar0->rx_w_round_robin_1);
1173                 val64 = 0x0001000001000001ULL;
1174                 writeq(val64, &bar0->rx_w_round_robin_2);
1175                 val64 = 0x0000010000010000ULL;
1176                 writeq(val64, &bar0->rx_w_round_robin_3);
1177                 val64 = 0x0100000000000000ULL;
1178                 writeq(val64, &bar0->rx_w_round_robin_4);
1179
1180                 val64 = 0x8080808040404040ULL;
1181                 writeq(val64, &bar0->rts_qos_steering);
1182                 break;
1183         case 3:
1184                 val64 = 0x0001000102000001ULL;
1185                 writeq(val64, &bar0->rx_w_round_robin_0);
1186                 val64 = 0x0001020000010001ULL;
1187                 writeq(val64, &bar0->rx_w_round_robin_1);
1188                 val64 = 0x0200000100010200ULL;
1189                 writeq(val64, &bar0->rx_w_round_robin_2);
1190                 val64 = 0x0001000102000001ULL;
1191                 writeq(val64, &bar0->rx_w_round_robin_3);
1192                 val64 = 0x0001020000000000ULL;
1193                 writeq(val64, &bar0->rx_w_round_robin_4);
1194
1195                 val64 = 0x8080804040402020ULL;
1196                 writeq(val64, &bar0->rts_qos_steering);
1197                 break;
1198         case 4:
1199                 val64 = 0x0001020300010200ULL;
1200                 writeq(val64, &bar0->rx_w_round_robin_0);
1201                 val64 = 0x0100000102030001ULL;
1202                 writeq(val64, &bar0->rx_w_round_robin_1);
1203                 val64 = 0x0200010000010203ULL;
1204                 writeq(val64, &bar0->rx_w_round_robin_2);
1205                 val64 = 0x0001020001000001ULL;
1206                 writeq(val64, &bar0->rx_w_round_robin_3);
1207                 val64 = 0x0203000100000000ULL;
1208                 writeq(val64, &bar0->rx_w_round_robin_4);
1209
1210                 val64 = 0x8080404020201010ULL;
1211                 writeq(val64, &bar0->rts_qos_steering);
1212                 break;
1213         case 5:
1214                 val64 = 0x0001000203000102ULL;
1215                 writeq(val64, &bar0->rx_w_round_robin_0);
1216                 val64 = 0x0001020001030004ULL;
1217                 writeq(val64, &bar0->rx_w_round_robin_1);
1218                 val64 = 0x0001000203000102ULL;
1219                 writeq(val64, &bar0->rx_w_round_robin_2);
1220                 val64 = 0x0001020001030004ULL;
1221                 writeq(val64, &bar0->rx_w_round_robin_3);
1222                 val64 = 0x0001000000000000ULL;
1223                 writeq(val64, &bar0->rx_w_round_robin_4);
1224
1225                 val64 = 0x8080404020201008ULL;
1226                 writeq(val64, &bar0->rts_qos_steering);
1227                 break;
1228         case 6:
1229                 val64 = 0x0001020304000102ULL;
1230                 writeq(val64, &bar0->rx_w_round_robin_0);
1231                 val64 = 0x0304050001020001ULL;
1232                 writeq(val64, &bar0->rx_w_round_robin_1);
1233                 val64 = 0x0203000100000102ULL;
1234                 writeq(val64, &bar0->rx_w_round_robin_2);
1235                 val64 = 0x0304000102030405ULL;
1236                 writeq(val64, &bar0->rx_w_round_robin_3);
1237                 val64 = 0x0001000200000000ULL;
1238                 writeq(val64, &bar0->rx_w_round_robin_4);
1239
1240                 val64 = 0x8080404020100804ULL;
1241                 writeq(val64, &bar0->rts_qos_steering);
1242                 break;
1243         case 7:
1244                 val64 = 0x0001020001020300ULL;
1245                 writeq(val64, &bar0->rx_w_round_robin_0);
1246                 val64 = 0x0102030400010203ULL;
1247                 writeq(val64, &bar0->rx_w_round_robin_1);
1248                 val64 = 0x0405060001020001ULL;
1249                 writeq(val64, &bar0->rx_w_round_robin_2);
1250                 val64 = 0x0304050000010200ULL;
1251                 writeq(val64, &bar0->rx_w_round_robin_3);
1252                 val64 = 0x0102030000000000ULL;
1253                 writeq(val64, &bar0->rx_w_round_robin_4);
1254
1255                 val64 = 0x8080402010080402ULL;
1256                 writeq(val64, &bar0->rts_qos_steering);
1257                 break;
1258         case 8:
1259                 val64 = 0x0001020300040105ULL;
1260                 writeq(val64, &bar0->rx_w_round_robin_0);
1261                 val64 = 0x0200030106000204ULL;
1262                 writeq(val64, &bar0->rx_w_round_robin_1);
1263                 val64 = 0x0103000502010007ULL;
1264                 writeq(val64, &bar0->rx_w_round_robin_2);
1265                 val64 = 0x0304010002060500ULL;
1266                 writeq(val64, &bar0->rx_w_round_robin_3);
1267                 val64 = 0x0103020400000000ULL;
1268                 writeq(val64, &bar0->rx_w_round_robin_4);
1269
1270                 val64 = 0x8040201008040201ULL;
1271                 writeq(val64, &bar0->rts_qos_steering);
1272                 break;
1273         }
1274
1275         /* UDP Fix */
1276         val64 = 0;
1277         for (i = 0; i < 8; i++)
1278                 writeq(val64, &bar0->rts_frm_len_n[i]);
1279
1280         /* Set the default rts frame length for the rings configured */
1281         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1282         for (i = 0 ; i < config->rx_ring_num ; i++)
1283                 writeq(val64, &bar0->rts_frm_len_n[i]);
1284
1285         /* Set the frame length for the configured rings
1286          * desired by the user
1287          */
1288         for (i = 0; i < config->rx_ring_num; i++) {
1289                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1290                  * specified frame length steering.
1291                  * If the user provides the frame length then program
1292                  * the rts_frm_len register for those values or else
1293                  * leave it as it is.
1294                  */
1295                 if (rts_frm_len[i] != 0) {
1296                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1297                                 &bar0->rts_frm_len_n[i]);
1298                 }
1299         }
1300
1301         /* Program statistics memory */
1302         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1303
1304         if (nic->device_type == XFRAME_II_DEVICE) {
1305                 val64 = STAT_BC(0x320);
1306                 writeq(val64, &bar0->stat_byte_cnt);
1307         }
1308
1309         /*
1310          * Initializing the sampling rate for the device to calculate the
1311          * bandwidth utilization.
1312          */
1313         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1314             MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1315         writeq(val64, &bar0->mac_link_util);
1316
1317
1318         /*
1319          * Initializing the Transmit and Receive Traffic Interrupt
1320          * Scheme.
1321          */
1322         /*
1323          * TTI Initialization. Default Tx timer gets us about
1324          * 250 interrupts per sec. Continuous interrupts are enabled
1325          * by default.
1326          */
1327         if (nic->device_type == XFRAME_II_DEVICE) {
1328                 int count = (nic->config.bus_speed * 125)/2;
1329                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1330         } else {
1331
1332                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1333         }
1334         val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1335             TTI_DATA1_MEM_TX_URNG_B(0x10) |
1336             TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1337                 if (use_continuous_tx_intrs)
1338                         val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1339         writeq(val64, &bar0->tti_data1_mem);
1340
1341         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1342             TTI_DATA2_MEM_TX_UFC_B(0x20) |
1343             TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1344         writeq(val64, &bar0->tti_data2_mem);
1345
1346         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1347         writeq(val64, &bar0->tti_command_mem);
1348
1349         /*
1350          * Once the operation completes, the Strobe bit of the command
1351          * register will be reset. We poll for this particular condition
1352          * We wait for a maximum of 500ms for the operation to complete,
1353          * if it's not complete by then we return error.
1354          */
1355         time = 0;
1356         while (TRUE) {
1357                 val64 = readq(&bar0->tti_command_mem);
1358                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1359                         break;
1360                 }
1361                 if (time > 10) {
1362                         DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1363                                   dev->name);
1364                         return -1;
1365                 }
1366                 msleep(50);
1367                 time++;
1368         }
1369
1370         if (nic->config.bimodal) {
1371                 int k = 0;
1372                 for (k = 0; k < config->rx_ring_num; k++) {
1373                         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1374                         val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1375                         writeq(val64, &bar0->tti_command_mem);
1376
1377                 /*
1378                  * Once the operation completes, the Strobe bit of the command
1379                  * register will be reset. We poll for this particular condition
1380                  * We wait for a maximum of 500ms for the operation to complete,
1381                  * if it's not complete by then we return error.
1382                 */
1383                         time = 0;
1384                         while (TRUE) {
1385                                 val64 = readq(&bar0->tti_command_mem);
1386                                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1387                                         break;
1388                                 }
1389                                 if (time > 10) {
1390                                         DBG_PRINT(ERR_DBG,
1391                                                 "%s: TTI init Failed\n",
1392                                         dev->name);
1393                                         return -1;
1394                                 }
1395                                 time++;
1396                                 msleep(50);
1397                         }
1398                 }
1399         } else {
1400
1401                 /* RTI Initialization */
1402                 if (nic->device_type == XFRAME_II_DEVICE) {
1403                         /*
1404                          * Programmed to generate Apprx 500 Intrs per
1405                          * second
1406                          */
1407                         int count = (nic->config.bus_speed * 125)/4;
1408                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1409                 } else {
1410                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1411                 }
1412                 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1413                     RTI_DATA1_MEM_RX_URNG_B(0x10) |
1414                     RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1415
1416                 writeq(val64, &bar0->rti_data1_mem);
1417
1418                 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1419                     RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1420                 if (nic->intr_type == MSI_X)
1421                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1422                                 RTI_DATA2_MEM_RX_UFC_D(0x40));
1423                 else
1424                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1425                                 RTI_DATA2_MEM_RX_UFC_D(0x80));
1426                 writeq(val64, &bar0->rti_data2_mem);
1427
1428                 for (i = 0; i < config->rx_ring_num; i++) {
1429                         val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1430                                         | RTI_CMD_MEM_OFFSET(i);
1431                         writeq(val64, &bar0->rti_command_mem);
1432
1433                         /*
1434                          * Once the operation completes, the Strobe bit of the
1435                          * command register will be reset. We poll for this
1436                          * particular condition. We wait for a maximum of 500ms
1437                          * for the operation to complete, if it's not complete
1438                          * by then we return error.
1439                          */
1440                         time = 0;
1441                         while (TRUE) {
1442                                 val64 = readq(&bar0->rti_command_mem);
1443                                 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1444                                         break;
1445                                 }
1446                                 if (time > 10) {
1447                                         DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1448                                                   dev->name);
1449                                         return -1;
1450                                 }
1451                                 time++;
1452                                 msleep(50);
1453                         }
1454                 }
1455         }
1456
1457         /*
1458          * Initializing proper values as Pause threshold into all
1459          * the 8 Queues on Rx side.
1460          */
1461         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1462         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1463
1464         /* Disable RMAC PAD STRIPPING */
1465         add = &bar0->mac_cfg;
1466         val64 = readq(&bar0->mac_cfg);
1467         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1468         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1469         writel((u32) (val64), add);
1470         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1471         writel((u32) (val64 >> 32), (add + 4));
1472         val64 = readq(&bar0->mac_cfg);
1473
1474         /*
1475          * Set the time value to be inserted in the pause frame
1476          * generated by xena.
1477          */
1478         val64 = readq(&bar0->rmac_pause_cfg);
1479         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1480         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1481         writeq(val64, &bar0->rmac_pause_cfg);
1482
1483         /*
1484          * Set the Threshold Limit for Generating the pause frame
1485          * If the amount of data in any Queue exceeds ratio of
1486          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1487          * pause frame is generated
1488          */
1489         val64 = 0;
1490         for (i = 0; i < 4; i++) {
1491                 val64 |=
1492                     (((u64) 0xFF00 | nic->mac_control.
1493                       mc_pause_threshold_q0q3)
1494                      << (i * 2 * 8));
1495         }
1496         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1497
1498         val64 = 0;
1499         for (i = 0; i < 4; i++) {
1500                 val64 |=
1501                     (((u64) 0xFF00 | nic->mac_control.
1502                       mc_pause_threshold_q4q7)
1503                      << (i * 2 * 8));
1504         }
1505         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1506
1507         /*
1508          * TxDMA will stop Read request if the number of read split has
1509          * exceeded the limit pointed by shared_splits
1510          */
1511         val64 = readq(&bar0->pic_control);
1512         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1513         writeq(val64, &bar0->pic_control);
1514
1515         /*
1516          * Programming the Herc to split every write transaction
1517          * that does not start on an ADB to reduce disconnects.
1518          */
1519         if (nic->device_type == XFRAME_II_DEVICE) {
1520                 val64 = WREQ_SPLIT_MASK_SET_MASK(255);
1521                 writeq(val64, &bar0->wreq_split_mask);
1522         }
1523
1524         /* Setting Link stability period to 64 ms */
1525         if (nic->device_type == XFRAME_II_DEVICE) {
1526                 val64 = MISC_LINK_STABILITY_PRD(3);
1527                 writeq(val64, &bar0->misc_control);
1528         }
1529
1530         return SUCCESS;
1531 }
1532 #define LINK_UP_DOWN_INTERRUPT          1
1533 #define MAC_RMAC_ERR_TIMER              2
1534
1535 int s2io_link_fault_indication(nic_t *nic)
1536 {
1537         if (nic->intr_type != INTA)
1538                 return MAC_RMAC_ERR_TIMER;
1539         if (nic->device_type == XFRAME_II_DEVICE)
1540                 return LINK_UP_DOWN_INTERRUPT;
1541         else
1542                 return MAC_RMAC_ERR_TIMER;
1543 }
1544
1545 /**
1546  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1547  *  @nic: device private variable,
1548  *  @mask: A mask indicating which Intr block must be modified and,
1549  *  @flag: A flag indicating whether to enable or disable the Intrs.
1550  *  Description: This function will either disable or enable the interrupts
1551  *  depending on the flag argument. The mask argument can be used to
1552  *  enable/disable any Intr block.
1553  *  Return Value: NONE.
1554  */
1555
1556 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1557 {
1558         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1559         register u64 val64 = 0, temp64 = 0;
1560
1561         /*  Top level interrupt classification */
1562         /*  PIC Interrupts */
1563         if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1564                 /*  Enable PIC Intrs in the general intr mask register */
1565                 val64 = TXPIC_INT_M | PIC_RX_INT_M;
1566                 if (flag == ENABLE_INTRS) {
1567                         temp64 = readq(&bar0->general_int_mask);
1568                         temp64 &= ~((u64) val64);
1569                         writeq(temp64, &bar0->general_int_mask);
1570                         /*
1571                          * If Hercules adapter enable GPIO otherwise
1572                          * disabled all PCIX, Flash, MDIO, IIC and GPIO
1573                          * interrupts for now.
1574                          * TODO
1575                          */
1576                         if (s2io_link_fault_indication(nic) ==
1577                                         LINK_UP_DOWN_INTERRUPT ) {
1578                                 temp64 = readq(&bar0->pic_int_mask);
1579                                 temp64 &= ~((u64) PIC_INT_GPIO);
1580                                 writeq(temp64, &bar0->pic_int_mask);
1581                                 temp64 = readq(&bar0->gpio_int_mask);
1582                                 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1583                                 writeq(temp64, &bar0->gpio_int_mask);
1584                         } else {
1585                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1586                         }
1587                         /*
1588                          * No MSI Support is available presently, so TTI and
1589                          * RTI interrupts are also disabled.
1590                          */
1591                 } else if (flag == DISABLE_INTRS) {
1592                         /*
1593                          * Disable PIC Intrs in the general
1594                          * intr mask register
1595                          */
1596                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1597                         temp64 = readq(&bar0->general_int_mask);
1598                         val64 |= temp64;
1599                         writeq(val64, &bar0->general_int_mask);
1600                 }
1601         }
1602
1603         /*  DMA Interrupts */
1604         /*  Enabling/Disabling Tx DMA interrupts */
1605         if (mask & TX_DMA_INTR) {
1606                 /* Enable TxDMA Intrs in the general intr mask register */
1607                 val64 = TXDMA_INT_M;
1608                 if (flag == ENABLE_INTRS) {
1609                         temp64 = readq(&bar0->general_int_mask);
1610                         temp64 &= ~((u64) val64);
1611                         writeq(temp64, &bar0->general_int_mask);
1612                         /*
1613                          * Keep all interrupts other than PFC interrupt
1614                          * and PCC interrupt disabled in DMA level.
1615                          */
1616                         val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
1617                                                       TXDMA_PCC_INT_M);
1618                         writeq(val64, &bar0->txdma_int_mask);
1619                         /*
1620                          * Enable only the MISC error 1 interrupt in PFC block
1621                          */
1622                         val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
1623                         writeq(val64, &bar0->pfc_err_mask);
1624                         /*
1625                          * Enable only the FB_ECC error interrupt in PCC block
1626                          */
1627                         val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
1628                         writeq(val64, &bar0->pcc_err_mask);
1629                 } else if (flag == DISABLE_INTRS) {
1630                         /*
1631                          * Disable TxDMA Intrs in the general intr mask
1632                          * register
1633                          */
1634                         writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
1635                         writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
1636                         temp64 = readq(&bar0->general_int_mask);
1637                         val64 |= temp64;
1638                         writeq(val64, &bar0->general_int_mask);
1639                 }
1640         }
1641
1642         /*  Enabling/Disabling Rx DMA interrupts */
1643         if (mask & RX_DMA_INTR) {
1644                 /*  Enable RxDMA Intrs in the general intr mask register */
1645                 val64 = RXDMA_INT_M;
1646                 if (flag == ENABLE_INTRS) {
1647                         temp64 = readq(&bar0->general_int_mask);
1648                         temp64 &= ~((u64) val64);
1649                         writeq(temp64, &bar0->general_int_mask);
1650                         /*
1651                          * All RxDMA block interrupts are disabled for now
1652                          * TODO
1653                          */
1654                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1655                 } else if (flag == DISABLE_INTRS) {
1656                         /*
1657                          * Disable RxDMA Intrs in the general intr mask
1658                          * register
1659                          */
1660                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1661                         temp64 = readq(&bar0->general_int_mask);
1662                         val64 |= temp64;
1663                         writeq(val64, &bar0->general_int_mask);
1664                 }
1665         }
1666
1667         /*  MAC Interrupts */
1668         /*  Enabling/Disabling MAC interrupts */
1669         if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1670                 val64 = TXMAC_INT_M | RXMAC_INT_M;
1671                 if (flag == ENABLE_INTRS) {
1672                         temp64 = readq(&bar0->general_int_mask);
1673                         temp64 &= ~((u64) val64);
1674                         writeq(temp64, &bar0->general_int_mask);
1675                         /*
1676                          * All MAC block error interrupts are disabled for now
1677                          * TODO
1678                          */
1679                 } else if (flag == DISABLE_INTRS) {
1680                         /*
1681                          * Disable MAC Intrs in the general intr mask register
1682                          */
1683                         writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1684                         writeq(DISABLE_ALL_INTRS,
1685                                &bar0->mac_rmac_err_mask);
1686
1687                         temp64 = readq(&bar0->general_int_mask);
1688                         val64 |= temp64;
1689                         writeq(val64, &bar0->general_int_mask);
1690                 }
1691         }
1692
1693         /*  XGXS Interrupts */
1694         if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) {
1695                 val64 = TXXGXS_INT_M | RXXGXS_INT_M;
1696                 if (flag == ENABLE_INTRS) {
1697                         temp64 = readq(&bar0->general_int_mask);
1698                         temp64 &= ~((u64) val64);
1699                         writeq(temp64, &bar0->general_int_mask);
1700                         /*
1701                          * All XGXS block error interrupts are disabled for now
1702                          * TODO
1703                          */
1704                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1705                 } else if (flag == DISABLE_INTRS) {
1706                         /*
1707                          * Disable MC Intrs in the general intr mask register
1708                          */
1709                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1710                         temp64 = readq(&bar0->general_int_mask);
1711                         val64 |= temp64;
1712                         writeq(val64, &bar0->general_int_mask);
1713                 }
1714         }
1715
1716         /*  Memory Controller(MC) interrupts */
1717         if (mask & MC_INTR) {
1718                 val64 = MC_INT_M;
1719                 if (flag == ENABLE_INTRS) {
1720                         temp64 = readq(&bar0->general_int_mask);
1721                         temp64 &= ~((u64) val64);
1722                         writeq(temp64, &bar0->general_int_mask);
1723                         /*
1724                          * Enable all MC Intrs.
1725                          */
1726                         writeq(0x0, &bar0->mc_int_mask);
1727                         writeq(0x0, &bar0->mc_err_mask);
1728                 } else if (flag == DISABLE_INTRS) {
1729                         /*
1730                          * Disable MC Intrs in the general intr mask register
1731                          */
1732                         writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
1733                         temp64 = readq(&bar0->general_int_mask);
1734                         val64 |= temp64;
1735                         writeq(val64, &bar0->general_int_mask);
1736                 }
1737         }
1738
1739
1740         /*  Tx traffic interrupts */
1741         if (mask & TX_TRAFFIC_INTR) {
1742                 val64 = TXTRAFFIC_INT_M;
1743                 if (flag == ENABLE_INTRS) {
1744                         temp64 = readq(&bar0->general_int_mask);
1745                         temp64 &= ~((u64) val64);
1746                         writeq(temp64, &bar0->general_int_mask);
1747                         /*
1748                          * Enable all the Tx side interrupts
1749                          * writing 0 Enables all 64 TX interrupt levels
1750                          */
1751                         writeq(0x0, &bar0->tx_traffic_mask);
1752                 } else if (flag == DISABLE_INTRS) {
1753                         /*
1754                          * Disable Tx Traffic Intrs in the general intr mask
1755                          * register.
1756                          */
1757                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1758                         temp64 = readq(&bar0->general_int_mask);
1759                         val64 |= temp64;
1760                         writeq(val64, &bar0->general_int_mask);
1761                 }
1762         }
1763
1764         /*  Rx traffic interrupts */
1765         if (mask & RX_TRAFFIC_INTR) {
1766                 val64 = RXTRAFFIC_INT_M;
1767                 if (flag == ENABLE_INTRS) {
1768                         temp64 = readq(&bar0->general_int_mask);
1769                         temp64 &= ~((u64) val64);
1770                         writeq(temp64, &bar0->general_int_mask);
1771                         /* writing 0 Enables all 8 RX interrupt levels */
1772                         writeq(0x0, &bar0->rx_traffic_mask);
1773                 } else if (flag == DISABLE_INTRS) {
1774                         /*
1775                          * Disable Rx Traffic Intrs in the general intr mask
1776                          * register.
1777                          */
1778                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1779                         temp64 = readq(&bar0->general_int_mask);
1780                         val64 |= temp64;
1781                         writeq(val64, &bar0->general_int_mask);
1782                 }
1783         }
1784 }
1785
1786 static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc)
1787 {
1788         int ret = 0;
1789
1790         if (flag == FALSE) {
1791                 if ((!herc && (rev_id >= 4)) || herc) {
1792                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1793                             ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1794                              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1795                                 ret = 1;
1796                         }
1797                 }else {
1798                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1799                             ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1800                              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1801                                 ret = 1;
1802                         }
1803                 }
1804         } else {
1805                 if ((!herc && (rev_id >= 4)) || herc) {
1806                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1807                              ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1808                             (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1809                              ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1810                               ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1811                                 ret = 1;
1812                         }
1813                 } else {
1814                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1815                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1816                             (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1817                              ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1818                               ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1819                                 ret = 1;
1820                         }
1821                 }
1822         }
1823
1824         return ret;
1825 }
1826 /**
1827  *  verify_xena_quiescence - Checks whether the H/W is ready
1828  *  @val64 :  Value read from adapter status register.
1829  *  @flag : indicates if the adapter enable bit was ever written once
1830  *  before.
1831  *  Description: Returns whether the H/W is ready to go or not. Depending
1832  *  on whether adapter enable bit was written or not the comparison
1833  *  differs and the calling function passes the input argument flag to
1834  *  indicate this.
1835  *  Return: 1 If xena is quiescence
1836  *          0 If Xena is not quiescence
1837  */
1838
1839 static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag)
1840 {
1841         int ret = 0, herc;
1842         u64 tmp64 = ~((u64) val64);
1843         int rev_id = get_xena_rev_id(sp->pdev);
1844
1845         herc = (sp->device_type == XFRAME_II_DEVICE);
1846         if (!
1847             (tmp64 &
1848              (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY |
1849               ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY |
1850               ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY |
1851               ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK |
1852               ADAPTER_STATUS_P_PLL_LOCK))) {
1853                 ret = check_prc_pcc_state(val64, flag, rev_id, herc);
1854         }
1855
1856         return ret;
1857 }
1858
1859 /**
1860  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
1861  * @sp: Pointer to device specifc structure
1862  * Description :
1863  * New procedure to clear mac address reading  problems on Alpha platforms
1864  *
1865  */
1866
1867 void fix_mac_address(nic_t * sp)
1868 {
1869         XENA_dev_config_t __iomem *bar0 = sp->bar0;
1870         u64 val64;
1871         int i = 0;
1872
1873         while (fix_mac[i] != END_SIGN) {
1874                 writeq(fix_mac[i++], &bar0->gpio_control);
1875                 udelay(10);
1876                 val64 = readq(&bar0->gpio_control);
1877         }
1878 }
1879
1880 /**
1881  *  start_nic - Turns the device on
1882  *  @nic : device private variable.
1883  *  Description:
1884  *  This function actually turns the device on. Before this  function is
1885  *  called,all Registers are configured from their reset states
1886  *  and shared memory is allocated but the NIC is still quiescent. On
1887  *  calling this function, the device interrupts are cleared and the NIC is
1888  *  literally switched on by writing into the adapter control register.
1889  *  Return Value:
1890  *  SUCCESS on success and -1 on failure.
1891  */
1892
1893 static int start_nic(struct s2io_nic *nic)
1894 {
1895         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1896         struct net_device *dev = nic->dev;
1897         register u64 val64 = 0;
1898         u16 interruptible;
1899         u16 subid, i;
1900         mac_info_t *mac_control;
1901         struct config_param *config;
1902
1903         mac_control = &nic->mac_control;
1904         config = &nic->config;
1905
1906         /*  PRC Initialization and configuration */
1907         for (i = 0; i < config->rx_ring_num; i++) {
1908                 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1909                        &bar0->prc_rxd0_n[i]);
1910
1911                 val64 = readq(&bar0->prc_ctrl_n[i]);
1912                 if (nic->config.bimodal)
1913                         val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
1914                 if (nic->rxd_mode == RXD_MODE_1)
1915                         val64 |= PRC_CTRL_RC_ENABLED;
1916                 else
1917                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
1918                 writeq(val64, &bar0->prc_ctrl_n[i]);
1919         }
1920
1921         if (nic->rxd_mode == RXD_MODE_3B) {
1922                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
1923                 val64 = readq(&bar0->rx_pa_cfg);
1924                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
1925                 writeq(val64, &bar0->rx_pa_cfg);
1926         }
1927
1928         /*
1929          * Enabling MC-RLDRAM. After enabling the device, we timeout
1930          * for around 100ms, which is approximately the time required
1931          * for the device to be ready for operation.
1932          */
1933         val64 = readq(&bar0->mc_rldram_mrs);
1934         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
1935         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
1936         val64 = readq(&bar0->mc_rldram_mrs);
1937
1938         msleep(100);    /* Delay by around 100 ms. */
1939
1940         /* Enabling ECC Protection. */
1941         val64 = readq(&bar0->adapter_control);
1942         val64 &= ~ADAPTER_ECC_EN;
1943         writeq(val64, &bar0->adapter_control);
1944
1945         /*
1946          * Clearing any possible Link state change interrupts that
1947          * could have popped up just before Enabling the card.
1948          */
1949         val64 = readq(&bar0->mac_rmac_err_reg);
1950         if (val64)
1951                 writeq(val64, &bar0->mac_rmac_err_reg);
1952
1953         /*
1954          * Verify if the device is ready to be enabled, if so enable
1955          * it.
1956          */
1957         val64 = readq(&bar0->adapter_status);
1958         if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
1959                 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
1960                 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
1961                           (unsigned long long) val64);
1962                 return FAILURE;
1963         }
1964
1965         /*  Enable select interrupts */
1966         if (nic->intr_type != INTA)
1967                 en_dis_able_nic_intrs(nic, ENA_ALL_INTRS, DISABLE_INTRS);
1968         else {
1969                 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
1970                 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
1971                 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
1972                 en_dis_able_nic_intrs(nic, interruptible, ENABLE_INTRS);
1973         }
1974
1975         /*
1976          * With some switches, link might be already up at this point.
1977          * Because of this weird behavior, when we enable laser,
1978          * we may not get link. We need to handle this. We cannot
1979          * figure out which switch is misbehaving. So we are forced to
1980          * make a global change.
1981          */
1982
1983         /* Enabling Laser. */
1984         val64 = readq(&bar0->adapter_control);
1985         val64 |= ADAPTER_EOI_TX_ON;
1986         writeq(val64, &bar0->adapter_control);
1987
1988         /* SXE-002: Initialize link and activity LED */
1989         subid = nic->pdev->subsystem_device;
1990         if (((subid & 0xFF) >= 0x07) &&
1991             (nic->device_type == XFRAME_I_DEVICE)) {
1992                 val64 = readq(&bar0->gpio_control);
1993                 val64 |= 0x0000800000000000ULL;
1994                 writeq(val64, &bar0->gpio_control);
1995                 val64 = 0x0411040400000000ULL;
1996                 writeq(val64, (void __iomem *)bar0 + 0x2700);
1997         }
1998
1999         /*
2000          * Don't see link state interrupts on certain switches, so
2001          * directly scheduling a link state task from here.
2002          */
2003         schedule_work(&nic->set_link_task);
2004
2005         return SUCCESS;
2006 }
2007
2008 /**
2009  *  free_tx_buffers - Free all queued Tx buffers
2010  *  @nic : device private variable.
2011  *  Description:
2012  *  Free all queued Tx buffers.
2013  *  Return Value: void
2014 */
2015
2016 static void free_tx_buffers(struct s2io_nic *nic)
2017 {
2018         struct net_device *dev = nic->dev;
2019         struct sk_buff *skb;
2020         TxD_t *txdp;
2021         int i, j;
2022         mac_info_t *mac_control;
2023         struct config_param *config;
2024         int cnt = 0, frg_cnt;
2025
2026         mac_control = &nic->mac_control;
2027         config = &nic->config;
2028
2029         for (i = 0; i < config->tx_fifo_num; i++) {
2030                 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2031                         txdp = (TxD_t *) mac_control->fifos[i].list_info[j].
2032                             list_virt_addr;
2033                         skb =
2034                             (struct sk_buff *) ((unsigned long) txdp->
2035                                                 Host_Control);
2036                         if (skb == NULL) {
2037                                 memset(txdp, 0, sizeof(TxD_t) *
2038                                        config->max_txds);
2039                                 continue;
2040                         }
2041                         frg_cnt = skb_shinfo(skb)->nr_frags;
2042                         pci_unmap_single(nic->pdev, (dma_addr_t)
2043                                          txdp->Buffer_Pointer,
2044                                          skb->len - skb->data_len,
2045                                          PCI_DMA_TODEVICE);
2046                         if (frg_cnt) {
2047                                 TxD_t *temp;
2048                                 temp = txdp;
2049                                 txdp++;
2050                                 for (j = 0; j < frg_cnt; j++, txdp++) {
2051                                         skb_frag_t *frag =
2052                                             &skb_shinfo(skb)->frags[j];
2053                                         pci_unmap_page(nic->pdev,
2054                                                        (dma_addr_t)
2055                                                        txdp->
2056                                                        Buffer_Pointer,
2057                                                        frag->size,
2058                                                        PCI_DMA_TODEVICE);
2059                                 }
2060                                 txdp = temp;
2061                         }
2062                         dev_kfree_skb(skb);
2063                         memset(txdp, 0, sizeof(TxD_t) * config->max_txds);
2064                         cnt++;
2065                 }
2066                 DBG_PRINT(INTR_DBG,
2067                           "%s:forcibly freeing %d skbs on FIFO%d\n",
2068                           dev->name, cnt, i);
2069                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2070                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2071         }
2072 }
2073
2074 /**
2075  *   stop_nic -  To stop the nic
2076  *   @nic ; device private variable.
2077  *   Description:
2078  *   This function does exactly the opposite of what the start_nic()
2079  *   function does. This function is called to stop the device.
2080  *   Return Value:
2081  *   void.
2082  */
2083
2084 static void stop_nic(struct s2io_nic *nic)
2085 {
2086         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2087         register u64 val64 = 0;
2088         u16 interruptible, i;
2089         mac_info_t *mac_control;
2090         struct config_param *config;
2091
2092         mac_control = &nic->mac_control;
2093         config = &nic->config;
2094
2095         /*  Disable all interrupts */
2096         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2097         interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2098         interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2099         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2100
2101         /*  Disable PRCs */
2102         for (i = 0; i < config->rx_ring_num; i++) {
2103                 val64 = readq(&bar0->prc_ctrl_n[i]);
2104                 val64 &= ~((u64) PRC_CTRL_RC_ENABLED);
2105                 writeq(val64, &bar0->prc_ctrl_n[i]);
2106         }
2107 }
2108
2109 int fill_rxd_3buf(nic_t *nic, RxD_t *rxdp, struct sk_buff *skb)
2110 {
2111         struct net_device *dev = nic->dev;
2112         struct sk_buff *frag_list;
2113         u64 tmp;
2114
2115         /* Buffer-1 receives L3/L4 headers */
2116         ((RxD3_t*)rxdp)->Buffer1_ptr = pci_map_single
2117                         (nic->pdev, skb->data, l3l4hdr_size + 4,
2118                         PCI_DMA_FROMDEVICE);
2119
2120         /* skb_shinfo(skb)->frag_list will have L4 data payload */
2121         skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
2122         if (skb_shinfo(skb)->frag_list == NULL) {
2123                 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
2124                 return -ENOMEM ;
2125         }
2126         frag_list = skb_shinfo(skb)->frag_list;
2127         frag_list->next = NULL;
2128         tmp = (u64) frag_list->data;
2129         tmp += ALIGN_SIZE;
2130         tmp &= ~ALIGN_SIZE;
2131         frag_list->data = (void *) tmp;
2132         frag_list->tail = (void *) tmp;
2133
2134         /* Buffer-2 receives L4 data payload */
2135         ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
2136                                 frag_list->data, dev->mtu,
2137                                 PCI_DMA_FROMDEVICE);
2138         rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
2139         rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
2140
2141         return SUCCESS;
2142 }
2143
2144 /**
2145  *  fill_rx_buffers - Allocates the Rx side skbs
2146  *  @nic:  device private variable
2147  *  @ring_no: ring number
2148  *  Description:
2149  *  The function allocates Rx side skbs and puts the physical
2150  *  address of these buffers into the RxD buffer pointers, so that the NIC
2151  *  can DMA the received frame into these locations.
2152  *  The NIC supports 3 receive modes, viz
2153  *  1. single buffer,
2154  *  2. three buffer and
2155  *  3. Five buffer modes.
2156  *  Each mode defines how many fragments the received frame will be split
2157  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2158  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2159  *  is split into 3 fragments. As of now only single buffer mode is
2160  *  supported.
2161  *   Return Value:
2162  *  SUCCESS on success or an appropriate -ve value on failure.
2163  */
2164
2165 int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2166 {
2167         struct net_device *dev = nic->dev;
2168         struct sk_buff *skb;
2169         RxD_t *rxdp;
2170         int off, off1, size, block_no, block_no1;
2171         u32 alloc_tab = 0;
2172         u32 alloc_cnt;
2173         mac_info_t *mac_control;
2174         struct config_param *config;
2175         u64 tmp;
2176         buffAdd_t *ba;
2177 #ifndef CONFIG_S2IO_NAPI
2178         unsigned long flags;
2179 #endif
2180         RxD_t *first_rxdp = NULL;
2181
2182         mac_control = &nic->mac_control;
2183         config = &nic->config;
2184         alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2185             atomic_read(&nic->rx_bufs_left[ring_no]);
2186
2187         while (alloc_tab < alloc_cnt) {
2188                 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2189                     block_index;
2190                 block_no1 = mac_control->rings[ring_no].rx_curr_get_info.
2191                     block_index;
2192                 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2193                 off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2194
2195                 rxdp = mac_control->rings[ring_no].
2196                                 rx_blocks[block_no].rxds[off].virt_addr;
2197
2198                 if ((block_no == block_no1) && (off == off1) &&
2199                                         (rxdp->Host_Control)) {
2200                         DBG_PRINT(INTR_DBG, "%s: Get and Put",
2201                                   dev->name);
2202                         DBG_PRINT(INTR_DBG, " info equated\n");
2203                         goto end;
2204                 }
2205                 if (off && (off == rxd_count[nic->rxd_mode])) {
2206                         mac_control->rings[ring_no].rx_curr_put_info.
2207                             block_index++;
2208                         if (mac_control->rings[ring_no].rx_curr_put_info.
2209                             block_index == mac_control->rings[ring_no].
2210                                         block_count)
2211                                 mac_control->rings[ring_no].rx_curr_put_info.
2212                                         block_index = 0;
2213                         block_no = mac_control->rings[ring_no].
2214                                         rx_curr_put_info.block_index;
2215                         if (off == rxd_count[nic->rxd_mode])
2216                                 off = 0;
2217                         mac_control->rings[ring_no].rx_curr_put_info.
2218                                 offset = off;
2219                         rxdp = mac_control->rings[ring_no].
2220                                 rx_blocks[block_no].block_virt_addr;
2221                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2222                                   dev->name, rxdp);
2223                 }
2224 #ifndef CONFIG_S2IO_NAPI
2225                 spin_lock_irqsave(&nic->put_lock, flags);
2226                 mac_control->rings[ring_no].put_pos =
2227                     (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2228                 spin_unlock_irqrestore(&nic->put_lock, flags);
2229 #endif
2230                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2231                         ((nic->rxd_mode >= RXD_MODE_3A) &&
2232                                 (rxdp->Control_2 & BIT(0)))) {
2233                         mac_control->rings[ring_no].rx_curr_put_info.
2234                                         offset = off;
2235                         goto end;
2236                 }
2237                 /* calculate size of skb based on ring mode */
2238                 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2239                                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2240                 if (nic->rxd_mode == RXD_MODE_1)
2241                         size += NET_IP_ALIGN;
2242                 else if (nic->rxd_mode == RXD_MODE_3B)
2243                         size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2244                 else
2245                         size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
2246
2247                 /* allocate skb */
2248                 skb = dev_alloc_skb(size);
2249                 if(!skb) {
2250                         DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
2251                         DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
2252                         if (first_rxdp) {
2253                                 wmb();
2254                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2255                         }
2256                         return -ENOMEM ;
2257                 }
2258                 if (nic->rxd_mode == RXD_MODE_1) {
2259                         /* 1 buffer mode - normal operation mode */
2260                         memset(rxdp, 0, sizeof(RxD1_t));
2261                         skb_reserve(skb, NET_IP_ALIGN);
2262                         ((RxD1_t*)rxdp)->Buffer0_ptr = pci_map_single
2263                             (nic->pdev, skb->data, size, PCI_DMA_FROMDEVICE);
2264                         rxdp->Control_2 &= (~MASK_BUFFER0_SIZE_1);
2265                         rxdp->Control_2 |= SET_BUFFER0_SIZE_1(size);
2266
2267                 } else if (nic->rxd_mode >= RXD_MODE_3A) {
2268                         /*
2269                          * 2 or 3 buffer mode -
2270                          * Both 2 buffer mode and 3 buffer mode provides 128
2271                          * byte aligned receive buffers.
2272                          *
2273                          * 3 buffer mode provides header separation where in
2274                          * skb->data will have L3/L4 headers where as
2275                          * skb_shinfo(skb)->frag_list will have the L4 data
2276                          * payload
2277                          */
2278
2279                         memset(rxdp, 0, sizeof(RxD3_t));
2280                         ba = &mac_control->rings[ring_no].ba[block_no][off];
2281                         skb_reserve(skb, BUF0_LEN);
2282                         tmp = (u64)(unsigned long) skb->data;
2283                         tmp += ALIGN_SIZE;
2284                         tmp &= ~ALIGN_SIZE;
2285                         skb->data = (void *) (unsigned long)tmp;
2286                         skb->tail = (void *) (unsigned long)tmp;
2287
2288                         ((RxD3_t*)rxdp)->Buffer0_ptr =
2289                             pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2290                                            PCI_DMA_FROMDEVICE);
2291                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2292                         if (nic->rxd_mode == RXD_MODE_3B) {
2293                                 /* Two buffer mode */
2294
2295                                 /*
2296                                  * Buffer2 will have L3/L4 header plus
2297                                  * L4 payload
2298                                  */
2299                                 ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single
2300                                 (nic->pdev, skb->data, dev->mtu + 4,
2301                                                 PCI_DMA_FROMDEVICE);
2302
2303                                 /* Buffer-1 will be dummy buffer not used */
2304                                 ((RxD3_t*)rxdp)->Buffer1_ptr =
2305                                 pci_map_single(nic->pdev, ba->ba_1, BUF1_LEN,
2306                                         PCI_DMA_FROMDEVICE);
2307                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2308                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2309                                                                 (dev->mtu + 4);
2310                         } else {
2311                                 /* 3 buffer mode */
2312                                 if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
2313                                         dev_kfree_skb_irq(skb);
2314                                         if (first_rxdp) {
2315                                                 wmb();
2316                                                 first_rxdp->Control_1 |=
2317                                                         RXD_OWN_XENA;
2318                                         }
2319                                         return -ENOMEM ;
2320                                 }
2321                         }
2322                         rxdp->Control_2 |= BIT(0);
2323                 }
2324                 rxdp->Host_Control = (unsigned long) (skb);
2325                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2326                         rxdp->Control_1 |= RXD_OWN_XENA;
2327                 off++;
2328                 if (off == (rxd_count[nic->rxd_mode] + 1))
2329                         off = 0;
2330                 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2331
2332                 rxdp->Control_2 |= SET_RXD_MARKER;
2333                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2334                         if (first_rxdp) {
2335                                 wmb();
2336                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2337                         }
2338                         first_rxdp = rxdp;
2339                 }
2340                 atomic_inc(&nic->rx_bufs_left[ring_no]);
2341                 alloc_tab++;
2342         }
2343
2344       end:
2345         /* Transfer ownership of first descriptor to adapter just before
2346          * exiting. Before that, use memory barrier so that ownership
2347          * and other fields are seen by adapter correctly.
2348          */
2349         if (first_rxdp) {
2350                 wmb();
2351                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2352         }
2353
2354         return SUCCESS;
2355 }
2356
2357 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2358 {
2359         struct net_device *dev = sp->dev;
2360         int j;
2361         struct sk_buff *skb;
2362         RxD_t *rxdp;
2363         mac_info_t *mac_control;
2364         buffAdd_t *ba;
2365
2366         mac_control = &sp->mac_control;
2367         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2368                 rxdp = mac_control->rings[ring_no].
2369                                 rx_blocks[blk].rxds[j].virt_addr;
2370                 skb = (struct sk_buff *)
2371                         ((unsigned long) rxdp->Host_Control);
2372                 if (!skb) {
2373                         continue;
2374                 }
2375                 if (sp->rxd_mode == RXD_MODE_1) {
2376                         pci_unmap_single(sp->pdev, (dma_addr_t)
2377                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2378                                  dev->mtu +
2379                                  HEADER_ETHERNET_II_802_3_SIZE
2380                                  + HEADER_802_2_SIZE +
2381                                  HEADER_SNAP_SIZE,
2382                                  PCI_DMA_FROMDEVICE);
2383                         memset(rxdp, 0, sizeof(RxD1_t));
2384                 } else if(sp->rxd_mode == RXD_MODE_3B) {
2385                         ba = &mac_control->rings[ring_no].
2386                                 ba[blk][j];
2387                         pci_unmap_single(sp->pdev, (dma_addr_t)
2388                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2389                                  BUF0_LEN,
2390                                  PCI_DMA_FROMDEVICE);
2391                         pci_unmap_single(sp->pdev, (dma_addr_t)
2392                                  ((RxD3_t*)rxdp)->Buffer1_ptr,
2393                                  BUF1_LEN,
2394                                  PCI_DMA_FROMDEVICE);
2395                         pci_unmap_single(sp->pdev, (dma_addr_t)
2396                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2397                                  dev->mtu + 4,
2398                                  PCI_DMA_FROMDEVICE);
2399                         memset(rxdp, 0, sizeof(RxD3_t));
2400                 } else {
2401                         pci_unmap_single(sp->pdev, (dma_addr_t)
2402                                 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2403                                 PCI_DMA_FROMDEVICE);
2404                         pci_unmap_single(sp->pdev, (dma_addr_t)
2405                                 ((RxD3_t*)rxdp)->Buffer1_ptr,
2406                                 l3l4hdr_size + 4,
2407                                 PCI_DMA_FROMDEVICE);
2408                         pci_unmap_single(sp->pdev, (dma_addr_t)
2409                                 ((RxD3_t*)rxdp)->Buffer2_ptr, dev->mtu,
2410                                 PCI_DMA_FROMDEVICE);
2411                         memset(rxdp, 0, sizeof(RxD3_t));
2412                 }
2413                 dev_kfree_skb(skb);
2414                 atomic_dec(&sp->rx_bufs_left[ring_no]);
2415         }
2416 }
2417
2418 /**
2419  *  free_rx_buffers - Frees all Rx buffers
2420  *  @sp: device private variable.
2421  *  Description:
2422  *  This function will free all Rx buffers allocated by host.
2423  *  Return Value:
2424  *  NONE.
2425  */
2426
2427 static void free_rx_buffers(struct s2io_nic *sp)
2428 {
2429         struct net_device *dev = sp->dev;
2430         int i, blk = 0, buf_cnt = 0;
2431         mac_info_t *mac_control;
2432         struct config_param *config;
2433
2434         mac_control = &sp->mac_control;
2435         config = &sp->config;
2436
2437         for (i = 0; i < config->rx_ring_num; i++) {
2438                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2439                         free_rxd_blk(sp,i,blk);
2440
2441                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2442                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2443                 mac_control->rings[i].rx_curr_put_info.offset = 0;
2444                 mac_control->rings[i].rx_curr_get_info.offset = 0;
2445                 atomic_set(&sp->rx_bufs_left[i], 0);
2446                 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2447                           dev->name, buf_cnt, i);
2448         }
2449 }
2450
2451 /**
2452  * s2io_poll - Rx interrupt handler for NAPI support
2453  * @dev : pointer to the device structure.
2454  * @budget : The number of packets that were budgeted to be processed
2455  * during  one pass through the 'Poll" function.
2456  * Description:
2457  * Comes into picture only if NAPI support has been incorporated. It does
2458  * the same thing that rx_intr_handler does, but not in a interrupt context
2459  * also It will process only a given number of packets.
2460  * Return value:
2461  * 0 on success and 1 if there are No Rx packets to be processed.
2462  */
2463
2464 #if defined(CONFIG_S2IO_NAPI)
2465 static int s2io_poll(struct net_device *dev, int *budget)
2466 {
2467         nic_t *nic = dev->priv;
2468         int pkt_cnt = 0, org_pkts_to_process;
2469         mac_info_t *mac_control;
2470         struct config_param *config;
2471         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2472         u64 val64;
2473         int i;
2474
2475         atomic_inc(&nic->isr_cnt);
2476         mac_control = &nic->mac_control;
2477         config = &nic->config;
2478
2479         nic->pkts_to_process = *budget;
2480         if (nic->pkts_to_process > dev->quota)
2481                 nic->pkts_to_process = dev->quota;
2482         org_pkts_to_process = nic->pkts_to_process;
2483
2484         val64 = readq(&bar0->rx_traffic_int);
2485         writeq(val64, &bar0->rx_traffic_int);
2486
2487         for (i = 0; i < config->rx_ring_num; i++) {
2488                 rx_intr_handler(&mac_control->rings[i]);
2489                 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2490                 if (!nic->pkts_to_process) {
2491                         /* Quota for the current iteration has been met */
2492                         goto no_rx;
2493                 }
2494         }
2495         if (!pkt_cnt)
2496                 pkt_cnt = 1;
2497
2498         dev->quota -= pkt_cnt;
2499         *budget -= pkt_cnt;
2500         netif_rx_complete(dev);
2501
2502         for (i = 0; i < config->rx_ring_num; i++) {
2503                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2504                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2505                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2506                         break;
2507                 }
2508         }
2509         /* Re enable the Rx interrupts. */
2510         en_dis_able_nic_intrs(nic, RX_TRAFFIC_INTR, ENABLE_INTRS);
2511         atomic_dec(&nic->isr_cnt);
2512         return 0;
2513
2514 no_rx:
2515         dev->quota -= pkt_cnt;
2516         *budget -= pkt_cnt;
2517
2518         for (i = 0; i < config->rx_ring_num; i++) {
2519                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2520                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2521                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2522                         break;
2523                 }
2524         }
2525         atomic_dec(&nic->isr_cnt);
2526         return 1;
2527 }
2528 #endif
2529
2530 /**
2531  *  rx_intr_handler - Rx interrupt handler
2532  *  @nic: device private variable.
2533  *  Description:
2534  *  If the interrupt is because of a received frame or if the
2535  *  receive ring contains fresh as yet un-processed frames,this function is
2536  *  called. It picks out the RxD at which place the last Rx processing had
2537  *  stopped and sends the skb to the OSM's Rx handler and then increments
2538  *  the offset.
2539  *  Return Value:
2540  *  NONE.
2541  */
2542 static void rx_intr_handler(ring_info_t *ring_data)
2543 {
2544         nic_t *nic = ring_data->nic;
2545         struct net_device *dev = (struct net_device *) nic->dev;
2546         int get_block, put_block, put_offset;
2547         rx_curr_get_info_t get_info, put_info;
2548         RxD_t *rxdp;
2549         struct sk_buff *skb;
2550 #ifndef CONFIG_S2IO_NAPI
2551         int pkt_cnt = 0;
2552 #endif
2553         spin_lock(&nic->rx_lock);
2554         if (atomic_read(&nic->card_state) == CARD_DOWN) {
2555                 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
2556                           __FUNCTION__, dev->name);
2557                 spin_unlock(&nic->rx_lock);
2558                 return;
2559         }
2560
2561         get_info = ring_data->rx_curr_get_info;
2562         get_block = get_info.block_index;
2563         put_info = ring_data->rx_curr_put_info;
2564         put_block = put_info.block_index;
2565         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2566 #ifndef CONFIG_S2IO_NAPI
2567         spin_lock(&nic->put_lock);
2568         put_offset = ring_data->put_pos;
2569         spin_unlock(&nic->put_lock);
2570 #else
2571         put_offset = (put_block * (rxd_count[nic->rxd_mode] + 1)) +
2572                 put_info.offset;
2573 #endif
2574         while (RXD_IS_UP2DT(rxdp)) {
2575                 /* If your are next to put index then it's FIFO full condition */
2576                 if ((get_block == put_block) &&
2577                     (get_info.offset + 1) == put_info.offset) {
2578                         DBG_PRINT(ERR_DBG, "%s: Ring Full\n",dev->name);
2579                         break;
2580                 }
2581                 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2582                 if (skb == NULL) {
2583                         DBG_PRINT(ERR_DBG, "%s: The skb is ",
2584                                   dev->name);
2585                         DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2586                         spin_unlock(&nic->rx_lock);
2587                         return;
2588                 }
2589                 if (nic->rxd_mode == RXD_MODE_1) {
2590                         pci_unmap_single(nic->pdev, (dma_addr_t)
2591                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2592                                  dev->mtu +
2593                                  HEADER_ETHERNET_II_802_3_SIZE +
2594                                  HEADER_802_2_SIZE +
2595                                  HEADER_SNAP_SIZE,
2596                                  PCI_DMA_FROMDEVICE);
2597                 } else if (nic->rxd_mode == RXD_MODE_3B) {
2598                         pci_unmap_single(nic->pdev, (dma_addr_t)
2599                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2600                                  BUF0_LEN, PCI_DMA_FROMDEVICE);
2601                         pci_unmap_single(nic->pdev, (dma_addr_t)
2602                                  ((RxD3_t*)rxdp)->Buffer1_ptr,
2603                                  BUF1_LEN, PCI_DMA_FROMDEVICE);
2604                         pci_unmap_single(nic->pdev, (dma_addr_t)
2605                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2606                                  dev->mtu + 4,
2607                                  PCI_DMA_FROMDEVICE);
2608                 } else {
2609                         pci_unmap_single(nic->pdev, (dma_addr_t)
2610                                          ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2611                                          PCI_DMA_FROMDEVICE);
2612                         pci_unmap_single(nic->pdev, (dma_addr_t)
2613                                          ((RxD3_t*)rxdp)->Buffer1_ptr,
2614                                          l3l4hdr_size + 4,
2615                                          PCI_DMA_FROMDEVICE);
2616                         pci_unmap_single(nic->pdev, (dma_addr_t)
2617                                          ((RxD3_t*)rxdp)->Buffer2_ptr,
2618                                          dev->mtu, PCI_DMA_FROMDEVICE);
2619                 }
2620                 rx_osm_handler(ring_data, rxdp);
2621                 get_info.offset++;
2622                 ring_data->rx_curr_get_info.offset = get_info.offset;
2623                 rxdp = ring_data->rx_blocks[get_block].
2624                                 rxds[get_info.offset].virt_addr;
2625                 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2626                         get_info.offset = 0;
2627                         ring_data->rx_curr_get_info.offset = get_info.offset;
2628                         get_block++;
2629                         if (get_block == ring_data->block_count)
2630                                 get_block = 0;
2631                         ring_data->rx_curr_get_info.block_index = get_block;
2632                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2633                 }
2634
2635 #ifdef CONFIG_S2IO_NAPI
2636                 nic->pkts_to_process -= 1;
2637                 if (!nic->pkts_to_process)
2638                         break;
2639 #else
2640                 pkt_cnt++;
2641                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2642                         break;
2643 #endif
2644         }
2645         spin_unlock(&nic->rx_lock);
2646 }
2647
2648 /**
2649  *  tx_intr_handler - Transmit interrupt handler
2650  *  @nic : device private variable
2651  *  Description:
2652  *  If an interrupt was raised to indicate DMA complete of the
2653  *  Tx packet, this function is called. It identifies the last TxD
2654  *  whose buffer was freed and frees all skbs whose data have already
2655  *  DMA'ed into the NICs internal memory.
2656  *  Return Value:
2657  *  NONE
2658  */
2659
2660 static void tx_intr_handler(fifo_info_t *fifo_data)
2661 {
2662         nic_t *nic = fifo_data->nic;
2663         struct net_device *dev = (struct net_device *) nic->dev;
2664         tx_curr_get_info_t get_info, put_info;
2665         struct sk_buff *skb;
2666         TxD_t *txdlp;
2667         u16 j, frg_cnt;
2668
2669         get_info = fifo_data->tx_curr_get_info;
2670         put_info = fifo_data->tx_curr_put_info;
2671         txdlp = (TxD_t *) fifo_data->list_info[get_info.offset].
2672             list_virt_addr;
2673         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2674                (get_info.offset != put_info.offset) &&
2675                (txdlp->Host_Control)) {
2676                 /* Check for TxD errors */
2677                 if (txdlp->Control_1 & TXD_T_CODE) {
2678                         unsigned long long err;
2679                         err = txdlp->Control_1 & TXD_T_CODE;
2680                         if ((err >> 48) == 0xA) {
2681                                 DBG_PRINT(TX_DBG, "TxD returned due \
2682 to loss of link\n");
2683                         }
2684                         else {
2685                                 DBG_PRINT(ERR_DBG, "***TxD error \
2686 %llx\n", err);
2687                         }
2688                 }
2689
2690                 skb = (struct sk_buff *) ((unsigned long)
2691                                 txdlp->Host_Control);
2692                 if (skb == NULL) {
2693                         DBG_PRINT(ERR_DBG, "%s: Null skb ",
2694                         __FUNCTION__);
2695                         DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2696                         return;
2697                 }
2698
2699                 frg_cnt = skb_shinfo(skb)->nr_frags;
2700                 nic->tx_pkt_count++;
2701
2702                 pci_unmap_single(nic->pdev, (dma_addr_t)
2703                                  txdlp->Buffer_Pointer,
2704                                  skb->len - skb->data_len,
2705                                  PCI_DMA_TODEVICE);
2706                 if (frg_cnt) {
2707                         TxD_t *temp;
2708                         temp = txdlp;
2709                         txdlp++;
2710                         for (j = 0; j < frg_cnt; j++, txdlp++) {
2711                                 skb_frag_t *frag =
2712                                     &skb_shinfo(skb)->frags[j];
2713                                 if (!txdlp->Buffer_Pointer)
2714                                         break;
2715                                 pci_unmap_page(nic->pdev,
2716                                                (dma_addr_t)
2717                                                txdlp->
2718                                                Buffer_Pointer,
2719                                                frag->size,
2720                                                PCI_DMA_TODEVICE);
2721                         }
2722                         txdlp = temp;
2723                 }
2724                 memset(txdlp, 0,
2725                        (sizeof(TxD_t) * fifo_data->max_txds));
2726
2727                 /* Updating the statistics block */
2728                 nic->stats.tx_bytes += skb->len;
2729                 dev_kfree_skb_irq(skb);
2730
2731                 get_info.offset++;
2732                 get_info.offset %= get_info.fifo_len + 1;
2733                 txdlp = (TxD_t *) fifo_data->list_info
2734                     [get_info.offset].list_virt_addr;
2735                 fifo_data->tx_curr_get_info.offset =
2736                     get_info.offset;
2737         }
2738
2739         spin_lock(&nic->tx_lock);
2740         if (netif_queue_stopped(dev))
2741                 netif_wake_queue(dev);
2742         spin_unlock(&nic->tx_lock);
2743 }
2744
2745 /**
2746  *  alarm_intr_handler - Alarm Interrrupt handler
2747  *  @nic: device private variable
2748  *  Description: If the interrupt was neither because of Rx packet or Tx
2749  *  complete, this function is called. If the interrupt was to indicate
2750  *  a loss of link, the OSM link status handler is invoked for any other
2751  *  alarm interrupt the block that raised the interrupt is displayed
2752  *  and a H/W reset is issued.
2753  *  Return Value:
2754  *  NONE
2755 */
2756
2757 static void alarm_intr_handler(struct s2io_nic *nic)
2758 {
2759         struct net_device *dev = (struct net_device *) nic->dev;
2760         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2761         register u64 val64 = 0, err_reg = 0;
2762
2763         /* Handling link status change error Intr */
2764         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2765                 err_reg = readq(&bar0->mac_rmac_err_reg);
2766                 writeq(err_reg, &bar0->mac_rmac_err_reg);
2767                 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
2768                         schedule_work(&nic->set_link_task);
2769                 }
2770         }
2771
2772         /* Handling Ecc errors */
2773         val64 = readq(&bar0->mc_err_reg);
2774         writeq(val64, &bar0->mc_err_reg);
2775         if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
2776                 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
2777                         nic->mac_control.stats_info->sw_stat.
2778                                 double_ecc_errs++;
2779                         DBG_PRINT(INIT_DBG, "%s: Device indicates ",
2780                                   dev->name);
2781                         DBG_PRINT(INIT_DBG, "double ECC error!!\n");
2782                         if (nic->device_type != XFRAME_II_DEVICE) {
2783                                 /* Reset XframeI only if critical error */
2784                                 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
2785                                              MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
2786                                         netif_stop_queue(dev);
2787                                         schedule_work(&nic->rst_timer_task);
2788                                 }
2789                         }
2790                 } else {
2791                         nic->mac_control.stats_info->sw_stat.
2792                                 single_ecc_errs++;
2793                 }
2794         }
2795
2796         /* In case of a serious error, the device will be Reset. */
2797         val64 = readq(&bar0->serr_source);
2798         if (val64 & SERR_SOURCE_ANY) {
2799                 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
2800                 DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
2801                           (unsigned long long)val64);
2802                 netif_stop_queue(dev);
2803                 schedule_work(&nic->rst_timer_task);
2804         }
2805
2806         /*
2807          * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
2808          * Error occurs, the adapter will be recycled by disabling the
2809          * adapter enable bit and enabling it again after the device
2810          * becomes Quiescent.
2811          */
2812         val64 = readq(&bar0->pcc_err_reg);
2813         writeq(val64, &bar0->pcc_err_reg);
2814         if (val64 & PCC_FB_ECC_DB_ERR) {
2815                 u64 ac = readq(&bar0->adapter_control);
2816                 ac &= ~(ADAPTER_CNTL_EN);
2817                 writeq(ac, &bar0->adapter_control);
2818                 ac = readq(&bar0->adapter_control);
2819                 schedule_work(&nic->set_link_task);
2820         }
2821
2822         /* Other type of interrupts are not being handled now,  TODO */
2823 }
2824
2825 /**
2826  *  wait_for_cmd_complete - waits for a command to complete.
2827  *  @sp : private member of the device structure, which is a pointer to the
2828  *  s2io_nic structure.
2829  *  Description: Function that waits for a command to Write into RMAC
2830  *  ADDR DATA registers to be completed and returns either success or
2831  *  error depending on whether the command was complete or not.
2832  *  Return value:
2833  *   SUCCESS on success and FAILURE on failure.
2834  */
2835
2836 int wait_for_cmd_complete(nic_t * sp)
2837 {
2838         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2839         int ret = FAILURE, cnt = 0;
2840         u64 val64;
2841
2842         while (TRUE) {
2843                 val64 = readq(&bar0->rmac_addr_cmd_mem);
2844                 if (!(val64 & RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
2845                         ret = SUCCESS;
2846                         break;
2847                 }
2848                 msleep(50);
2849                 if (cnt++ > 10)
2850                         break;
2851         }
2852
2853         return ret;
2854 }
2855
2856 /**
2857  *  s2io_reset - Resets the card.
2858  *  @sp : private member of the device structure.
2859  *  Description: Function to Reset the card. This function then also
2860  *  restores the previously saved PCI configuration space registers as
2861  *  the card reset also resets the configuration space.
2862  *  Return value:
2863  *  void.
2864  */
2865
2866 void s2io_reset(nic_t * sp)
2867 {
2868         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2869         u64 val64;
2870         u16 subid, pci_cmd;
2871
2872         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
2873         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
2874
2875         val64 = SW_RESET_ALL;
2876         writeq(val64, &bar0->sw_reset);
2877
2878         /*
2879          * At this stage, if the PCI write is indeed completed, the
2880          * card is reset and so is the PCI Config space of the device.
2881          * So a read cannot be issued at this stage on any of the
2882          * registers to ensure the write into "sw_reset" register
2883          * has gone through.
2884          * Question: Is there any system call that will explicitly force
2885          * all the write commands still pending on the bus to be pushed
2886          * through?
2887          * As of now I'am just giving a 250ms delay and hoping that the
2888          * PCI write to sw_reset register is done by this time.
2889          */
2890         msleep(250);
2891
2892         /* Restore the PCI state saved during initialization. */
2893         pci_restore_state(sp->pdev);
2894         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
2895                                      pci_cmd);
2896         s2io_init_pci(sp);
2897
2898         msleep(250);
2899
2900         /* Set swapper to enable I/O register access */
2901         s2io_set_swapper(sp);
2902
2903         /* Restore the MSIX table entries from local variables */
2904         restore_xmsi_data(sp);
2905
2906         /* Clear certain PCI/PCI-X fields after reset */
2907         if (sp->device_type == XFRAME_II_DEVICE) {
2908                 /* Clear parity err detect bit */
2909                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
2910
2911                 /* Clearing PCIX Ecc status register */
2912                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
2913
2914                 /* Clearing PCI_STATUS error reflected here */
2915                 writeq(BIT(62), &bar0->txpic_int_reg);
2916         }
2917
2918         /* Reset device statistics maintained by OS */
2919         memset(&sp->stats, 0, sizeof (struct net_device_stats));
2920
2921         /* SXE-002: Configure link and activity LED to turn it off */
2922         subid = sp->pdev->subsystem_device;
2923         if (((subid & 0xFF) >= 0x07) &&
2924             (sp->device_type == XFRAME_I_DEVICE)) {
2925                 val64 = readq(&bar0->gpio_control);
2926                 val64 |= 0x0000800000000000ULL;
2927                 writeq(val64, &bar0->gpio_control);
2928                 val64 = 0x0411040400000000ULL;
2929                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2930         }
2931
2932         /*
2933          * Clear spurious ECC interrupts that would have occured on
2934          * XFRAME II cards after reset.
2935          */
2936         if (sp->device_type == XFRAME_II_DEVICE) {
2937                 val64 = readq(&bar0->pcc_err_reg);
2938                 writeq(val64, &bar0->pcc_err_reg);
2939         }
2940
2941         sp->device_enabled_once = FALSE;
2942 }
2943
2944 /**
2945  *  s2io_set_swapper - to set the swapper controle on the card
2946  *  @sp : private member of the device structure,
2947  *  pointer to the s2io_nic structure.
2948  *  Description: Function to set the swapper control on the card
2949  *  correctly depending on the 'endianness' of the system.
2950  *  Return value:
2951  *  SUCCESS on success and FAILURE on failure.
2952  */
2953
2954 int s2io_set_swapper(nic_t * sp)
2955 {
2956         struct net_device *dev = sp->dev;
2957         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2958         u64 val64, valt, valr;
2959
2960         /*
2961          * Set proper endian settings and verify the same by reading
2962          * the PIF Feed-back register.
2963          */
2964
2965         val64 = readq(&bar0->pif_rd_swapper_fb);
2966         if (val64 != 0x0123456789ABCDEFULL) {
2967                 int i = 0;
2968                 u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
2969                                 0x8100008181000081ULL,  /* FE=1, SE=0 */
2970                                 0x4200004242000042ULL,  /* FE=0, SE=1 */
2971                                 0};                     /* FE=0, SE=0 */
2972
2973                 while(i<4) {
2974                         writeq(value[i], &bar0->swapper_ctrl);
2975                         val64 = readq(&bar0->pif_rd_swapper_fb);
2976                         if (val64 == 0x0123456789ABCDEFULL)
2977                                 break;
2978                         i++;
2979                 }
2980                 if (i == 4) {
2981                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
2982                                 dev->name);
2983                         DBG_PRINT(ERR_DBG, "feedback read %llx\n",
2984                                 (unsigned long long) val64);
2985                         return FAILURE;
2986                 }
2987                 valr = value[i];
2988         } else {
2989                 valr = readq(&bar0->swapper_ctrl);
2990         }
2991
2992         valt = 0x0123456789ABCDEFULL;
2993         writeq(valt, &bar0->xmsi_address);
2994         val64 = readq(&bar0->xmsi_address);
2995
2996         if(val64 != valt) {
2997                 int i = 0;
2998                 u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
2999                                 0x0081810000818100ULL,  /* FE=1, SE=0 */
3000                                 0x0042420000424200ULL,  /* FE=0, SE=1 */
3001                                 0};                     /* FE=0, SE=0 */
3002
3003                 while(i<4) {
3004                         writeq((value[i] | valr), &bar0->swapper_ctrl);
3005                         writeq(valt, &bar0->xmsi_address);
3006                         val64 = readq(&bar0->xmsi_address);
3007                         if(val64 == valt)
3008                                 break;
3009                         i++;
3010                 }
3011                 if(i == 4) {
3012                         unsigned long long x = val64;
3013                         DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3014                         DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3015                         return FAILURE;
3016                 }
3017         }
3018         val64 = readq(&bar0->swapper_ctrl);
3019         val64 &= 0xFFFF000000000000ULL;
3020
3021 #ifdef  __BIG_ENDIAN
3022         /*
3023          * The device by default set to a big endian format, so a
3024          * big endian driver need not set anything.
3025          */
3026         val64 |= (SWAPPER_CTRL_TXP_FE |
3027                  SWAPPER_CTRL_TXP_SE |
3028                  SWAPPER_CTRL_TXD_R_FE |
3029                  SWAPPER_CTRL_TXD_W_FE |
3030                  SWAPPER_CTRL_TXF_R_FE |
3031                  SWAPPER_CTRL_RXD_R_FE |
3032                  SWAPPER_CTRL_RXD_W_FE |
3033                  SWAPPER_CTRL_RXF_W_FE |
3034                  SWAPPER_CTRL_XMSI_FE |
3035                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3036         if (sp->intr_type == INTA)
3037                 val64 |= SWAPPER_CTRL_XMSI_SE;
3038         writeq(val64, &bar0->swapper_ctrl);
3039 #else
3040         /*
3041          * Initially we enable all bits to make it accessible by the
3042          * driver, then we selectively enable only those bits that
3043          * we want to set.
3044          */
3045         val64 |= (SWAPPER_CTRL_TXP_FE |
3046                  SWAPPER_CTRL_TXP_SE |
3047                  SWAPPER_CTRL_TXD_R_FE |
3048                  SWAPPER_CTRL_TXD_R_SE |
3049                  SWAPPER_CTRL_TXD_W_FE |
3050                  SWAPPER_CTRL_TXD_W_SE |
3051                  SWAPPER_CTRL_TXF_R_FE |
3052                  SWAPPER_CTRL_RXD_R_FE |
3053                  SWAPPER_CTRL_RXD_R_SE |
3054                  SWAPPER_CTRL_RXD_W_FE |
3055                  SWAPPER_CTRL_RXD_W_SE |
3056                  SWAPPER_CTRL_RXF_W_FE |
3057                  SWAPPER_CTRL_XMSI_FE |
3058                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3059         if (sp->intr_type == INTA)
3060                 val64 |= SWAPPER_CTRL_XMSI_SE;
3061         writeq(val64, &bar0->swapper_ctrl);
3062 #endif
3063         val64 = readq(&bar0->swapper_ctrl);
3064
3065         /*
3066          * Verifying if endian settings are accurate by reading a
3067          * feedback register.
3068          */
3069         val64 = readq(&bar0->pif_rd_swapper_fb);
3070         if (val64 != 0x0123456789ABCDEFULL) {
3071                 /* Endian settings are incorrect, calls for another dekko. */
3072                 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3073                           dev->name);
3074                 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3075                           (unsigned long long) val64);
3076                 return FAILURE;
3077         }
3078
3079         return SUCCESS;
3080 }
3081
3082 int wait_for_msix_trans(nic_t *nic, int i)
3083 {
3084         XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
3085         u64 val64;
3086         int ret = 0, cnt = 0;
3087
3088         do {
3089                 val64 = readq(&bar0->xmsi_access);
3090                 if (!(val64 & BIT(15)))
3091                         break;
3092                 mdelay(1);
3093                 cnt++;
3094         } while(cnt < 5);
3095         if (cnt == 5) {
3096                 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3097                 ret = 1;
3098         }
3099
3100         return ret;
3101 }
3102
3103 void restore_xmsi_data(nic_t *nic)
3104 {
3105         XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
3106         u64 val64;
3107         int i;
3108
3109         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3110                 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3111                 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3112                 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3113                 writeq(val64, &bar0->xmsi_access);
3114                 if (wait_for_msix_trans(nic, i)) {
3115                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3116                         continue;
3117                 }
3118         }
3119 }
3120
3121 void store_xmsi_data(nic_t *nic)
3122 {
3123         XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
3124         u64 val64, addr, data;
3125         int i;
3126
3127         /* Store and display */
3128         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3129                 val64 = (BIT(15) | vBIT(i, 26, 6));
3130                 writeq(val64, &bar0->xmsi_access);
3131                 if (wait_for_msix_trans(nic, i)) {
3132                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3133                         continue;
3134                 }
3135                 addr = readq(&bar0->xmsi_address);
3136                 data = readq(&bar0->xmsi_data);
3137                 if (addr && data) {
3138                         nic->msix_info[i].addr = addr;
3139                         nic->msix_info[i].data = data;
3140                 }
3141         }
3142 }
3143
3144 int s2io_enable_msi(nic_t *nic)
3145 {
3146         XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
3147         u16 msi_ctrl, msg_val;
3148         struct config_param *config = &nic->config;
3149         struct net_device *dev = nic->dev;
3150         u64 val64, tx_mat, rx_mat;
3151         int i, err;
3152
3153         val64 = readq(&bar0->pic_control);
3154         val64 &= ~BIT(1);
3155         writeq(val64, &bar0->pic_control);
3156
3157         err = pci_enable_msi(nic->pdev);
3158         if (err) {
3159                 DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",
3160                           nic->dev->name);
3161                 return err;
3162         }
3163
3164         /*
3165          * Enable MSI and use MSI-1 in stead of the standard MSI-0
3166          * for interrupt handling.
3167          */
3168         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3169         msg_val ^= 0x1;
3170         pci_write_config_word(nic->pdev, 0x4c, msg_val);
3171         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3172
3173         pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);
3174         msi_ctrl |= 0x10;
3175         pci_write_config_word(nic->pdev, 0x42, msi_ctrl);
3176
3177         /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3178         tx_mat = readq(&bar0->tx_mat0_n[0]);
3179         for (i=0; i<config->tx_fifo_num; i++) {
3180                 tx_mat |= TX_MAT_SET(i, 1);
3181         }
3182         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3183
3184         rx_mat = readq(&bar0->rx_mat);
3185         for (i=0; i<config->rx_ring_num; i++) {
3186                 rx_mat |= RX_MAT_SET(i, 1);
3187         }
3188         writeq(rx_mat, &bar0->rx_mat);
3189
3190         dev->irq = nic->pdev->irq;
3191         return 0;
3192 }
3193
3194 int s2io_enable_msi_x(nic_t *nic)
3195 {
3196         XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
3197         u64 tx_mat, rx_mat;
3198         u16 msi_control; /* Temp variable */
3199         int ret, i, j, msix_indx = 1;
3200
3201         nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3202                                GFP_KERNEL);
3203         if (nic->entries == NULL) {
3204                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3205                 return -ENOMEM;
3206         }
3207         memset(nic->entries, 0, MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3208
3209         nic->s2io_entries =
3210                 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3211                                    GFP_KERNEL);
3212         if (nic->s2io_entries == NULL) {
3213                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3214                 kfree(nic->entries);
3215                 return -ENOMEM;
3216         }
3217         memset(nic->s2io_entries, 0,
3218                MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3219
3220         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3221                 nic->entries[i].entry = i;
3222                 nic->s2io_entries[i].entry = i;
3223                 nic->s2io_entries[i].arg = NULL;
3224                 nic->s2io_entries[i].in_use = 0;
3225         }
3226
3227         tx_mat = readq(&bar0->tx_mat0_n[0]);
3228         for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3229                 tx_mat |= TX_MAT_SET(i, msix_indx);
3230                 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3231                 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3232                 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3233         }
3234         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3235
3236         if (!nic->config.bimodal) {
3237                 rx_mat = readq(&bar0->rx_mat);
3238                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3239                         rx_mat |= RX_MAT_SET(j, msix_indx);
3240                         nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3241                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3242                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3243                 }
3244                 writeq(rx_mat, &bar0->rx_mat);
3245         } else {
3246                 tx_mat = readq(&bar0->tx_mat0_n[7]);
3247                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3248                         tx_mat |= TX_MAT_SET(i, msix_indx);
3249                         nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3250                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3251                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3252                 }
3253                 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3254         }
3255
3256         ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
3257         if (ret) {
3258                 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3259                 kfree(nic->entries);
3260                 kfree(nic->s2io_entries);
3261                 nic->entries = NULL;
3262                 nic->s2io_entries = NULL;
3263                 return -ENOMEM;
3264         }
3265
3266         /*
3267          * To enable MSI-X, MSI also needs to be enabled, due to a bug
3268          * in the herc NIC. (Temp change, needs to be removed later)
3269          */
3270         pci_read_config_word(nic->pdev, 0x42, &msi_control);
3271         msi_control |= 0x1; /* Enable MSI */
3272         pci_write_config_word(nic->pdev, 0x42, msi_control);
3273
3274         return 0;
3275 }
3276
3277 /* ********************************************************* *
3278  * Functions defined below concern the OS part of the driver *
3279  * ********************************************************* */
3280
3281 /**
3282  *  s2io_open - open entry point of the driver
3283  *  @dev : pointer to the device structure.
3284  *  Description:
3285  *  This function is the open entry point of the driver. It mainly calls a
3286  *  function to allocate Rx buffers and inserts them into the buffer
3287  *  descriptors and then enables the Rx part of the NIC.
3288  *  Return value:
3289  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3290  *   file on failure.
3291  */
3292
3293 int s2io_open(struct net_device *dev)
3294 {
3295         nic_t *sp = dev->priv;
3296         int err = 0;
3297         int i;
3298         u16 msi_control; /* Temp variable */
3299
3300         /*
3301          * Make sure you have link off by default every time
3302          * Nic is initialized
3303          */
3304         netif_carrier_off(dev);
3305         sp->last_link_state = 0;
3306
3307         /* Initialize H/W and enable interrupts */
3308         if (s2io_card_up(sp)) {
3309                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3310                           dev->name);
3311                 err = -ENODEV;
3312                 goto hw_init_failed;
3313         }
3314
3315         /* Store the values of the MSIX table in the nic_t structure */
3316         store_xmsi_data(sp);
3317
3318         /* After proper initialization of H/W, register ISR */
3319         if (sp->intr_type == MSI) {
3320                 err = request_irq((int) sp->pdev->irq, s2io_msi_handle,
3321                         SA_SHIRQ, sp->name, dev);
3322                 if (err) {
3323                         DBG_PRINT(ERR_DBG, "%s: MSI registration \
3324 failed\n", dev->name);
3325                         goto isr_registration_failed;
3326                 }
3327         }
3328         if (sp->intr_type == MSI_X) {
3329                 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
3330                         if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
3331                                 sprintf(sp->desc1, "%s:MSI-X-%d-TX",
3332                                         dev->name, i);
3333                                 err = request_irq(sp->entries[i].vector,
3334                                           s2io_msix_fifo_handle, 0, sp->desc1,
3335                                           sp->s2io_entries[i].arg);
3336                                 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc1,
3337                                                         sp->msix_info[i].addr);
3338                         } else {
3339                                 sprintf(sp->desc2, "%s:MSI-X-%d-RX",
3340                                         dev->name, i);
3341                                 err = request_irq(sp->entries[i].vector,
3342                                           s2io_msix_ring_handle, 0, sp->desc2,
3343                                           sp->s2io_entries[i].arg);
3344                                 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc2,
3345                                                         sp->msix_info[i].addr);
3346                         }
3347                         if (err) {
3348                                 DBG_PRINT(ERR_DBG, "%s: MSI-X-%d registration \
3349 failed\n", dev->name, i);
3350                                 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
3351                                 goto isr_registration_failed;
3352                         }
3353                         sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
3354                 }
3355         }
3356         if (sp->intr_type == INTA) {
3357                 err = request_irq((int) sp->pdev->irq, s2io_isr, SA_SHIRQ,
3358                                 sp->name, dev);
3359                 if (err) {
3360                         DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
3361                                   dev->name);
3362                         goto isr_registration_failed;
3363                 }
3364         }
3365
3366         if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3367                 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3368                 err = -ENODEV;
3369                 goto setting_mac_address_failed;
3370         }
3371
3372         netif_start_queue(dev);
3373         return 0;
3374
3375 setting_mac_address_failed:
3376         if (sp->intr_type != MSI_X)
3377                 free_irq(sp->pdev->irq, dev);
3378 isr_registration_failed:
3379         del_timer_sync(&sp->alarm_timer);
3380         if (sp->intr_type == MSI_X) {
3381                 if (sp->device_type == XFRAME_II_DEVICE) {
3382                         for (i=1; (sp->s2io_entries[i].in_use ==
3383                                 MSIX_REGISTERED_SUCCESS); i++) {
3384                                 int vector = sp->entries[i].vector;
3385                                 void *arg = sp->s2io_entries[i].arg;
3386
3387                                 free_irq(vector, arg);
3388                         }
3389                         pci_disable_msix(sp->pdev);
3390
3391                         /* Temp */
3392                         pci_read_config_word(sp->pdev, 0x42, &msi_control);
3393                         msi_control &= 0xFFFE; /* Disable MSI */
3394                         pci_write_config_word(sp->pdev, 0x42, msi_control);
3395                 }
3396         }
3397         else if (sp->intr_type == MSI)
3398                 pci_disable_msi(sp->pdev);
3399         s2io_reset(sp);
3400 hw_init_failed:
3401         if (sp->intr_type == MSI_X) {
3402                 if (sp->entries)
3403                         kfree(sp->entries);
3404                 if (sp->s2io_entries)
3405                         kfree(sp->s2io_entries);
3406         }
3407         return err;
3408 }
3409
3410 /**
3411  *  s2io_close -close entry point of the driver
3412  *  @dev : device pointer.
3413  *  Description:
3414  *  This is the stop entry point of the driver. It needs to undo exactly
3415  *  whatever was done by the open entry point,thus it's usually referred to
3416  *  as the close function.Among other things this function mainly stops the
3417  *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3418  *  Return value:
3419  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3420  *  file on failure.
3421  */
3422
3423 int s2io_close(struct net_device *dev)
3424 {
3425         nic_t *sp = dev->priv;
3426         int i;
3427         u16 msi_control;
3428
3429         flush_scheduled_work();
3430         netif_stop_queue(dev);
3431         /* Reset card, kill tasklet and free Tx and Rx buffers. */
3432         s2io_card_down(sp);
3433
3434         if (sp->intr_type == MSI_X) {
3435                 if (sp->device_type == XFRAME_II_DEVICE) {
3436                         for (i=1; (sp->s2io_entries[i].in_use ==
3437                                         MSIX_REGISTERED_SUCCESS); i++) {
3438                                 int vector = sp->entries[i].vector;
3439                                 void *arg = sp->s2io_entries[i].arg;
3440
3441                                 free_irq(vector, arg);
3442                         }
3443                         pci_read_config_word(sp->pdev, 0x42, &msi_control);
3444                         msi_control &= 0xFFFE; /* Disable MSI */
3445                         pci_write_config_word(sp->pdev, 0x42, msi_control);
3446
3447                         pci_disable_msix(sp->pdev);
3448                 }
3449         }
3450         else {
3451                 free_irq(sp->pdev->irq, dev);
3452                 if (sp->intr_type == MSI)
3453                         pci_disable_msi(sp->pdev);
3454         }
3455         sp->device_close_flag = TRUE;   /* Device is shut down. */
3456         return 0;
3457 }
3458
3459 /**
3460  *  s2io_xmit - Tx entry point of te driver
3461  *  @skb : the socket buffer containing the Tx data.
3462  *  @dev : device pointer.
3463  *  Description :
3464  *  This function is the Tx entry point of the driver. S2IO NIC supports
3465  *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
3466  *  NOTE: when device cant queue the pkt,just the trans_start variable will
3467  *  not be upadted.
3468  *  Return value:
3469  *  0 on success & 1 on failure.
3470  */
3471
3472 int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3473 {
3474         nic_t *sp = dev->priv;
3475         u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3476         register u64 val64;
3477         TxD_t *txdp;
3478         TxFIFO_element_t __iomem *tx_fifo;
3479         unsigned long flags;
3480 #ifdef NETIF_F_TSO
3481         int mss;
3482 #endif
3483         u16 vlan_tag = 0;
3484         int vlan_priority = 0;
3485         mac_info_t *mac_control;
3486         struct config_param *config;
3487
3488         mac_control = &sp->mac_control;
3489         config = &sp->config;
3490
3491         DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
3492         spin_lock_irqsave(&sp->tx_lock, flags);
3493         if (atomic_read(&sp->card_state) == CARD_DOWN) {
3494                 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
3495                           dev->name);
3496                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3497                 dev_kfree_skb(skb);
3498                 return 0;
3499         }
3500
3501         queue = 0;
3502
3503         /* Get Fifo number to Transmit based on vlan priority */
3504         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3505                 vlan_tag = vlan_tx_tag_get(skb);
3506                 vlan_priority = vlan_tag >> 13;
3507                 queue = config->fifo_mapping[vlan_priority];
3508         }
3509
3510         put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
3511         get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
3512         txdp = (TxD_t *) mac_control->fifos[queue].list_info[put_off].
3513                 list_virt_addr;
3514
3515         queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
3516         /* Avoid "put" pointer going beyond "get" pointer */
3517         if (txdp->Host_Control || (((put_off + 1) % queue_len) == get_off)) {
3518                 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3519                 netif_stop_queue(dev);
3520                 dev_kfree_skb(skb);
3521                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3522                 return 0;
3523         }
3524
3525         /* A buffer with no data will be dropped */
3526         if (!skb->len) {
3527                 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3528                 dev_kfree_skb(skb);
3529                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3530                 return 0;
3531         }
3532
3533 #ifdef NETIF_F_TSO
3534         mss = skb_shinfo(skb)->tso_size;
3535         if (mss) {
3536                 txdp->Control_1 |= TXD_TCP_LSO_EN;
3537                 txdp->Control_1 |= TXD_TCP_LSO_MSS(mss);
3538         }
3539 #endif
3540
3541         frg_cnt = skb_shinfo(skb)->nr_frags;
3542         frg_len = skb->len - skb->data_len;
3543
3544         txdp->Buffer_Pointer = pci_map_single
3545             (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
3546         txdp->Host_Control = (unsigned long) skb;
3547         if (skb->ip_summed == CHECKSUM_HW) {
3548                 txdp->Control_2 |=
3549                     (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
3550                      TXD_TX_CKO_UDP_EN);
3551         }
3552
3553         txdp->Control_2 |= config->tx_intr_type;
3554
3555         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3556                 txdp->Control_2 |= TXD_VLAN_ENABLE;
3557                 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
3558         }
3559
3560         txdp->Control_1 |= (TXD_BUFFER0_SIZE(frg_len) |
3561                             TXD_GATHER_CODE_FIRST);
3562         txdp->Control_1 |= TXD_LIST_OWN_XENA;
3563
3564         /* For fragmented SKB. */
3565         for (i = 0; i < frg_cnt; i++) {
3566                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3567                 /* A '0' length fragment will be ignored */
3568                 if (!frag->size)
3569                         continue;
3570                 txdp++;
3571                 txdp->Buffer_Pointer = (u64) pci_map_page
3572                     (sp->pdev, frag->page, frag->page_offset,
3573                      frag->size, PCI_DMA_TODEVICE);
3574                 txdp->Control_1 |= TXD_BUFFER0_SIZE(frag->size);
3575         }
3576         txdp->Control_1 |= TXD_GATHER_CODE_LAST;
3577
3578         tx_fifo = mac_control->tx_FIFO_start[queue];
3579         val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
3580         writeq(val64, &tx_fifo->TxDL_Pointer);
3581
3582         val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
3583                  TX_FIFO_LAST_LIST);
3584
3585 #ifdef NETIF_F_TSO
3586         if (mss)
3587                 val64 |= TX_FIFO_SPECIAL_FUNC;
3588 #endif
3589         writeq(val64, &tx_fifo->List_Control);
3590
3591         mmiowb();
3592
3593         put_off++;
3594         put_off %= mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
3595         mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
3596
3597         /* Avoid "put" pointer going beyond "get" pointer */
3598         if (((put_off + 1) % queue_len) == get_off) {
3599                 DBG_PRINT(TX_DBG,
3600                           "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
3601                           put_off, get_off);
3602                 netif_stop_queue(dev);
3603         }
3604
3605         dev->trans_start = jiffies;
3606         spin_unlock_irqrestore(&sp->tx_lock, flags);
3607
3608         return 0;
3609 }
3610
3611 static void
3612 s2io_alarm_handle(unsigned long data)
3613 {
3614         nic_t *sp = (nic_t *)data;
3615
3616         alarm_intr_handler(sp);
3617         mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
3618 }
3619
3620 static irqreturn_t
3621 s2io_msi_handle(int irq, void *dev_id, struct pt_regs *regs)
3622 {
3623         struct net_device *dev = (struct net_device *) dev_id;
3624         nic_t *sp = dev->priv;
3625         int i;
3626         int ret;
3627         mac_info_t *mac_control;
3628         struct config_param *config;
3629
3630         atomic_inc(&sp->isr_cnt);
3631         mac_control = &sp->mac_control;
3632         config = &sp->config;
3633         DBG_PRINT(INTR_DBG, "%s: MSI handler\n", __FUNCTION__);
3634
3635         /* If Intr is because of Rx Traffic */
3636         for (i = 0; i < config->rx_ring_num; i++)
3637                 rx_intr_handler(&mac_control->rings[i]);
3638
3639         /* If Intr is because of Tx Traffic */
3640         for (i = 0; i < config->tx_fifo_num; i++)
3641                 tx_intr_handler(&mac_control->fifos[i]);
3642
3643         /*
3644          * If the Rx buffer count is below the panic threshold then
3645          * reallocate the buffers from the interrupt handler itself,
3646          * else schedule a tasklet to reallocate the buffers.
3647          */
3648         for (i = 0; i < config->rx_ring_num; i++) {
3649                 int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
3650                 int level = rx_buffer_level(sp, rxb_size, i);
3651
3652                 if ((level == PANIC) && (!TASKLET_IN_USE)) {
3653                         DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", dev->name);
3654                         DBG_PRINT(INTR_DBG, "PANIC levels\n");
3655                         if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) {
3656                                 DBG_PRINT(ERR_DBG, "%s:Out of memory",
3657                                           dev->name);
3658                                 DBG_PRINT(ERR_DBG, " in ISR!!\n");
3659                                 clear_bit(0, (&sp->tasklet_status));
3660                                 atomic_dec(&sp->isr_cnt);
3661                                 return IRQ_HANDLED;
3662                         }
3663                         clear_bit(0, (&sp->tasklet_status));
3664                 } else if (level == LOW) {
3665                         tasklet_schedule(&sp->task);
3666                 }
3667         }
3668
3669         atomic_dec(&sp->isr_cnt);
3670         return IRQ_HANDLED;
3671 }
3672
3673 static irqreturn_t
3674 s2io_msix_ring_handle(int irq, void *dev_id, struct pt_regs *regs)
3675 {
3676         ring_info_t *ring = (ring_info_t *)dev_id;
3677         nic_t *sp = ring->nic;
3678         int rxb_size, level, rng_n;
3679
3680         atomic_inc(&sp->isr_cnt);
3681         rx_intr_handler(ring);
3682
3683         rng_n = ring->ring_no;
3684         rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
3685         level = rx_buffer_level(sp, rxb_size, rng_n);
3686
3687         if ((level == PANIC) && (!TASKLET_IN_USE)) {
3688                 int ret;
3689                 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
3690                 DBG_PRINT(INTR_DBG, "PANIC levels\n");
3691                 if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
3692                         DBG_PRINT(ERR_DBG, "Out of memory in %s",
3693                                   __FUNCTION__);
3694                         clear_bit(0, (&sp->tasklet_status));
3695                         return IRQ_HANDLED;
3696                 }
3697                 clear_bit(0, (&sp->tasklet_status));
3698         } else if (level == LOW) {
3699                 tasklet_schedule(&sp->task);
3700         }
3701         atomic_dec(&sp->isr_cnt);
3702
3703         return IRQ_HANDLED;
3704 }
3705
3706 static irqreturn_t
3707 s2io_msix_fifo_handle(int irq, void *dev_id, struct pt_regs *regs)
3708 {
3709         fifo_info_t *fifo = (fifo_info_t *)dev_id;
3710         nic_t *sp = fifo->nic;
3711
3712         atomic_inc(&sp->isr_cnt);
3713         tx_intr_handler(fifo);
3714         atomic_dec(&sp->isr_cnt);
3715         return IRQ_HANDLED;
3716 }
3717
3718 static void s2io_txpic_intr_handle(nic_t *sp)
3719 {
3720         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3721         u64 val64;
3722
3723         val64 = readq(&bar0->pic_int_status);
3724         if (val64 & PIC_INT_GPIO) {
3725                 val64 = readq(&bar0->gpio_int_reg);
3726                 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
3727                     (val64 & GPIO_INT_REG_LINK_UP)) {
3728                         val64 |=  GPIO_INT_REG_LINK_DOWN;
3729                         val64 |= GPIO_INT_REG_LINK_UP;
3730                         writeq(val64, &bar0->gpio_int_reg);
3731                         goto masking;
3732                 }
3733
3734                 if (((sp->last_link_state == LINK_UP) &&
3735                         (val64 & GPIO_INT_REG_LINK_DOWN)) ||
3736                 ((sp->last_link_state == LINK_DOWN) &&
3737                 (val64 & GPIO_INT_REG_LINK_UP))) {
3738                         val64 = readq(&bar0->gpio_int_mask);
3739                         val64 |=  GPIO_INT_MASK_LINK_DOWN;
3740                         val64 |= GPIO_INT_MASK_LINK_UP;
3741                         writeq(val64, &bar0->gpio_int_mask);
3742                         s2io_set_link((unsigned long)sp);
3743                 }
3744 masking:
3745                 if (sp->last_link_state == LINK_UP) {
3746                         /*enable down interrupt */
3747                         val64 = readq(&bar0->gpio_int_mask);
3748                         /* unmasks link down intr */
3749                         val64 &=  ~GPIO_INT_MASK_LINK_DOWN;
3750                         /* masks link up intr */
3751                         val64 |= GPIO_INT_MASK_LINK_UP;
3752                         writeq(val64, &bar0->gpio_int_mask);
3753                 } else {
3754                         /*enable UP Interrupt */
3755                         val64 = readq(&bar0->gpio_int_mask);
3756                         /* unmasks link up interrupt */
3757                         val64 &= ~GPIO_INT_MASK_LINK_UP;
3758                         /* masks link down interrupt */
3759                         val64 |=  GPIO_INT_MASK_LINK_DOWN;
3760                         writeq(val64, &bar0->gpio_int_mask);
3761                 }
3762         }
3763 }
3764
3765 /**
3766  *  s2io_isr - ISR handler of the device .
3767  *  @irq: the irq of the device.
3768  *  @dev_id: a void pointer to the dev structure of the NIC.
3769  *  @pt_regs: pointer to the registers pushed on the stack.
3770  *  Description:  This function is the ISR handler of the device. It
3771  *  identifies the reason for the interrupt and calls the relevant
3772  *  service routines. As a contongency measure, this ISR allocates the
3773  *  recv buffers, if their numbers are below the panic value which is
3774  *  presently set to 25% of the original number of rcv buffers allocated.
3775  *  Return value:
3776  *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
3777  *   IRQ_NONE: will be returned if interrupt is not from our device
3778  */
3779 static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
3780 {
3781         struct net_device *dev = (struct net_device *) dev_id;
3782         nic_t *sp = dev->priv;
3783         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3784         int i;
3785         u64 reason = 0, val64;
3786         mac_info_t *mac_control;
3787         struct config_param *config;
3788
3789         atomic_inc(&sp->isr_cnt);
3790         mac_control = &sp->mac_control;
3791         config = &sp->config;
3792
3793         /*
3794          * Identify the cause for interrupt and call the appropriate
3795          * interrupt handler. Causes for the interrupt could be;
3796          * 1. Rx of packet.
3797          * 2. Tx complete.
3798          * 3. Link down.
3799          * 4. Error in any functional blocks of the NIC.
3800          */
3801         reason = readq(&bar0->general_int_status);
3802
3803         if (!reason) {
3804                 /* The interrupt was not raised by Xena. */
3805                 atomic_dec(&sp->isr_cnt);
3806                 return IRQ_NONE;
3807         }
3808
3809 #ifdef CONFIG_S2IO_NAPI
3810         if (reason & GEN_INTR_RXTRAFFIC) {
3811                 if (netif_rx_schedule_prep(dev)) {
3812                         en_dis_able_nic_intrs(sp, RX_TRAFFIC_INTR,
3813                                               DISABLE_INTRS);
3814                         __netif_rx_schedule(dev);
3815                 }
3816         }
3817 #else
3818         /* If Intr is because of Rx Traffic */
3819         if (reason & GEN_INTR_RXTRAFFIC) {
3820                 /*
3821                  * rx_traffic_int reg is an R1 register, writing all 1's
3822                  * will ensure that the actual interrupt causing bit get's
3823                  * cleared and hence a read can be avoided.
3824                  */
3825                 val64 = 0xFFFFFFFFFFFFFFFFULL;
3826                 writeq(val64, &bar0->rx_traffic_int);
3827                 for (i = 0; i < config->rx_ring_num; i++) {
3828                         rx_intr_handler(&mac_control->rings[i]);
3829                 }
3830         }
3831 #endif
3832
3833         /* If Intr is because of Tx Traffic */
3834         if (reason & GEN_INTR_TXTRAFFIC) {
3835                 /*
3836                  * tx_traffic_int reg is an R1 register, writing all 1's
3837                  * will ensure that the actual interrupt causing bit get's
3838                  * cleared and hence a read can be avoided.
3839                  */
3840                 val64 = 0xFFFFFFFFFFFFFFFFULL;
3841                 writeq(val64, &bar0->tx_traffic_int);
3842
3843                 for (i = 0; i < config->tx_fifo_num; i++)
3844                         tx_intr_handler(&mac_control->fifos[i]);
3845         }
3846
3847         if (reason & GEN_INTR_TXPIC)
3848                 s2io_txpic_intr_handle(sp);
3849         /*
3850          * If the Rx buffer count is below the panic threshold then
3851          * reallocate the buffers from the interrupt handler itself,
3852          * else schedule a tasklet to reallocate the buffers.
3853          */
3854 #ifndef CONFIG_S2IO_NAPI
3855         for (i = 0; i < config->rx_ring_num; i++) {
3856                 int ret;
3857                 int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
3858                 int level = rx_buffer_level(sp, rxb_size, i);
3859
3860                 if ((level == PANIC) && (!TASKLET_IN_USE)) {
3861                         DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", dev->name);
3862                         DBG_PRINT(INTR_DBG, "PANIC levels\n");
3863                         if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) {
3864                                 DBG_PRINT(ERR_DBG, "%s:Out of memory",
3865                                           dev->name);
3866                                 DBG_PRINT(ERR_DBG, " in ISR!!\n");
3867                                 clear_bit(0, (&sp->tasklet_status));
3868                                 atomic_dec(&sp->isr_cnt);
3869                                 return IRQ_HANDLED;
3870                         }
3871                         clear_bit(0, (&sp->tasklet_status));
3872                 } else if (level == LOW) {
3873                         tasklet_schedule(&sp->task);
3874                 }
3875         }
3876 #endif
3877
3878         atomic_dec(&sp->isr_cnt);
3879         return IRQ_HANDLED;
3880 }
3881
3882 /**
3883  * s2io_updt_stats -
3884  */
3885 static void s2io_updt_stats(nic_t *sp)
3886 {
3887         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3888         u64 val64;
3889         int cnt = 0;
3890
3891         if (atomic_read(&sp->card_state) == CARD_UP) {
3892                 /* Apprx 30us on a 133 MHz bus */
3893                 val64 = SET_UPDT_CLICKS(10) |
3894                         STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
3895                 writeq(val64, &bar0->stat_cfg);
3896                 do {
3897                         udelay(100);
3898                         val64 = readq(&bar0->stat_cfg);
3899                         if (!(val64 & BIT(0)))
3900                                 break;
3901                         cnt++;
3902                         if (cnt == 5)
3903                                 break; /* Updt failed */
3904                 } while(1);
3905         }
3906 }
3907
3908 /**
3909  *  s2io_get_stats - Updates the device statistics structure.
3910  *  @dev : pointer to the device structure.
3911  *  Description:
3912  *  This function updates the device statistics structure in the s2io_nic
3913  *  structure and returns a pointer to the same.
3914  *  Return value:
3915  *  pointer to the updated net_device_stats structure.
3916  */
3917
3918 struct net_device_stats *s2io_get_stats(struct net_device *dev)
3919 {
3920         nic_t *sp = dev->priv;
3921         mac_info_t *mac_control;
3922         struct config_param *config;
3923
3924
3925         mac_control = &sp->mac_control;
3926         config = &sp->config;
3927
3928         /* Configure Stats for immediate updt */
3929         s2io_updt_stats(sp);
3930
3931         sp->stats.tx_packets =
3932                 le32_to_cpu(mac_control->stats_info->tmac_frms);
3933         sp->stats.tx_errors =
3934                 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
3935         sp->stats.rx_errors =
3936                 le32_to_cpu(mac_control->stats_info->rmac_drop_frms);
3937         sp->stats.multicast =
3938                 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
3939         sp->stats.rx_length_errors =
3940                 le32_to_cpu(mac_control->stats_info->rmac_long_frms);
3941
3942         return (&sp->stats);
3943 }
3944
3945 /**
3946  *  s2io_set_multicast - entry point for multicast address enable/disable.
3947  *  @dev : pointer to the device structure
3948  *  Description:
3949  *  This function is a driver entry point which gets called by the kernel
3950  *  whenever multicast addresses must be enabled/disabled. This also gets
3951  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
3952  *  determine, if multicast address must be enabled or if promiscuous mode
3953  *  is to be disabled etc.
3954  *  Return value:
3955  *  void.
3956  */
3957
3958 static void s2io_set_multicast(struct net_device *dev)
3959 {
3960         int i, j, prev_cnt;
3961         struct dev_mc_list *mclist;
3962         nic_t *sp = dev->priv;
3963         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3964         u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
3965             0xfeffffffffffULL;
3966         u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
3967         void __iomem *add;
3968
3969         if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
3970                 /*  Enable all Multicast addresses */
3971                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
3972                        &bar0->rmac_addr_data0_mem);
3973                 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
3974                        &bar0->rmac_addr_data1_mem);
3975                 val64 = RMAC_ADDR_CMD_MEM_WE |
3976                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
3977                     RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
3978                 writeq(val64, &bar0->rmac_addr_cmd_mem);
3979                 /* Wait till command completes */
3980                 wait_for_cmd_complete(sp);
3981
3982                 sp->m_cast_flg = 1;
3983                 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
3984         } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
3985                 /*  Disable all Multicast addresses */
3986                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
3987                        &bar0->rmac_addr_data0_mem);
3988                 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
3989                        &bar0->rmac_addr_data1_mem);
3990                 val64 = RMAC_ADDR_CMD_MEM_WE |
3991                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
3992                     RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
3993                 writeq(val64, &bar0->rmac_addr_cmd_mem);
3994                 /* Wait till command completes */
3995                 wait_for_cmd_complete(sp);
3996
3997                 sp->m_cast_flg = 0;
3998                 sp->all_multi_pos = 0;
3999         }
4000
4001         if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4002                 /*  Put the NIC into promiscuous mode */
4003                 add = &bar0->mac_cfg;
4004                 val64 = readq(&bar0->mac_cfg);
4005                 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4006
4007                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4008                 writel((u32) val64, add);
4009                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4010                 writel((u32) (val64 >> 32), (add + 4));
4011
4012                 val64 = readq(&bar0->mac_cfg);
4013                 sp->promisc_flg = 1;
4014                 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
4015                           dev->name);
4016         } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4017                 /*  Remove the NIC from promiscuous mode */
4018                 add = &bar0->mac_cfg;
4019                 val64 = readq(&bar0->mac_cfg);
4020                 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4021
4022                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4023                 writel((u32) val64, add);
4024                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4025                 writel((u32) (val64 >> 32), (add + 4));
4026
4027                 val64 = readq(&bar0->mac_cfg);
4028                 sp->promisc_flg = 0;
4029                 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
4030                           dev->name);
4031         }
4032
4033         /*  Update individual M_CAST address list */
4034         if ((!sp->m_cast_flg) && dev->mc_count) {
4035                 if (dev->mc_count >
4036                     (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4037                         DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4038                                   dev->name);
4039                         DBG_PRINT(ERR_DBG, "can be added, please enable ");
4040                         DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4041                         return;
4042                 }
4043
4044                 prev_cnt = sp->mc_addr_count;
4045                 sp->mc_addr_count = dev->mc_count;
4046
4047                 /* Clear out the previous list of Mc in the H/W. */
4048                 for (i = 0; i < prev_cnt; i++) {
4049                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4050                                &bar0->rmac_addr_data0_mem);
4051                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4052                                 &bar0->rmac_addr_data1_mem);
4053                         val64 = RMAC_ADDR_CMD_MEM_WE |
4054                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4055                             RMAC_ADDR_CMD_MEM_OFFSET
4056                             (MAC_MC_ADDR_START_OFFSET + i);
4057                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4058
4059                         /* Wait for command completes */
4060                         if (wait_for_cmd_complete(sp)) {
4061                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4062                                           dev->name);
4063                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4064                                 return;
4065                         }
4066                 }
4067
4068                 /* Create the new Rx filter list and update the same in H/W. */
4069                 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4070                      i++, mclist = mclist->next) {
4071                         memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4072                                ETH_ALEN);
4073                         for (j = 0; j < ETH_ALEN; j++) {
4074                                 mac_addr |= mclist->dmi_addr[j];
4075                                 mac_addr <<= 8;
4076                         }
4077                         mac_addr >>= 8;
4078                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4079                                &bar0->rmac_addr_data0_mem);
4080                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4081                                 &bar0->rmac_addr_data1_mem);
4082                         val64 = RMAC_ADDR_CMD_MEM_WE |
4083                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4084                             RMAC_ADDR_CMD_MEM_OFFSET
4085                             (i + MAC_MC_ADDR_START_OFFSET);
4086                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4087
4088                         /* Wait for command completes */
4089                         if (wait_for_cmd_complete(sp)) {
4090                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4091                                           dev->name);
4092                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4093                                 return;
4094                         }
4095                 }
4096         }
4097 }
4098
4099 /**
4100  *  s2io_set_mac_addr - Programs the Xframe mac address
4101  *  @dev : pointer to the device structure.
4102  *  @addr: a uchar pointer to the new mac address which is to be set.
4103  *  Description : This procedure will program the Xframe to receive
4104  *  frames with new Mac Address
4105  *  Return value: SUCCESS on success and an appropriate (-)ve integer
4106  *  as defined in errno.h file on failure.
4107  */
4108
4109 int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
4110 {
4111         nic_t *sp = dev->priv;
4112         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4113         register u64 val64, mac_addr = 0;
4114         int i;
4115
4116         /*
4117          * Set the new MAC address as the new unicast filter and reflect this
4118          * change on the device address registered with the OS. It will be
4119          * at offset 0.
4120          */
4121         for (i = 0; i < ETH_ALEN; i++) {
4122                 mac_addr <<= 8;
4123                 mac_addr |= addr[i];
4124         }
4125
4126         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4127                &bar0->rmac_addr_data0_mem);
4128
4129         val64 =
4130             RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4131             RMAC_ADDR_CMD_MEM_OFFSET(0);
4132         writeq(val64, &bar0->rmac_addr_cmd_mem);
4133         /* Wait till command completes */
4134         if (wait_for_cmd_complete(sp)) {
4135                 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4136                 return FAILURE;
4137         }
4138
4139         return SUCCESS;
4140 }
4141
4142 /**
4143  * s2io_ethtool_sset - Sets different link parameters.
4144  * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
4145  * @info: pointer to the structure with parameters given by ethtool to set
4146  * link information.
4147  * Description:
4148  * The function sets different link parameters provided by the user onto
4149  * the NIC.
4150  * Return value:
4151  * 0 on success.
4152 */
4153
4154 static int s2io_ethtool_sset(struct net_device *dev,
4155                              struct ethtool_cmd *info)
4156 {
4157         nic_t *sp = dev->priv;
4158         if ((info->autoneg == AUTONEG_ENABLE) ||
4159             (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4160                 return -EINVAL;
4161         else {
4162                 s2io_close(sp->dev);
4163                 s2io_open(sp->dev);
4164         }
4165
4166         return 0;
4167 }
4168
4169 /**
4170  * s2io_ethtol_gset - Return link specific information.
4171  * @sp : private member of the device structure, pointer to the
4172  *      s2io_nic structure.
4173  * @info : pointer to the structure with parameters given by ethtool
4174  * to return link information.
4175  * Description:
4176  * Returns link specific information like speed, duplex etc.. to ethtool.
4177  * Return value :
4178  * return 0 on success.
4179  */
4180
4181 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4182 {
4183         nic_t *sp = dev->priv;
4184         info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4185         info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4186         info->port = PORT_FIBRE;
4187         /* info->transceiver?? TODO */
4188
4189         if (netif_carrier_ok(sp->dev)) {
4190                 info->speed = 10000;
4191                 info->duplex = DUPLEX_FULL;
4192         } else {
4193                 info->speed = -1;
4194                 info->duplex = -1;
4195         }
4196
4197         info->autoneg = AUTONEG_DISABLE;
4198         return 0;
4199 }
4200
4201 /**
4202  * s2io_ethtool_gdrvinfo - Returns driver specific information.
4203  * @sp : private member of the device structure, which is a pointer to the
4204  * s2io_nic structure.
4205  * @info : pointer to the structure with parameters given by ethtool to
4206  * return driver information.
4207  * Description:
4208  * Returns driver specefic information like name, version etc.. to ethtool.
4209  * Return value:
4210  *  void
4211  */
4212
4213 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
4214                                   struct ethtool_drvinfo *info)
4215 {
4216         nic_t *sp = dev->priv;
4217
4218         strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
4219         strncpy(info->version, s2io_driver_version, sizeof(info->version));
4220         strncpy(info->fw_version, "", sizeof(info->fw_version));
4221         strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
4222         info->regdump_len = XENA_REG_SPACE;
4223         info->eedump_len = XENA_EEPROM_SPACE;
4224         info->testinfo_len = S2IO_TEST_LEN;
4225         info->n_stats = S2IO_STAT_LEN;
4226 }
4227
4228 /**
4229  *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
4230  *  @sp: private member of the device structure, which is a pointer to the
4231  *  s2io_nic structure.
4232  *  @regs : pointer to the structure with parameters given by ethtool for
4233  *  dumping the registers.
4234  *  @reg_space: The input argumnet into which all the registers are dumped.
4235  *  Description:
4236  *  Dumps the entire register space of xFrame NIC into the user given
4237  *  buffer area.
4238  * Return value :
4239  * void .
4240 */
4241
4242 static void s2io_ethtool_gregs(struct net_device *dev,
4243                                struct ethtool_regs *regs, void *space)
4244 {
4245         int i;
4246         u64 reg;
4247         u8 *reg_space = (u8 *) space;
4248         nic_t *sp = dev->priv;
4249
4250         regs->len = XENA_REG_SPACE;
4251         regs->version = sp->pdev->subsystem_device;
4252
4253         for (i = 0; i < regs->len; i += 8) {
4254                 reg = readq(sp->bar0 + i);
4255                 memcpy((reg_space + i), &reg, 8);
4256         }
4257 }
4258
4259 /**
4260  *  s2io_phy_id  - timer function that alternates adapter LED.
4261  *  @data : address of the private member of the device structure, which
4262  *  is a pointer to the s2io_nic structure, provided as an u32.
4263  * Description: This is actually the timer function that alternates the
4264  * adapter LED bit of the adapter control bit to set/reset every time on
4265  * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
4266  *  once every second.
4267 */
4268 static void s2io_phy_id(unsigned long data)
4269 {
4270         nic_t *sp = (nic_t *) data;
4271         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4272         u64 val64 = 0;
4273         u16 subid;
4274
4275         subid = sp->pdev->subsystem_device;
4276         if ((sp->device_type == XFRAME_II_DEVICE) ||
4277                    ((subid & 0xFF) >= 0x07)) {
4278                 val64 = readq(&bar0->gpio_control);
4279                 val64 ^= GPIO_CTRL_GPIO_0;
4280                 writeq(val64, &bar0->gpio_control);
4281         } else {
4282                 val64 = readq(&bar0->adapter_control);
4283                 val64 ^= ADAPTER_LED_ON;
4284                 writeq(val64, &bar0->adapter_control);
4285         }
4286
4287         mod_timer(&sp->id_timer, jiffies + HZ / 2);
4288 }
4289
4290 /**
4291  * s2io_ethtool_idnic - To physically identify the nic on the system.
4292  * @sp : private member of the device structure, which is a pointer to the
4293  * s2io_nic structure.
4294  * @id : pointer to the structure with identification parameters given by
4295  * ethtool.
4296  * Description: Used to physically identify the NIC on the system.
4297  * The Link LED will blink for a time specified by the user for
4298  * identification.
4299  * NOTE: The Link has to be Up to be able to blink the LED. Hence
4300  * identification is possible only if it's link is up.
4301  * Return value:
4302  * int , returns 0 on success
4303  */
4304
4305 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
4306 {
4307         u64 val64 = 0, last_gpio_ctrl_val;
4308         nic_t *sp = dev->priv;
4309         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4310         u16 subid;
4311
4312         subid = sp->pdev->subsystem_device;
4313         last_gpio_ctrl_val = readq(&bar0->gpio_control);
4314         if ((sp->device_type == XFRAME_I_DEVICE) &&
4315                 ((subid & 0xFF) < 0x07)) {
4316                 val64 = readq(&bar0->adapter_control);
4317                 if (!(val64 & ADAPTER_CNTL_EN)) {
4318                         printk(KERN_ERR
4319                                "Adapter Link down, cannot blink LED\n");
4320                         return -EFAULT;
4321                 }
4322         }
4323         if (sp->id_timer.function == NULL) {
4324                 init_timer(&sp->id_timer);
4325                 sp->id_timer.function = s2io_phy_id;
4326                 sp->id_timer.data = (unsigned long) sp;
4327         }
4328         mod_timer(&sp->id_timer, jiffies);
4329         if (data)
4330                 msleep_interruptible(data * HZ);
4331         else
4332                 msleep_interruptible(MAX_FLICKER_TIME);
4333         del_timer_sync(&sp->id_timer);
4334
4335         if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
4336                 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
4337                 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4338         }
4339
4340         return 0;
4341 }
4342
4343 /**
4344  * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
4345  * @sp : private member of the device structure, which is a pointer to the
4346  *      s2io_nic structure.
4347  * @ep : pointer to the structure with pause parameters given by ethtool.
4348  * Description:
4349  * Returns the Pause frame generation and reception capability of the NIC.
4350  * Return value:
4351  *  void
4352  */
4353 static void s2io_ethtool_getpause_data(struct net_device *dev,
4354                                        struct ethtool_pauseparam *ep)
4355 {
4356         u64 val64;
4357         nic_t *sp = dev->priv;
4358         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4359
4360         val64 = readq(&bar0->rmac_pause_cfg);
4361         if (val64 & RMAC_PAUSE_GEN_ENABLE)
4362                 ep->tx_pause = TRUE;
4363         if (val64 & RMAC_PAUSE_RX_ENABLE)
4364                 ep->rx_pause = TRUE;
4365         ep->autoneg = FALSE;
4366 }
4367
4368 /**
4369  * s2io_ethtool_setpause_data -  set/reset pause frame generation.
4370  * @sp : private member of the device structure, which is a pointer to the
4371  *      s2io_nic structure.
4372  * @ep : pointer to the structure with pause parameters given by ethtool.
4373  * Description:
4374  * It can be used to set or reset Pause frame generation or reception
4375  * support of the NIC.
4376  * Return value:
4377  * int, returns 0 on Success
4378  */
4379
4380 static int s2io_ethtool_setpause_data(struct net_device *dev,
4381                                struct ethtool_pauseparam *ep)
4382 {
4383         u64 val64;
4384         nic_t *sp = dev->priv;
4385         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4386
4387         val64 = readq(&bar0->rmac_pause_cfg);
4388         if (ep->tx_pause)
4389                 val64 |= RMAC_PAUSE_GEN_ENABLE;
4390         else
4391                 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
4392         if (ep->rx_pause)
4393                 val64 |= RMAC_PAUSE_RX_ENABLE;
4394         else
4395                 val64 &= ~RMAC_PAUSE_RX_ENABLE;
4396         writeq(val64, &bar0->rmac_pause_cfg);
4397         return 0;
4398 }
4399
4400 /**
4401  * read_eeprom - reads 4 bytes of data from user given offset.
4402  * @sp : private member of the device structure, which is a pointer to the
4403  *      s2io_nic structure.
4404  * @off : offset at which the data must be written
4405  * @data : Its an output parameter where the data read at the given
4406  *      offset is stored.
4407  * Description:
4408  * Will read 4 bytes of data from the user given offset and return the
4409  * read data.
4410  * NOTE: Will allow to read only part of the EEPROM visible through the
4411  *   I2C bus.
4412  * Return value:
4413  *  -1 on failure and 0 on success.
4414  */
4415
4416 #define S2IO_DEV_ID             5
4417 static int read_eeprom(nic_t * sp, int off, u64 * data)
4418 {
4419         int ret = -1;
4420         u32 exit_cnt = 0;
4421         u64 val64;
4422         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4423
4424         if (sp->device_type == XFRAME_I_DEVICE) {
4425                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4426                     I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
4427                     I2C_CONTROL_CNTL_START;
4428                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4429
4430                 while (exit_cnt < 5) {
4431                         val64 = readq(&bar0->i2c_control);
4432                         if (I2C_CONTROL_CNTL_END(val64)) {
4433                                 *data = I2C_CONTROL_GET_DATA(val64);
4434                                 ret = 0;
4435                                 break;
4436                         }
4437                         msleep(50);
4438                         exit_cnt++;
4439                 }
4440         }
4441
4442         if (sp->device_type == XFRAME_II_DEVICE) {
4443                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4444                         SPI_CONTROL_BYTECNT(0x3) |
4445                         SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
4446                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4447                 val64 |= SPI_CONTROL_REQ;
4448                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4449                 while (exit_cnt < 5) {
4450                         val64 = readq(&bar0->spi_control);
4451                         if (val64 & SPI_CONTROL_NACK) {
4452                                 ret = 1;
4453                                 break;
4454                         } else if (val64 & SPI_CONTROL_DONE) {
4455                                 *data = readq(&bar0->spi_data);
4456                                 *data &= 0xffffff;
4457                                 ret = 0;
4458                                 break;
4459                         }
4460                         msleep(50);
4461                         exit_cnt++;
4462                 }
4463         }
4464         return ret;
4465 }
4466
4467 /**
4468  *  write_eeprom - actually writes the relevant part of the data value.
4469  *  @sp : private member of the device structure, which is a pointer to the
4470  *       s2io_nic structure.
4471  *  @off : offset at which the data must be written
4472  *  @data : The data that is to be written
4473  *  @cnt : Number of bytes of the data that are actually to be written into
4474  *  the Eeprom. (max of 3)
4475  * Description:
4476  *  Actually writes the relevant part of the data value into the Eeprom
4477  *  through the I2C bus.
4478  * Return value:
4479  *  0 on success, -1 on failure.
4480  */
4481
4482 static int write_eeprom(nic_t * sp, int off, u64 data, int cnt)
4483 {
4484         int exit_cnt = 0, ret = -1;
4485         u64 val64;
4486         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4487
4488         if (sp->device_type == XFRAME_I_DEVICE) {
4489                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4490                     I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
4491                     I2C_CONTROL_CNTL_START;
4492                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4493
4494                 while (exit_cnt < 5) {
4495                         val64 = readq(&bar0->i2c_control);
4496                         if (I2C_CONTROL_CNTL_END(val64)) {
4497                                 if (!(val64 & I2C_CONTROL_NACK))
4498                                         ret = 0;
4499                                 break;
4500                         }
4501                         msleep(50);
4502                         exit_cnt++;
4503                 }
4504         }
4505
4506         if (sp->device_type == XFRAME_II_DEVICE) {
4507                 int write_cnt = (cnt == 8) ? 0 : cnt;
4508                 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
4509
4510                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4511                         SPI_CONTROL_BYTECNT(write_cnt) |
4512                         SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
4513                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4514                 val64 |= SPI_CONTROL_REQ;
4515                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4516                 while (exit_cnt < 5) {
4517                         val64 = readq(&bar0->spi_control);
4518                         if (val64 & SPI_CONTROL_NACK) {
4519                                 ret = 1;
4520                                 break;
4521                         } else if (val64 & SPI_CONTROL_DONE) {
4522                                 ret = 0;
4523                                 break;
4524                         }
4525                         msleep(50);
4526                         exit_cnt++;
4527                 }
4528         }
4529         return ret;
4530 }
4531
4532 /**
4533  *  s2io_ethtool_geeprom  - reads the value stored in the Eeprom.
4534  *  @sp : private member of the device structure, which is a pointer to the *       s2io_nic structure.
4535  *  @eeprom : pointer to the user level structure provided by ethtool,
4536  *  containing all relevant information.
4537  *  @data_buf : user defined value to be written into Eeprom.
4538  *  Description: Reads the values stored in the Eeprom at given offset
4539  *  for a given length. Stores these values int the input argument data
4540  *  buffer 'data_buf' and returns these to the caller (ethtool.)
4541  *  Return value:
4542  *  int  0 on success
4543  */
4544
4545 static int s2io_ethtool_geeprom(struct net_device *dev,
4546                          struct ethtool_eeprom *eeprom, u8 * data_buf)
4547 {
4548         u32 i, valid;
4549         u64 data;
4550         nic_t *sp = dev->priv;
4551
4552         eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
4553
4554         if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
4555                 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
4556
4557         for (i = 0; i < eeprom->len; i += 4) {
4558                 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
4559                         DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
4560                         return -EFAULT;
4561                 }
4562                 valid = INV(data);
4563                 memcpy((data_buf + i), &valid, 4);
4564         }
4565         return 0;
4566 }
4567
4568 /**
4569  *  s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
4570  *  @sp : private member of the device structure, which is a pointer to the
4571  *  s2io_nic structure.
4572  *  @eeprom : pointer to the user level structure provided by ethtool,
4573  *  containing all relevant information.
4574  *  @data_buf ; user defined value to be written into Eeprom.
4575  *  Description:
4576  *  Tries to write the user provided value in the Eeprom, at the offset
4577  *  given by the user.
4578  *  Return value:
4579  *  0 on success, -EFAULT on failure.
4580  */
4581
4582 static int s2io_ethtool_seeprom(struct net_device *dev,
4583                                 struct ethtool_eeprom *eeprom,
4584                                 u8 * data_buf)
4585 {
4586         int len = eeprom->len, cnt = 0;
4587         u64 valid = 0, data;
4588         nic_t *sp = dev->priv;
4589
4590         if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
4591                 DBG_PRINT(ERR_DBG,
4592                           "ETHTOOL_WRITE_EEPROM Err: Magic value ");
4593                 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
4594                           eeprom->magic);
4595                 return -EFAULT;
4596         }
4597
4598         while (len) {
4599                 data = (u32) data_buf[cnt] & 0x000000FF;
4600                 if (data) {
4601                         valid = (u32) (data << 24);
4602                 } else
4603                         valid = data;
4604
4605                 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
4606                         DBG_PRINT(ERR_DBG,
4607                                   "ETHTOOL_WRITE_EEPROM Err: Cannot ");
4608                         DBG_PRINT(ERR_DBG,
4609                                   "write into the specified offset\n");
4610                         return -EFAULT;
4611                 }
4612                 cnt++;
4613                 len--;
4614         }
4615
4616         return 0;
4617 }
4618
4619 /**
4620  * s2io_register_test - reads and writes into all clock domains.
4621  * @sp : private member of the device structure, which is a pointer to the
4622  * s2io_nic structure.
4623  * @data : variable that returns the result of each of the test conducted b
4624  * by the driver.
4625  * Description:
4626  * Read and write into all clock domains. The NIC has 3 clock domains,
4627  * see that registers in all the three regions are accessible.
4628  * Return value:
4629  * 0 on success.
4630  */
4631
4632 static int s2io_register_test(nic_t * sp, uint64_t * data)
4633 {
4634         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4635         u64 val64 = 0, exp_val;
4636         int fail = 0;
4637
4638         val64 = readq(&bar0->pif_rd_swapper_fb);
4639         if (val64 != 0x123456789abcdefULL) {
4640                 fail = 1;
4641                 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
4642         }
4643
4644         val64 = readq(&bar0->rmac_pause_cfg);
4645         if (val64 != 0xc000ffff00000000ULL) {
4646                 fail = 1;
4647                 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
4648         }
4649
4650         val64 = readq(&bar0->rx_queue_cfg);
4651         if (sp->device_type == XFRAME_II_DEVICE)
4652                 exp_val = 0x0404040404040404ULL;
4653         else
4654                 exp_val = 0x0808080808080808ULL;
4655         if (val64 != exp_val) {
4656                 fail = 1;
4657                 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
4658         }
4659
4660         val64 = readq(&bar0->xgxs_efifo_cfg);
4661         if (val64 != 0x000000001923141EULL) {
4662                 fail = 1;
4663                 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
4664         }
4665
4666         val64 = 0x5A5A5A5A5A5A5A5AULL;
4667         writeq(val64, &bar0->xmsi_data);
4668         val64 = readq(&bar0->xmsi_data);
4669         if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
4670                 fail = 1;
4671                 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
4672         }
4673
4674         val64 = 0xA5A5A5A5A5A5A5A5ULL;
4675         writeq(val64, &bar0->xmsi_data);
4676         val64 = readq(&bar0->xmsi_data);
4677         if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
4678                 fail = 1;
4679                 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
4680         }
4681
4682         *data = fail;
4683         return fail;
4684 }
4685
4686 /**
4687  * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
4688  * @sp : private member of the device structure, which is a pointer to the
4689  * s2io_nic structure.
4690  * @data:variable that returns the result of each of the test conducted by
4691  * the driver.
4692  * Description:
4693  * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
4694  * register.
4695  * Return value:
4696  * 0 on success.
4697  */
4698
4699 static int s2io_eeprom_test(nic_t * sp, uint64_t * data)
4700 {
4701         int fail = 0;
4702         u64 ret_data, org_4F0, org_7F0;
4703         u8 saved_4F0 = 0, saved_7F0 = 0;
4704         struct net_device *dev = sp->dev;
4705
4706         /* Test Write Error at offset 0 */
4707         /* Note that SPI interface allows write access to all areas
4708          * of EEPROM. Hence doing all negative testing only for Xframe I.
4709          */
4710         if (sp->device_type == XFRAME_I_DEVICE)
4711                 if (!write_eeprom(sp, 0, 0, 3))
4712                         fail = 1;
4713
4714         /* Save current values at offsets 0x4F0 and 0x7F0 */
4715         if (!read_eeprom(sp, 0x4F0, &org_4F0))
4716                 saved_4F0 = 1;
4717         if (!read_eeprom(sp, 0x7F0, &org_7F0))
4718                 saved_7F0 = 1;
4719
4720         /* Test Write at offset 4f0 */
4721         if (write_eeprom(sp, 0x4F0, 0x012345, 3))
4722                 fail = 1;
4723         if (read_eeprom(sp, 0x4F0, &ret_data))
4724                 fail = 1;
4725
4726         if (ret_data != 0x012345) {
4727                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. Data written %llx Data read %llx\n", dev->name, (u64)0x12345, ret_data);
4728                 fail = 1;
4729         }
4730
4731         /* Reset the EEPROM data go FFFF */
4732         write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
4733
4734         /* Test Write Request Error at offset 0x7c */
4735         if (sp->device_type == XFRAME_I_DEVICE)
4736                 if (!write_eeprom(sp, 0x07C, 0, 3))
4737                         fail = 1;
4738
4739         /* Test Write Request at offset 0x7f0 */
4740         if (write_eeprom(sp, 0x7F0, 0x012345, 3))
4741                 fail = 1;
4742         if (read_eeprom(sp, 0x7F0, &ret_data))
4743                 fail = 1;
4744
4745         if (ret_data != 0x012345) {
4746                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. Data written %llx Data read %llx\n", dev->name, (u64)0x12345, ret_data);
4747                 fail = 1;
4748         }
4749
4750         /* Reset the EEPROM data go FFFF */
4751         write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
4752
4753         if (sp->device_type == XFRAME_I_DEVICE) {
4754                 /* Test Write Error at offset 0x80 */
4755                 if (!write_eeprom(sp, 0x080, 0, 3))
4756                         fail = 1;
4757
4758                 /* Test Write Error at offset 0xfc */
4759                 if (!write_eeprom(sp, 0x0FC, 0, 3))
4760                         fail = 1;
4761
4762                 /* Test Write Error at offset 0x100 */
4763                 if (!write_eeprom(sp, 0x100, 0, 3))
4764                         fail = 1;
4765
4766                 /* Test Write Error at offset 4ec */
4767                 if (!write_eeprom(sp, 0x4EC, 0, 3))
4768                         fail = 1;
4769         }
4770
4771         /* Restore values at offsets 0x4F0 and 0x7F0 */
4772         if (saved_4F0)
4773                 write_eeprom(sp, 0x4F0, org_4F0, 3);
4774         if (saved_7F0)
4775                 write_eeprom(sp, 0x7F0, org_7F0, 3);
4776
4777         *data = fail;
4778         return fail;
4779 }
4780
4781 /**
4782  * s2io_bist_test - invokes the MemBist test of the card .
4783  * @sp : private member of the device structure, which is a pointer to the
4784  * s2io_nic structure.
4785  * @data:variable that returns the result of each of the test conducted by
4786  * the driver.
4787  * Description:
4788  * This invokes the MemBist test of the card. We give around
4789  * 2 secs time for the Test to complete. If it's still not complete
4790  * within this peiod, we consider that the test failed.
4791  * Return value:
4792  * 0 on success and -1 on failure.
4793  */
4794
4795 static int s2io_bist_test(nic_t * sp, uint64_t * data)
4796 {
4797         u8 bist = 0;
4798         int cnt = 0, ret = -1;
4799
4800         pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
4801         bist |= PCI_BIST_START;
4802         pci_write_config_word(sp->pdev, PCI_BIST, bist);
4803
4804         while (cnt < 20) {
4805                 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
4806                 if (!(bist & PCI_BIST_START)) {
4807                         *data = (bist & PCI_BIST_CODE_MASK);
4808                         ret = 0;
4809                         break;
4810                 }
4811                 msleep(100);
4812                 cnt++;
4813         }
4814
4815         return ret;
4816 }
4817
4818 /**
4819  * s2io-link_test - verifies the link state of the nic
4820  * @sp ; private member of the device structure, which is a pointer to the
4821  * s2io_nic structure.
4822  * @data: variable that returns the result of each of the test conducted by
4823  * the driver.
4824  * Description:
4825  * The function verifies the link state of the NIC and updates the input
4826  * argument 'data' appropriately.
4827  * Return value:
4828  * 0 on success.
4829  */
4830
4831 static int s2io_link_test(nic_t * sp, uint64_t * data)
4832 {
4833         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4834         u64 val64;
4835
4836         val64 = readq(&bar0->adapter_status);
4837         if (val64 & ADAPTER_STATUS_RMAC_LOCAL_FAULT)
4838                 *data = 1;
4839
4840         return 0;
4841 }
4842
4843 /**
4844  * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
4845  * @sp - private member of the device structure, which is a pointer to the
4846  * s2io_nic structure.
4847  * @data - variable that returns the result of each of the test
4848  * conducted by the driver.
4849  * Description:
4850  *  This is one of the offline test that tests the read and write
4851  *  access to the RldRam chip on the NIC.
4852  * Return value:
4853  *  0 on success.
4854  */
4855
4856 static int s2io_rldram_test(nic_t * sp, uint64_t * data)
4857 {
4858         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4859         u64 val64;
4860         int cnt, iteration = 0, test_fail = 0;
4861
4862         val64 = readq(&bar0->adapter_control);
4863         val64 &= ~ADAPTER_ECC_EN;
4864         writeq(val64, &bar0->adapter_control);
4865
4866         val64 = readq(&bar0->mc_rldram_test_ctrl);
4867         val64 |= MC_RLDRAM_TEST_MODE;
4868         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
4869
4870         val64 = readq(&bar0->mc_rldram_mrs);
4871         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
4872         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
4873
4874         val64 |= MC_RLDRAM_MRS_ENABLE;
4875         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
4876
4877         while (iteration < 2) {
4878                 val64 = 0x55555555aaaa0000ULL;
4879                 if (iteration == 1) {
4880                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
4881                 }
4882                 writeq(val64, &bar0->mc_rldram_test_d0);
4883
4884                 val64 = 0xaaaa5a5555550000ULL;
4885                 if (iteration == 1) {
4886                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
4887                 }
4888                 writeq(val64, &bar0->mc_rldram_test_d1);
4889
4890                 val64 = 0x55aaaaaaaa5a0000ULL;
4891                 if (iteration == 1) {
4892                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
4893                 }
4894                 writeq(val64, &bar0->mc_rldram_test_d2);
4895
4896                 val64 = (u64) (0x0000003ffffe0100ULL);
4897                 writeq(val64, &bar0->mc_rldram_test_add);
4898
4899                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
4900                         MC_RLDRAM_TEST_GO;
4901                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
4902
4903                 for (cnt = 0; cnt < 5; cnt++) {
4904                         val64 = readq(&bar0->mc_rldram_test_ctrl);
4905                         if (val64 & MC_RLDRAM_TEST_DONE)
4906                                 break;
4907                         msleep(200);
4908                 }
4909
4910                 if (cnt == 5)
4911                         break;
4912
4913                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
4914                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
4915
4916                 for (cnt = 0; cnt < 5; cnt++) {
4917                         val64 = readq(&bar0->mc_rldram_test_ctrl);
4918                         if (val64 & MC_RLDRAM_TEST_DONE)
4919                                 break;
4920                         msleep(500);
4921                 }
4922
4923                 if (cnt == 5)
4924                         break;
4925
4926                 val64 = readq(&bar0->mc_rldram_test_ctrl);
4927                 if (!(val64 & MC_RLDRAM_TEST_PASS))
4928                         test_fail = 1;
4929
4930                 iteration++;
4931         }
4932
4933         *data = test_fail;
4934
4935         /* Bring the adapter out of test mode */
4936         SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
4937
4938         return test_fail;
4939 }
4940
4941 /**
4942  *  s2io_ethtool_test - conducts 6 tsets to determine the health of card.
4943  *  @sp : private member of the device structure, which is a pointer to the
4944  *  s2io_nic structure.
4945  *  @ethtest : pointer to a ethtool command specific structure that will be
4946  *  returned to the user.
4947  *  @data : variable that returns the result of each of the test
4948  * conducted by the driver.
4949  * Description:
4950  *  This function conducts 6 tests ( 4 offline and 2 online) to determine
4951  *  the health of the card.
4952  * Return value:
4953  *  void
4954  */
4955
4956 static void s2io_ethtool_test(struct net_device *dev,
4957                               struct ethtool_test *ethtest,
4958                               uint64_t * data)
4959 {
4960         nic_t *sp = dev->priv;
4961         int orig_state = netif_running(sp->dev);
4962
4963         if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
4964                 /* Offline Tests. */
4965                 if (orig_state)
4966                         s2io_close(sp->dev);
4967
4968                 if (s2io_register_test(sp, &data[0]))
4969                         ethtest->flags |= ETH_TEST_FL_FAILED;
4970
4971                 s2io_reset(sp);
4972
4973                 if (s2io_rldram_test(sp, &data[3]))
4974                         ethtest->flags |= ETH_TEST_FL_FAILED;
4975
4976                 s2io_reset(sp);
4977
4978                 if (s2io_eeprom_test(sp, &data[1]))
4979                         ethtest->flags |= ETH_TEST_FL_FAILED;
4980
4981                 if (s2io_bist_test(sp, &data[4]))
4982                         ethtest->flags |= ETH_TEST_FL_FAILED;
4983
4984                 if (orig_state)
4985                         s2io_open(sp->dev);
4986
4987                 data[2] = 0;
4988         } else {
4989                 /* Online Tests. */
4990                 if (!orig_state) {
4991                         DBG_PRINT(ERR_DBG,
4992                                   "%s: is not up, cannot run test\n",
4993                                   dev->name);
4994                         data[0] = -1;
4995                         data[1] = -1;
4996                         data[2] = -1;
4997                         data[3] = -1;
4998                         data[4] = -1;
4999                 }
5000
5001                 if (s2io_link_test(sp, &data[2]))
5002                         ethtest->flags |= ETH_TEST_FL_FAILED;
5003
5004                 data[0] = 0;
5005                 data[1] = 0;
5006                 data[3] = 0;
5007                 data[4] = 0;
5008         }
5009 }
5010
5011 static void s2io_get_ethtool_stats(struct net_device *dev,
5012                                    struct ethtool_stats *estats,
5013                                    u64 * tmp_stats)
5014 {
5015         int i = 0;
5016         nic_t *sp = dev->priv;
5017         StatInfo_t *stat_info = sp->mac_control.stats_info;
5018
5019         s2io_updt_stats(sp);
5020         tmp_stats[i++] =
5021                 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32  |
5022                 le32_to_cpu(stat_info->tmac_frms);
5023         tmp_stats[i++] =
5024                 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5025                 le32_to_cpu(stat_info->tmac_data_octets);
5026         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
5027         tmp_stats[i++] =
5028                 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5029                 le32_to_cpu(stat_info->tmac_mcst_frms);
5030         tmp_stats[i++] =
5031                 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5032                 le32_to_cpu(stat_info->tmac_bcst_frms);
5033         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
5034         tmp_stats[i++] =
5035                 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5036                 le32_to_cpu(stat_info->tmac_any_err_frms);
5037         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
5038         tmp_stats[i++] =
5039                 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5040                 le32_to_cpu(stat_info->tmac_vld_ip);
5041         tmp_stats[i++] =
5042                 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5043                 le32_to_cpu(stat_info->tmac_drop_ip);
5044         tmp_stats[i++] =
5045                 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5046                 le32_to_cpu(stat_info->tmac_icmp);
5047         tmp_stats[i++] =
5048                 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5049                 le32_to_cpu(stat_info->tmac_rst_tcp);
5050         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
5051         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5052                 le32_to_cpu(stat_info->tmac_udp);
5053         tmp_stats[i++] =
5054                 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5055                 le32_to_cpu(stat_info->rmac_vld_frms);
5056         tmp_stats[i++] =
5057                 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5058                 le32_to_cpu(stat_info->rmac_data_octets);
5059         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5060         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
5061         tmp_stats[i++] =
5062                 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5063                 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5064         tmp_stats[i++] =
5065                 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5066                 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
5067         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
5068         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5069         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
5070         tmp_stats[i++] =
5071                 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
5072                 le32_to_cpu(stat_info->rmac_discarded_frms);
5073         tmp_stats[i++] =
5074                 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
5075                 le32_to_cpu(stat_info->rmac_usized_frms);
5076         tmp_stats[i++] =
5077                 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
5078                 le32_to_cpu(stat_info->rmac_osized_frms);
5079         tmp_stats[i++] =
5080                 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
5081                 le32_to_cpu(stat_info->rmac_frag_frms);
5082         tmp_stats[i++] =
5083                 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
5084                 le32_to_cpu(stat_info->rmac_jabber_frms);
5085         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
5086                 le32_to_cpu(stat_info->rmac_ip);
5087         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
5088         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
5089         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
5090                 le32_to_cpu(stat_info->rmac_drop_ip);
5091         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
5092                 le32_to_cpu(stat_info->rmac_icmp);
5093         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
5094         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
5095                 le32_to_cpu(stat_info->rmac_udp);
5096         tmp_stats[i++] =
5097                 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
5098                 le32_to_cpu(stat_info->rmac_err_drp_udp);
5099         tmp_stats[i++] =
5100                 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
5101                 le32_to_cpu(stat_info->rmac_pause_cnt);
5102         tmp_stats[i++] =
5103                 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
5104                 le32_to_cpu(stat_info->rmac_accepted_ip);
5105         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
5106         tmp_stats[i++] = 0;
5107         tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
5108         tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
5109 }
5110
5111 int s2io_ethtool_get_regs_len(struct net_device *dev)
5112 {
5113         return (XENA_REG_SPACE);
5114 }
5115
5116
5117 u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
5118 {
5119         nic_t *sp = dev->priv;
5120
5121         return (sp->rx_csum);
5122 }
5123 int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
5124 {
5125         nic_t *sp = dev->priv;
5126
5127         if (data)
5128                 sp->rx_csum = 1;
5129         else
5130                 sp->rx_csum = 0;
5131
5132         return 0;
5133 }
5134 int s2io_get_eeprom_len(struct net_device *dev)
5135 {
5136         return (XENA_EEPROM_SPACE);
5137 }
5138
5139 int s2io_ethtool_self_test_count(struct net_device *dev)
5140 {
5141         return (S2IO_TEST_LEN);
5142 }
5143 void s2io_ethtool_get_strings(struct net_device *dev,
5144                               u32 stringset, u8 * data)
5145 {
5146         switch (stringset) {
5147         case ETH_SS_TEST:
5148                 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
5149                 break;
5150         case ETH_SS_STATS:
5151                 memcpy(data, &ethtool_stats_keys,
5152                        sizeof(ethtool_stats_keys));
5153         }
5154 }
5155 static int s2io_ethtool_get_stats_count(struct net_device *dev)
5156 {
5157         return (S2IO_STAT_LEN);
5158 }
5159
5160 int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
5161 {
5162         if (data)
5163                 dev->features |= NETIF_F_IP_CSUM;
5164         else
5165                 dev->features &= ~NETIF_F_IP_CSUM;
5166
5167         return 0;
5168 }
5169
5170
5171 static struct ethtool_ops netdev_ethtool_ops = {
5172         .get_settings = s2io_ethtool_gset,
5173         .set_settings = s2io_ethtool_sset,
5174         .get_drvinfo = s2io_ethtool_gdrvinfo,
5175         .get_regs_len = s2io_ethtool_get_regs_len,
5176         .get_regs = s2io_ethtool_gregs,
5177         .get_link = ethtool_op_get_link,
5178         .get_eeprom_len = s2io_get_eeprom_len,
5179         .get_eeprom = s2io_ethtool_geeprom,
5180         .set_eeprom = s2io_ethtool_seeprom,
5181         .get_pauseparam = s2io_ethtool_getpause_data,
5182         .set_pauseparam = s2io_ethtool_setpause_data,
5183         .get_rx_csum = s2io_ethtool_get_rx_csum,
5184         .set_rx_csum = s2io_ethtool_set_rx_csum,
5185         .get_tx_csum = ethtool_op_get_tx_csum,
5186         .set_tx_csum = s2io_ethtool_op_set_tx_csum,
5187         .get_sg = ethtool_op_get_sg,
5188         .set_sg = ethtool_op_set_sg,
5189 #ifdef NETIF_F_TSO
5190         .get_tso = ethtool_op_get_tso,
5191         .set_tso = ethtool_op_set_tso,
5192 #endif
5193         .self_test_count = s2io_ethtool_self_test_count,
5194         .self_test = s2io_ethtool_test,
5195         .get_strings = s2io_ethtool_get_strings,
5196         .phys_id = s2io_ethtool_idnic,
5197         .get_stats_count = s2io_ethtool_get_stats_count,
5198         .get_ethtool_stats = s2io_get_ethtool_stats
5199 };
5200
5201 /**
5202  *  s2io_ioctl - Entry point for the Ioctl
5203  *  @dev :  Device pointer.
5204  *  @ifr :  An IOCTL specefic structure, that can contain a pointer to
5205  *  a proprietary structure used to pass information to the driver.
5206  *  @cmd :  This is used to distinguish between the different commands that
5207  *  can be passed to the IOCTL functions.
5208  *  Description:
5209  *  Currently there are no special functionality supported in IOCTL, hence
5210  *  function always return EOPNOTSUPPORTED
5211  */
5212
5213 int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5214 {
5215         return -EOPNOTSUPP;
5216 }
5217
5218 /**
5219  *  s2io_change_mtu - entry point to change MTU size for the device.
5220  *   @dev : device pointer.
5221  *   @new_mtu : the new MTU size for the device.
5222  *   Description: A driver entry point to change MTU size for the device.
5223  *   Before changing the MTU the device must be stopped.
5224  *  Return value:
5225  *   0 on success and an appropriate (-)ve integer as defined in errno.h
5226  *   file on failure.
5227  */
5228
5229 int s2io_change_mtu(struct net_device *dev, int new_mtu)
5230 {
5231         nic_t *sp = dev->priv;
5232
5233         if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
5234                 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
5235                           dev->name);
5236                 return -EPERM;
5237         }
5238
5239         dev->mtu = new_mtu;
5240         if (netif_running(dev)) {
5241                 s2io_card_down(sp);
5242                 netif_stop_queue(dev);
5243                 if (s2io_card_up(sp)) {
5244                         DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5245                                   __FUNCTION__);
5246                 }
5247                 if (netif_queue_stopped(dev))
5248                         netif_wake_queue(dev);
5249         } else { /* Device is down */
5250                 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5251                 u64 val64 = new_mtu;
5252
5253                 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
5254         }
5255
5256         return 0;
5257 }
5258
5259 /**
5260  *  s2io_tasklet - Bottom half of the ISR.
5261  *  @dev_adr : address of the device structure in dma_addr_t format.
5262  *  Description:
5263  *  This is the tasklet or the bottom half of the ISR. This is
5264  *  an extension of the ISR which is scheduled by the scheduler to be run
5265  *  when the load on the CPU is low. All low priority tasks of the ISR can
5266  *  be pushed into the tasklet. For now the tasklet is used only to
5267  *  replenish the Rx buffers in the Rx buffer descriptors.
5268  *  Return value:
5269  *  void.
5270  */
5271
5272 static void s2io_tasklet(unsigned long dev_addr)
5273 {
5274         struct net_device *dev = (struct net_device *) dev_addr;
5275         nic_t *sp = dev->priv;
5276         int i, ret;
5277         mac_info_t *mac_control;
5278         struct config_param *config;
5279
5280         mac_control = &sp->mac_control;
5281         config = &sp->config;
5282
5283         if (!TASKLET_IN_USE) {
5284                 for (i = 0; i < config->rx_ring_num; i++) {
5285                         ret = fill_rx_buffers(sp, i);
5286                         if (ret == -ENOMEM) {
5287                                 DBG_PRINT(ERR_DBG, "%s: Out of ",
5288                                           dev->name);
5289                                 DBG_PRINT(ERR_DBG, "memory in tasklet\n");
5290                                 break;
5291                         } else if (ret == -EFILL) {
5292                                 DBG_PRINT(ERR_DBG,
5293                                           "%s: Rx Ring %d is full\n",
5294                                           dev->name, i);
5295                                 break;
5296                         }
5297                 }
5298                 clear_bit(0, (&sp->tasklet_status));
5299         }
5300 }
5301
5302 /**
5303  * s2io_set_link - Set the LInk status
5304  * @data: long pointer to device private structue
5305  * Description: Sets the link status for the adapter
5306  */
5307
5308 static void s2io_set_link(unsigned long data)
5309 {
5310         nic_t *nic = (nic_t *) data;
5311         struct net_device *dev = nic->dev;
5312         XENA_dev_config_t __iomem *bar0 = nic->bar0;
5313         register u64 val64;
5314         u16 subid;
5315
5316         if (test_and_set_bit(0, &(nic->link_state))) {
5317                 /* The card is being reset, no point doing anything */
5318                 return;
5319         }
5320
5321         subid = nic->pdev->subsystem_device;
5322         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
5323                 /*
5324                  * Allow a small delay for the NICs self initiated
5325                  * cleanup to complete.
5326                  */
5327                 msleep(100);
5328         }
5329
5330         val64 = readq(&bar0->adapter_status);
5331         if (verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
5332                 if (LINK_IS_UP(val64)) {
5333                         val64 = readq(&bar0->adapter_control);
5334                         val64 |= ADAPTER_CNTL_EN;
5335                         writeq(val64, &bar0->adapter_control);
5336                         if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5337                                                              subid)) {
5338                                 val64 = readq(&bar0->gpio_control);
5339                                 val64 |= GPIO_CTRL_GPIO_0;
5340                                 writeq(val64, &bar0->gpio_control);
5341                                 val64 = readq(&bar0->gpio_control);
5342                         } else {
5343                                 val64 |= ADAPTER_LED_ON;
5344                                 writeq(val64, &bar0->adapter_control);
5345                         }
5346                         if (s2io_link_fault_indication(nic) ==
5347                                                 MAC_RMAC_ERR_TIMER) {
5348                                 val64 = readq(&bar0->adapter_status);
5349                                 if (!LINK_IS_UP(val64)) {
5350                                         DBG_PRINT(ERR_DBG, "%s:", dev->name);
5351                                         DBG_PRINT(ERR_DBG, " Link down");
5352                                         DBG_PRINT(ERR_DBG, "after ");
5353                                         DBG_PRINT(ERR_DBG, "enabling ");
5354                                         DBG_PRINT(ERR_DBG, "device \n");
5355                                 }
5356                         }
5357                         if (nic->device_enabled_once == FALSE) {
5358                                 nic->device_enabled_once = TRUE;
5359                         }
5360                         s2io_link(nic, LINK_UP);
5361                 } else {
5362                         if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5363                                                               subid)) {
5364                                 val64 = readq(&bar0->gpio_control);
5365                                 val64 &= ~GPIO_CTRL_GPIO_0;
5366                                 writeq(val64, &bar0->gpio_control);
5367                                 val64 = readq(&bar0->gpio_control);
5368                         }
5369                         s2io_link(nic, LINK_DOWN);
5370                 }
5371         } else {                /* NIC is not Quiescent. */
5372                 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
5373                 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
5374                 netif_stop_queue(dev);
5375         }
5376         clear_bit(0, &(nic->link_state));
5377 }
5378
5379 static void s2io_card_down(nic_t * sp)
5380 {
5381         int cnt = 0;
5382         XENA_dev_config_t __iomem *bar0 = sp->bar0;
5383         unsigned long flags;
5384         register u64 val64 = 0;
5385
5386         del_timer_sync(&sp->alarm_timer);
5387         /* If s2io_set_link task is executing, wait till it completes. */
5388         while (test_and_set_bit(0, &(sp->link_state))) {
5389                 msleep(50);
5390         }
5391         atomic_set(&sp->card_state, CARD_DOWN);
5392
5393         /* disable Tx and Rx traffic on the NIC */
5394         stop_nic(sp);
5395
5396         /* Kill tasklet. */
5397         tasklet_kill(&sp->task);
5398
5399         /* Check if the device is Quiescent and then Reset the NIC */
5400         do {
5401                 val64 = readq(&bar0->adapter_status);
5402                 if (verify_xena_quiescence(sp, val64, sp->device_enabled_once)) {
5403                         break;
5404                 }
5405
5406                 msleep(50);
5407                 cnt++;
5408                 if (cnt == 10) {
5409                         DBG_PRINT(ERR_DBG,
5410                                   "s2io_close:Device not Quiescent ");
5411                         DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
5412                                   (unsigned long long) val64);
5413                         break;
5414                 }
5415         } while (1);
5416         s2io_reset(sp);
5417
5418         /* Waiting till all Interrupt handlers are complete */
5419         cnt = 0;
5420         do {
5421                 msleep(10);
5422                 if (!atomic_read(&sp->isr_cnt))
5423                         break;
5424                 cnt++;
5425         } while(cnt < 5);
5426
5427         spin_lock_irqsave(&sp->tx_lock, flags);
5428         /* Free all Tx buffers */
5429         free_tx_buffers(sp);
5430         spin_unlock_irqrestore(&sp->tx_lock, flags);
5431
5432         /* Free all Rx buffers */
5433         spin_lock_irqsave(&sp->rx_lock, flags);
5434         free_rx_buffers(sp);
5435         spin_unlock_irqrestore(&sp->rx_lock, flags);
5436
5437         clear_bit(0, &(sp->link_state));
5438 }
5439
5440 static int s2io_card_up(nic_t * sp)
5441 {
5442         int i, ret = 0;
5443         mac_info_t *mac_control;
5444         struct config_param *config;
5445         struct net_device *dev = (struct net_device *) sp->dev;
5446
5447         /* Initialize the H/W I/O registers */
5448         if (init_nic(sp) != 0) {
5449                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
5450                           dev->name);
5451                 return -ENODEV;
5452         }
5453
5454         if (sp->intr_type == MSI)
5455                 ret = s2io_enable_msi(sp);
5456         else if (sp->intr_type == MSI_X)
5457                 ret = s2io_enable_msi_x(sp);
5458         if (ret) {
5459                 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
5460                 sp->intr_type = INTA;
5461         }
5462
5463         /*
5464          * Initializing the Rx buffers. For now we are considering only 1
5465          * Rx ring and initializing buffers into 30 Rx blocks
5466          */
5467         mac_control = &sp->mac_control;
5468         config = &sp->config;
5469
5470         for (i = 0; i < config->rx_ring_num; i++) {
5471                 if ((ret = fill_rx_buffers(sp, i))) {
5472                         DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
5473                                   dev->name);
5474                         s2io_reset(sp);
5475                         free_rx_buffers(sp);
5476                         return -ENOMEM;
5477                 }
5478                 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
5479                           atomic_read(&sp->rx_bufs_left[i]));
5480         }
5481
5482         /* Setting its receive mode */
5483         s2io_set_multicast(dev);
5484
5485         /* Enable tasklet for the device */
5486         tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
5487
5488         /* Enable Rx Traffic and interrupts on the NIC */
5489         if (start_nic(sp)) {
5490                 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
5491                 tasklet_kill(&sp->task);
5492                 s2io_reset(sp);
5493                 free_irq(dev->irq, dev);
5494                 free_rx_buffers(sp);
5495                 return -ENODEV;
5496         }
5497
5498         S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
5499
5500         atomic_set(&sp->card_state, CARD_UP);
5501         return 0;
5502 }
5503
5504 /**
5505  * s2io_restart_nic - Resets the NIC.
5506  * @data : long pointer to the device private structure
5507  * Description:
5508  * This function is scheduled to be run by the s2io_tx_watchdog
5509  * function after 0.5 secs to reset the NIC. The idea is to reduce
5510  * the run time of the watch dog routine which is run holding a
5511  * spin lock.
5512  */
5513
5514 static void s2io_restart_nic(unsigned long data)
5515 {
5516         struct net_device *dev = (struct net_device *) data;
5517         nic_t *sp = dev->priv;
5518
5519         s2io_card_down(sp);
5520         if (s2io_card_up(sp)) {
5521                 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5522                           dev->name);
5523         }
5524         netif_wake_queue(dev);
5525         DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
5526                   dev->name);
5527
5528 }
5529
5530 /**
5531  *  s2io_tx_watchdog - Watchdog for transmit side.
5532  *  @dev : Pointer to net device structure
5533  *  Description:
5534  *  This function is triggered if the Tx Queue is stopped
5535  *  for a pre-defined amount of time when the Interface is still up.
5536  *  If the Interface is jammed in such a situation, the hardware is
5537  *  reset (by s2io_close) and restarted again (by s2io_open) to
5538  *  overcome any problem that might have been caused in the hardware.
5539  *  Return value:
5540  *  void
5541  */
5542
5543 static void s2io_tx_watchdog(struct net_device *dev)
5544 {
5545         nic_t *sp = dev->priv;
5546
5547         if (netif_carrier_ok(dev)) {
5548                 schedule_work(&sp->rst_timer_task);
5549         }
5550 }
5551
5552 /**
5553  *   rx_osm_handler - To perform some OS related operations on SKB.
5554  *   @sp: private member of the device structure,pointer to s2io_nic structure.
5555  *   @skb : the socket buffer pointer.
5556  *   @len : length of the packet
5557  *   @cksum : FCS checksum of the frame.
5558  *   @ring_no : the ring from which this RxD was extracted.
5559  *   Description:
5560  *   This function is called by the Tx interrupt serivce routine to perform
5561  *   some OS related operations on the SKB before passing it to the upper
5562  *   layers. It mainly checks if the checksum is OK, if so adds it to the
5563  *   SKBs cksum variable, increments the Rx packet count and passes the SKB
5564  *   to the upper layer. If the checksum is wrong, it increments the Rx
5565  *   packet error count, frees the SKB and returns error.
5566  *   Return value:
5567  *   SUCCESS on success and -1 on failure.
5568  */
5569 static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
5570 {
5571         nic_t *sp = ring_data->nic;
5572         struct net_device *dev = (struct net_device *) sp->dev;
5573         struct sk_buff *skb = (struct sk_buff *)
5574                 ((unsigned long) rxdp->Host_Control);
5575         int ring_no = ring_data->ring_no;
5576         u16 l3_csum, l4_csum;
5577
5578         skb->dev = dev;
5579         if (rxdp->Control_1 & RXD_T_CODE) {
5580                 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
5581                 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
5582                           dev->name, err);
5583                 dev_kfree_skb(skb);
5584                 sp->stats.rx_crc_errors++;
5585                 atomic_dec(&sp->rx_bufs_left[ring_no]);
5586                 rxdp->Host_Control = 0;
5587                 return 0;
5588         }
5589
5590         /* Updating statistics */
5591         rxdp->Host_Control = 0;
5592         sp->rx_pkt_count++;
5593         sp->stats.rx_packets++;
5594         if (sp->rxd_mode == RXD_MODE_1) {
5595                 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
5596
5597                 sp->stats.rx_bytes += len;
5598                 skb_put(skb, len);
5599
5600         } else if (sp->rxd_mode >= RXD_MODE_3A) {
5601                 int get_block = ring_data->rx_curr_get_info.block_index;
5602                 int get_off = ring_data->rx_curr_get_info.offset;
5603                 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
5604                 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
5605                 unsigned char *buff = skb_push(skb, buf0_len);
5606
5607                 buffAdd_t *ba = &ring_data->ba[get_block][get_off];
5608                 sp->stats.rx_bytes += buf0_len + buf2_len;
5609                 memcpy(buff, ba->ba_0, buf0_len);
5610
5611                 if (sp->rxd_mode == RXD_MODE_3A) {
5612                         int buf1_len = RXD_GET_BUFFER1_SIZE_3(rxdp->Control_2);
5613
5614                         skb_put(skb, buf1_len);
5615                         skb->len += buf2_len;
5616                         skb->data_len += buf2_len;
5617                         skb->truesize += buf2_len;
5618                         skb_put(skb_shinfo(skb)->frag_list, buf2_len);
5619                         sp->stats.rx_bytes += buf1_len;
5620
5621                 } else
5622                         skb_put(skb, buf2_len);
5623         }
5624
5625         if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
5626             (sp->rx_csum)) {
5627                 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
5628                 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
5629                 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
5630                         /*
5631                          * NIC verifies if the Checksum of the received
5632                          * frame is Ok or not and accordingly returns
5633                          * a flag in the RxD.
5634                          */
5635                         skb->ip_summed = CHECKSUM_UNNECESSARY;
5636                 } else {
5637                         /*
5638                          * Packet with erroneous checksum, let the
5639                          * upper layers deal with it.
5640                          */
5641                         skb->ip_summed = CHECKSUM_NONE;
5642                 }
5643         } else {
5644                 skb->ip_summed = CHECKSUM_NONE;
5645         }
5646
5647         skb->protocol = eth_type_trans(skb, dev);
5648 #ifdef CONFIG_S2IO_NAPI
5649         if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
5650                 /* Queueing the vlan frame to the upper layer */
5651                 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
5652                         RXD_GET_VLAN_TAG(rxdp->Control_2));
5653         } else {
5654                 netif_receive_skb(skb);
5655         }
5656 #else
5657         if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
5658                 /* Queueing the vlan frame to the upper layer */
5659                 vlan_hwaccel_rx(skb, sp->vlgrp,
5660                         RXD_GET_VLAN_TAG(rxdp->Control_2));
5661         } else {
5662                 netif_rx(skb);
5663         }
5664 #endif
5665         dev->last_rx = jiffies;
5666         atomic_dec(&sp->rx_bufs_left[ring_no]);
5667         return SUCCESS;
5668 }
5669
5670 /**
5671  *  s2io_link - stops/starts the Tx queue.
5672  *  @sp : private member of the device structure, which is a pointer to the
5673  *  s2io_nic structure.
5674  *  @link : inidicates whether link is UP/DOWN.
5675  *  Description:
5676  *  This function stops/starts the Tx queue depending on whether the link
5677  *  status of the NIC is is down or up. This is called by the Alarm
5678  *  interrupt handler whenever a link change interrupt comes up.
5679  *  Return value:
5680  *  void.
5681  */
5682
5683 void s2io_link(nic_t * sp, int link)
5684 {
5685         struct net_device *dev = (struct net_device *) sp->dev;
5686
5687         if (link != sp->last_link_state) {
5688                 if (link == LINK_DOWN) {
5689                         DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
5690                         netif_carrier_off(dev);
5691                 } else {
5692                         DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
5693                         netif_carrier_on(dev);
5694                 }
5695         }
5696         sp->last_link_state = link;
5697 }
5698
5699 /**
5700  *  get_xena_rev_id - to identify revision ID of xena.
5701  *  @pdev : PCI Dev structure
5702  *  Description:
5703  *  Function to identify the Revision ID of xena.
5704  *  Return value:
5705  *  returns the revision ID of the device.
5706  */
5707
5708 int get_xena_rev_id(struct pci_dev *pdev)
5709 {
5710         u8 id = 0;
5711         int ret;
5712         ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
5713         return id;
5714 }
5715
5716 /**
5717  *  s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
5718  *  @sp : private member of the device structure, which is a pointer to the
5719  *  s2io_nic structure.
5720  *  Description:
5721  *  This function initializes a few of the PCI and PCI-X configuration registers
5722  *  with recommended values.
5723  *  Return value:
5724  *  void
5725  */
5726
5727 static void s2io_init_pci(nic_t * sp)
5728 {
5729         u16 pci_cmd = 0, pcix_cmd = 0;
5730
5731         /* Enable Data Parity Error Recovery in PCI-X command register. */
5732         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
5733                              &(pcix_cmd));
5734         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
5735                               (pcix_cmd | 1));
5736         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
5737                              &(pcix_cmd));
5738
5739         /* Set the PErr Response bit in PCI command register. */
5740         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
5741         pci_write_config_word(sp->pdev, PCI_COMMAND,
5742                               (pci_cmd | PCI_COMMAND_PARITY));
5743         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
5744
5745         /* Forcibly disabling relaxed ordering capability of the card. */
5746         pcix_cmd &= 0xfffd;
5747         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
5748                               pcix_cmd);
5749         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
5750                              &(pcix_cmd));
5751 }
5752
5753 MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
5754 MODULE_LICENSE("GPL");
5755 MODULE_VERSION(DRV_VERSION);
5756
5757 module_param(tx_fifo_num, int, 0);
5758 module_param(rx_ring_num, int, 0);
5759 module_param(rx_ring_mode, int, 0);
5760 module_param_array(tx_fifo_len, uint, NULL, 0);
5761 module_param_array(rx_ring_sz, uint, NULL, 0);
5762 module_param_array(rts_frm_len, uint, NULL, 0);
5763 module_param(use_continuous_tx_intrs, int, 1);
5764 module_param(rmac_pause_time, int, 0);
5765 module_param(mc_pause_threshold_q0q3, int, 0);
5766 module_param(mc_pause_threshold_q4q7, int, 0);
5767 module_param(shared_splits, int, 0);
5768 module_param(tmac_util_period, int, 0);
5769 module_param(rmac_util_period, int, 0);
5770 module_param(bimodal, bool, 0);
5771 module_param(l3l4hdr_size, int , 0);
5772 #ifndef CONFIG_S2IO_NAPI
5773 module_param(indicate_max_pkts, int, 0);
5774 #endif
5775 module_param(rxsync_frequency, int, 0);
5776 module_param(intr_type, int, 0);
5777
5778 /**
5779  *  s2io_init_nic - Initialization of the adapter .
5780  *  @pdev : structure containing the PCI related information of the device.
5781  *  @pre: List of PCI devices supported by the driver listed in s2io_tbl.
5782  *  Description:
5783  *  The function initializes an adapter identified by the pci_dec structure.
5784  *  All OS related initialization including memory and device structure and
5785  *  initlaization of the device private variable is done. Also the swapper
5786  *  control register is initialized to enable read and write into the I/O
5787  *  registers of the device.
5788  *  Return value:
5789  *  returns 0 on success and negative on failure.
5790  */
5791
5792 static int __devinit
5793 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
5794 {
5795         nic_t *sp;
5796         struct net_device *dev;
5797         int i, j, ret;
5798         int dma_flag = FALSE;
5799         u32 mac_up, mac_down;
5800         u64 val64 = 0, tmp64 = 0;
5801         XENA_dev_config_t __iomem *bar0 = NULL;
5802         u16 subid;
5803         mac_info_t *mac_control;
5804         struct config_param *config;
5805         int mode;
5806         u8 dev_intr_type = intr_type;
5807
5808 #ifdef CONFIG_S2IO_NAPI
5809         if (dev_intr_type != INTA) {
5810                 DBG_PRINT(ERR_DBG, "NAPI cannot be enabled when MSI/MSI-X \
5811 is enabled. Defaulting to INTA\n");
5812                 dev_intr_type = INTA;
5813         }
5814         else
5815                 DBG_PRINT(ERR_DBG, "NAPI support has been enabled\n");
5816 #endif
5817
5818         if ((ret = pci_enable_device(pdev))) {
5819                 DBG_PRINT(ERR_DBG,
5820                           "s2io_init_nic: pci_enable_device failed\n");
5821                 return ret;
5822         }
5823
5824         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
5825                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
5826                 dma_flag = TRUE;
5827                 if (pci_set_consistent_dma_mask
5828                     (pdev, DMA_64BIT_MASK)) {
5829                         DBG_PRINT(ERR_DBG,
5830                                   "Unable to obtain 64bit DMA for \
5831                                         consistent allocations\n");
5832                         pci_disable_device(pdev);
5833                         return -ENOMEM;
5834                 }
5835         } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
5836                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
5837         } else {
5838                 pci_disable_device(pdev);
5839                 return -ENOMEM;
5840         }
5841
5842         if ((dev_intr_type == MSI_X) &&
5843                         ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
5844                         (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
5845                 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. \
5846 Defaulting to INTA\n");
5847                 dev_intr_type = INTA;
5848         }
5849         if (dev_intr_type != MSI_X) {
5850                 if (pci_request_regions(pdev, s2io_driver_name)) {
5851                         DBG_PRINT(ERR_DBG, "Request Regions failed\n"),
5852                             pci_disable_device(pdev);
5853                         return -ENODEV;
5854                 }
5855         }
5856         else {
5857                 if (!(request_mem_region(pci_resource_start(pdev, 0),
5858                          pci_resource_len(pdev, 0), s2io_driver_name))) {
5859                         DBG_PRINT(ERR_DBG, "bar0 Request Regions failed\n");
5860                         pci_disable_device(pdev);
5861                         return -ENODEV;
5862                 }
5863                 if (!(request_mem_region(pci_resource_start(pdev, 2),
5864                          pci_resource_len(pdev, 2), s2io_driver_name))) {
5865                         DBG_PRINT(ERR_DBG, "bar1 Request Regions failed\n");
5866                         release_mem_region(pci_resource_start(pdev, 0),
5867                                    pci_resource_len(pdev, 0));
5868                         pci_disable_device(pdev);
5869                         return -ENODEV;
5870                 }
5871         }
5872
5873         dev = alloc_etherdev(sizeof(nic_t));
5874         if (dev == NULL) {
5875                 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
5876                 pci_disable_device(pdev);
5877                 pci_release_regions(pdev);
5878                 return -ENODEV;
5879         }
5880
5881         pci_set_master(pdev);
5882         pci_set_drvdata(pdev, dev);
5883         SET_MODULE_OWNER(dev);
5884         SET_NETDEV_DEV(dev, &pdev->dev);
5885
5886         /*  Private member variable initialized to s2io NIC structure */
5887         sp = dev->priv;
5888         memset(sp, 0, sizeof(nic_t));
5889         sp->dev = dev;
5890         sp->pdev = pdev;
5891         sp->high_dma_flag = dma_flag;
5892         sp->device_enabled_once = FALSE;
5893         if (rx_ring_mode == 1)
5894                 sp->rxd_mode = RXD_MODE_1;
5895         if (rx_ring_mode == 2)
5896                 sp->rxd_mode = RXD_MODE_3B;
5897         if (rx_ring_mode == 3)
5898                 sp->rxd_mode = RXD_MODE_3A;
5899
5900         sp->intr_type = dev_intr_type;
5901
5902         if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
5903                 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
5904                 sp->device_type = XFRAME_II_DEVICE;
5905         else
5906                 sp->device_type = XFRAME_I_DEVICE;
5907
5908
5909         /* Initialize some PCI/PCI-X fields of the NIC. */
5910         s2io_init_pci(sp);
5911
5912         /*
5913          * Setting the device configuration parameters.
5914          * Most of these parameters can be specified by the user during
5915          * module insertion as they are module loadable parameters. If
5916          * these parameters are not not specified during load time, they
5917          * are initialized with default values.
5918          */
5919         mac_control = &sp->mac_control;
5920         config = &sp->config;
5921
5922         /* Tx side parameters. */
5923         if (tx_fifo_len[0] == 0)
5924                 tx_fifo_len[0] = DEFAULT_FIFO_LEN; /* Default value. */
5925         config->tx_fifo_num = tx_fifo_num;
5926         for (i = 0; i < MAX_TX_FIFOS; i++) {
5927                 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
5928                 config->tx_cfg[i].fifo_priority = i;
5929         }
5930
5931         /* mapping the QoS priority to the configured fifos */
5932         for (i = 0; i < MAX_TX_FIFOS; i++)
5933                 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
5934
5935         config->tx_intr_type = TXD_INT_TYPE_UTILZ;
5936         for (i = 0; i < config->tx_fifo_num; i++) {
5937                 config->tx_cfg[i].f_no_snoop =
5938                     (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
5939                 if (config->tx_cfg[i].fifo_len < 65) {
5940                         config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
5941                         break;
5942                 }
5943         }
5944         config->max_txds = MAX_SKB_FRAGS + 1;
5945
5946         /* Rx side parameters. */
5947         if (rx_ring_sz[0] == 0)
5948                 rx_ring_sz[0] = SMALL_BLK_CNT; /* Default value. */
5949         config->rx_ring_num = rx_ring_num;
5950         for (i = 0; i < MAX_RX_RINGS; i++) {
5951                 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
5952                     (rxd_count[sp->rxd_mode] + 1);
5953                 config->rx_cfg[i].ring_priority = i;
5954         }
5955
5956         for (i = 0; i < rx_ring_num; i++) {
5957                 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
5958                 config->rx_cfg[i].f_no_snoop =
5959                     (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
5960         }
5961
5962         /*  Setting Mac Control parameters */
5963         mac_control->rmac_pause_time = rmac_pause_time;
5964         mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
5965         mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
5966
5967
5968         /* Initialize Ring buffer parameters. */
5969         for (i = 0; i < config->rx_ring_num; i++)
5970                 atomic_set(&sp->rx_bufs_left[i], 0);
5971
5972         /* Initialize the number of ISRs currently running */
5973         atomic_set(&sp->isr_cnt, 0);
5974
5975         /*  initialize the shared memory used by the NIC and the host */
5976         if (init_shared_mem(sp)) {
5977                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
5978                           __FUNCTION__);
5979                 ret = -ENOMEM;
5980                 goto mem_alloc_failed;
5981         }
5982
5983         sp->bar0 = ioremap(pci_resource_start(pdev, 0),
5984                                      pci_resource_len(pdev, 0));
5985         if (!sp->bar0) {
5986                 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem1\n",
5987                           dev->name);
5988                 ret = -ENOMEM;
5989                 goto bar0_remap_failed;
5990         }
5991
5992         sp->bar1 = ioremap(pci_resource_start(pdev, 2),
5993                                      pci_resource_len(pdev, 2));
5994         if (!sp->bar1) {
5995                 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem2\n",
5996                           dev->name);
5997                 ret = -ENOMEM;
5998                 goto bar1_remap_failed;
5999         }
6000
6001         dev->irq = pdev->irq;
6002         dev->base_addr = (unsigned long) sp->bar0;
6003
6004         /* Initializing the BAR1 address as the start of the FIFO pointer. */
6005         for (j = 0; j < MAX_TX_FIFOS; j++) {
6006                 mac_control->tx_FIFO_start[j] = (TxFIFO_element_t __iomem *)
6007                     (sp->bar1 + (j * 0x00020000));
6008         }
6009
6010         /*  Driver entry points */
6011         dev->open = &s2io_open;
6012         dev->stop = &s2io_close;
6013         dev->hard_start_xmit = &s2io_xmit;
6014         dev->get_stats = &s2io_get_stats;
6015         dev->set_multicast_list = &s2io_set_multicast;
6016         dev->do_ioctl = &s2io_ioctl;
6017         dev->change_mtu = &s2io_change_mtu;
6018         SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
6019         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6020         dev->vlan_rx_register = s2io_vlan_rx_register;
6021         dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
6022
6023         /*
6024          * will use eth_mac_addr() for  dev->set_mac_address
6025          * mac address will be set every time dev->open() is called
6026          */
6027 #if defined(CONFIG_S2IO_NAPI)
6028         dev->poll = s2io_poll;
6029         dev->weight = 32;
6030 #endif
6031
6032         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
6033         if (sp->high_dma_flag == TRUE)
6034                 dev->features |= NETIF_F_HIGHDMA;
6035 #ifdef NETIF_F_TSO
6036         dev->features |= NETIF_F_TSO;
6037 #endif
6038
6039         dev->tx_timeout = &s2io_tx_watchdog;
6040         dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
6041         INIT_WORK(&sp->rst_timer_task,
6042                   (void (*)(void *)) s2io_restart_nic, dev);
6043         INIT_WORK(&sp->set_link_task,
6044                   (void (*)(void *)) s2io_set_link, sp);
6045
6046         pci_save_state(sp->pdev);
6047
6048         /* Setting swapper control on the NIC, for proper reset operation */
6049         if (s2io_set_swapper(sp)) {
6050                 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
6051                           dev->name);
6052                 ret = -EAGAIN;
6053                 goto set_swap_failed;
6054         }
6055
6056         /* Verify if the Herc works on the slot its placed into */
6057         if (sp->device_type & XFRAME_II_DEVICE) {
6058                 mode = s2io_verify_pci_mode(sp);
6059                 if (mode < 0) {
6060                         DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
6061                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
6062                         ret = -EBADSLT;
6063                         goto set_swap_failed;
6064                 }
6065         }
6066
6067         /* Not needed for Herc */
6068         if (sp->device_type & XFRAME_I_DEVICE) {
6069                 /*
6070                  * Fix for all "FFs" MAC address problems observed on
6071                  * Alpha platforms
6072                  */
6073                 fix_mac_address(sp);
6074                 s2io_reset(sp);
6075         }
6076
6077         /*
6078          * MAC address initialization.
6079          * For now only one mac address will be read and used.
6080          */
6081         bar0 = sp->bar0;
6082         val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
6083             RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
6084         writeq(val64, &bar0->rmac_addr_cmd_mem);
6085         wait_for_cmd_complete(sp);
6086
6087         tmp64 = readq(&bar0->rmac_addr_data0_mem);
6088         mac_down = (u32) tmp64;
6089         mac_up = (u32) (tmp64 >> 32);
6090
6091         memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
6092
6093         sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
6094         sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
6095         sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
6096         sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
6097         sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
6098         sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
6099
6100         /*  Set the factory defined MAC address initially   */
6101         dev->addr_len = ETH_ALEN;
6102         memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
6103
6104         /*
6105          * Initialize the tasklet status and link state flags
6106          * and the card state parameter
6107          */
6108         atomic_set(&(sp->card_state), 0);
6109         sp->tasklet_status = 0;
6110         sp->link_state = 0;
6111
6112         /* Initialize spinlocks */
6113         spin_lock_init(&sp->tx_lock);
6114 #ifndef CONFIG_S2IO_NAPI
6115         spin_lock_init(&sp->put_lock);
6116 #endif
6117         spin_lock_init(&sp->rx_lock);
6118
6119         /*
6120          * SXE-002: Configure link and activity LED to init state
6121          * on driver load.
6122          */
6123         subid = sp->pdev->subsystem_device;
6124         if ((subid & 0xFF) >= 0x07) {
6125                 val64 = readq(&bar0->gpio_control);
6126                 val64 |= 0x0000800000000000ULL;
6127                 writeq(val64, &bar0->gpio_control);
6128                 val64 = 0x0411040400000000ULL;
6129                 writeq(val64, (void __iomem *) bar0 + 0x2700);
6130                 val64 = readq(&bar0->gpio_control);
6131         }
6132
6133         sp->rx_csum = 1;        /* Rx chksum verify enabled by default */
6134
6135         if (register_netdev(dev)) {
6136                 DBG_PRINT(ERR_DBG, "Device registration failed\n");
6137                 ret = -ENODEV;
6138                 goto register_failed;
6139         }
6140
6141         if (sp->device_type & XFRAME_II_DEVICE) {
6142                 DBG_PRINT(ERR_DBG, "%s: Neterion Xframe II 10GbE adapter ",
6143                           dev->name);
6144                 DBG_PRINT(ERR_DBG, "(rev %d), Version %s",
6145                                 get_xena_rev_id(sp->pdev),
6146                                 s2io_driver_version);
6147                 switch(sp->intr_type) {
6148                         case INTA:
6149                                 DBG_PRINT(ERR_DBG, ", Intr type INTA");
6150                                 break;
6151                         case MSI:
6152                                 DBG_PRINT(ERR_DBG, ", Intr type MSI");
6153                                 break;
6154                         case MSI_X:
6155                                 DBG_PRINT(ERR_DBG, ", Intr type MSI-X");
6156                                 break;
6157                 }
6158
6159                 DBG_PRINT(ERR_DBG, "\nCopyright(c) 2002-2005 Neterion Inc.\n");
6160                 DBG_PRINT(ERR_DBG, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
6161                           sp->def_mac_addr[0].mac_addr[0],
6162                           sp->def_mac_addr[0].mac_addr[1],
6163                           sp->def_mac_addr[0].mac_addr[2],
6164                           sp->def_mac_addr[0].mac_addr[3],
6165                           sp->def_mac_addr[0].mac_addr[4],
6166                           sp->def_mac_addr[0].mac_addr[5]);
6167                 mode = s2io_print_pci_mode(sp);
6168                 if (mode < 0) {
6169                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode ");
6170                         ret = -EBADSLT;
6171                         goto set_swap_failed;
6172                 }
6173         } else {
6174                 DBG_PRINT(ERR_DBG, "%s: Neterion Xframe I 10GbE adapter ",
6175                           dev->name);
6176                 DBG_PRINT(ERR_DBG, "(rev %d), Version %s",
6177                                         get_xena_rev_id(sp->pdev),
6178                                         s2io_driver_version);
6179                 switch(sp->intr_type) {
6180                         case INTA:
6181                                 DBG_PRINT(ERR_DBG, ", Intr type INTA");
6182                                 break;
6183                         case MSI:
6184                                 DBG_PRINT(ERR_DBG, ", Intr type MSI");
6185                                 break;
6186                         case MSI_X:
6187                                 DBG_PRINT(ERR_DBG, ", Intr type MSI-X");
6188                                 break;
6189                 }
6190                 DBG_PRINT(ERR_DBG, "\nCopyright(c) 2002-2005 Neterion Inc.\n");
6191                 DBG_PRINT(ERR_DBG, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
6192                           sp->def_mac_addr[0].mac_addr[0],
6193                           sp->def_mac_addr[0].mac_addr[1],
6194                           sp->def_mac_addr[0].mac_addr[2],
6195                           sp->def_mac_addr[0].mac_addr[3],
6196                           sp->def_mac_addr[0].mac_addr[4],
6197                           sp->def_mac_addr[0].mac_addr[5]);
6198         }
6199         if (sp->rxd_mode == RXD_MODE_3B)
6200                 DBG_PRINT(ERR_DBG, "%s: 2-Buffer mode support has been "
6201                           "enabled\n",dev->name);
6202         if (sp->rxd_mode == RXD_MODE_3A)
6203                 DBG_PRINT(ERR_DBG, "%s: 3-Buffer mode support has been "
6204                           "enabled\n",dev->name);
6205
6206         /* Initialize device name */
6207         strcpy(sp->name, dev->name);
6208         if (sp->device_type & XFRAME_II_DEVICE)
6209                 strcat(sp->name, ": Neterion Xframe II 10GbE adapter");
6210         else
6211                 strcat(sp->name, ": Neterion Xframe I 10GbE adapter");
6212
6213         /* Initialize bimodal Interrupts */
6214         sp->config.bimodal = bimodal;
6215         if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
6216                 sp->config.bimodal = 0;
6217                 DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
6218                         dev->name);
6219         }
6220
6221         /*
6222          * Make Link state as off at this point, when the Link change
6223          * interrupt comes the state will be automatically changed to
6224          * the right state.
6225          */
6226         netif_carrier_off(dev);
6227
6228         return 0;
6229
6230       register_failed:
6231       set_swap_failed:
6232         iounmap(sp->bar1);
6233       bar1_remap_failed:
6234         iounmap(sp->bar0);
6235       bar0_remap_failed:
6236       mem_alloc_failed:
6237         free_shared_mem(sp);
6238         pci_disable_device(pdev);
6239         if (dev_intr_type != MSI_X)
6240                 pci_release_regions(pdev);
6241         else {
6242                 release_mem_region(pci_resource_start(pdev, 0),
6243                         pci_resource_len(pdev, 0));
6244                 release_mem_region(pci_resource_start(pdev, 2),
6245                         pci_resource_len(pdev, 2));
6246         }
6247         pci_set_drvdata(pdev, NULL);
6248         free_netdev(dev);
6249
6250         return ret;
6251 }
6252
6253 /**
6254  * s2io_rem_nic - Free the PCI device
6255  * @pdev: structure containing the PCI related information of the device.
6256  * Description: This function is called by the Pci subsystem to release a
6257  * PCI device and free up all resource held up by the device. This could
6258  * be in response to a Hot plug event or when the driver is to be removed
6259  * from memory.
6260  */
6261
6262 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
6263 {
6264         struct net_device *dev =
6265             (struct net_device *) pci_get_drvdata(pdev);
6266         nic_t *sp;
6267
6268         if (dev == NULL) {
6269                 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
6270                 return;
6271         }
6272
6273         sp = dev->priv;
6274         unregister_netdev(dev);
6275
6276         free_shared_mem(sp);
6277         iounmap(sp->bar0);
6278         iounmap(sp->bar1);
6279         pci_disable_device(pdev);
6280         if (sp->intr_type != MSI_X)
6281                 pci_release_regions(pdev);
6282         else {
6283                 release_mem_region(pci_resource_start(pdev, 0),
6284                         pci_resource_len(pdev, 0));
6285                 release_mem_region(pci_resource_start(pdev, 2),
6286                         pci_resource_len(pdev, 2));
6287         }
6288         pci_set_drvdata(pdev, NULL);
6289         free_netdev(dev);
6290 }
6291
6292 /**
6293  * s2io_starter - Entry point for the driver
6294  * Description: This function is the entry point for the driver. It verifies
6295  * the module loadable parameters and initializes PCI configuration space.
6296  */
6297
6298 int __init s2io_starter(void)
6299 {
6300         return pci_module_init(&s2io_driver);
6301 }
6302
6303 /**
6304  * s2io_closer - Cleanup routine for the driver
6305  * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
6306  */
6307
6308 void s2io_closer(void)
6309 {
6310         pci_unregister_driver(&s2io_driver);
6311         DBG_PRINT(INIT_DBG, "cleanup done\n");
6312 }
6313
6314 module_init(s2io_starter);
6315 module_exit(s2io_closer);