Merge commit 'v2.6.29' into x86/setup-lzma
[linux-2.6] / drivers / dma / iop-adma.c
1 /*
2  * offload engine driver for the Intel Xscale series of i/o processors
3  * Copyright © 2006, Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17  *
18  */
19
20 /*
21  * This driver supports the asynchrounous DMA copy and RAID engines available
22  * on the Intel Xscale(R) family of I/O Processors (IOP 32x, 33x, 134x)
23  */
24
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/delay.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/spinlock.h>
30 #include <linux/interrupt.h>
31 #include <linux/platform_device.h>
32 #include <linux/memory.h>
33 #include <linux/ioport.h>
34
35 #include <mach/adma.h>
36
37 #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common)
38 #define to_iop_adma_device(dev) \
39         container_of(dev, struct iop_adma_device, common)
40 #define tx_to_iop_adma_slot(tx) \
41         container_of(tx, struct iop_adma_desc_slot, async_tx)
42
43 /**
44  * iop_adma_free_slots - flags descriptor slots for reuse
45  * @slot: Slot to free
46  * Caller must hold &iop_chan->lock while calling this function
47  */
48 static void iop_adma_free_slots(struct iop_adma_desc_slot *slot)
49 {
50         int stride = slot->slots_per_op;
51
52         while (stride--) {
53                 slot->slots_per_op = 0;
54                 slot = list_entry(slot->slot_node.next,
55                                 struct iop_adma_desc_slot,
56                                 slot_node);
57         }
58 }
59
60 static dma_cookie_t
61 iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc,
62         struct iop_adma_chan *iop_chan, dma_cookie_t cookie)
63 {
64         BUG_ON(desc->async_tx.cookie < 0);
65         if (desc->async_tx.cookie > 0) {
66                 cookie = desc->async_tx.cookie;
67                 desc->async_tx.cookie = 0;
68
69                 /* call the callback (must not sleep or submit new
70                  * operations to this channel)
71                  */
72                 if (desc->async_tx.callback)
73                         desc->async_tx.callback(
74                                 desc->async_tx.callback_param);
75
76                 /* unmap dma addresses
77                  * (unmap_single vs unmap_page?)
78                  */
79                 if (desc->group_head && desc->unmap_len) {
80                         struct iop_adma_desc_slot *unmap = desc->group_head;
81                         struct device *dev =
82                                 &iop_chan->device->pdev->dev;
83                         u32 len = unmap->unmap_len;
84                         enum dma_ctrl_flags flags = desc->async_tx.flags;
85                         u32 src_cnt;
86                         dma_addr_t addr;
87                         dma_addr_t dest;
88
89                         src_cnt = unmap->unmap_src_cnt;
90                         dest = iop_desc_get_dest_addr(unmap, iop_chan);
91                         if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
92                                 enum dma_data_direction dir;
93
94                                 if (src_cnt > 1) /* is xor? */
95                                         dir = DMA_BIDIRECTIONAL;
96                                 else
97                                         dir = DMA_FROM_DEVICE;
98
99                                 dma_unmap_page(dev, dest, len, dir);
100                         }
101
102                         if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
103                                 while (src_cnt--) {
104                                         addr = iop_desc_get_src_addr(unmap,
105                                                                      iop_chan,
106                                                                      src_cnt);
107                                         if (addr == dest)
108                                                 continue;
109                                         dma_unmap_page(dev, addr, len,
110                                                        DMA_TO_DEVICE);
111                                 }
112                         }
113                         desc->group_head = NULL;
114                 }
115         }
116
117         /* run dependent operations */
118         dma_run_dependencies(&desc->async_tx);
119
120         return cookie;
121 }
122
123 static int
124 iop_adma_clean_slot(struct iop_adma_desc_slot *desc,
125         struct iop_adma_chan *iop_chan)
126 {
127         /* the client is allowed to attach dependent operations
128          * until 'ack' is set
129          */
130         if (!async_tx_test_ack(&desc->async_tx))
131                 return 0;
132
133         /* leave the last descriptor in the chain
134          * so we can append to it
135          */
136         if (desc->chain_node.next == &iop_chan->chain)
137                 return 1;
138
139         dev_dbg(iop_chan->device->common.dev,
140                 "\tfree slot: %d slots_per_op: %d\n",
141                 desc->idx, desc->slots_per_op);
142
143         list_del(&desc->chain_node);
144         iop_adma_free_slots(desc);
145
146         return 0;
147 }
148
149 static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
150 {
151         struct iop_adma_desc_slot *iter, *_iter, *grp_start = NULL;
152         dma_cookie_t cookie = 0;
153         u32 current_desc = iop_chan_get_current_descriptor(iop_chan);
154         int busy = iop_chan_is_busy(iop_chan);
155         int seen_current = 0, slot_cnt = 0, slots_per_op = 0;
156
157         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
158         /* free completed slots from the chain starting with
159          * the oldest descriptor
160          */
161         list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
162                                         chain_node) {
163                 pr_debug("\tcookie: %d slot: %d busy: %d "
164                         "this_desc: %#x next_desc: %#x ack: %d\n",
165                         iter->async_tx.cookie, iter->idx, busy,
166                         iter->async_tx.phys, iop_desc_get_next_desc(iter),
167                         async_tx_test_ack(&iter->async_tx));
168                 prefetch(_iter);
169                 prefetch(&_iter->async_tx);
170
171                 /* do not advance past the current descriptor loaded into the
172                  * hardware channel, subsequent descriptors are either in
173                  * process or have not been submitted
174                  */
175                 if (seen_current)
176                         break;
177
178                 /* stop the search if we reach the current descriptor and the
179                  * channel is busy, or if it appears that the current descriptor
180                  * needs to be re-read (i.e. has been appended to)
181                  */
182                 if (iter->async_tx.phys == current_desc) {
183                         BUG_ON(seen_current++);
184                         if (busy || iop_desc_get_next_desc(iter))
185                                 break;
186                 }
187
188                 /* detect the start of a group transaction */
189                 if (!slot_cnt && !slots_per_op) {
190                         slot_cnt = iter->slot_cnt;
191                         slots_per_op = iter->slots_per_op;
192                         if (slot_cnt <= slots_per_op) {
193                                 slot_cnt = 0;
194                                 slots_per_op = 0;
195                         }
196                 }
197
198                 if (slot_cnt) {
199                         pr_debug("\tgroup++\n");
200                         if (!grp_start)
201                                 grp_start = iter;
202                         slot_cnt -= slots_per_op;
203                 }
204
205                 /* all the members of a group are complete */
206                 if (slots_per_op != 0 && slot_cnt == 0) {
207                         struct iop_adma_desc_slot *grp_iter, *_grp_iter;
208                         int end_of_chain = 0;
209                         pr_debug("\tgroup end\n");
210
211                         /* collect the total results */
212                         if (grp_start->xor_check_result) {
213                                 u32 zero_sum_result = 0;
214                                 slot_cnt = grp_start->slot_cnt;
215                                 grp_iter = grp_start;
216
217                                 list_for_each_entry_from(grp_iter,
218                                         &iop_chan->chain, chain_node) {
219                                         zero_sum_result |=
220                                             iop_desc_get_zero_result(grp_iter);
221                                             pr_debug("\titer%d result: %d\n",
222                                             grp_iter->idx, zero_sum_result);
223                                         slot_cnt -= slots_per_op;
224                                         if (slot_cnt == 0)
225                                                 break;
226                                 }
227                                 pr_debug("\tgrp_start->xor_check_result: %p\n",
228                                         grp_start->xor_check_result);
229                                 *grp_start->xor_check_result = zero_sum_result;
230                         }
231
232                         /* clean up the group */
233                         slot_cnt = grp_start->slot_cnt;
234                         grp_iter = grp_start;
235                         list_for_each_entry_safe_from(grp_iter, _grp_iter,
236                                 &iop_chan->chain, chain_node) {
237                                 cookie = iop_adma_run_tx_complete_actions(
238                                         grp_iter, iop_chan, cookie);
239
240                                 slot_cnt -= slots_per_op;
241                                 end_of_chain = iop_adma_clean_slot(grp_iter,
242                                         iop_chan);
243
244                                 if (slot_cnt == 0 || end_of_chain)
245                                         break;
246                         }
247
248                         /* the group should be complete at this point */
249                         BUG_ON(slot_cnt);
250
251                         slots_per_op = 0;
252                         grp_start = NULL;
253                         if (end_of_chain)
254                                 break;
255                         else
256                                 continue;
257                 } else if (slots_per_op) /* wait for group completion */
258                         continue;
259
260                 /* write back zero sum results (single descriptor case) */
261                 if (iter->xor_check_result && iter->async_tx.cookie)
262                         *iter->xor_check_result =
263                                 iop_desc_get_zero_result(iter);
264
265                 cookie = iop_adma_run_tx_complete_actions(
266                                         iter, iop_chan, cookie);
267
268                 if (iop_adma_clean_slot(iter, iop_chan))
269                         break;
270         }
271
272         if (cookie > 0) {
273                 iop_chan->completed_cookie = cookie;
274                 pr_debug("\tcompleted cookie %d\n", cookie);
275         }
276 }
277
278 static void
279 iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
280 {
281         spin_lock_bh(&iop_chan->lock);
282         __iop_adma_slot_cleanup(iop_chan);
283         spin_unlock_bh(&iop_chan->lock);
284 }
285
286 static void iop_adma_tasklet(unsigned long data)
287 {
288         struct iop_adma_chan *iop_chan = (struct iop_adma_chan *) data;
289
290         spin_lock(&iop_chan->lock);
291         __iop_adma_slot_cleanup(iop_chan);
292         spin_unlock(&iop_chan->lock);
293 }
294
295 static struct iop_adma_desc_slot *
296 iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots,
297                         int slots_per_op)
298 {
299         struct iop_adma_desc_slot *iter, *_iter, *alloc_start = NULL;
300         LIST_HEAD(chain);
301         int slots_found, retry = 0;
302
303         /* start search from the last allocated descrtiptor
304          * if a contiguous allocation can not be found start searching
305          * from the beginning of the list
306          */
307 retry:
308         slots_found = 0;
309         if (retry == 0)
310                 iter = iop_chan->last_used;
311         else
312                 iter = list_entry(&iop_chan->all_slots,
313                         struct iop_adma_desc_slot,
314                         slot_node);
315
316         list_for_each_entry_safe_continue(
317                 iter, _iter, &iop_chan->all_slots, slot_node) {
318                 prefetch(_iter);
319                 prefetch(&_iter->async_tx);
320                 if (iter->slots_per_op) {
321                         /* give up after finding the first busy slot
322                          * on the second pass through the list
323                          */
324                         if (retry)
325                                 break;
326
327                         slots_found = 0;
328                         continue;
329                 }
330
331                 /* start the allocation if the slot is correctly aligned */
332                 if (!slots_found++) {
333                         if (iop_desc_is_aligned(iter, slots_per_op))
334                                 alloc_start = iter;
335                         else {
336                                 slots_found = 0;
337                                 continue;
338                         }
339                 }
340
341                 if (slots_found == num_slots) {
342                         struct iop_adma_desc_slot *alloc_tail = NULL;
343                         struct iop_adma_desc_slot *last_used = NULL;
344                         iter = alloc_start;
345                         while (num_slots) {
346                                 int i;
347                                 dev_dbg(iop_chan->device->common.dev,
348                                         "allocated slot: %d "
349                                         "(desc %p phys: %#x) slots_per_op %d\n",
350                                         iter->idx, iter->hw_desc,
351                                         iter->async_tx.phys, slots_per_op);
352
353                                 /* pre-ack all but the last descriptor */
354                                 if (num_slots != slots_per_op)
355                                         async_tx_ack(&iter->async_tx);
356
357                                 list_add_tail(&iter->chain_node, &chain);
358                                 alloc_tail = iter;
359                                 iter->async_tx.cookie = 0;
360                                 iter->slot_cnt = num_slots;
361                                 iter->xor_check_result = NULL;
362                                 for (i = 0; i < slots_per_op; i++) {
363                                         iter->slots_per_op = slots_per_op - i;
364                                         last_used = iter;
365                                         iter = list_entry(iter->slot_node.next,
366                                                 struct iop_adma_desc_slot,
367                                                 slot_node);
368                                 }
369                                 num_slots -= slots_per_op;
370                         }
371                         alloc_tail->group_head = alloc_start;
372                         alloc_tail->async_tx.cookie = -EBUSY;
373                         list_splice(&chain, &alloc_tail->async_tx.tx_list);
374                         iop_chan->last_used = last_used;
375                         iop_desc_clear_next_desc(alloc_start);
376                         iop_desc_clear_next_desc(alloc_tail);
377                         return alloc_tail;
378                 }
379         }
380         if (!retry++)
381                 goto retry;
382
383         /* perform direct reclaim if the allocation fails */
384         __iop_adma_slot_cleanup(iop_chan);
385
386         return NULL;
387 }
388
389 static dma_cookie_t
390 iop_desc_assign_cookie(struct iop_adma_chan *iop_chan,
391         struct iop_adma_desc_slot *desc)
392 {
393         dma_cookie_t cookie = iop_chan->common.cookie;
394         cookie++;
395         if (cookie < 0)
396                 cookie = 1;
397         iop_chan->common.cookie = desc->async_tx.cookie = cookie;
398         return cookie;
399 }
400
401 static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan)
402 {
403         dev_dbg(iop_chan->device->common.dev, "pending: %d\n",
404                 iop_chan->pending);
405
406         if (iop_chan->pending >= IOP_ADMA_THRESHOLD) {
407                 iop_chan->pending = 0;
408                 iop_chan_append(iop_chan);
409         }
410 }
411
412 static dma_cookie_t
413 iop_adma_tx_submit(struct dma_async_tx_descriptor *tx)
414 {
415         struct iop_adma_desc_slot *sw_desc = tx_to_iop_adma_slot(tx);
416         struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan);
417         struct iop_adma_desc_slot *grp_start, *old_chain_tail;
418         int slot_cnt;
419         int slots_per_op;
420         dma_cookie_t cookie;
421         dma_addr_t next_dma;
422
423         grp_start = sw_desc->group_head;
424         slot_cnt = grp_start->slot_cnt;
425         slots_per_op = grp_start->slots_per_op;
426
427         spin_lock_bh(&iop_chan->lock);
428         cookie = iop_desc_assign_cookie(iop_chan, sw_desc);
429
430         old_chain_tail = list_entry(iop_chan->chain.prev,
431                 struct iop_adma_desc_slot, chain_node);
432         list_splice_init(&sw_desc->async_tx.tx_list,
433                          &old_chain_tail->chain_node);
434
435         /* fix up the hardware chain */
436         next_dma = grp_start->async_tx.phys;
437         iop_desc_set_next_desc(old_chain_tail, next_dma);
438         BUG_ON(iop_desc_get_next_desc(old_chain_tail) != next_dma); /* flush */
439
440         /* check for pre-chained descriptors */
441         iop_paranoia(iop_desc_get_next_desc(sw_desc));
442
443         /* increment the pending count by the number of slots
444          * memcpy operations have a 1:1 (slot:operation) relation
445          * other operations are heavier and will pop the threshold
446          * more often.
447          */
448         iop_chan->pending += slot_cnt;
449         iop_adma_check_threshold(iop_chan);
450         spin_unlock_bh(&iop_chan->lock);
451
452         dev_dbg(iop_chan->device->common.dev, "%s cookie: %d slot: %d\n",
453                 __func__, sw_desc->async_tx.cookie, sw_desc->idx);
454
455         return cookie;
456 }
457
458 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan);
459 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan);
460
461 /**
462  * iop_adma_alloc_chan_resources -  returns the number of allocated descriptors
463  * @chan - allocate descriptor resources for this channel
464  * @client - current client requesting the channel be ready for requests
465  *
466  * Note: We keep the slots for 1 operation on iop_chan->chain at all times.  To
467  * avoid deadlock, via async_xor, num_descs_in_pool must at a minimum be
468  * greater than 2x the number slots needed to satisfy a device->max_xor
469  * request.
470  * */
471 static int iop_adma_alloc_chan_resources(struct dma_chan *chan)
472 {
473         char *hw_desc;
474         int idx;
475         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
476         struct iop_adma_desc_slot *slot = NULL;
477         int init = iop_chan->slots_allocated ? 0 : 1;
478         struct iop_adma_platform_data *plat_data =
479                 iop_chan->device->pdev->dev.platform_data;
480         int num_descs_in_pool = plat_data->pool_size/IOP_ADMA_SLOT_SIZE;
481
482         /* Allocate descriptor slots */
483         do {
484                 idx = iop_chan->slots_allocated;
485                 if (idx == num_descs_in_pool)
486                         break;
487
488                 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
489                 if (!slot) {
490                         printk(KERN_INFO "IOP ADMA Channel only initialized"
491                                 " %d descriptor slots", idx);
492                         break;
493                 }
494                 hw_desc = (char *) iop_chan->device->dma_desc_pool_virt;
495                 slot->hw_desc = (void *) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
496
497                 dma_async_tx_descriptor_init(&slot->async_tx, chan);
498                 slot->async_tx.tx_submit = iop_adma_tx_submit;
499                 INIT_LIST_HEAD(&slot->chain_node);
500                 INIT_LIST_HEAD(&slot->slot_node);
501                 INIT_LIST_HEAD(&slot->async_tx.tx_list);
502                 hw_desc = (char *) iop_chan->device->dma_desc_pool;
503                 slot->async_tx.phys =
504                         (dma_addr_t) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
505                 slot->idx = idx;
506
507                 spin_lock_bh(&iop_chan->lock);
508                 iop_chan->slots_allocated++;
509                 list_add_tail(&slot->slot_node, &iop_chan->all_slots);
510                 spin_unlock_bh(&iop_chan->lock);
511         } while (iop_chan->slots_allocated < num_descs_in_pool);
512
513         if (idx && !iop_chan->last_used)
514                 iop_chan->last_used = list_entry(iop_chan->all_slots.next,
515                                         struct iop_adma_desc_slot,
516                                         slot_node);
517
518         dev_dbg(iop_chan->device->common.dev,
519                 "allocated %d descriptor slots last_used: %p\n",
520                 iop_chan->slots_allocated, iop_chan->last_used);
521
522         /* initialize the channel and the chain with a null operation */
523         if (init) {
524                 if (dma_has_cap(DMA_MEMCPY,
525                         iop_chan->device->common.cap_mask))
526                         iop_chan_start_null_memcpy(iop_chan);
527                 else if (dma_has_cap(DMA_XOR,
528                         iop_chan->device->common.cap_mask))
529                         iop_chan_start_null_xor(iop_chan);
530                 else
531                         BUG();
532         }
533
534         return (idx > 0) ? idx : -ENOMEM;
535 }
536
537 static struct dma_async_tx_descriptor *
538 iop_adma_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
539 {
540         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
541         struct iop_adma_desc_slot *sw_desc, *grp_start;
542         int slot_cnt, slots_per_op;
543
544         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
545
546         spin_lock_bh(&iop_chan->lock);
547         slot_cnt = iop_chan_interrupt_slot_count(&slots_per_op, iop_chan);
548         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
549         if (sw_desc) {
550                 grp_start = sw_desc->group_head;
551                 iop_desc_init_interrupt(grp_start, iop_chan);
552                 grp_start->unmap_len = 0;
553                 sw_desc->async_tx.flags = flags;
554         }
555         spin_unlock_bh(&iop_chan->lock);
556
557         return sw_desc ? &sw_desc->async_tx : NULL;
558 }
559
560 static struct dma_async_tx_descriptor *
561 iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest,
562                          dma_addr_t dma_src, size_t len, unsigned long flags)
563 {
564         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
565         struct iop_adma_desc_slot *sw_desc, *grp_start;
566         int slot_cnt, slots_per_op;
567
568         if (unlikely(!len))
569                 return NULL;
570         BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
571
572         dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
573                 __func__, len);
574
575         spin_lock_bh(&iop_chan->lock);
576         slot_cnt = iop_chan_memcpy_slot_count(len, &slots_per_op);
577         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
578         if (sw_desc) {
579                 grp_start = sw_desc->group_head;
580                 iop_desc_init_memcpy(grp_start, flags);
581                 iop_desc_set_byte_count(grp_start, iop_chan, len);
582                 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
583                 iop_desc_set_memcpy_src_addr(grp_start, dma_src);
584                 sw_desc->unmap_src_cnt = 1;
585                 sw_desc->unmap_len = len;
586                 sw_desc->async_tx.flags = flags;
587         }
588         spin_unlock_bh(&iop_chan->lock);
589
590         return sw_desc ? &sw_desc->async_tx : NULL;
591 }
592
593 static struct dma_async_tx_descriptor *
594 iop_adma_prep_dma_memset(struct dma_chan *chan, dma_addr_t dma_dest,
595                          int value, size_t len, unsigned long flags)
596 {
597         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
598         struct iop_adma_desc_slot *sw_desc, *grp_start;
599         int slot_cnt, slots_per_op;
600
601         if (unlikely(!len))
602                 return NULL;
603         BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
604
605         dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
606                 __func__, len);
607
608         spin_lock_bh(&iop_chan->lock);
609         slot_cnt = iop_chan_memset_slot_count(len, &slots_per_op);
610         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
611         if (sw_desc) {
612                 grp_start = sw_desc->group_head;
613                 iop_desc_init_memset(grp_start, flags);
614                 iop_desc_set_byte_count(grp_start, iop_chan, len);
615                 iop_desc_set_block_fill_val(grp_start, value);
616                 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
617                 sw_desc->unmap_src_cnt = 1;
618                 sw_desc->unmap_len = len;
619                 sw_desc->async_tx.flags = flags;
620         }
621         spin_unlock_bh(&iop_chan->lock);
622
623         return sw_desc ? &sw_desc->async_tx : NULL;
624 }
625
626 static struct dma_async_tx_descriptor *
627 iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest,
628                       dma_addr_t *dma_src, unsigned int src_cnt, size_t len,
629                       unsigned long flags)
630 {
631         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
632         struct iop_adma_desc_slot *sw_desc, *grp_start;
633         int slot_cnt, slots_per_op;
634
635         if (unlikely(!len))
636                 return NULL;
637         BUG_ON(unlikely(len > IOP_ADMA_XOR_MAX_BYTE_COUNT));
638
639         dev_dbg(iop_chan->device->common.dev,
640                 "%s src_cnt: %d len: %u flags: %lx\n",
641                 __func__, src_cnt, len, flags);
642
643         spin_lock_bh(&iop_chan->lock);
644         slot_cnt = iop_chan_xor_slot_count(len, src_cnt, &slots_per_op);
645         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
646         if (sw_desc) {
647                 grp_start = sw_desc->group_head;
648                 iop_desc_init_xor(grp_start, src_cnt, flags);
649                 iop_desc_set_byte_count(grp_start, iop_chan, len);
650                 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
651                 sw_desc->unmap_src_cnt = src_cnt;
652                 sw_desc->unmap_len = len;
653                 sw_desc->async_tx.flags = flags;
654                 while (src_cnt--)
655                         iop_desc_set_xor_src_addr(grp_start, src_cnt,
656                                                   dma_src[src_cnt]);
657         }
658         spin_unlock_bh(&iop_chan->lock);
659
660         return sw_desc ? &sw_desc->async_tx : NULL;
661 }
662
663 static struct dma_async_tx_descriptor *
664 iop_adma_prep_dma_zero_sum(struct dma_chan *chan, dma_addr_t *dma_src,
665                            unsigned int src_cnt, size_t len, u32 *result,
666                            unsigned long flags)
667 {
668         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
669         struct iop_adma_desc_slot *sw_desc, *grp_start;
670         int slot_cnt, slots_per_op;
671
672         if (unlikely(!len))
673                 return NULL;
674
675         dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n",
676                 __func__, src_cnt, len);
677
678         spin_lock_bh(&iop_chan->lock);
679         slot_cnt = iop_chan_zero_sum_slot_count(len, src_cnt, &slots_per_op);
680         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
681         if (sw_desc) {
682                 grp_start = sw_desc->group_head;
683                 iop_desc_init_zero_sum(grp_start, src_cnt, flags);
684                 iop_desc_set_zero_sum_byte_count(grp_start, len);
685                 grp_start->xor_check_result = result;
686                 pr_debug("\t%s: grp_start->xor_check_result: %p\n",
687                         __func__, grp_start->xor_check_result);
688                 sw_desc->unmap_src_cnt = src_cnt;
689                 sw_desc->unmap_len = len;
690                 sw_desc->async_tx.flags = flags;
691                 while (src_cnt--)
692                         iop_desc_set_zero_sum_src_addr(grp_start, src_cnt,
693                                                        dma_src[src_cnt]);
694         }
695         spin_unlock_bh(&iop_chan->lock);
696
697         return sw_desc ? &sw_desc->async_tx : NULL;
698 }
699
700 static void iop_adma_free_chan_resources(struct dma_chan *chan)
701 {
702         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
703         struct iop_adma_desc_slot *iter, *_iter;
704         int in_use_descs = 0;
705
706         iop_adma_slot_cleanup(iop_chan);
707
708         spin_lock_bh(&iop_chan->lock);
709         list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
710                                         chain_node) {
711                 in_use_descs++;
712                 list_del(&iter->chain_node);
713         }
714         list_for_each_entry_safe_reverse(
715                 iter, _iter, &iop_chan->all_slots, slot_node) {
716                 list_del(&iter->slot_node);
717                 kfree(iter);
718                 iop_chan->slots_allocated--;
719         }
720         iop_chan->last_used = NULL;
721
722         dev_dbg(iop_chan->device->common.dev, "%s slots_allocated %d\n",
723                 __func__, iop_chan->slots_allocated);
724         spin_unlock_bh(&iop_chan->lock);
725
726         /* one is ok since we left it on there on purpose */
727         if (in_use_descs > 1)
728                 printk(KERN_ERR "IOP: Freeing %d in use descriptors!\n",
729                         in_use_descs - 1);
730 }
731
732 /**
733  * iop_adma_is_complete - poll the status of an ADMA transaction
734  * @chan: ADMA channel handle
735  * @cookie: ADMA transaction identifier
736  */
737 static enum dma_status iop_adma_is_complete(struct dma_chan *chan,
738                                         dma_cookie_t cookie,
739                                         dma_cookie_t *done,
740                                         dma_cookie_t *used)
741 {
742         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
743         dma_cookie_t last_used;
744         dma_cookie_t last_complete;
745         enum dma_status ret;
746
747         last_used = chan->cookie;
748         last_complete = iop_chan->completed_cookie;
749
750         if (done)
751                 *done = last_complete;
752         if (used)
753                 *used = last_used;
754
755         ret = dma_async_is_complete(cookie, last_complete, last_used);
756         if (ret == DMA_SUCCESS)
757                 return ret;
758
759         iop_adma_slot_cleanup(iop_chan);
760
761         last_used = chan->cookie;
762         last_complete = iop_chan->completed_cookie;
763
764         if (done)
765                 *done = last_complete;
766         if (used)
767                 *used = last_used;
768
769         return dma_async_is_complete(cookie, last_complete, last_used);
770 }
771
772 static irqreturn_t iop_adma_eot_handler(int irq, void *data)
773 {
774         struct iop_adma_chan *chan = data;
775
776         dev_dbg(chan->device->common.dev, "%s\n", __func__);
777
778         tasklet_schedule(&chan->irq_tasklet);
779
780         iop_adma_device_clear_eot_status(chan);
781
782         return IRQ_HANDLED;
783 }
784
785 static irqreturn_t iop_adma_eoc_handler(int irq, void *data)
786 {
787         struct iop_adma_chan *chan = data;
788
789         dev_dbg(chan->device->common.dev, "%s\n", __func__);
790
791         tasklet_schedule(&chan->irq_tasklet);
792
793         iop_adma_device_clear_eoc_status(chan);
794
795         return IRQ_HANDLED;
796 }
797
798 static irqreturn_t iop_adma_err_handler(int irq, void *data)
799 {
800         struct iop_adma_chan *chan = data;
801         unsigned long status = iop_chan_get_status(chan);
802
803         dev_printk(KERN_ERR, chan->device->common.dev,
804                 "error ( %s%s%s%s%s%s%s)\n",
805                 iop_is_err_int_parity(status, chan) ? "int_parity " : "",
806                 iop_is_err_mcu_abort(status, chan) ? "mcu_abort " : "",
807                 iop_is_err_int_tabort(status, chan) ? "int_tabort " : "",
808                 iop_is_err_int_mabort(status, chan) ? "int_mabort " : "",
809                 iop_is_err_pci_tabort(status, chan) ? "pci_tabort " : "",
810                 iop_is_err_pci_mabort(status, chan) ? "pci_mabort " : "",
811                 iop_is_err_split_tx(status, chan) ? "split_tx " : "");
812
813         iop_adma_device_clear_err_status(chan);
814
815         BUG();
816
817         return IRQ_HANDLED;
818 }
819
820 static void iop_adma_issue_pending(struct dma_chan *chan)
821 {
822         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
823
824         if (iop_chan->pending) {
825                 iop_chan->pending = 0;
826                 iop_chan_append(iop_chan);
827         }
828 }
829
830 /*
831  * Perform a transaction to verify the HW works.
832  */
833 #define IOP_ADMA_TEST_SIZE 2000
834
835 static int __devinit iop_adma_memcpy_self_test(struct iop_adma_device *device)
836 {
837         int i;
838         void *src, *dest;
839         dma_addr_t src_dma, dest_dma;
840         struct dma_chan *dma_chan;
841         dma_cookie_t cookie;
842         struct dma_async_tx_descriptor *tx;
843         int err = 0;
844         struct iop_adma_chan *iop_chan;
845
846         dev_dbg(device->common.dev, "%s\n", __func__);
847
848         src = kmalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
849         if (!src)
850                 return -ENOMEM;
851         dest = kzalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
852         if (!dest) {
853                 kfree(src);
854                 return -ENOMEM;
855         }
856
857         /* Fill in src buffer */
858         for (i = 0; i < IOP_ADMA_TEST_SIZE; i++)
859                 ((u8 *) src)[i] = (u8)i;
860
861         /* Start copy, using first DMA channel */
862         dma_chan = container_of(device->common.channels.next,
863                                 struct dma_chan,
864                                 device_node);
865         if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
866                 err = -ENODEV;
867                 goto out;
868         }
869
870         dest_dma = dma_map_single(dma_chan->device->dev, dest,
871                                 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
872         src_dma = dma_map_single(dma_chan->device->dev, src,
873                                 IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE);
874         tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
875                                       IOP_ADMA_TEST_SIZE,
876                                       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
877
878         cookie = iop_adma_tx_submit(tx);
879         iop_adma_issue_pending(dma_chan);
880         msleep(1);
881
882         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
883                         DMA_SUCCESS) {
884                 dev_printk(KERN_ERR, dma_chan->device->dev,
885                         "Self-test copy timed out, disabling\n");
886                 err = -ENODEV;
887                 goto free_resources;
888         }
889
890         iop_chan = to_iop_adma_chan(dma_chan);
891         dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
892                 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
893         if (memcmp(src, dest, IOP_ADMA_TEST_SIZE)) {
894                 dev_printk(KERN_ERR, dma_chan->device->dev,
895                         "Self-test copy failed compare, disabling\n");
896                 err = -ENODEV;
897                 goto free_resources;
898         }
899
900 free_resources:
901         iop_adma_free_chan_resources(dma_chan);
902 out:
903         kfree(src);
904         kfree(dest);
905         return err;
906 }
907
908 #define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */
909 static int __devinit
910 iop_adma_xor_zero_sum_self_test(struct iop_adma_device *device)
911 {
912         int i, src_idx;
913         struct page *dest;
914         struct page *xor_srcs[IOP_ADMA_NUM_SRC_TEST];
915         struct page *zero_sum_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
916         dma_addr_t dma_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
917         dma_addr_t dma_addr, dest_dma;
918         struct dma_async_tx_descriptor *tx;
919         struct dma_chan *dma_chan;
920         dma_cookie_t cookie;
921         u8 cmp_byte = 0;
922         u32 cmp_word;
923         u32 zero_sum_result;
924         int err = 0;
925         struct iop_adma_chan *iop_chan;
926
927         dev_dbg(device->common.dev, "%s\n", __func__);
928
929         for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
930                 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
931                 if (!xor_srcs[src_idx]) {
932                         while (src_idx--)
933                                 __free_page(xor_srcs[src_idx]);
934                         return -ENOMEM;
935                 }
936         }
937
938         dest = alloc_page(GFP_KERNEL);
939         if (!dest) {
940                 while (src_idx--)
941                         __free_page(xor_srcs[src_idx]);
942                 return -ENOMEM;
943         }
944
945         /* Fill in src buffers */
946         for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
947                 u8 *ptr = page_address(xor_srcs[src_idx]);
948                 for (i = 0; i < PAGE_SIZE; i++)
949                         ptr[i] = (1 << src_idx);
950         }
951
952         for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++)
953                 cmp_byte ^= (u8) (1 << src_idx);
954
955         cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
956                         (cmp_byte << 8) | cmp_byte;
957
958         memset(page_address(dest), 0, PAGE_SIZE);
959
960         dma_chan = container_of(device->common.channels.next,
961                                 struct dma_chan,
962                                 device_node);
963         if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
964                 err = -ENODEV;
965                 goto out;
966         }
967
968         /* test xor */
969         dest_dma = dma_map_page(dma_chan->device->dev, dest, 0,
970                                 PAGE_SIZE, DMA_FROM_DEVICE);
971         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
972                 dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
973                                            0, PAGE_SIZE, DMA_TO_DEVICE);
974         tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
975                                    IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE,
976                                    DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
977
978         cookie = iop_adma_tx_submit(tx);
979         iop_adma_issue_pending(dma_chan);
980         msleep(8);
981
982         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
983                 DMA_SUCCESS) {
984                 dev_printk(KERN_ERR, dma_chan->device->dev,
985                         "Self-test xor timed out, disabling\n");
986                 err = -ENODEV;
987                 goto free_resources;
988         }
989
990         iop_chan = to_iop_adma_chan(dma_chan);
991         dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
992                 PAGE_SIZE, DMA_FROM_DEVICE);
993         for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
994                 u32 *ptr = page_address(dest);
995                 if (ptr[i] != cmp_word) {
996                         dev_printk(KERN_ERR, dma_chan->device->dev,
997                                 "Self-test xor failed compare, disabling\n");
998                         err = -ENODEV;
999                         goto free_resources;
1000                 }
1001         }
1002         dma_sync_single_for_device(&iop_chan->device->pdev->dev, dest_dma,
1003                 PAGE_SIZE, DMA_TO_DEVICE);
1004
1005         /* skip zero sum if the capability is not present */
1006         if (!dma_has_cap(DMA_ZERO_SUM, dma_chan->device->cap_mask))
1007                 goto free_resources;
1008
1009         /* zero sum the sources with the destintation page */
1010         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
1011                 zero_sum_srcs[i] = xor_srcs[i];
1012         zero_sum_srcs[i] = dest;
1013
1014         zero_sum_result = 1;
1015
1016         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1017                 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1018                                            zero_sum_srcs[i], 0, PAGE_SIZE,
1019                                            DMA_TO_DEVICE);
1020         tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs,
1021                                         IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1022                                         &zero_sum_result,
1023                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1024
1025         cookie = iop_adma_tx_submit(tx);
1026         iop_adma_issue_pending(dma_chan);
1027         msleep(8);
1028
1029         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1030                 dev_printk(KERN_ERR, dma_chan->device->dev,
1031                         "Self-test zero sum timed out, disabling\n");
1032                 err = -ENODEV;
1033                 goto free_resources;
1034         }
1035
1036         if (zero_sum_result != 0) {
1037                 dev_printk(KERN_ERR, dma_chan->device->dev,
1038                         "Self-test zero sum failed compare, disabling\n");
1039                 err = -ENODEV;
1040                 goto free_resources;
1041         }
1042
1043         /* test memset */
1044         dma_addr = dma_map_page(dma_chan->device->dev, dest, 0,
1045                         PAGE_SIZE, DMA_FROM_DEVICE);
1046         tx = iop_adma_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE,
1047                                       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1048
1049         cookie = iop_adma_tx_submit(tx);
1050         iop_adma_issue_pending(dma_chan);
1051         msleep(8);
1052
1053         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1054                 dev_printk(KERN_ERR, dma_chan->device->dev,
1055                         "Self-test memset timed out, disabling\n");
1056                 err = -ENODEV;
1057                 goto free_resources;
1058         }
1059
1060         for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) {
1061                 u32 *ptr = page_address(dest);
1062                 if (ptr[i]) {
1063                         dev_printk(KERN_ERR, dma_chan->device->dev,
1064                                 "Self-test memset failed compare, disabling\n");
1065                         err = -ENODEV;
1066                         goto free_resources;
1067                 }
1068         }
1069
1070         /* test for non-zero parity sum */
1071         zero_sum_result = 0;
1072         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1073                 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1074                                            zero_sum_srcs[i], 0, PAGE_SIZE,
1075                                            DMA_TO_DEVICE);
1076         tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs,
1077                                         IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1078                                         &zero_sum_result,
1079                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1080
1081         cookie = iop_adma_tx_submit(tx);
1082         iop_adma_issue_pending(dma_chan);
1083         msleep(8);
1084
1085         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1086                 dev_printk(KERN_ERR, dma_chan->device->dev,
1087                         "Self-test non-zero sum timed out, disabling\n");
1088                 err = -ENODEV;
1089                 goto free_resources;
1090         }
1091
1092         if (zero_sum_result != 1) {
1093                 dev_printk(KERN_ERR, dma_chan->device->dev,
1094                         "Self-test non-zero sum failed compare, disabling\n");
1095                 err = -ENODEV;
1096                 goto free_resources;
1097         }
1098
1099 free_resources:
1100         iop_adma_free_chan_resources(dma_chan);
1101 out:
1102         src_idx = IOP_ADMA_NUM_SRC_TEST;
1103         while (src_idx--)
1104                 __free_page(xor_srcs[src_idx]);
1105         __free_page(dest);
1106         return err;
1107 }
1108
1109 static int __devexit iop_adma_remove(struct platform_device *dev)
1110 {
1111         struct iop_adma_device *device = platform_get_drvdata(dev);
1112         struct dma_chan *chan, *_chan;
1113         struct iop_adma_chan *iop_chan;
1114         struct iop_adma_platform_data *plat_data = dev->dev.platform_data;
1115
1116         dma_async_device_unregister(&device->common);
1117
1118         dma_free_coherent(&dev->dev, plat_data->pool_size,
1119                         device->dma_desc_pool_virt, device->dma_desc_pool);
1120
1121         list_for_each_entry_safe(chan, _chan, &device->common.channels,
1122                                 device_node) {
1123                 iop_chan = to_iop_adma_chan(chan);
1124                 list_del(&chan->device_node);
1125                 kfree(iop_chan);
1126         }
1127         kfree(device);
1128
1129         return 0;
1130 }
1131
1132 static int __devinit iop_adma_probe(struct platform_device *pdev)
1133 {
1134         struct resource *res;
1135         int ret = 0, i;
1136         struct iop_adma_device *adev;
1137         struct iop_adma_chan *iop_chan;
1138         struct dma_device *dma_dev;
1139         struct iop_adma_platform_data *plat_data = pdev->dev.platform_data;
1140
1141         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1142         if (!res)
1143                 return -ENODEV;
1144
1145         if (!devm_request_mem_region(&pdev->dev, res->start,
1146                                 res->end - res->start, pdev->name))
1147                 return -EBUSY;
1148
1149         adev = kzalloc(sizeof(*adev), GFP_KERNEL);
1150         if (!adev)
1151                 return -ENOMEM;
1152         dma_dev = &adev->common;
1153
1154         /* allocate coherent memory for hardware descriptors
1155          * note: writecombine gives slightly better performance, but
1156          * requires that we explicitly flush the writes
1157          */
1158         if ((adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev,
1159                                         plat_data->pool_size,
1160                                         &adev->dma_desc_pool,
1161                                         GFP_KERNEL)) == NULL) {
1162                 ret = -ENOMEM;
1163                 goto err_free_adev;
1164         }
1165
1166         dev_dbg(&pdev->dev, "%s: allocted descriptor pool virt %p phys %p\n",
1167                 __func__, adev->dma_desc_pool_virt,
1168                 (void *) adev->dma_desc_pool);
1169
1170         adev->id = plat_data->hw_id;
1171
1172         /* discover transaction capabilites from the platform data */
1173         dma_dev->cap_mask = plat_data->cap_mask;
1174
1175         adev->pdev = pdev;
1176         platform_set_drvdata(pdev, adev);
1177
1178         INIT_LIST_HEAD(&dma_dev->channels);
1179
1180         /* set base routines */
1181         dma_dev->device_alloc_chan_resources = iop_adma_alloc_chan_resources;
1182         dma_dev->device_free_chan_resources = iop_adma_free_chan_resources;
1183         dma_dev->device_is_tx_complete = iop_adma_is_complete;
1184         dma_dev->device_issue_pending = iop_adma_issue_pending;
1185         dma_dev->dev = &pdev->dev;
1186
1187         /* set prep routines based on capability */
1188         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1189                 dma_dev->device_prep_dma_memcpy = iop_adma_prep_dma_memcpy;
1190         if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask))
1191                 dma_dev->device_prep_dma_memset = iop_adma_prep_dma_memset;
1192         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1193                 dma_dev->max_xor = iop_adma_get_max_xor();
1194                 dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor;
1195         }
1196         if (dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask))
1197                 dma_dev->device_prep_dma_zero_sum =
1198                         iop_adma_prep_dma_zero_sum;
1199         if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
1200                 dma_dev->device_prep_dma_interrupt =
1201                         iop_adma_prep_dma_interrupt;
1202
1203         iop_chan = kzalloc(sizeof(*iop_chan), GFP_KERNEL);
1204         if (!iop_chan) {
1205                 ret = -ENOMEM;
1206                 goto err_free_dma;
1207         }
1208         iop_chan->device = adev;
1209
1210         iop_chan->mmr_base = devm_ioremap(&pdev->dev, res->start,
1211                                         res->end - res->start);
1212         if (!iop_chan->mmr_base) {
1213                 ret = -ENOMEM;
1214                 goto err_free_iop_chan;
1215         }
1216         tasklet_init(&iop_chan->irq_tasklet, iop_adma_tasklet, (unsigned long)
1217                 iop_chan);
1218
1219         /* clear errors before enabling interrupts */
1220         iop_adma_device_clear_err_status(iop_chan);
1221
1222         for (i = 0; i < 3; i++) {
1223                 irq_handler_t handler[] = { iop_adma_eot_handler,
1224                                         iop_adma_eoc_handler,
1225                                         iop_adma_err_handler };
1226                 int irq = platform_get_irq(pdev, i);
1227                 if (irq < 0) {
1228                         ret = -ENXIO;
1229                         goto err_free_iop_chan;
1230                 } else {
1231                         ret = devm_request_irq(&pdev->dev, irq,
1232                                         handler[i], 0, pdev->name, iop_chan);
1233                         if (ret)
1234                                 goto err_free_iop_chan;
1235                 }
1236         }
1237
1238         spin_lock_init(&iop_chan->lock);
1239         INIT_LIST_HEAD(&iop_chan->chain);
1240         INIT_LIST_HEAD(&iop_chan->all_slots);
1241         iop_chan->common.device = dma_dev;
1242         list_add_tail(&iop_chan->common.device_node, &dma_dev->channels);
1243
1244         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1245                 ret = iop_adma_memcpy_self_test(adev);
1246                 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1247                 if (ret)
1248                         goto err_free_iop_chan;
1249         }
1250
1251         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask) ||
1252                 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
1253                 ret = iop_adma_xor_zero_sum_self_test(adev);
1254                 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1255                 if (ret)
1256                         goto err_free_iop_chan;
1257         }
1258
1259         dev_printk(KERN_INFO, &pdev->dev, "Intel(R) IOP: "
1260           "( %s%s%s%s%s%s%s%s%s%s)\n",
1261           dma_has_cap(DMA_PQ_XOR, dma_dev->cap_mask) ? "pq_xor " : "",
1262           dma_has_cap(DMA_PQ_UPDATE, dma_dev->cap_mask) ? "pq_update " : "",
1263           dma_has_cap(DMA_PQ_ZERO_SUM, dma_dev->cap_mask) ? "pq_zero_sum " : "",
1264           dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1265           dma_has_cap(DMA_DUAL_XOR, dma_dev->cap_mask) ? "dual_xor " : "",
1266           dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask) ? "xor_zero_sum " : "",
1267           dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)  ? "fill " : "",
1268           dma_has_cap(DMA_MEMCPY_CRC32C, dma_dev->cap_mask) ? "cpy+crc " : "",
1269           dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1270           dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1271
1272         dma_async_device_register(dma_dev);
1273         goto out;
1274
1275  err_free_iop_chan:
1276         kfree(iop_chan);
1277  err_free_dma:
1278         dma_free_coherent(&adev->pdev->dev, plat_data->pool_size,
1279                         adev->dma_desc_pool_virt, adev->dma_desc_pool);
1280  err_free_adev:
1281         kfree(adev);
1282  out:
1283         return ret;
1284 }
1285
1286 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan)
1287 {
1288         struct iop_adma_desc_slot *sw_desc, *grp_start;
1289         dma_cookie_t cookie;
1290         int slot_cnt, slots_per_op;
1291
1292         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1293
1294         spin_lock_bh(&iop_chan->lock);
1295         slot_cnt = iop_chan_memcpy_slot_count(0, &slots_per_op);
1296         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1297         if (sw_desc) {
1298                 grp_start = sw_desc->group_head;
1299
1300                 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1301                 async_tx_ack(&sw_desc->async_tx);
1302                 iop_desc_init_memcpy(grp_start, 0);
1303                 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1304                 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1305                 iop_desc_set_memcpy_src_addr(grp_start, 0);
1306
1307                 cookie = iop_chan->common.cookie;
1308                 cookie++;
1309                 if (cookie <= 1)
1310                         cookie = 2;
1311
1312                 /* initialize the completed cookie to be less than
1313                  * the most recently used cookie
1314                  */
1315                 iop_chan->completed_cookie = cookie - 1;
1316                 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1317
1318                 /* channel should not be busy */
1319                 BUG_ON(iop_chan_is_busy(iop_chan));
1320
1321                 /* clear any prior error-status bits */
1322                 iop_adma_device_clear_err_status(iop_chan);
1323
1324                 /* disable operation */
1325                 iop_chan_disable(iop_chan);
1326
1327                 /* set the descriptor address */
1328                 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1329
1330                 /* 1/ don't add pre-chained descriptors
1331                  * 2/ dummy read to flush next_desc write
1332                  */
1333                 BUG_ON(iop_desc_get_next_desc(sw_desc));
1334
1335                 /* run the descriptor */
1336                 iop_chan_enable(iop_chan);
1337         } else
1338                 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1339                          "failed to allocate null descriptor\n");
1340         spin_unlock_bh(&iop_chan->lock);
1341 }
1342
1343 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan)
1344 {
1345         struct iop_adma_desc_slot *sw_desc, *grp_start;
1346         dma_cookie_t cookie;
1347         int slot_cnt, slots_per_op;
1348
1349         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1350
1351         spin_lock_bh(&iop_chan->lock);
1352         slot_cnt = iop_chan_xor_slot_count(0, 2, &slots_per_op);
1353         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1354         if (sw_desc) {
1355                 grp_start = sw_desc->group_head;
1356                 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1357                 async_tx_ack(&sw_desc->async_tx);
1358                 iop_desc_init_null_xor(grp_start, 2, 0);
1359                 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1360                 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1361                 iop_desc_set_xor_src_addr(grp_start, 0, 0);
1362                 iop_desc_set_xor_src_addr(grp_start, 1, 0);
1363
1364                 cookie = iop_chan->common.cookie;
1365                 cookie++;
1366                 if (cookie <= 1)
1367                         cookie = 2;
1368
1369                 /* initialize the completed cookie to be less than
1370                  * the most recently used cookie
1371                  */
1372                 iop_chan->completed_cookie = cookie - 1;
1373                 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1374
1375                 /* channel should not be busy */
1376                 BUG_ON(iop_chan_is_busy(iop_chan));
1377
1378                 /* clear any prior error-status bits */
1379                 iop_adma_device_clear_err_status(iop_chan);
1380
1381                 /* disable operation */
1382                 iop_chan_disable(iop_chan);
1383
1384                 /* set the descriptor address */
1385                 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1386
1387                 /* 1/ don't add pre-chained descriptors
1388                  * 2/ dummy read to flush next_desc write
1389                  */
1390                 BUG_ON(iop_desc_get_next_desc(sw_desc));
1391
1392                 /* run the descriptor */
1393                 iop_chan_enable(iop_chan);
1394         } else
1395                 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1396                         "failed to allocate null descriptor\n");
1397         spin_unlock_bh(&iop_chan->lock);
1398 }
1399
1400 MODULE_ALIAS("platform:iop-adma");
1401
1402 static struct platform_driver iop_adma_driver = {
1403         .probe          = iop_adma_probe,
1404         .remove         = __devexit_p(iop_adma_remove),
1405         .driver         = {
1406                 .owner  = THIS_MODULE,
1407                 .name   = "iop-adma",
1408         },
1409 };
1410
1411 static int __init iop_adma_init (void)
1412 {
1413         return platform_driver_register(&iop_adma_driver);
1414 }
1415
1416 static void __exit iop_adma_exit (void)
1417 {
1418         platform_driver_unregister(&iop_adma_driver);
1419         return;
1420 }
1421 module_exit(iop_adma_exit);
1422 module_init(iop_adma_init);
1423
1424 MODULE_AUTHOR("Intel Corporation");
1425 MODULE_DESCRIPTION("IOP ADMA Engine Driver");
1426 MODULE_LICENSE("GPL");