git.oblomov.eu Git - linux-2.6/blob - drivers/media/video/cx18/cx18-mailbox.c

   1 /*
   2  *  cx18 mailbox functions
   3  *
   4  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
   5  *  Copyright (C) 2008  Andy Walls <awalls@radix.net>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  20  *  02111-1307  USA
  21  */
  22
  23 #include <stdarg.h>
  24
  25 #include "cx18-driver.h"
  26 #include "cx18-io.h"
  27 #include "cx18-scb.h"
  28 #include "cx18-irq.h"
  29 #include "cx18-mailbox.h"
  30 #include "cx18-queue.h"
  31 #include "cx18-streams.h"
  32
  33 static const char *rpu_str[] = { "APU", "CPU", "EPU", "HPU" };
  34
  35 #define API_FAST (1 << 2) /* Short timeout */
  36 #define API_SLOW (1 << 3) /* Additional 300ms timeout */
  37
  38 struct cx18_api_info {
  39         u32 cmd;
  40         u8 flags;               /* Flags, see above */
  41         u8 rpu;                 /* Processing unit */
  42         const char *name;       /* The name of the command */
  43 };
  44
  45 #define API_ENTRY(rpu, x, f) { (x), (f), (rpu), #x }
  46
  47 static const struct cx18_api_info api_info[] = {
  48         /* MPEG encoder API */
  49         API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE,               0),
  50         API_ENTRY(CPU, CX18_EPU_DEBUG,                          0),
  51         API_ENTRY(CPU, CX18_CREATE_TASK,                        0),
  52         API_ENTRY(CPU, CX18_DESTROY_TASK,                       0),
  53         API_ENTRY(CPU, CX18_CPU_CAPTURE_START,                  API_SLOW),
  54         API_ENTRY(CPU, CX18_CPU_CAPTURE_STOP,                   API_SLOW),
  55         API_ENTRY(CPU, CX18_CPU_CAPTURE_PAUSE,                  0),
  56         API_ENTRY(CPU, CX18_CPU_CAPTURE_RESUME,                 0),
  57         API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE,               0),
  58         API_ENTRY(CPU, CX18_CPU_SET_STREAM_OUTPUT_TYPE,         0),
  59         API_ENTRY(CPU, CX18_CPU_SET_VIDEO_IN,                   0),
  60         API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RATE,                 0),
  61         API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RESOLUTION,           0),
  62         API_ENTRY(CPU, CX18_CPU_SET_FILTER_PARAM,               0),
  63         API_ENTRY(CPU, CX18_CPU_SET_SPATIAL_FILTER_TYPE,        0),
  64         API_ENTRY(CPU, CX18_CPU_SET_MEDIAN_CORING,              0),
  65         API_ENTRY(CPU, CX18_CPU_SET_INDEXTABLE,                 0),
  66         API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PARAMETERS,           0),
  67         API_ENTRY(CPU, CX18_CPU_SET_VIDEO_MUTE,                 0),
  68         API_ENTRY(CPU, CX18_CPU_SET_AUDIO_MUTE,                 0),
  69         API_ENTRY(CPU, CX18_CPU_SET_MISC_PARAMETERS,            0),
  70         API_ENTRY(CPU, CX18_CPU_SET_RAW_VBI_PARAM,              API_SLOW),
  71         API_ENTRY(CPU, CX18_CPU_SET_CAPTURE_LINE_NO,            0),
  72         API_ENTRY(CPU, CX18_CPU_SET_COPYRIGHT,                  0),
  73         API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PID,                  0),
  74         API_ENTRY(CPU, CX18_CPU_SET_VIDEO_PID,                  0),
  75         API_ENTRY(CPU, CX18_CPU_SET_VER_CROP_LINE,              0),
  76         API_ENTRY(CPU, CX18_CPU_SET_GOP_STRUCTURE,              0),
  77         API_ENTRY(CPU, CX18_CPU_SET_SCENE_CHANGE_DETECTION,     0),
  78         API_ENTRY(CPU, CX18_CPU_SET_ASPECT_RATIO,               0),
  79         API_ENTRY(CPU, CX18_CPU_SET_SKIP_INPUT_FRAME,           0),
  80         API_ENTRY(CPU, CX18_CPU_SET_SLICED_VBI_PARAM,           0),
  81         API_ENTRY(CPU, CX18_CPU_SET_USERDATA_PLACE_HOLDER,      0),
  82         API_ENTRY(CPU, CX18_CPU_GET_ENC_PTS,                    0),
  83         API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK,                 0),
  84         API_ENTRY(CPU, CX18_CPU_DE_SET_MDL,                     API_FAST),
  85         API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL,                 API_SLOW),
  86         API_ENTRY(APU, CX18_APU_START,                          0),
  87         API_ENTRY(APU, CX18_APU_STOP,                           0),
  88         API_ENTRY(APU, CX18_APU_RESETAI,                        0),
  89         API_ENTRY(CPU, CX18_CPU_DEBUG_PEEK32,                   0),
  90         API_ENTRY(0, 0,                                         0),
  91 };
  92
  93 static const struct cx18_api_info *find_api_info(u32 cmd)
  94 {
  95         int i;
  96
  97         for (i = 0; api_info[i].cmd; i++)
  98                 if (api_info[i].cmd == cmd)
  99                         return &api_info[i];
 100         return NULL;
 101 }
 102
 103 /* Call with buf of n*11+1 bytes */
 104 static char *u32arr2hex(u32 data[], int n, char *buf)
 105 {
 106         char *p;
 107         int i;
 108
 109         for (i = 0, p = buf; i < n; i++, p += 11) {
 110                 /* kernel snprintf() appends '\0' always */
 111                 snprintf(p, 12, " %#010x", data[i]);
 112         }
 113         *p = '\0';
 114         return buf;
 115 }
 116
 117 static void dump_mb(struct cx18 *cx, struct cx18_mailbox *mb, char *name)
 118 {
 119         char argstr[MAX_MB_ARGUMENTS*11+1];
 120
 121         if (!(cx18_debug & CX18_DBGFLG_API))
 122                 return;
 123
 124         CX18_DEBUG_API("%s: req %#010x ack %#010x cmd %#010x err %#010x args%s"
 125                        "\n", name, mb->request, mb->ack, mb->cmd, mb->error,
 126                        u32arr2hex(mb->args, MAX_MB_ARGUMENTS, argstr));
 127 }
 128
 129
 130 /*
 131  * Functions that run in a work_queue work handling context
 132  */
 133
 134 static void epu_dma_done(struct cx18 *cx, struct cx18_in_work_order *order)
 135 {
 136         u32 handle, mdl_ack_count, id;
 137         struct cx18_mailbox *mb;
 138         struct cx18_mdl_ack *mdl_ack;
 139         struct cx18_stream *s;
 140         struct cx18_buffer *buf;
 141         int i;
 142
 143         mb = &order->mb;
 144         handle = mb->args[0];
 145         s = cx18_handle_to_stream(cx, handle);
 146
 147         if (s == NULL) {
 148                 CX18_WARN("Got DMA done notification for unknown/inactive"
 149                           " handle %d, %s mailbox seq no %d\n", handle,
 150                           (order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) ?
 151                           "stale" : "good", mb->request);
 152                 return;
 153         }
 154
 155         mdl_ack_count = mb->args[2];
 156         mdl_ack = order->mdl_ack;
 157         for (i = 0; i < mdl_ack_count; i++, mdl_ack++) {
 158                 id = mdl_ack->id;
 159                 /*
 160                  * Simple integrity check for processing a stale (and possibly
 161                  * inconsistent mailbox): make sure the buffer id is in the
 162                  * valid range for the stream.
 163                  *
 164                  * We go through the trouble of dealing with stale mailboxes
 165                  * because most of the time, the mailbox data is still valid and
 166                  * unchanged (and in practice the firmware ping-pongs the
 167                  * two mdl_ack buffers so mdl_acks are not stale).
 168                  *
 169                  * There are occasions when we get a half changed mailbox,
 170                  * which this check catches for a handle & id mismatch.  If the
 171                  * handle and id do correspond, the worst case is that we
 172                  * completely lost the old buffer, but pick up the new buffer
 173                  * early (but the new mdl_ack is guaranteed to be good in this
 174                  * case as the firmware wouldn't point us to a new mdl_ack until
 175                  * it's filled in).
 176                  *
 177                  * cx18_queue_get buf() will detect the lost buffers
 178                  * and send them back to q_free for fw rotation eventually.
 179                  */
 180                 if ((order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) &&
 181                     !(id >= s->mdl_offset &&
 182                       id < (s->mdl_offset + s->buffers))) {
 183                         CX18_WARN("Fell behind! Ignoring stale mailbox with "
 184                                   " inconsistent data. Lost buffer for mailbox "
 185                                   "seq no %d\n", mb->request);
 186                         break;
 187                 }
 188                 buf = cx18_queue_get_buf(s, id, mdl_ack->data_used);
 189
 190                 CX18_DEBUG_HI_DMA("DMA DONE for %s (buffer %d)\n", s->name, id);
 191                 if (buf == NULL) {
 192                         CX18_WARN("Could not find buf %d for stream %s\n",
 193                                   id, s->name);
 194                         continue;
 195                 }
 196
 197                 CX18_DEBUG_HI_DMA("%s recv bytesused = %d\n",
 198                                   s->name, buf->bytesused);
 199
 200                 if (s->type != CX18_ENC_STREAM_TYPE_TS)
 201                         cx18_enqueue(s, buf, &s->q_full);
 202                 else {
 203                         if (s->dvb.enabled)
 204                                 dvb_dmx_swfilter(&s->dvb.demux, buf->buf,
 205                                                  buf->bytesused);
 206                         cx18_enqueue(s, buf, &s->q_free);
 207                 }
 208         }
 209         /* Put as many buffers as possible back into fw use */
 210         cx18_stream_load_fw_queue(s);
 211
 212         wake_up(&cx->dma_waitq);
 213         if (s->id != -1)
 214                 wake_up(&s->waitq);
 215 }
 216
 217 static void epu_debug(struct cx18 *cx, struct cx18_in_work_order *order)
 218 {
 219         char *p;
 220         char *str = order->str;
 221
 222         CX18_DEBUG_INFO("%x %s\n", order->mb.args[0], str);
 223         p = strchr(str, '.');
 224         if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags) && p && p > str)
 225                 CX18_INFO("FW version: %s\n", p - 1);
 226 }
 227
 228 static void epu_cmd(struct cx18 *cx, struct cx18_in_work_order *order)
 229 {
 230         switch (order->rpu) {
 231         case CPU:
 232         {
 233                 switch (order->mb.cmd) {
 234                 case CX18_EPU_DMA_DONE:
 235                         epu_dma_done(cx, order);
 236                         break;
 237                 case CX18_EPU_DEBUG:
 238                         epu_debug(cx, order);
 239                         break;
 240                 default:
 241                         CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
 242                                   order->mb.cmd);
 243                         break;
 244                 }
 245                 break;
 246         }
 247         case APU:
 248                 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
 249                           order->mb.cmd);
 250                 break;
 251         default:
 252                 break;
 253         }
 254 }
 255
 256 static
 257 void free_in_work_order(struct cx18 *cx, struct cx18_in_work_order *order)
 258 {
 259         atomic_set(&order->pending, 0);
 260 }
 261
 262 void cx18_in_work_handler(struct work_struct *work)
 263 {
 264         struct cx18_in_work_order *order =
 265                         container_of(work, struct cx18_in_work_order, work);
 266         struct cx18 *cx = order->cx;
 267         epu_cmd(cx, order);
 268         free_in_work_order(cx, order);
 269 }
 270
 271
 272 /*
 273  * Functions that run in an interrupt handling context
 274  */
 275
 276 static void mb_ack_irq(struct cx18 *cx, struct cx18_in_work_order *order)
 277 {
 278         struct cx18_mailbox __iomem *ack_mb;
 279         u32 ack_irq, req;
 280
 281         switch (order->rpu) {
 282         case APU:
 283                 ack_irq = IRQ_EPU_TO_APU_ACK;
 284                 ack_mb = &cx->scb->apu2epu_mb;
 285                 break;
 286         case CPU:
 287                 ack_irq = IRQ_EPU_TO_CPU_ACK;
 288                 ack_mb = &cx->scb->cpu2epu_mb;
 289                 break;
 290         default:
 291                 CX18_WARN("Unhandled RPU (%d) for command %x ack\n",
 292                           order->rpu, order->mb.cmd);
 293                 return;
 294         }
 295
 296         req = order->mb.request;
 297         /* Don't ack if the RPU has gotten impatient and timed us out */
 298         if (req != cx18_readl(cx, &ack_mb->request) ||
 299             req == cx18_readl(cx, &ack_mb->ack)) {
 300                 CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our "
 301                                 "incoming %s to EPU mailbox (sequence no. %u) "
 302                                 "while processing\n",
 303                                 rpu_str[order->rpu], rpu_str[order->rpu], req);
 304                 order->flags |= CX18_F_EWO_MB_STALE_WHILE_PROC;
 305                 return;
 306         }
 307         cx18_writel(cx, req, &ack_mb->ack);
 308         cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq);
 309         return;
 310 }
 311
 312 static int epu_dma_done_irq(struct cx18 *cx, struct cx18_in_work_order *order)
 313 {
 314         u32 handle, mdl_ack_offset, mdl_ack_count;
 315         struct cx18_mailbox *mb;
 316
 317         mb = &order->mb;
 318         handle = mb->args[0];
 319         mdl_ack_offset = mb->args[1];
 320         mdl_ack_count = mb->args[2];
 321
 322         if (handle == CX18_INVALID_TASK_HANDLE ||
 323             mdl_ack_count == 0 || mdl_ack_count > CX18_MAX_MDL_ACKS) {
 324                 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
 325                         mb_ack_irq(cx, order);
 326                 return -1;
 327         }
 328
 329         cx18_memcpy_fromio(cx, order->mdl_ack, cx->enc_mem + mdl_ack_offset,
 330                            sizeof(struct cx18_mdl_ack) * mdl_ack_count);
 331
 332         if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
 333                 mb_ack_irq(cx, order);
 334         return 1;
 335 }
 336
 337 static
 338 int epu_debug_irq(struct cx18 *cx, struct cx18_in_work_order *order)
 339 {
 340         u32 str_offset;
 341         char *str = order->str;
 342
 343         str[0] = '\0';
 344         str_offset = order->mb.args[1];
 345         if (str_offset) {
 346                 cx18_setup_page(cx, str_offset);
 347                 cx18_memcpy_fromio(cx, str, cx->enc_mem + str_offset, 252);
 348                 str[252] = '\0';
 349                 cx18_setup_page(cx, SCB_OFFSET);
 350         }
 351
 352         if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
 353                 mb_ack_irq(cx, order);
 354
 355         return str_offset ? 1 : 0;
 356 }
 357
 358 static inline
 359 int epu_cmd_irq(struct cx18 *cx, struct cx18_in_work_order *order)
 360 {
 361         int ret = -1;
 362
 363         switch (order->rpu) {
 364         case CPU:
 365         {
 366                 switch (order->mb.cmd) {
 367                 case CX18_EPU_DMA_DONE:
 368                         ret = epu_dma_done_irq(cx, order);
 369                         break;
 370                 case CX18_EPU_DEBUG:
 371                         ret = epu_debug_irq(cx, order);
 372                         break;
 373                 default:
 374                         CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
 375                                   order->mb.cmd);
 376                         break;
 377                 }
 378                 break;
 379         }
 380         case APU:
 381                 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
 382                           order->mb.cmd);
 383                 break;
 384         default:
 385                 break;
 386         }
 387         return ret;
 388 }
 389
 390 static inline
 391 struct cx18_in_work_order *alloc_in_work_order_irq(struct cx18 *cx)
 392 {
 393         int i;
 394         struct cx18_in_work_order *order = NULL;
 395
 396         for (i = 0; i < CX18_MAX_IN_WORK_ORDERS; i++) {
 397                 /*
 398                  * We only need "pending" atomic to inspect its contents,
 399                  * and need not do a check and set because:
 400                  * 1. Any work handler thread only clears "pending" and only
 401                  * on one, particular work order at a time, per handler thread.
 402                  * 2. "pending" is only set here, and we're serialized because
 403                  * we're called in an IRQ handler context.
 404                  */
 405                 if (atomic_read(&cx->in_work_order[i].pending) == 0) {
 406                         order = &cx->in_work_order[i];
 407                         atomic_set(&order->pending, 1);
 408                         break;
 409                 }
 410         }
 411         return order;
 412 }
 413
 414 void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu)
 415 {
 416         struct cx18_mailbox __iomem *mb;
 417         struct cx18_mailbox *order_mb;
 418         struct cx18_in_work_order *order;
 419         int submit;
 420
 421         switch (rpu) {
 422         case CPU:
 423                 mb = &cx->scb->cpu2epu_mb;
 424                 break;
 425         case APU:
 426                 mb = &cx->scb->apu2epu_mb;
 427                 break;
 428         default:
 429                 return;
 430         }
 431
 432         order = alloc_in_work_order_irq(cx);
 433         if (order == NULL) {
 434                 CX18_WARN("Unable to find blank work order form to schedule "
 435                           "incoming mailbox command processing\n");
 436                 return;
 437         }
 438
 439         order->flags = 0;
 440         order->rpu = rpu;
 441         order_mb = &order->mb;
 442
 443         /* mb->cmd and mb->args[0] through mb->args[2] */
 444         cx18_memcpy_fromio(cx, &order_mb->cmd, &mb->cmd, 4 * sizeof(u32));
 445         /* mb->request and mb->ack.  N.B. we want to read mb->ack last */
 446         cx18_memcpy_fromio(cx, &order_mb->request, &mb->request,
 447                            2 * sizeof(u32));
 448
 449         if (order_mb->request == order_mb->ack) {
 450                 CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our "
 451                                 "incoming %s to EPU mailbox (sequence no. %u)"
 452                                 "\n",
 453                                 rpu_str[rpu], rpu_str[rpu], order_mb->request);
 454                 if (cx18_debug & CX18_DBGFLG_WARN)
 455                         dump_mb(cx, order_mb, "incoming");
 456                 order->flags = CX18_F_EWO_MB_STALE_UPON_RECEIPT;
 457         }
 458
 459         /*
 460          * Individual EPU command processing is responsible for ack-ing
 461          * a non-stale mailbox as soon as possible
 462          */
 463         submit = epu_cmd_irq(cx, order);
 464         if (submit > 0) {
 465                 queue_work(cx->in_work_queue, &order->work);
 466         }
 467 }
 468
 469
 470 /*
 471  * Functions called from a non-interrupt, non work_queue context
 472  */
 473
 474 static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
 475 {
 476         const struct cx18_api_info *info = find_api_info(cmd);
 477         u32 state, irq, req, ack, err;
 478         struct cx18_mailbox __iomem *mb;
 479         u32 __iomem *xpu_state;
 480         wait_queue_head_t *waitq;
 481         struct mutex *mb_lock;
 482         unsigned long int t0, timeout, ret;
 483         int i;
 484         char argstr[MAX_MB_ARGUMENTS*11+1];
 485         DEFINE_WAIT(w);
 486
 487         if (info == NULL) {
 488                 CX18_WARN("unknown cmd %x\n", cmd);
 489                 return -EINVAL;
 490         }
 491
 492         if (cx18_debug & CX18_DBGFLG_API) { /* only call u32arr2hex if needed */
 493                 if (cmd == CX18_CPU_DE_SET_MDL) {
 494                         if (cx18_debug & CX18_DBGFLG_HIGHVOL)
 495                                 CX18_DEBUG_HI_API("%s\tcmd %#010x args%s\n",
 496                                                 info->name, cmd,
 497                                                 u32arr2hex(data, args, argstr));
 498                 } else
 499                         CX18_DEBUG_API("%s\tcmd %#010x args%s\n",
 500                                        info->name, cmd,
 501                                        u32arr2hex(data, args, argstr));
 502         }
 503
 504         switch (info->rpu) {
 505         case APU:
 506                 waitq = &cx->mb_apu_waitq;
 507                 mb_lock = &cx->epu2apu_mb_lock;
 508                 irq = IRQ_EPU_TO_APU;
 509                 mb = &cx->scb->epu2apu_mb;
 510                 xpu_state = &cx->scb->apu_state;
 511                 break;
 512         case CPU:
 513                 waitq = &cx->mb_cpu_waitq;
 514                 mb_lock = &cx->epu2cpu_mb_lock;
 515                 irq = IRQ_EPU_TO_CPU;
 516                 mb = &cx->scb->epu2cpu_mb;
 517                 xpu_state = &cx->scb->cpu_state;
 518                 break;
 519         default:
 520                 CX18_WARN("Unknown RPU (%d) for API call\n", info->rpu);
 521                 return -EINVAL;
 522         }
 523
 524         mutex_lock(mb_lock);
 525         /*
 526          * Wait for an in-use mailbox to complete
 527          *
 528          * If the XPU is responding with Ack's, the mailbox shouldn't be in
 529          * a busy state, since we serialize access to it on our end.
 530          *
 531          * If the wait for ack after sending a previous command was interrupted
 532          * by a signal, we may get here and find a busy mailbox.  After waiting,
 533          * mark it "not busy" from our end, if the XPU hasn't ack'ed it still.
 534          */
 535         state = cx18_readl(cx, xpu_state);
 536         req = cx18_readl(cx, &mb->request);
 537         timeout = msecs_to_jiffies(10);
 538         ret = wait_event_timeout(*waitq,
 539                                  (ack = cx18_readl(cx, &mb->ack)) == req,
 540                                  timeout);
 541         if (req != ack) {
 542                 /* waited long enough, make the mbox "not busy" from our end */
 543                 cx18_writel(cx, req, &mb->ack);
 544                 CX18_ERR("mbox was found stuck busy when setting up for %s; "
 545                          "clearing busy and trying to proceed\n", info->name);
 546         } else if (ret != timeout)
 547                 CX18_DEBUG_API("waited %u msecs for busy mbox to be acked\n",
 548                                jiffies_to_msecs(timeout-ret));
 549
 550         /* Build the outgoing mailbox */
 551         req = ((req & 0xfffffffe) == 0xfffffffe) ? 1 : req + 1;
 552
 553         cx18_writel(cx, cmd, &mb->cmd);
 554         for (i = 0; i < args; i++)
 555                 cx18_writel(cx, data[i], &mb->args[i]);
 556         cx18_writel(cx, 0, &mb->error);
 557         cx18_writel(cx, req, &mb->request);
 558         cx18_writel(cx, req - 1, &mb->ack); /* ensure ack & req are distinct */
 559
 560         /*
 561          * Notify the XPU and wait for it to send an Ack back
 562          */
 563         timeout = msecs_to_jiffies((info->flags & API_FAST) ? 10 : 20);
 564
 565         CX18_DEBUG_HI_IRQ("sending interrupt SW1: %x to send %s\n",
 566                           irq, info->name);
 567
 568         /* So we don't miss the wakeup, prepare to wait before notifying fw */
 569         prepare_to_wait(waitq, &w, TASK_UNINTERRUPTIBLE);
 570         cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq);
 571
 572         t0 = jiffies;
 573         ack = cx18_readl(cx, &mb->ack);
 574         if (ack != req) {
 575                 schedule_timeout(timeout);
 576                 ret = jiffies - t0;
 577                 ack = cx18_readl(cx, &mb->ack);
 578         } else {
 579                 ret = jiffies - t0;
 580         }
 581
 582         finish_wait(waitq, &w);
 583
 584         if (req != ack) {
 585                 mutex_unlock(mb_lock);
 586                 if (ret >= timeout) {
 587                         /* Timed out */
 588                         CX18_DEBUG_WARN("sending %s timed out waiting %d msecs "
 589                                         "for RPU acknowledgement\n",
 590                                         info->name, jiffies_to_msecs(ret));
 591                 } else {
 592                         CX18_DEBUG_WARN("woken up before mailbox ack was ready "
 593                                         "after submitting %s to RPU.  only "
 594                                         "waited %d msecs on req %u but awakened"
 595                                         " with unmatched ack %u\n",
 596                                         info->name,
 597                                         jiffies_to_msecs(ret),
 598                                         req, ack);
 599                 }
 600                 return -EINVAL;
 601         }
 602
 603         if (ret >= timeout)
 604                 CX18_DEBUG_WARN("failed to be awakened upon RPU acknowledgment "
 605                                 "sending %s; timed out waiting %d msecs\n",
 606                                 info->name, jiffies_to_msecs(ret));
 607         else
 608                 CX18_DEBUG_HI_API("waited %u msecs for %s to be acked\n",
 609                                   jiffies_to_msecs(ret), info->name);
 610
 611         /* Collect data returned by the XPU */
 612         for (i = 0; i < MAX_MB_ARGUMENTS; i++)
 613                 data[i] = cx18_readl(cx, &mb->args[i]);
 614         err = cx18_readl(cx, &mb->error);
 615         mutex_unlock(mb_lock);
 616
 617         /*
 618          * Wait for XPU to perform extra actions for the caller in some cases.
 619          * e.g. CX18_CPU_DE_RELEASE_MDL will cause the CPU to send all buffers
 620          * back in a burst shortly thereafter
 621          */
 622         if (info->flags & API_SLOW)
 623                 cx18_msleep_timeout(300, 0);
 624
 625         if (err)
 626                 CX18_DEBUG_API("mailbox error %08x for command %s\n", err,
 627                                 info->name);
 628         return err ? -EIO : 0;
 629 }
 630
 631 int cx18_api(struct cx18 *cx, u32 cmd, int args, u32 data[])
 632 {
 633         return cx18_api_call(cx, cmd, args, data);
 634 }
 635
 636 static int cx18_set_filter_param(struct cx18_stream *s)
 637 {
 638         struct cx18 *cx = s->cx;
 639         u32 mode;
 640         int ret;
 641
 642         mode = (cx->filter_mode & 1) ? 2 : (cx->spatial_strength ? 1 : 0);
 643         ret = cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
 644                         s->handle, 1, mode, cx->spatial_strength);
 645         mode = (cx->filter_mode & 2) ? 2 : (cx->temporal_strength ? 1 : 0);
 646         ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
 647                         s->handle, 0, mode, cx->temporal_strength);
 648         ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
 649                         s->handle, 2, cx->filter_mode >> 2, 0);
 650         return ret;
 651 }
 652
 653 int cx18_api_func(void *priv, u32 cmd, int in, int out,
 654                 u32 data[CX2341X_MBOX_MAX_DATA])
 655 {
 656         struct cx18_api_func_private *api_priv = priv;
 657         struct cx18 *cx = api_priv->cx;
 658         struct cx18_stream *s = api_priv->s;
 659
 660         switch (cmd) {
 661         case CX2341X_ENC_SET_OUTPUT_PORT:
 662                 return 0;
 663         case CX2341X_ENC_SET_FRAME_RATE:
 664                 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_IN, 6,
 665                                 s->handle, 0, 0, 0, 0, data[0]);
 666         case CX2341X_ENC_SET_FRAME_SIZE:
 667                 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RESOLUTION, 3,
 668                                 s->handle, data[1], data[0]);
 669         case CX2341X_ENC_SET_STREAM_TYPE:
 670                 return cx18_vapi(cx, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 2,
 671                                 s->handle, data[0]);
 672         case CX2341X_ENC_SET_ASPECT_RATIO:
 673                 return cx18_vapi(cx, CX18_CPU_SET_ASPECT_RATIO, 2,
 674                                 s->handle, data[0]);
 675
 676         case CX2341X_ENC_SET_GOP_PROPERTIES:
 677                 return cx18_vapi(cx, CX18_CPU_SET_GOP_STRUCTURE, 3,
 678                                 s->handle, data[0], data[1]);
 679         case CX2341X_ENC_SET_GOP_CLOSURE:
 680                 return 0;
 681         case CX2341X_ENC_SET_AUDIO_PROPERTIES:
 682                 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_PARAMETERS, 2,
 683                                 s->handle, data[0]);
 684         case CX2341X_ENC_MUTE_AUDIO:
 685                 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_MUTE, 2,
 686                                 s->handle, data[0]);
 687         case CX2341X_ENC_SET_BIT_RATE:
 688                 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RATE, 5,
 689                                 s->handle, data[0], data[1], data[2], data[3]);
 690         case CX2341X_ENC_MUTE_VIDEO:
 691                 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2,
 692                                 s->handle, data[0]);
 693         case CX2341X_ENC_SET_FRAME_DROP_RATE:
 694                 return cx18_vapi(cx, CX18_CPU_SET_SKIP_INPUT_FRAME, 2,
 695                                 s->handle, data[0]);
 696         case CX2341X_ENC_MISC:
 697                 return cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 4,
 698                                 s->handle, data[0], data[1], data[2]);
 699         case CX2341X_ENC_SET_DNR_FILTER_MODE:
 700                 cx->filter_mode = (data[0] & 3) | (data[1] << 2);
 701                 return cx18_set_filter_param(s);
 702         case CX2341X_ENC_SET_DNR_FILTER_PROPS:
 703                 cx->spatial_strength = data[0];
 704                 cx->temporal_strength = data[1];
 705                 return cx18_set_filter_param(s);
 706         case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
 707                 return cx18_vapi(cx, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 3,
 708                                 s->handle, data[0], data[1]);
 709         case CX2341X_ENC_SET_CORING_LEVELS:
 710                 return cx18_vapi(cx, CX18_CPU_SET_MEDIAN_CORING, 5,
 711                                 s->handle, data[0], data[1], data[2], data[3]);
 712         }
 713         CX18_WARN("Unknown cmd %x\n", cmd);
 714         return 0;
 715 }
 716
 717 int cx18_vapi_result(struct cx18 *cx, u32 data[MAX_MB_ARGUMENTS],
 718                 u32 cmd, int args, ...)
 719 {
 720         va_list ap;
 721         int i;
 722
 723         va_start(ap, args);
 724         for (i = 0; i < args; i++)
 725                 data[i] = va_arg(ap, u32);
 726         va_end(ap);
 727         return cx18_api(cx, cmd, args, data);
 728 }
 729
 730 int cx18_vapi(struct cx18 *cx, u32 cmd, int args, ...)
 731 {
 732         u32 data[MAX_MB_ARGUMENTS];
 733         va_list ap;
 734         int i;
 735
 736         if (cx == NULL) {
 737                 CX18_ERR("cx == NULL (cmd=%x)\n", cmd);
 738                 return 0;
 739         }
 740         if (args > MAX_MB_ARGUMENTS) {
 741                 CX18_ERR("args too big (cmd=%x)\n", cmd);
 742                 args = MAX_MB_ARGUMENTS;
 743         }
 744         va_start(ap, args);
 745         for (i = 0; i < args; i++)
 746                 data[i] = va_arg(ap, u32);
 747         va_end(ap);
 748         return cx18_api(cx, cmd, args, data);
 749 }