2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
7 * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
8 * Copyright (C) 1999 Silicon Graphics, Inc.
9 * Copyright (C) 2007 Maciej W. Rozycki
11 #ifndef _ASM_STACKFRAME_H
12 #define _ASM_STACKFRAME_H
14 #include <linux/threads.h>
17 #include <asm/asmmacro.h>
18 #include <asm/mipsregs.h>
19 #include <asm/asm-offsets.h>
22 * For SMTC kernel, global IE should be left set, and interrupts
23 * controlled exclusively via IXMT.
25 #ifdef CONFIG_MIPS_MT_SMTC
27 #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
33 #ifdef CONFIG_MIPS_MT_SMTC
34 #include <asm/mipsmtregs.h>
35 #endif /* CONFIG_MIPS_MT_SMTC */
45 #ifdef CONFIG_CPU_HAS_SMARTMIPS
62 LONG_S $10, PT_R10(sp)
63 LONG_S $11, PT_R11(sp)
64 LONG_S $12, PT_R12(sp)
65 LONG_S $13, PT_R13(sp)
66 LONG_S $14, PT_R14(sp)
67 LONG_S $15, PT_R15(sp)
68 LONG_S $24, PT_R24(sp)
72 LONG_S $16, PT_R16(sp)
73 LONG_S $17, PT_R17(sp)
74 LONG_S $18, PT_R18(sp)
75 LONG_S $19, PT_R19(sp)
76 LONG_S $20, PT_R20(sp)
77 LONG_S $21, PT_R21(sp)
78 LONG_S $22, PT_R22(sp)
79 LONG_S $23, PT_R23(sp)
80 LONG_S $30, PT_R30(sp)
84 #ifdef CONFIG_MIPS_MT_SMTC
85 #define PTEBASE_SHIFT 19 /* TCBIND */
87 #define PTEBASE_SHIFT 23 /* CONTEXT */
89 .macro get_saved_sp /* SMP variation */
90 #ifdef CONFIG_MIPS_MT_SMTC
95 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
98 lui k1, %highest(kernelsp)
99 daddiu k1, %higher(kernelsp)
101 daddiu k1, %hi(kernelsp)
104 LONG_SRL k0, PTEBASE_SHIFT
106 LONG_L k1, %lo(kernelsp)(k1)
109 .macro set_saved_sp stackp temp temp2
110 #ifdef CONFIG_MIPS_MT_SMTC
111 mfc0 \temp, CP0_TCBIND
113 MFC0 \temp, CP0_CONTEXT
115 LONG_SRL \temp, PTEBASE_SHIFT
116 LONG_S \stackp, kernelsp(\temp)
119 .macro get_saved_sp /* Uniprocessor variation */
120 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
121 lui k1, %hi(kernelsp)
123 lui k1, %highest(kernelsp)
124 daddiu k1, %higher(kernelsp)
126 daddiu k1, %hi(kernelsp)
129 LONG_L k1, %lo(kernelsp)(k1)
132 .macro set_saved_sp stackp temp temp2
133 LONG_S \stackp, kernelsp
142 sll k0, 3 /* extract cu0 bit */
147 /* Called from user mode, new stack. */
149 #ifndef CONFIG_CPU_DADDI_WORKAROUNDS
151 PTR_SUBU sp, k1, PT_SIZE
154 8: PTR_SUBU k1, PT_SIZE
159 LONG_S k0, PT_R29(sp)
162 * You might think that you don't need to save $0,
163 * but the FPU emulator and gdb remote debug stub
164 * need it to operate correctly
169 LONG_S v1, PT_STATUS(sp)
170 #ifdef CONFIG_MIPS_MT_SMTC
172 * Ideally, these instructions would be shuffled in
173 * to cover the pipeline delay.
176 mfc0 v1, CP0_TCSTATUS
178 LONG_S v1, PT_TCSTATUS(sp)
179 #endif /* CONFIG_MIPS_MT_SMTC */
183 LONG_S v1, PT_CAUSE(sp)
191 LONG_S v1, PT_EPC(sp)
192 LONG_S $25, PT_R25(sp)
193 LONG_S $28, PT_R28(sp)
194 LONG_S $31, PT_R31(sp)
195 ori $28, sp, _THREAD_MASK
196 xori $28, _THREAD_MASK
197 #ifdef CONFIG_CPU_CAVIUM_OCTEON
199 pref 0, 0($28) /* Prefetch the current pointer */
200 pref 0, PT_R31(sp) /* Prefetch the $31(ra) */
201 /* The Octeon multiplier state is affected by general multiply
202 instructions. It must be saved before and kernel code might
205 LONG_L v1, 0($28) /* Load the current pointer */
206 /* Restore $31(ra) that was changed by the jal */
207 LONG_L ra, PT_R31(sp)
208 pref 0, 0(v1) /* Prefetch the current thread */
228 #ifdef CONFIG_CPU_HAS_SMARTMIPS
229 LONG_L $24, PT_ACX(sp)
231 LONG_L $24, PT_HI(sp)
233 LONG_L $24, PT_LO(sp)
236 LONG_L $24, PT_LO(sp)
238 LONG_L $24, PT_HI(sp)
245 LONG_L $10, PT_R10(sp)
246 LONG_L $11, PT_R11(sp)
247 LONG_L $12, PT_R12(sp)
248 LONG_L $13, PT_R13(sp)
249 LONG_L $14, PT_R14(sp)
250 LONG_L $15, PT_R15(sp)
251 LONG_L $24, PT_R24(sp)
254 .macro RESTORE_STATIC
255 LONG_L $16, PT_R16(sp)
256 LONG_L $17, PT_R17(sp)
257 LONG_L $18, PT_R18(sp)
258 LONG_L $19, PT_R19(sp)
259 LONG_L $20, PT_R20(sp)
260 LONG_L $21, PT_R21(sp)
261 LONG_L $22, PT_R22(sp)
262 LONG_L $23, PT_R23(sp)
263 LONG_L $30, PT_R30(sp)
266 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
278 LONG_L v0, PT_STATUS(sp)
283 LONG_L $31, PT_R31(sp)
284 LONG_L $28, PT_R28(sp)
285 LONG_L $25, PT_R25(sp)
295 .macro RESTORE_SP_AND_RET
298 LONG_L k0, PT_EPC(sp)
299 LONG_L sp, PT_R29(sp)
310 #ifdef CONFIG_MIPS_MT_SMTC
313 * We need to make sure the read-modify-write
314 * of Status below isn't perturbed by an interrupt
315 * or cross-TC access, so we need to do at least a DMT,
316 * protected by an interrupt-inhibit. But setting IXMT
317 * also creates a few-cycle window where an IPI could
318 * be queued and not be detected before potentially
319 * returning to a WAIT or user-mode loop. It must be
322 * We're in the middle of a context switch, and
323 * we can't dispatch it directly without trashing
324 * some registers, so we'll try to detect this unlikely
325 * case and program a software interrupt in the VPE,
326 * as would be done for a cross-VPE IPI. To accomodate
327 * the handling of that case, we're doing a DVPE instead
328 * of just a DMT here to protect against other threads.
329 * This is a lot of cruft to cover a tiny window.
330 * If you can find a better design, implement it!
333 mfc0 v0, CP0_TCSTATUS
334 ori v0, TCSTATUS_IXMT
335 mtc0 v0, CP0_TCSTATUS
339 #endif /* CONFIG_MIPS_MT_SMTC */
340 #ifdef CONFIG_CPU_CAVIUM_OCTEON
341 /* Restore the Octeon multiplier state */
342 jal octeon_mult_restore
350 LONG_L v0, PT_STATUS(sp)
355 #ifdef CONFIG_MIPS_MT_SMTC
357 * Only after EXL/ERL have been restored to status can we
358 * restore TCStatus.IXMT.
360 LONG_L v1, PT_TCSTATUS(sp)
362 mfc0 a0, CP0_TCSTATUS
363 andi v1, TCSTATUS_IXMT
367 * We'd like to detect any IPIs queued in the tiny window
368 * above and request an software interrupt to service them
371 * Computing the offset into the IPIQ array of the executing
372 * TC's IPI queue in-line would be tedious. We use part of
373 * the TCContext register to hold 16 bits of offset that we
374 * can add in-line to find the queue head.
376 mfc0 v0, CP0_TCCONTEXT
383 * If we have a queue, provoke dispatch within the VPE by setting C_SW1
390 * This test should really never branch but
391 * let's be prudent here. Having atomized
392 * the shared register modifications, we can
393 * now EVPE, and must do so before interrupts
394 * are potentially re-enabled.
396 andi a1, a1, MVPCONTROL_EVP
400 /* We know that TCStatua.IXMT should be set from above */
401 xori a0, a0, TCSTATUS_IXMT
403 mtc0 a0, CP0_TCSTATUS
407 #endif /* CONFIG_MIPS_MT_SMTC */
408 LONG_L v1, PT_EPC(sp)
410 LONG_L $31, PT_R31(sp)
411 LONG_L $28, PT_R28(sp)
412 LONG_L $25, PT_R25(sp)
426 .macro RESTORE_SP_AND_RET
427 LONG_L sp, PT_R29(sp)
436 LONG_L sp, PT_R29(sp)
447 .macro RESTORE_ALL_AND_RET
456 * Move to kernel mode and disable interrupts.
457 * Set cp0 enable bit as sign that we're running on the kernel stack
460 #if !defined(CONFIG_MIPS_MT_SMTC)
462 li t1, ST0_CU0 | STATMASK
466 #else /* CONFIG_MIPS_MT_SMTC */
468 * For SMTC, we need to set privilege
469 * and disable interrupts only for the
470 * current TC, using the TCStatus register.
472 mfc0 t0, CP0_TCSTATUS
473 /* Fortunately CU 0 is in the same place in both registers */
474 /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
475 li t1, ST0_CU0 | 0x08001c00
477 /* Clear TKSU, leave IXMT */
479 mtc0 t0, CP0_TCSTATUS
481 /* We need to leave the global IE bit set, but clear EXL...*/
483 ori t0, ST0_EXL | ST0_ERL
484 xori t0, ST0_EXL | ST0_ERL
486 #endif /* CONFIG_MIPS_MT_SMTC */
491 * Move to kernel mode and enable interrupts.
492 * Set cp0 enable bit as sign that we're running on the kernel stack
495 #if !defined(CONFIG_MIPS_MT_SMTC)
497 li t1, ST0_CU0 | STATMASK
499 xori t0, STATMASK & ~1
501 #else /* CONFIG_MIPS_MT_SMTC */
503 * For SMTC, we need to set privilege
504 * and enable interrupts only for the
505 * current TC, using the TCStatus register.
508 mfc0 t0, CP0_TCSTATUS
509 /* Fortunately CU 0 is in the same place in both registers */
510 /* Set TCU0, TKSU (for later inversion) and IXMT */
511 li t1, ST0_CU0 | 0x08001c00
513 /* Clear TKSU *and* IXMT */
515 mtc0 t0, CP0_TCSTATUS
517 /* We need to leave the global IE bit set, but clear EXL...*/
522 /* irq_enable_hazard below should expand to EHB for 24K/34K cpus */
523 #endif /* CONFIG_MIPS_MT_SMTC */
528 * Just move to kernel mode and leave interrupts as they are. Note
529 * for the R3000 this means copying the previous enable from IEp.
530 * Set cp0 enable bit as sign that we're running on the kernel stack
533 #ifdef CONFIG_MIPS_MT_SMTC
535 * This gets baroque in SMTC. We want to
536 * protect the non-atomic clearing of EXL
537 * with DMT/EMT, but we don't want to take
538 * an interrupt while DMT is still in effect.
541 /* KMODE gets invoked from both reorder and noreorder code */
545 mfc0 v0, CP0_TCSTATUS
546 andi v1, v0, TCSTATUS_IXMT
547 ori v0, TCSTATUS_IXMT
548 mtc0 v0, CP0_TCSTATUS
552 * We don't know a priori if ra is "live"
558 #endif /* CONFIG_MIPS_MT_SMTC */
560 li t1, ST0_CU0 | (STATMASK & ~1)
561 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
567 xori t0, STATMASK & ~1
569 #ifdef CONFIG_MIPS_MT_SMTC
571 andi v0, v0, VPECONTROL_TE
576 mfc0 v0, CP0_TCSTATUS
577 /* Clear IXMT, then OR in previous value */
578 ori v0, TCSTATUS_IXMT
579 xori v0, TCSTATUS_IXMT
581 mtc0 v0, CP0_TCSTATUS
583 * irq_disable_hazard below should expand to EHB
587 #endif /* CONFIG_MIPS_MT_SMTC */
591 #endif /* _ASM_STACKFRAME_H */