git.oblomov.eu Git - linux-2.6/blob - arch/arm/mach-at91/at91sam9rl_devices.c

   1 /*
   2  *  Copyright (C) 2007 Atmel Corporation
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file COPYING in the main directory of this archive for
   6  * more details.
   7  */
   8
   9 #include <asm/mach/arch.h>
  10 #include <asm/mach/map.h>
  11
  12 #include <linux/dma-mapping.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/i2c-gpio.h>
  15
  16 #include <linux/fb.h>
  17 #include <video/atmel_lcdc.h>
  18
  19 #include <asm/arch/board.h>
  20 #include <asm/arch/gpio.h>
  21 #include <asm/arch/at91sam9rl.h>
  22 #include <asm/arch/at91sam9rl_matrix.h>
  23 #include <asm/arch/at91sam9_smc.h>
  24
  25 #include "generic.h"
  26
  27
  28 /* --------------------------------------------------------------------
  29  *  MMC / SD
  30  * -------------------------------------------------------------------- */
  31
  32 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
  33 static u64 mmc_dmamask = DMA_BIT_MASK(32);
  34 static struct at91_mmc_data mmc_data;
  35
  36 static struct resource mmc_resources[] = {
  37         [0] = {
  38                 .start  = AT91SAM9RL_BASE_MCI,
  39                 .end    = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
  40                 .flags  = IORESOURCE_MEM,
  41         },
  42         [1] = {
  43                 .start  = AT91SAM9RL_ID_MCI,
  44                 .end    = AT91SAM9RL_ID_MCI,
  45                 .flags  = IORESOURCE_IRQ,
  46         },
  47 };
  48
  49 static struct platform_device at91sam9rl_mmc_device = {
  50         .name           = "at91_mci",
  51         .id             = -1,
  52         .dev            = {
  53                                 .dma_mask               = &mmc_dmamask,
  54                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
  55                                 .platform_data          = &mmc_data,
  56         },
  57         .resource       = mmc_resources,
  58         .num_resources  = ARRAY_SIZE(mmc_resources),
  59 };
  60
  61 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
  62 {
  63         if (!data)
  64                 return;
  65
  66         /* input/irq */
  67         if (data->det_pin) {
  68                 at91_set_gpio_input(data->det_pin, 1);
  69                 at91_set_deglitch(data->det_pin, 1);
  70         }
  71         if (data->wp_pin)
  72                 at91_set_gpio_input(data->wp_pin, 1);
  73         if (data->vcc_pin)
  74                 at91_set_gpio_output(data->vcc_pin, 0);
  75
  76         /* CLK */
  77         at91_set_A_periph(AT91_PIN_PA2, 0);
  78
  79         /* CMD */
  80         at91_set_A_periph(AT91_PIN_PA1, 1);
  81
  82         /* DAT0, maybe DAT1..DAT3 */
  83         at91_set_A_periph(AT91_PIN_PA0, 1);
  84         if (data->wire4) {
  85                 at91_set_A_periph(AT91_PIN_PA3, 1);
  86                 at91_set_A_periph(AT91_PIN_PA4, 1);
  87                 at91_set_A_periph(AT91_PIN_PA5, 1);
  88         }
  89
  90         mmc_data = *data;
  91         platform_device_register(&at91sam9rl_mmc_device);
  92 }
  93 #else
  94 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
  95 #endif
  96
  97
  98 /* --------------------------------------------------------------------
  99  *  NAND / SmartMedia
 100  * -------------------------------------------------------------------- */
 101
 102 #if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
 103 static struct at91_nand_data nand_data;
 104
 105 #define NAND_BASE       AT91_CHIPSELECT_3
 106
 107 static struct resource nand_resources[] = {
 108         [0] = {
 109                 .start  = NAND_BASE,
 110                 .end    = NAND_BASE + SZ_256M - 1,
 111                 .flags  = IORESOURCE_MEM,
 112         },
 113         [1] = {
 114                 .start  = AT91_BASE_SYS + AT91_ECC,
 115                 .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
 116                 .flags  = IORESOURCE_MEM,
 117         }
 118 };
 119
 120 static struct platform_device at91_nand_device = {
 121         .name           = "at91_nand",
 122         .id             = -1,
 123         .dev            = {
 124                                 .platform_data  = &nand_data,
 125         },
 126         .resource       = nand_resources,
 127         .num_resources  = ARRAY_SIZE(nand_resources),
 128 };
 129
 130 void __init at91_add_device_nand(struct at91_nand_data *data)
 131 {
 132         unsigned long csa;
 133
 134         if (!data)
 135                 return;
 136
 137         csa = at91_sys_read(AT91_MATRIX_EBICSA);
 138         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 139
 140         /* set the bus interface characteristics */
 141         at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
 142                         | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
 143
 144         at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
 145                         | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
 146
 147         at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
 148
 149         at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
 150
 151         /* enable pin */
 152         if (data->enable_pin)
 153                 at91_set_gpio_output(data->enable_pin, 1);
 154
 155         /* ready/busy pin */
 156         if (data->rdy_pin)
 157                 at91_set_gpio_input(data->rdy_pin, 1);
 158
 159         /* card detect pin */
 160         if (data->det_pin)
 161                 at91_set_gpio_input(data->det_pin, 1);
 162
 163         at91_set_A_periph(AT91_PIN_PB4, 0);             /* NANDOE */
 164         at91_set_A_periph(AT91_PIN_PB5, 0);             /* NANDWE */
 165
 166         nand_data = *data;
 167         platform_device_register(&at91_nand_device);
 168 }
 169
 170 #else
 171 void __init at91_add_device_nand(struct at91_nand_data *data) {}
 172 #endif
 173
 174
 175 /* --------------------------------------------------------------------
 176  *  TWI (i2c)
 177  * -------------------------------------------------------------------- */
 178
 179 /*
 180  * Prefer the GPIO code since the TWI controller isn't robust
 181  * (gets overruns and underruns under load) and can only issue
 182  * repeated STARTs in one scenario (the driver doesn't yet handle them).
 183  */
 184 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
 185
 186 static struct i2c_gpio_platform_data pdata = {
 187         .sda_pin                = AT91_PIN_PA23,
 188         .sda_is_open_drain      = 1,
 189         .scl_pin                = AT91_PIN_PA24,
 190         .scl_is_open_drain      = 1,
 191         .udelay                 = 2,            /* ~100 kHz */
 192 };
 193
 194 static struct platform_device at91sam9rl_twi_device = {
 195         .name                   = "i2c-gpio",
 196         .id                     = -1,
 197         .dev.platform_data      = &pdata,
 198 };
 199
 200 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
 201 {
 202         at91_set_GPIO_periph(AT91_PIN_PA23, 1);         /* TWD (SDA) */
 203         at91_set_multi_drive(AT91_PIN_PA23, 1);
 204
 205         at91_set_GPIO_periph(AT91_PIN_PA24, 1);         /* TWCK (SCL) */
 206         at91_set_multi_drive(AT91_PIN_PA24, 1);
 207
 208         i2c_register_board_info(0, devices, nr_devices);
 209         platform_device_register(&at91sam9rl_twi_device);
 210 }
 211
 212 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
 213
 214 static struct resource twi_resources[] = {
 215         [0] = {
 216                 .start  = AT91SAM9RL_BASE_TWI0,
 217                 .end    = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
 218                 .flags  = IORESOURCE_MEM,
 219         },
 220         [1] = {
 221                 .start  = AT91SAM9RL_ID_TWI0,
 222                 .end    = AT91SAM9RL_ID_TWI0,
 223                 .flags  = IORESOURCE_IRQ,
 224         },
 225 };
 226
 227 static struct platform_device at91sam9rl_twi_device = {
 228         .name           = "at91_i2c",
 229         .id             = -1,
 230         .resource       = twi_resources,
 231         .num_resources  = ARRAY_SIZE(twi_resources),
 232 };
 233
 234 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
 235 {
 236         /* pins used for TWI interface */
 237         at91_set_A_periph(AT91_PIN_PA23, 0);            /* TWD */
 238         at91_set_multi_drive(AT91_PIN_PA23, 1);
 239
 240         at91_set_A_periph(AT91_PIN_PA24, 0);            /* TWCK */
 241         at91_set_multi_drive(AT91_PIN_PA24, 1);
 242
 243         i2c_register_board_info(0, devices, nr_devices);
 244         platform_device_register(&at91sam9rl_twi_device);
 245 }
 246 #else
 247 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
 248 #endif
 249
 250
 251 /* --------------------------------------------------------------------
 252  *  SPI
 253  * -------------------------------------------------------------------- */
 254
 255 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
 256 static u64 spi_dmamask = DMA_BIT_MASK(32);
 257
 258 static struct resource spi_resources[] = {
 259         [0] = {
 260                 .start  = AT91SAM9RL_BASE_SPI,
 261                 .end    = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
 262                 .flags  = IORESOURCE_MEM,
 263         },
 264         [1] = {
 265                 .start  = AT91SAM9RL_ID_SPI,
 266                 .end    = AT91SAM9RL_ID_SPI,
 267                 .flags  = IORESOURCE_IRQ,
 268         },
 269 };
 270
 271 static struct platform_device at91sam9rl_spi_device = {
 272         .name           = "atmel_spi",
 273         .id             = 0,
 274         .dev            = {
 275                                 .dma_mask               = &spi_dmamask,
 276                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 277         },
 278         .resource       = spi_resources,
 279         .num_resources  = ARRAY_SIZE(spi_resources),
 280 };
 281
 282 static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
 283
 284
 285 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 286 {
 287         int i;
 288         unsigned long cs_pin;
 289
 290         at91_set_A_periph(AT91_PIN_PA25, 0);    /* MISO */
 291         at91_set_A_periph(AT91_PIN_PA26, 0);    /* MOSI */
 292         at91_set_A_periph(AT91_PIN_PA27, 0);    /* SPCK */
 293
 294         /* Enable SPI chip-selects */
 295         for (i = 0; i < nr_devices; i++) {
 296                 if (devices[i].controller_data)
 297                         cs_pin = (unsigned long) devices[i].controller_data;
 298                 else
 299                         cs_pin = spi_standard_cs[devices[i].chip_select];
 300
 301                 /* enable chip-select pin */
 302                 at91_set_gpio_output(cs_pin, 1);
 303
 304                 /* pass chip-select pin to driver */
 305                 devices[i].controller_data = (void *) cs_pin;
 306         }
 307
 308         spi_register_board_info(devices, nr_devices);
 309         platform_device_register(&at91sam9rl_spi_device);
 310 }
 311 #else
 312 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
 313 #endif
 314
 315
 316 /* --------------------------------------------------------------------
 317  *  LCD Controller
 318  * -------------------------------------------------------------------- */
 319
 320 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
 321 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
 322 static struct atmel_lcdfb_info lcdc_data;
 323
 324 static struct resource lcdc_resources[] = {
 325         [0] = {
 326                 .start  = AT91SAM9RL_LCDC_BASE,
 327                 .end    = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
 328                 .flags  = IORESOURCE_MEM,
 329         },
 330         [1] = {
 331                 .start  = AT91SAM9RL_ID_LCDC,
 332                 .end    = AT91SAM9RL_ID_LCDC,
 333                 .flags  = IORESOURCE_IRQ,
 334         },
 335 #if defined(CONFIG_FB_INTSRAM)
 336         [2] = {
 337                 .start  = AT91SAM9RL_SRAM_BASE,
 338                 .end    = AT91SAM9RL_SRAM_BASE + AT91SAM9RL_SRAM_SIZE - 1,
 339                 .flags  = IORESOURCE_MEM,
 340         },
 341 #endif
 342 };
 343
 344 static struct platform_device at91_lcdc_device = {
 345         .name           = "atmel_lcdfb",
 346         .id             = 0,
 347         .dev            = {
 348                                 .dma_mask               = &lcdc_dmamask,
 349                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 350                                 .platform_data          = &lcdc_data,
 351         },
 352         .resource       = lcdc_resources,
 353         .num_resources  = ARRAY_SIZE(lcdc_resources),
 354 };
 355
 356 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
 357 {
 358         if (!data) {
 359                 return;
 360         }
 361
 362         at91_set_B_periph(AT91_PIN_PC1, 0);     /* LCDPWR */
 363         at91_set_A_periph(AT91_PIN_PC5, 0);     /* LCDHSYNC */
 364         at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDDOTCK */
 365         at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDDEN */
 366         at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDCC */
 367         at91_set_B_periph(AT91_PIN_PC9, 0);     /* LCDD3 */
 368         at91_set_B_periph(AT91_PIN_PC10, 0);    /* LCDD4 */
 369         at91_set_B_periph(AT91_PIN_PC11, 0);    /* LCDD5 */
 370         at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD6 */
 371         at91_set_B_periph(AT91_PIN_PC13, 0);    /* LCDD7 */
 372         at91_set_B_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
 373         at91_set_B_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
 374         at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
 375         at91_set_B_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
 376         at91_set_B_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
 377         at91_set_B_periph(AT91_PIN_PC20, 0);    /* LCDD18 */
 378         at91_set_B_periph(AT91_PIN_PC21, 0);    /* LCDD19 */
 379         at91_set_B_periph(AT91_PIN_PC22, 0);    /* LCDD20 */
 380         at91_set_B_periph(AT91_PIN_PC23, 0);    /* LCDD21 */
 381         at91_set_B_periph(AT91_PIN_PC24, 0);    /* LCDD22 */
 382         at91_set_B_periph(AT91_PIN_PC25, 0);    /* LCDD23 */
 383
 384         lcdc_data = *data;
 385         platform_device_register(&at91_lcdc_device);
 386 }
 387 #else
 388 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
 389 #endif
 390
 391
 392 /* --------------------------------------------------------------------
 393  *  Timer/Counter block
 394  * -------------------------------------------------------------------- */
 395
 396 #ifdef CONFIG_ATMEL_TCLIB
 397
 398 static struct resource tcb_resources[] = {
 399         [0] = {
 400                 .start  = AT91SAM9RL_BASE_TCB0,
 401                 .end    = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1,
 402                 .flags  = IORESOURCE_MEM,
 403         },
 404         [1] = {
 405                 .start  = AT91SAM9RL_ID_TC0,
 406                 .end    = AT91SAM9RL_ID_TC0,
 407                 .flags  = IORESOURCE_IRQ,
 408         },
 409         [2] = {
 410                 .start  = AT91SAM9RL_ID_TC1,
 411                 .end    = AT91SAM9RL_ID_TC1,
 412                 .flags  = IORESOURCE_IRQ,
 413         },
 414         [3] = {
 415                 .start  = AT91SAM9RL_ID_TC2,
 416                 .end    = AT91SAM9RL_ID_TC2,
 417                 .flags  = IORESOURCE_IRQ,
 418         },
 419 };
 420
 421 static struct platform_device at91sam9rl_tcb_device = {
 422         .name           = "atmel_tcb",
 423         .id             = 0,
 424         .resource       = tcb_resources,
 425         .num_resources  = ARRAY_SIZE(tcb_resources),
 426 };
 427
 428 static void __init at91_add_device_tc(void)
 429 {
 430         /* this chip has a separate clock and irq for each TC channel */
 431         at91_clock_associate("tc0_clk", &at91sam9rl_tcb_device.dev, "t0_clk");
 432         at91_clock_associate("tc1_clk", &at91sam9rl_tcb_device.dev, "t1_clk");
 433         at91_clock_associate("tc2_clk", &at91sam9rl_tcb_device.dev, "t2_clk");
 434         platform_device_register(&at91sam9rl_tcb_device);
 435 }
 436 #else
 437 static void __init at91_add_device_tc(void) { }
 438 #endif
 439
 440
 441 /* --------------------------------------------------------------------
 442  *  RTC
 443  * -------------------------------------------------------------------- */
 444
 445 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
 446 static struct platform_device at91sam9rl_rtc_device = {
 447         .name           = "at91_rtc",
 448         .id             = -1,
 449         .num_resources  = 0,
 450 };
 451
 452 static void __init at91_add_device_rtc(void)
 453 {
 454         platform_device_register(&at91sam9rl_rtc_device);
 455 }
 456 #else
 457 static void __init at91_add_device_rtc(void) {}
 458 #endif
 459
 460
 461 /* --------------------------------------------------------------------
 462  *  RTT
 463  * -------------------------------------------------------------------- */
 464
 465 static struct resource rtt_resources[] = {
 466         {
 467                 .start  = AT91_BASE_SYS + AT91_RTT,
 468                 .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
 469                 .flags  = IORESOURCE_MEM,
 470         }
 471 };
 472
 473 static struct platform_device at91sam9rl_rtt_device = {
 474         .name           = "at91_rtt",
 475         .id             = 0,
 476         .resource       = rtt_resources,
 477         .num_resources  = ARRAY_SIZE(rtt_resources),
 478 };
 479
 480 static void __init at91_add_device_rtt(void)
 481 {
 482         platform_device_register(&at91sam9rl_rtt_device);
 483 }
 484
 485
 486 /* --------------------------------------------------------------------
 487  *  Watchdog
 488  * -------------------------------------------------------------------- */
 489
 490 #if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
 491 static struct platform_device at91sam9rl_wdt_device = {
 492         .name           = "at91_wdt",
 493         .id             = -1,
 494         .num_resources  = 0,
 495 };
 496
 497 static void __init at91_add_device_watchdog(void)
 498 {
 499         platform_device_register(&at91sam9rl_wdt_device);
 500 }
 501 #else
 502 static void __init at91_add_device_watchdog(void) {}
 503 #endif
 504
 505
 506 /* --------------------------------------------------------------------
 507  *  SSC -- Synchronous Serial Controller
 508  * -------------------------------------------------------------------- */
 509
 510 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
 511 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
 512
 513 static struct resource ssc0_resources[] = {
 514         [0] = {
 515                 .start  = AT91SAM9RL_BASE_SSC0,
 516                 .end    = AT91SAM9RL_BASE_SSC0 + SZ_16K - 1,
 517                 .flags  = IORESOURCE_MEM,
 518         },
 519         [1] = {
 520                 .start  = AT91SAM9RL_ID_SSC0,
 521                 .end    = AT91SAM9RL_ID_SSC0,
 522                 .flags  = IORESOURCE_IRQ,
 523         },
 524 };
 525
 526 static struct platform_device at91sam9rl_ssc0_device = {
 527         .name   = "ssc",
 528         .id     = 0,
 529         .dev    = {
 530                 .dma_mask               = &ssc0_dmamask,
 531                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 532         },
 533         .resource       = ssc0_resources,
 534         .num_resources  = ARRAY_SIZE(ssc0_resources),
 535 };
 536
 537 static inline void configure_ssc0_pins(unsigned pins)
 538 {
 539         if (pins & ATMEL_SSC_TF)
 540                 at91_set_A_periph(AT91_PIN_PC0, 1);
 541         if (pins & ATMEL_SSC_TK)
 542                 at91_set_A_periph(AT91_PIN_PC1, 1);
 543         if (pins & ATMEL_SSC_TD)
 544                 at91_set_A_periph(AT91_PIN_PA15, 1);
 545         if (pins & ATMEL_SSC_RD)
 546                 at91_set_A_periph(AT91_PIN_PA16, 1);
 547         if (pins & ATMEL_SSC_RK)
 548                 at91_set_B_periph(AT91_PIN_PA10, 1);
 549         if (pins & ATMEL_SSC_RF)
 550                 at91_set_B_periph(AT91_PIN_PA22, 1);
 551 }
 552
 553 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
 554
 555 static struct resource ssc1_resources[] = {
 556         [0] = {
 557                 .start  = AT91SAM9RL_BASE_SSC1,
 558                 .end    = AT91SAM9RL_BASE_SSC1 + SZ_16K - 1,
 559                 .flags  = IORESOURCE_MEM,
 560         },
 561         [1] = {
 562                 .start  = AT91SAM9RL_ID_SSC1,
 563                 .end    = AT91SAM9RL_ID_SSC1,
 564                 .flags  = IORESOURCE_IRQ,
 565         },
 566 };
 567
 568 static struct platform_device at91sam9rl_ssc1_device = {
 569         .name   = "ssc",
 570         .id     = 1,
 571         .dev    = {
 572                 .dma_mask               = &ssc1_dmamask,
 573                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 574         },
 575         .resource       = ssc1_resources,
 576         .num_resources  = ARRAY_SIZE(ssc1_resources),
 577 };
 578
 579 static inline void configure_ssc1_pins(unsigned pins)
 580 {
 581         if (pins & ATMEL_SSC_TF)
 582                 at91_set_B_periph(AT91_PIN_PA29, 1);
 583         if (pins & ATMEL_SSC_TK)
 584                 at91_set_B_periph(AT91_PIN_PA30, 1);
 585         if (pins & ATMEL_SSC_TD)
 586                 at91_set_B_periph(AT91_PIN_PA13, 1);
 587         if (pins & ATMEL_SSC_RD)
 588                 at91_set_B_periph(AT91_PIN_PA14, 1);
 589         if (pins & ATMEL_SSC_RK)
 590                 at91_set_B_periph(AT91_PIN_PA9, 1);
 591         if (pins & ATMEL_SSC_RF)
 592                 at91_set_B_periph(AT91_PIN_PA8, 1);
 593 }
 594
 595 /*
 596  * SSC controllers are accessed through library code, instead of any
 597  * kind of all-singing/all-dancing driver.  For example one could be
 598  * used by a particular I2S audio codec's driver, while another one
 599  * on the same system might be used by a custom data capture driver.
 600  */
 601 void __init at91_add_device_ssc(unsigned id, unsigned pins)
 602 {
 603         struct platform_device *pdev;
 604
 605         /*
 606          * NOTE: caller is responsible for passing information matching
 607          * "pins" to whatever will be using each particular controller.
 608          */
 609         switch (id) {
 610         case AT91SAM9RL_ID_SSC0:
 611                 pdev = &at91sam9rl_ssc0_device;
 612                 configure_ssc0_pins(pins);
 613                 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
 614                 break;
 615         case AT91SAM9RL_ID_SSC1:
 616                 pdev = &at91sam9rl_ssc1_device;
 617                 configure_ssc1_pins(pins);
 618                 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
 619                 break;
 620         default:
 621                 return;
 622         }
 623
 624         platform_device_register(pdev);
 625 }
 626
 627 #else
 628 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
 629 #endif
 630
 631
 632 /* --------------------------------------------------------------------
 633  *  UART
 634  * -------------------------------------------------------------------- */
 635
 636 #if defined(CONFIG_SERIAL_ATMEL)
 637 static struct resource dbgu_resources[] = {
 638         [0] = {
 639                 .start  = AT91_VA_BASE_SYS + AT91_DBGU,
 640                 .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
 641                 .flags  = IORESOURCE_MEM,
 642         },
 643         [1] = {
 644                 .start  = AT91_ID_SYS,
 645                 .end    = AT91_ID_SYS,
 646                 .flags  = IORESOURCE_IRQ,
 647         },
 648 };
 649
 650 static struct atmel_uart_data dbgu_data = {
 651         .use_dma_tx     = 0,
 652         .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
 653         .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
 654 };
 655
 656 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
 657
 658 static struct platform_device at91sam9rl_dbgu_device = {
 659         .name           = "atmel_usart",
 660         .id             = 0,
 661         .dev            = {
 662                                 .dma_mask               = &dbgu_dmamask,
 663                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 664                                 .platform_data          = &dbgu_data,
 665         },
 666         .resource       = dbgu_resources,
 667         .num_resources  = ARRAY_SIZE(dbgu_resources),
 668 };
 669
 670 static inline void configure_dbgu_pins(void)
 671 {
 672         at91_set_A_periph(AT91_PIN_PA21, 0);            /* DRXD */
 673         at91_set_A_periph(AT91_PIN_PA22, 1);            /* DTXD */
 674 }
 675
 676 static struct resource uart0_resources[] = {
 677         [0] = {
 678                 .start  = AT91SAM9RL_BASE_US0,
 679                 .end    = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
 680                 .flags  = IORESOURCE_MEM,
 681         },
 682         [1] = {
 683                 .start  = AT91SAM9RL_ID_US0,
 684                 .end    = AT91SAM9RL_ID_US0,
 685                 .flags  = IORESOURCE_IRQ,
 686         },
 687 };
 688
 689 static struct atmel_uart_data uart0_data = {
 690         .use_dma_tx     = 1,
 691         .use_dma_rx     = 1,
 692 };
 693
 694 static u64 uart0_dmamask = DMA_BIT_MASK(32);
 695
 696 static struct platform_device at91sam9rl_uart0_device = {
 697         .name           = "atmel_usart",
 698         .id             = 1,
 699         .dev            = {
 700                                 .dma_mask               = &uart0_dmamask,
 701                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 702                                 .platform_data          = &uart0_data,
 703         },
 704         .resource       = uart0_resources,
 705         .num_resources  = ARRAY_SIZE(uart0_resources),
 706 };
 707
 708 static inline void configure_usart0_pins(unsigned pins)
 709 {
 710         at91_set_A_periph(AT91_PIN_PA6, 1);             /* TXD0 */
 711         at91_set_A_periph(AT91_PIN_PA7, 0);             /* RXD0 */
 712
 713         if (pins & ATMEL_UART_RTS)
 714                 at91_set_A_periph(AT91_PIN_PA9, 0);     /* RTS0 */
 715         if (pins & ATMEL_UART_CTS)
 716                 at91_set_A_periph(AT91_PIN_PA10, 0);    /* CTS0 */
 717         if (pins & ATMEL_UART_DSR)
 718                 at91_set_A_periph(AT91_PIN_PD14, 0);    /* DSR0 */
 719         if (pins & ATMEL_UART_DTR)
 720                 at91_set_A_periph(AT91_PIN_PD15, 0);    /* DTR0 */
 721         if (pins & ATMEL_UART_DCD)
 722                 at91_set_A_periph(AT91_PIN_PD16, 0);    /* DCD0 */
 723         if (pins & ATMEL_UART_RI)
 724                 at91_set_A_periph(AT91_PIN_PD17, 0);    /* RI0 */
 725 }
 726
 727 static struct resource uart1_resources[] = {
 728         [0] = {
 729                 .start  = AT91SAM9RL_BASE_US1,
 730                 .end    = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
 731                 .flags  = IORESOURCE_MEM,
 732         },
 733         [1] = {
 734                 .start  = AT91SAM9RL_ID_US1,
 735                 .end    = AT91SAM9RL_ID_US1,
 736                 .flags  = IORESOURCE_IRQ,
 737         },
 738 };
 739
 740 static struct atmel_uart_data uart1_data = {
 741         .use_dma_tx     = 1,
 742         .use_dma_rx     = 1,
 743 };
 744
 745 static u64 uart1_dmamask = DMA_BIT_MASK(32);
 746
 747 static struct platform_device at91sam9rl_uart1_device = {
 748         .name           = "atmel_usart",
 749         .id             = 2,
 750         .dev            = {
 751                                 .dma_mask               = &uart1_dmamask,
 752                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 753                                 .platform_data          = &uart1_data,
 754         },
 755         .resource       = uart1_resources,
 756         .num_resources  = ARRAY_SIZE(uart1_resources),
 757 };
 758
 759 static inline void configure_usart1_pins(unsigned pins)
 760 {
 761         at91_set_A_periph(AT91_PIN_PA11, 1);            /* TXD1 */
 762         at91_set_A_periph(AT91_PIN_PA12, 0);            /* RXD1 */
 763
 764         if (pins & ATMEL_UART_RTS)
 765                 at91_set_B_periph(AT91_PIN_PA18, 0);    /* RTS1 */
 766         if (pins & ATMEL_UART_CTS)
 767                 at91_set_B_periph(AT91_PIN_PA19, 0);    /* CTS1 */
 768 }
 769
 770 static struct resource uart2_resources[] = {
 771         [0] = {
 772                 .start  = AT91SAM9RL_BASE_US2,
 773                 .end    = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
 774                 .flags  = IORESOURCE_MEM,
 775         },
 776         [1] = {
 777                 .start  = AT91SAM9RL_ID_US2,
 778                 .end    = AT91SAM9RL_ID_US2,
 779                 .flags  = IORESOURCE_IRQ,
 780         },
 781 };
 782
 783 static struct atmel_uart_data uart2_data = {
 784         .use_dma_tx     = 1,
 785         .use_dma_rx     = 1,
 786 };
 787
 788 static u64 uart2_dmamask = DMA_BIT_MASK(32);
 789
 790 static struct platform_device at91sam9rl_uart2_device = {
 791         .name           = "atmel_usart",
 792         .id             = 3,
 793         .dev            = {
 794                                 .dma_mask               = &uart2_dmamask,
 795                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 796                                 .platform_data          = &uart2_data,
 797         },
 798         .resource       = uart2_resources,
 799         .num_resources  = ARRAY_SIZE(uart2_resources),
 800 };
 801
 802 static inline void configure_usart2_pins(unsigned pins)
 803 {
 804         at91_set_A_periph(AT91_PIN_PA13, 1);            /* TXD2 */
 805         at91_set_A_periph(AT91_PIN_PA14, 0);            /* RXD2 */
 806
 807         if (pins & ATMEL_UART_RTS)
 808                 at91_set_A_periph(AT91_PIN_PA29, 0);    /* RTS2 */
 809         if (pins & ATMEL_UART_CTS)
 810                 at91_set_A_periph(AT91_PIN_PA30, 0);    /* CTS2 */
 811 }
 812
 813 static struct resource uart3_resources[] = {
 814         [0] = {
 815                 .start  = AT91SAM9RL_BASE_US3,
 816                 .end    = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
 817                 .flags  = IORESOURCE_MEM,
 818         },
 819         [1] = {
 820                 .start  = AT91SAM9RL_ID_US3,
 821                 .end    = AT91SAM9RL_ID_US3,
 822                 .flags  = IORESOURCE_IRQ,
 823         },
 824 };
 825
 826 static struct atmel_uart_data uart3_data = {
 827         .use_dma_tx     = 1,
 828         .use_dma_rx     = 1,
 829 };
 830
 831 static u64 uart3_dmamask = DMA_BIT_MASK(32);
 832
 833 static struct platform_device at91sam9rl_uart3_device = {
 834         .name           = "atmel_usart",
 835         .id             = 4,
 836         .dev            = {
 837                                 .dma_mask               = &uart3_dmamask,
 838                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 839                                 .platform_data          = &uart3_data,
 840         },
 841         .resource       = uart3_resources,
 842         .num_resources  = ARRAY_SIZE(uart3_resources),
 843 };
 844
 845 static inline void configure_usart3_pins(unsigned pins)
 846 {
 847         at91_set_A_periph(AT91_PIN_PB0, 1);             /* TXD3 */
 848         at91_set_A_periph(AT91_PIN_PB1, 0);             /* RXD3 */
 849
 850         if (pins & ATMEL_UART_RTS)
 851                 at91_set_B_periph(AT91_PIN_PD4, 0);     /* RTS3 */
 852         if (pins & ATMEL_UART_CTS)
 853                 at91_set_B_periph(AT91_PIN_PD3, 0);     /* CTS3 */
 854 }
 855
 856 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
 857 struct platform_device *atmel_default_console_device;   /* the serial console device */
 858
 859 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 860 {
 861         struct platform_device *pdev;
 862
 863         switch (id) {
 864                 case 0:         /* DBGU */
 865                         pdev = &at91sam9rl_dbgu_device;
 866                         configure_dbgu_pins();
 867                         at91_clock_associate("mck", &pdev->dev, "usart");
 868                         break;
 869                 case AT91SAM9RL_ID_US0:
 870                         pdev = &at91sam9rl_uart0_device;
 871                         configure_usart0_pins(pins);
 872                         at91_clock_associate("usart0_clk", &pdev->dev, "usart");
 873                         break;
 874                 case AT91SAM9RL_ID_US1:
 875                         pdev = &at91sam9rl_uart1_device;
 876                         configure_usart1_pins(pins);
 877                         at91_clock_associate("usart1_clk", &pdev->dev, "usart");
 878                         break;
 879                 case AT91SAM9RL_ID_US2:
 880                         pdev = &at91sam9rl_uart2_device;
 881                         configure_usart2_pins(pins);
 882                         at91_clock_associate("usart2_clk", &pdev->dev, "usart");
 883                         break;
 884                 case AT91SAM9RL_ID_US3:
 885                         pdev = &at91sam9rl_uart3_device;
 886                         configure_usart3_pins(pins);
 887                         at91_clock_associate("usart3_clk", &pdev->dev, "usart");
 888                         break;
 889                 default:
 890                         return;
 891         }
 892         pdev->id = portnr;              /* update to mapped ID */
 893
 894         if (portnr < ATMEL_MAX_UART)
 895                 at91_uarts[portnr] = pdev;
 896 }
 897
 898 void __init at91_set_serial_console(unsigned portnr)
 899 {
 900         if (portnr < ATMEL_MAX_UART)
 901                 atmel_default_console_device = at91_uarts[portnr];
 902 }
 903
 904 void __init at91_add_device_serial(void)
 905 {
 906         int i;
 907
 908         for (i = 0; i < ATMEL_MAX_UART; i++) {
 909                 if (at91_uarts[i])
 910                         platform_device_register(at91_uarts[i]);
 911         }
 912
 913         if (!atmel_default_console_device)
 914                 printk(KERN_INFO "AT91: No default serial console defined.\n");
 915 }
 916 #else
 917 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
 918 void __init at91_set_serial_console(unsigned portnr) {}
 919 void __init at91_add_device_serial(void) {}
 920 #endif
 921
 922
 923 /* -------------------------------------------------------------------- */
 924
 925 /*
 926  * These devices are always present and don't need any board-specific
 927  * setup.
 928  */
 929 static int __init at91_add_standard_devices(void)
 930 {
 931         at91_add_device_rtc();
 932         at91_add_device_rtt();
 933         at91_add_device_watchdog();
 934         at91_add_device_tc();
 935         return 0;
 936 }
 937
 938 arch_initcall(at91_add_standard_devices);