git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/ath9k/eeprom.h

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef EEPROM_H
  18 #define EEPROM_H
  19
  20 #define AH_USE_EEPROM   0x1
  21
  22 #ifdef __BIG_ENDIAN
  23 #define AR5416_EEPROM_MAGIC 0x5aa5
  24 #else
  25 #define AR5416_EEPROM_MAGIC 0xa55a
  26 #endif
  27
  28 #define CTRY_DEBUG   0x1ff
  29 #define CTRY_DEFAULT 0
  30
  31 #define AR_EEPROM_EEPCAP_COMPRESS_DIS   0x0001
  32 #define AR_EEPROM_EEPCAP_AES_DIS        0x0002
  33 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS  0x0004
  34 #define AR_EEPROM_EEPCAP_BURST_DIS      0x0008
  35 #define AR_EEPROM_EEPCAP_MAXQCU         0x01F0
  36 #define AR_EEPROM_EEPCAP_MAXQCU_S       4
  37 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN  0x0200
  38 #define AR_EEPROM_EEPCAP_KC_ENTRIES     0xF000
  39 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S   12
  40
  41 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND   0x0040
  42 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN    0x0080
  43 #define AR_EEPROM_EEREGCAP_EN_KK_U2         0x0100
  44 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND    0x0200
  45 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD     0x0400
  46 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A    0x0800
  47
  48 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0  0x4000
  49 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
  50
  51 #define AR5416_EEPROM_MAGIC_OFFSET  0x0
  52 #define AR5416_EEPROM_S             2
  53 #define AR5416_EEPROM_OFFSET        0x2000
  54 #define AR5416_EEPROM_MAX           0xae0
  55
  56 #define AR5416_EEPROM_START_ADDR \
  57         (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
  58
  59 #define SD_NO_CTL               0xE0
  60 #define NO_CTL                  0xff
  61 #define CTL_MODE_M              7
  62 #define CTL_11A                 0
  63 #define CTL_11B                 1
  64 #define CTL_11G                 2
  65 #define CTL_2GHT20              5
  66 #define CTL_5GHT20              6
  67 #define CTL_2GHT40              7
  68 #define CTL_5GHT40              8
  69
  70 #define EXT_ADDITIVE (0x8000)
  71 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
  72 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
  73 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
  74
  75 #define SUB_NUM_CTL_MODES_AT_5G_40 2
  76 #define SUB_NUM_CTL_MODES_AT_2G_40 3
  77
  78 #define INCREASE_MAXPOW_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
  79 #define INCREASE_MAXPOW_BY_THREE_CHAIN   10 /* 10*log10(3)*2 */
  80
  81 /*
  82  * For AR9285 and later chipsets, the following bits are not being programmed
  83  * in EEPROM and so need to be enabled always.
  84  *
  85  * Bit 0: en_fcc_mid
  86  * Bit 1: en_jap_mid
  87  * Bit 2: en_fcc_dfs_ht40
  88  * Bit 3: en_jap_ht40
  89  * Bit 4: en_jap_dfs_ht40
  90  */
  91 #define AR9285_RDEXT_DEFAULT    0x1F
  92
  93 #define AR_EEPROM_MAC(i)        (0x1d+(i))
  94 #define ATH9K_POW_SM(_r, _s)    (((_r) & 0x3f) << (_s))
  95 #define FREQ2FBIN(x, y)         ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
  96 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
  97
  98 #define AR_EEPROM_RFSILENT_GPIO_SEL     0x001c
  99 #define AR_EEPROM_RFSILENT_GPIO_SEL_S   2
 100 #define AR_EEPROM_RFSILENT_POLARITY     0x0002
 101 #define AR_EEPROM_RFSILENT_POLARITY_S   1
 102
 103 #define EEP_RFSILENT_ENABLED        0x0001
 104 #define EEP_RFSILENT_ENABLED_S      0
 105 #define EEP_RFSILENT_POLARITY       0x0002
 106 #define EEP_RFSILENT_POLARITY_S     1
 107 #define EEP_RFSILENT_GPIO_SEL       0x001c
 108 #define EEP_RFSILENT_GPIO_SEL_S     2
 109
 110 #define AR5416_OPFLAGS_11A           0x01
 111 #define AR5416_OPFLAGS_11G           0x02
 112 #define AR5416_OPFLAGS_N_5G_HT40     0x04
 113 #define AR5416_OPFLAGS_N_2G_HT40     0x08
 114 #define AR5416_OPFLAGS_N_5G_HT20     0x10
 115 #define AR5416_OPFLAGS_N_2G_HT20     0x20
 116
 117 #define AR5416_EEP_NO_BACK_VER       0x1
 118 #define AR5416_EEP_VER               0xE
 119 #define AR5416_EEP_VER_MINOR_MASK    0x0FFF
 120 #define AR5416_EEP_MINOR_VER_2       0x2
 121 #define AR5416_EEP_MINOR_VER_3       0x3
 122 #define AR5416_EEP_MINOR_VER_7       0x7
 123 #define AR5416_EEP_MINOR_VER_9       0x9
 124 #define AR5416_EEP_MINOR_VER_16      0x10
 125 #define AR5416_EEP_MINOR_VER_17      0x11
 126 #define AR5416_EEP_MINOR_VER_19      0x13
 127 #define AR5416_EEP_MINOR_VER_20      0x14
 128 #define AR5416_EEP_MINOR_VER_22      0x16
 129
 130 #define AR5416_NUM_5G_CAL_PIERS         8
 131 #define AR5416_NUM_2G_CAL_PIERS         4
 132 #define AR5416_NUM_5G_20_TARGET_POWERS  8
 133 #define AR5416_NUM_5G_40_TARGET_POWERS  8
 134 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3
 135 #define AR5416_NUM_2G_20_TARGET_POWERS  4
 136 #define AR5416_NUM_2G_40_TARGET_POWERS  4
 137 #define AR5416_NUM_CTLS                 24
 138 #define AR5416_NUM_BAND_EDGES           8
 139 #define AR5416_NUM_PD_GAINS             4
 140 #define AR5416_PD_GAINS_IN_MASK         4
 141 #define AR5416_PD_GAIN_ICEPTS           5
 142 #define AR5416_EEPROM_MODAL_SPURS       5
 143 #define AR5416_MAX_RATE_POWER           63
 144 #define AR5416_NUM_PDADC_VALUES         128
 145 #define AR5416_BCHAN_UNUSED             0xFF
 146 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
 147 #define AR5416_MAX_CHAINS               3
 148 #define AR5416_PWR_TABLE_OFFSET         -5
 149
 150 /* Rx gain type values */
 151 #define AR5416_EEP_RXGAIN_23DB_BACKOFF     0
 152 #define AR5416_EEP_RXGAIN_13DB_BACKOFF     1
 153 #define AR5416_EEP_RXGAIN_ORIG             2
 154
 155 /* Tx gain type values */
 156 #define AR5416_EEP_TXGAIN_ORIGINAL         0
 157 #define AR5416_EEP_TXGAIN_HIGH_POWER       1
 158
 159 #define AR5416_EEP4K_START_LOC                64
 160 #define AR5416_EEP4K_NUM_2G_CAL_PIERS         3
 161 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
 162 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS  3
 163 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS  3
 164 #define AR5416_EEP4K_NUM_CTLS                 12
 165 #define AR5416_EEP4K_NUM_BAND_EDGES           4
 166 #define AR5416_EEP4K_NUM_PD_GAINS             2
 167 #define AR5416_EEP4K_PD_GAINS_IN_MASK         4
 168 #define AR5416_EEP4K_PD_GAIN_ICEPTS           5
 169 #define AR5416_EEP4K_MAX_CHAINS               1
 170
 171 #define AR9280_TX_GAIN_TABLE_SIZE 22
 172
 173 enum eeprom_param {
 174         EEP_NFTHRESH_5,
 175         EEP_NFTHRESH_2,
 176         EEP_MAC_MSW,
 177         EEP_MAC_MID,
 178         EEP_MAC_LSW,
 179         EEP_REG_0,
 180         EEP_REG_1,
 181         EEP_OP_CAP,
 182         EEP_OP_MODE,
 183         EEP_RF_SILENT,
 184         EEP_OB_5,
 185         EEP_DB_5,
 186         EEP_OB_2,
 187         EEP_DB_2,
 188         EEP_MINOR_REV,
 189         EEP_TX_MASK,
 190         EEP_RX_MASK,
 191         EEP_RXGAIN_TYPE,
 192         EEP_TXGAIN_TYPE,
 193         EEP_OL_PWRCTRL,
 194         EEP_RC_CHAIN_MASK,
 195         EEP_DAC_HPWR_5G,
 196         EEP_FRAC_N_5G
 197 };
 198
 199 enum ar5416_rates {
 200         rate6mb, rate9mb, rate12mb, rate18mb,
 201         rate24mb, rate36mb, rate48mb, rate54mb,
 202         rate1l, rate2l, rate2s, rate5_5l,
 203         rate5_5s, rate11l, rate11s, rateXr,
 204         rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
 205         rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
 206         rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
 207         rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
 208         rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
 209         Ar5416RateSize
 210 };
 211
 212 enum ath9k_hal_freq_band {
 213         ATH9K_HAL_FREQ_BAND_5GHZ = 0,
 214         ATH9K_HAL_FREQ_BAND_2GHZ = 1
 215 };
 216
 217 struct base_eep_header {
 218         u16 length;
 219         u16 checksum;
 220         u16 version;
 221         u8 opCapFlags;
 222         u8 eepMisc;
 223         u16 regDmn[2];
 224         u8 macAddr[6];
 225         u8 rxMask;
 226         u8 txMask;
 227         u16 rfSilent;
 228         u16 blueToothOptions;
 229         u16 deviceCap;
 230         u32 binBuildNumber;
 231         u8 deviceType;
 232         u8 pwdclkind;
 233         u8 futureBase_1[2];
 234         u8 rxGainType;
 235         u8 dacHiPwrMode_5G;
 236         u8 openLoopPwrCntl;
 237         u8 dacLpMode;
 238         u8 txGainType;
 239         u8 rcChainMask;
 240         u8 desiredScaleCCK;
 241         u8 power_table_offset;
 242         u8 frac_n_5g;
 243         u8 futureBase_3[21];
 244 } __packed;
 245
 246 struct base_eep_header_4k {
 247         u16 length;
 248         u16 checksum;
 249         u16 version;
 250         u8 opCapFlags;
 251         u8 eepMisc;
 252         u16 regDmn[2];
 253         u8 macAddr[6];
 254         u8 rxMask;
 255         u8 txMask;
 256         u16 rfSilent;
 257         u16 blueToothOptions;
 258         u16 deviceCap;
 259         u32 binBuildNumber;
 260         u8 deviceType;
 261         u8 futureBase[1];
 262 } __packed;
 263
 264
 265 struct spur_chan {
 266         u16 spurChan;
 267         u8 spurRangeLow;
 268         u8 spurRangeHigh;
 269 } __packed;
 270
 271 struct modal_eep_header {
 272         u32 antCtrlChain[AR5416_MAX_CHAINS];
 273         u32 antCtrlCommon;
 274         u8 antennaGainCh[AR5416_MAX_CHAINS];
 275         u8 switchSettling;
 276         u8 txRxAttenCh[AR5416_MAX_CHAINS];
 277         u8 rxTxMarginCh[AR5416_MAX_CHAINS];
 278         u8 adcDesiredSize;
 279         u8 pgaDesiredSize;
 280         u8 xlnaGainCh[AR5416_MAX_CHAINS];
 281         u8 txEndToXpaOff;
 282         u8 txEndToRxOn;
 283         u8 txFrameToXpaOn;
 284         u8 thresh62;
 285         u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
 286         u8 xpdGain;
 287         u8 xpd;
 288         u8 iqCalICh[AR5416_MAX_CHAINS];
 289         u8 iqCalQCh[AR5416_MAX_CHAINS];
 290         u8 pdGainOverlap;
 291         u8 ob;
 292         u8 db;
 293         u8 xpaBiasLvl;
 294         u8 pwrDecreaseFor2Chain;
 295         u8 pwrDecreaseFor3Chain;
 296         u8 txFrameToDataStart;
 297         u8 txFrameToPaOn;
 298         u8 ht40PowerIncForPdadc;
 299         u8 bswAtten[AR5416_MAX_CHAINS];
 300         u8 bswMargin[AR5416_MAX_CHAINS];
 301         u8 swSettleHt40;
 302         u8 xatten2Db[AR5416_MAX_CHAINS];
 303         u8 xatten2Margin[AR5416_MAX_CHAINS];
 304         u8 ob_ch1;
 305         u8 db_ch1;
 306         u8 useAnt1:1,
 307             force_xpaon:1,
 308             local_bias:1,
 309             femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
 310         u8 miscBits;
 311         u16 xpaBiasLvlFreq[3];
 312         u8 futureModal[6];
 313
 314         struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
 315 } __packed;
 316
 317 struct calDataPerFreqOpLoop {
 318         u8 pwrPdg[2][5];
 319         u8 vpdPdg[2][5];
 320         u8 pcdac[2][5];
 321         u8 empty[2][5];
 322 } __packed;
 323
 324 struct modal_eep_4k_header {
 325         u32  antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
 326         u32  antCtrlCommon;
 327         u8   antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
 328         u8   switchSettling;
 329         u8   txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
 330         u8   rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
 331         u8   adcDesiredSize;
 332         u8   pgaDesiredSize;
 333         u8   xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
 334         u8   txEndToXpaOff;
 335         u8   txEndToRxOn;
 336         u8   txFrameToXpaOn;
 337         u8   thresh62;
 338         u8   noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
 339         u8   xpdGain;
 340         u8   xpd;
 341         u8   iqCalICh[AR5416_EEP4K_MAX_CHAINS];
 342         u8   iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
 343         u8   pdGainOverlap;
 344         u8   ob_01;
 345         u8   db1_01;
 346         u8   xpaBiasLvl;
 347         u8   txFrameToDataStart;
 348         u8   txFrameToPaOn;
 349         u8   ht40PowerIncForPdadc;
 350         u8   bswAtten[AR5416_EEP4K_MAX_CHAINS];
 351         u8   bswMargin[AR5416_EEP4K_MAX_CHAINS];
 352         u8   swSettleHt40;
 353         u8   xatten2Db[AR5416_EEP4K_MAX_CHAINS];
 354         u8   xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
 355         u8   db2_01;
 356         u8   version;
 357         u16  ob_234;
 358         u16  db1_234;
 359         u16  db2_234;
 360         u8   futureModal[4];
 361
 362         struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
 363 } __packed;
 364
 365
 366 struct cal_data_per_freq {
 367         u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 368         u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 369 } __packed;
 370
 371 struct cal_data_per_freq_4k {
 372         u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
 373         u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
 374 } __packed;
 375
 376 struct cal_target_power_leg {
 377         u8 bChannel;
 378         u8 tPow2x[4];
 379 } __packed;
 380
 381 struct cal_target_power_ht {
 382         u8 bChannel;
 383         u8 tPow2x[8];
 384 } __packed;
 385
 386
 387 #ifdef __BIG_ENDIAN_BITFIELD
 388 struct cal_ctl_edges {
 389         u8 bChannel;
 390         u8 flag:2, tPower:6;
 391 } __packed;
 392 #else
 393 struct cal_ctl_edges {
 394         u8 bChannel;
 395         u8 tPower:6, flag:2;
 396 } __packed;
 397 #endif
 398
 399 struct cal_ctl_data {
 400         struct cal_ctl_edges
 401         ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
 402 } __packed;
 403
 404 struct cal_ctl_data_4k {
 405         struct cal_ctl_edges
 406         ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
 407 } __packed;
 408
 409 struct ar5416_eeprom_def {
 410         struct base_eep_header baseEepHeader;
 411         u8 custData[64];
 412         struct modal_eep_header modalHeader[2];
 413         u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
 414         u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
 415         struct cal_data_per_freq
 416          calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
 417         struct cal_data_per_freq
 418          calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
 419         struct cal_target_power_leg
 420          calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
 421         struct cal_target_power_ht
 422          calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
 423         struct cal_target_power_ht
 424          calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
 425         struct cal_target_power_leg
 426          calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
 427         struct cal_target_power_leg
 428          calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
 429         struct cal_target_power_ht
 430          calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
 431         struct cal_target_power_ht
 432          calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
 433         u8 ctlIndex[AR5416_NUM_CTLS];
 434         struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
 435         u8 padding;
 436 } __packed;
 437
 438 struct ar5416_eeprom_4k {
 439         struct base_eep_header_4k baseEepHeader;
 440         u8 custData[20];
 441         struct modal_eep_4k_header modalHeader;
 442         u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
 443         struct cal_data_per_freq_4k
 444         calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
 445         struct cal_target_power_leg
 446         calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
 447         struct cal_target_power_leg
 448         calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
 449         struct cal_target_power_ht
 450         calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
 451         struct cal_target_power_ht
 452         calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
 453         u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
 454         struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
 455         u8 padding;
 456 } __packed;
 457
 458 enum reg_ext_bitmap {
 459         REG_EXT_JAPAN_MIDBAND = 1,
 460         REG_EXT_FCC_DFS_HT40 = 2,
 461         REG_EXT_JAPAN_NONDFS_HT40 = 3,
 462         REG_EXT_JAPAN_DFS_HT40 = 4
 463 };
 464
 465 struct ath9k_country_entry {
 466         u16 countryCode;
 467         u16 regDmnEnum;
 468         u16 regDmn5G;
 469         u16 regDmn2G;
 470         u8 isMultidomain;
 471         u8 iso[3];
 472 };
 473
 474 enum ath9k_eep_map {
 475         EEP_MAP_DEFAULT = 0x0,
 476         EEP_MAP_4KBITS,
 477         EEP_MAP_MAX
 478 };
 479
 480 struct eeprom_ops {
 481         int (*check_eeprom)(struct ath_hw *hw);
 482         u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
 483         bool (*fill_eeprom)(struct ath_hw *hw);
 484         int (*get_eeprom_ver)(struct ath_hw *hw);
 485         int (*get_eeprom_rev)(struct ath_hw *hw);
 486         u8 (*get_num_ant_config)(struct ath_hw *hw, enum ieee80211_band band);
 487         u16 (*get_eeprom_antenna_cfg)(struct ath_hw *hw,
 488                                       struct ath9k_channel *chan);
 489         bool (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
 490         void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
 491         int (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
 492                            u16 cfgCtl, u8 twiceAntennaReduction,
 493                            u8 twiceMaxRegulatoryPower, u8 powerLimit);
 494         u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
 495 };
 496
 497 #define ar5416_get_ntxchains(_txchainmask)                      \
 498         (((_txchainmask >> 2) & 1) +                            \
 499          ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
 500
 501 int ath9k_hw_eeprom_attach(struct ath_hw *ah);
 502
 503 #endif /* EEPROM_H */