git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "ath9k.h"
  21 #include "initvals.h"
  22
  23 static int btcoex_enable;
  24 module_param(btcoex_enable, bool, 0);
  25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
  26
  27 #define ATH9K_CLOCK_RATE_CCK            22
  28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  30
  31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
  33                               enum ath9k_ht_macmode macmode);
  34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  35                               struct ar5416_eeprom_def *pEepData,
  36                               u32 reg, u32 value);
  37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  39
  40 /********************/
  41 /* Helper Functions */
  42 /********************/
  43
  44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
  45 {
  46         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  47
  48         if (!ah->curchan) /* should really check for CCK instead */
  49                 return clks / ATH9K_CLOCK_RATE_CCK;
  50         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  51                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
  52
  53         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
  54 }
  55
  56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
  57 {
  58         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  59
  60         if (conf_is_ht40(conf))
  61                 return ath9k_hw_mac_usec(ah, clks) / 2;
  62         else
  63                 return ath9k_hw_mac_usec(ah, clks);
  64 }
  65
  66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  67 {
  68         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  69
  70         if (!ah->curchan) /* should really check for CCK instead */
  71                 return usecs *ATH9K_CLOCK_RATE_CCK;
  72         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  73                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  74         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  75 }
  76
  77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  78 {
  79         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  80
  81         if (conf_is_ht40(conf))
  82                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  83         else
  84                 return ath9k_hw_mac_clks(ah, usecs);
  85 }
  86
  87 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
  88 {
  89         int i;
  90
  91         BUG_ON(timeout < AH_TIME_QUANTUM);
  92
  93         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
  94                 if ((REG_READ(ah, reg) & mask) == val)
  95                         return true;
  96
  97                 udelay(AH_TIME_QUANTUM);
  98         }
  99
 100         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 101                 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 102                 timeout, reg, REG_READ(ah, reg), mask, val);
 103
 104         return false;
 105 }
 106
 107 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 108 {
 109         u32 retval;
 110         int i;
 111
 112         for (i = 0, retval = 0; i < n; i++) {
 113                 retval = (retval << 1) | (val & 1);
 114                 val >>= 1;
 115         }
 116         return retval;
 117 }
 118
 119 bool ath9k_get_channel_edges(struct ath_hw *ah,
 120                              u16 flags, u16 *low,
 121                              u16 *high)
 122 {
 123         struct ath9k_hw_capabilities *pCap = &ah->caps;
 124
 125         if (flags & CHANNEL_5GHZ) {
 126                 *low = pCap->low_5ghz_chan;
 127                 *high = pCap->high_5ghz_chan;
 128                 return true;
 129         }
 130         if ((flags & CHANNEL_2GHZ)) {
 131                 *low = pCap->low_2ghz_chan;
 132                 *high = pCap->high_2ghz_chan;
 133                 return true;
 134         }
 135         return false;
 136 }
 137
 138 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 139                            struct ath_rate_table *rates,
 140                            u32 frameLen, u16 rateix,
 141                            bool shortPreamble)
 142 {
 143         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 144         u32 kbps;
 145
 146         kbps = rates->info[rateix].ratekbps;
 147
 148         if (kbps == 0)
 149                 return 0;
 150
 151         switch (rates->info[rateix].phy) {
 152         case WLAN_RC_PHY_CCK:
 153                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 154                 if (shortPreamble && rates->info[rateix].short_preamble)
 155                         phyTime >>= 1;
 156                 numBits = frameLen << 3;
 157                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 158                 break;
 159         case WLAN_RC_PHY_OFDM:
 160                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 161                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 162                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 163                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 164                         txTime = OFDM_SIFS_TIME_QUARTER
 165                                 + OFDM_PREAMBLE_TIME_QUARTER
 166                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 167                 } else if (ah->curchan &&
 168                            IS_CHAN_HALF_RATE(ah->curchan)) {
 169                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 170                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 171                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 172                         txTime = OFDM_SIFS_TIME_HALF +
 173                                 OFDM_PREAMBLE_TIME_HALF
 174                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 175                 } else {
 176                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 177                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 178                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 179                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 180                                 + (numSymbols * OFDM_SYMBOL_TIME);
 181                 }
 182                 break;
 183         default:
 184                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 185                         "Unknown phy %u (rate ix %u)\n",
 186                         rates->info[rateix].phy, rateix);
 187                 txTime = 0;
 188                 break;
 189         }
 190
 191         return txTime;
 192 }
 193
 194 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 195                                   struct ath9k_channel *chan,
 196                                   struct chan_centers *centers)
 197 {
 198         int8_t extoff;
 199
 200         if (!IS_CHAN_HT40(chan)) {
 201                 centers->ctl_center = centers->ext_center =
 202                         centers->synth_center = chan->channel;
 203                 return;
 204         }
 205
 206         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 207             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 208                 centers->synth_center =
 209                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 210                 extoff = 1;
 211         } else {
 212                 centers->synth_center =
 213                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 214                 extoff = -1;
 215         }
 216
 217         centers->ctl_center =
 218                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 219         centers->ext_center =
 220                 centers->synth_center + (extoff *
 221                          ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
 222                           HT40_CHANNEL_CENTER_SHIFT : 15));
 223 }
 224
 225 /******************/
 226 /* Chip Revisions */
 227 /******************/
 228
 229 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 230 {
 231         u32 val;
 232
 233         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 234
 235         if (val == 0xFF) {
 236                 val = REG_READ(ah, AR_SREV);
 237                 ah->hw_version.macVersion =
 238                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 239                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 240                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 241         } else {
 242                 if (!AR_SREV_9100(ah))
 243                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 244
 245                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 246
 247                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 248                         ah->is_pciexpress = true;
 249         }
 250 }
 251
 252 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 253 {
 254         u32 val;
 255         int i;
 256
 257         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 258
 259         for (i = 0; i < 8; i++)
 260                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 261         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 262         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 263
 264         return ath9k_hw_reverse_bits(val, 8);
 265 }
 266
 267 /************************************/
 268 /* HW Attach, Detach, Init Routines */
 269 /************************************/
 270
 271 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 272 {
 273         if (AR_SREV_9100(ah))
 274                 return;
 275
 276         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 277         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 278         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 279         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 280         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 281         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 282         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 283         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 284         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 285
 286         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 287 }
 288
 289 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 290 {
 291         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 292         u32 regHold[2];
 293         u32 patternData[4] = { 0x55555555,
 294                                0xaaaaaaaa,
 295                                0x66666666,
 296                                0x99999999 };
 297         int i, j;
 298
 299         for (i = 0; i < 2; i++) {
 300                 u32 addr = regAddr[i];
 301                 u32 wrData, rdData;
 302
 303                 regHold[i] = REG_READ(ah, addr);
 304                 for (j = 0; j < 0x100; j++) {
 305                         wrData = (j << 16) | j;
 306                         REG_WRITE(ah, addr, wrData);
 307                         rdData = REG_READ(ah, addr);
 308                         if (rdData != wrData) {
 309                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 310                                         "address test failed "
 311                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 312                                         addr, wrData, rdData);
 313                                 return false;
 314                         }
 315                 }
 316                 for (j = 0; j < 4; j++) {
 317                         wrData = patternData[j];
 318                         REG_WRITE(ah, addr, wrData);
 319                         rdData = REG_READ(ah, addr);
 320                         if (wrData != rdData) {
 321                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 322                                         "address test failed "
 323                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 324                                         addr, wrData, rdData);
 325                                 return false;
 326                         }
 327                 }
 328                 REG_WRITE(ah, regAddr[i], regHold[i]);
 329         }
 330         udelay(100);
 331
 332         return true;
 333 }
 334
 335 static const char *ath9k_hw_devname(u16 devid)
 336 {
 337         switch (devid) {
 338         case AR5416_DEVID_PCI:
 339                 return "Atheros 5416";
 340         case AR5416_DEVID_PCIE:
 341                 return "Atheros 5418";
 342         case AR9160_DEVID_PCI:
 343                 return "Atheros 9160";
 344         case AR5416_AR9100_DEVID:
 345                 return "Atheros 9100";
 346         case AR9280_DEVID_PCI:
 347         case AR9280_DEVID_PCIE:
 348                 return "Atheros 9280";
 349         case AR9285_DEVID_PCIE:
 350                 return "Atheros 9285";
 351         }
 352
 353         return NULL;
 354 }
 355
 356 static void ath9k_hw_set_defaults(struct ath_hw *ah)
 357 {
 358         int i;
 359
 360         ah->config.dma_beacon_response_time = 2;
 361         ah->config.sw_beacon_response_time = 10;
 362         ah->config.additional_swba_backoff = 0;
 363         ah->config.ack_6mb = 0x0;
 364         ah->config.cwm_ignore_extcca = 0;
 365         ah->config.pcie_powersave_enable = 0;
 366         ah->config.pcie_l1skp_enable = 0;
 367         ah->config.pcie_clock_req = 0;
 368         ah->config.pcie_power_reset = 0x100;
 369         ah->config.pcie_restore = 0;
 370         ah->config.pcie_waen = 0;
 371         ah->config.analog_shiftreg = 1;
 372         ah->config.ht_enable = 1;
 373         ah->config.ofdm_trig_low = 200;
 374         ah->config.ofdm_trig_high = 500;
 375         ah->config.cck_trig_high = 200;
 376         ah->config.cck_trig_low = 100;
 377         ah->config.enable_ani = 1;
 378         ah->config.noise_immunity_level = 4;
 379         ah->config.ofdm_weaksignal_det = 1;
 380         ah->config.cck_weaksignal_thr = 0;
 381         ah->config.spur_immunity_level = 2;
 382         ah->config.firstep_level = 0;
 383         ah->config.rssi_thr_high = 40;
 384         ah->config.rssi_thr_low = 7;
 385         ah->config.diversity_control = 0;
 386         ah->config.antenna_switch_swap = 0;
 387
 388         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 389                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 390                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 391         }
 392
 393         ah->config.intr_mitigation = 1;
 394 }
 395
 396 static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
 397                                         int *status)
 398 {
 399         struct ath_hw *ah;
 400
 401         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
 402         if (ah == NULL) {
 403                 DPRINTF(sc, ATH_DBG_FATAL,
 404                         "Cannot allocate memory for state block\n");
 405                 *status = -ENOMEM;
 406                 return NULL;
 407         }
 408
 409         ah->ah_sc = sc;
 410         ah->hw_version.magic = AR5416_MAGIC;
 411         ah->regulatory.country_code = CTRY_DEFAULT;
 412         ah->hw_version.devid = devid;
 413         ah->hw_version.subvendorid = 0;
 414
 415         ah->ah_flags = 0;
 416         if ((devid == AR5416_AR9100_DEVID))
 417                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 418         if (!AR_SREV_9100(ah))
 419                 ah->ah_flags = AH_USE_EEPROM;
 420
 421         ah->regulatory.power_limit = MAX_RATE_POWER;
 422         ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
 423         ah->atim_window = 0;
 424         ah->diversity_control = ah->config.diversity_control;
 425         ah->antenna_switch_swap =
 426                 ah->config.antenna_switch_swap;
 427         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 428         ah->beacon_interval = 100;
 429         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 430         ah->slottime = (u32) -1;
 431         ah->acktimeout = (u32) -1;
 432         ah->ctstimeout = (u32) -1;
 433         ah->globaltxtimeout = (u32) -1;
 434
 435         ah->gbeacon_rate = 0;
 436
 437         return ah;
 438 }
 439
 440 static int ath9k_hw_rfattach(struct ath_hw *ah)
 441 {
 442         bool rfStatus = false;
 443         int ecode = 0;
 444
 445         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 446         if (!rfStatus) {
 447                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 448                         "RF setup failed, status %u\n", ecode);
 449                 return ecode;
 450         }
 451
 452         return 0;
 453 }
 454
 455 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 456 {
 457         u32 val;
 458
 459         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 460
 461         val = ath9k_hw_get_radiorev(ah);
 462         switch (val & AR_RADIO_SREV_MAJOR) {
 463         case 0:
 464                 val = AR_RAD5133_SREV_MAJOR;
 465                 break;
 466         case AR_RAD5133_SREV_MAJOR:
 467         case AR_RAD5122_SREV_MAJOR:
 468         case AR_RAD2133_SREV_MAJOR:
 469         case AR_RAD2122_SREV_MAJOR:
 470                 break;
 471         default:
 472                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 473                         "5G Radio Chip Rev 0x%02X is not "
 474                         "supported by this driver\n",
 475                         ah->hw_version.analog5GhzRev);
 476                 return -EOPNOTSUPP;
 477         }
 478
 479         ah->hw_version.analog5GhzRev = val;
 480
 481         return 0;
 482 }
 483
 484 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 485 {
 486         u32 sum;
 487         int i;
 488         u16 eeval;
 489
 490         sum = 0;
 491         for (i = 0; i < 3; i++) {
 492                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 493                 sum += eeval;
 494                 ah->macaddr[2 * i] = eeval >> 8;
 495                 ah->macaddr[2 * i + 1] = eeval & 0xff;
 496         }
 497         if (sum == 0 || sum == 0xffff * 3) {
 498                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 499                         "mac address read failed: %pM\n",
 500                         ah->macaddr);
 501                 return -EADDRNOTAVAIL;
 502         }
 503
 504         return 0;
 505 }
 506
 507 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 508 {
 509         u32 rxgain_type;
 510
 511         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 512                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 513
 514                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 515                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 516                         ar9280Modes_backoff_13db_rxgain_9280_2,
 517                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 518                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 519                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 520                         ar9280Modes_backoff_23db_rxgain_9280_2,
 521                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 522                 else
 523                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 524                         ar9280Modes_original_rxgain_9280_2,
 525                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 526         } else {
 527                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 528                         ar9280Modes_original_rxgain_9280_2,
 529                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 530         }
 531 }
 532
 533 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 534 {
 535         u32 txgain_type;
 536
 537         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 538                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 539
 540                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 541                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 542                         ar9280Modes_high_power_tx_gain_9280_2,
 543                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 544                 else
 545                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 546                         ar9280Modes_original_tx_gain_9280_2,
 547                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 548         } else {
 549                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 550                 ar9280Modes_original_tx_gain_9280_2,
 551                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 552         }
 553 }
 554
 555 static int ath9k_hw_post_attach(struct ath_hw *ah)
 556 {
 557         int ecode;
 558
 559         if (!ath9k_hw_chip_test(ah)) {
 560                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 561                         "hardware self-test failed\n");
 562                 return -ENODEV;
 563         }
 564
 565         ecode = ath9k_hw_rf_claim(ah);
 566         if (ecode != 0)
 567                 return ecode;
 568
 569         ecode = ath9k_hw_eeprom_attach(ah);
 570         if (ecode != 0)
 571                 return ecode;
 572         ecode = ath9k_hw_rfattach(ah);
 573         if (ecode != 0)
 574                 return ecode;
 575
 576         if (!AR_SREV_9100(ah)) {
 577                 ath9k_hw_ani_setup(ah);
 578                 ath9k_hw_ani_attach(ah);
 579         }
 580
 581         return 0;
 582 }
 583
 584 static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
 585                                          int *status)
 586 {
 587         struct ath_hw *ah;
 588         int ecode;
 589         u32 i, j;
 590
 591         ah = ath9k_hw_newstate(devid, sc, status);
 592         if (ah == NULL)
 593                 return NULL;
 594
 595         ath9k_hw_set_defaults(ah);
 596
 597         if (ah->config.intr_mitigation != 0)
 598                 ah->intr_mitigation = true;
 599
 600         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 601                 DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n");
 602                 ecode = -EIO;
 603                 goto bad;
 604         }
 605
 606         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 607                 DPRINTF(sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
 608                 ecode = -EIO;
 609                 goto bad;
 610         }
 611
 612         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 613                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) {
 614                         ah->config.serialize_regmode =
 615                                 SER_REG_MODE_ON;
 616                 } else {
 617                         ah->config.serialize_regmode =
 618                                 SER_REG_MODE_OFF;
 619                 }
 620         }
 621
 622         DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
 623                 ah->config.serialize_regmode);
 624
 625         if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
 626             (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
 627             (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
 628             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
 629                 DPRINTF(sc, ATH_DBG_RESET,
 630                         "Mac Chip Rev 0x%02x.%x is not supported by "
 631                         "this driver\n", ah->hw_version.macVersion,
 632                         ah->hw_version.macRev);
 633                 ecode = -EOPNOTSUPP;
 634                 goto bad;
 635         }
 636
 637         if (AR_SREV_9100(ah)) {
 638                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 639                 ah->supp_cals = IQ_MISMATCH_CAL;
 640                 ah->is_pciexpress = false;
 641         }
 642         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 643
 644         if (AR_SREV_9160_10_OR_LATER(ah)) {
 645                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 646                         ah->iq_caldata.calData = &iq_cal_single_sample;
 647                         ah->adcgain_caldata.calData =
 648                                 &adc_gain_cal_single_sample;
 649                         ah->adcdc_caldata.calData =
 650                                 &adc_dc_cal_single_sample;
 651                         ah->adcdc_calinitdata.calData =
 652                                 &adc_init_dc_cal;
 653                 } else {
 654                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 655                         ah->adcgain_caldata.calData =
 656                                 &adc_gain_cal_multi_sample;
 657                         ah->adcdc_caldata.calData =
 658                                 &adc_dc_cal_multi_sample;
 659                         ah->adcdc_calinitdata.calData =
 660                                 &adc_init_dc_cal;
 661                 }
 662                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 663         }
 664
 665         if (AR_SREV_9160(ah)) {
 666                 ah->config.enable_ani = 1;
 667                 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
 668                                         ATH9K_ANI_FIRSTEP_LEVEL);
 669         } else {
 670                 ah->ani_function = ATH9K_ANI_ALL;
 671                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 672                         ah->ani_function &=     ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 673                 }
 674         }
 675
 676         DPRINTF(sc, ATH_DBG_RESET,
 677                 "This Mac Chip Rev 0x%02x.%x is \n",
 678                 ah->hw_version.macVersion, ah->hw_version.macRev);
 679
 680         if (AR_SREV_9285_12_OR_LATER(ah)) {
 681                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 682                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 683                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 684                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 685
 686                 if (ah->config.pcie_clock_req) {
 687                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 688                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 689                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 690                 } else {
 691                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 692                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 693                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 694                                   2);
 695                 }
 696         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 697                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 698                                ARRAY_SIZE(ar9285Modes_9285), 6);
 699                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 700                                ARRAY_SIZE(ar9285Common_9285), 2);
 701
 702                 if (ah->config.pcie_clock_req) {
 703                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 704                         ar9285PciePhy_clkreq_off_L1_9285,
 705                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 706                 } else {
 707                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 708                         ar9285PciePhy_clkreq_always_on_L1_9285,
 709                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 710                 }
 711         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 712                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 713                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 714                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 715                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 716
 717                 if (ah->config.pcie_clock_req) {
 718                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 719                                ar9280PciePhy_clkreq_off_L1_9280,
 720                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 721                 } else {
 722                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 723                                ar9280PciePhy_clkreq_always_on_L1_9280,
 724                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 725                 }
 726                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 727                                ar9280Modes_fast_clock_9280_2,
 728                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 729         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 730                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 731                                ARRAY_SIZE(ar9280Modes_9280), 6);
 732                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 733                                ARRAY_SIZE(ar9280Common_9280), 2);
 734         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 735                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 736                                ARRAY_SIZE(ar5416Modes_9160), 6);
 737                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 738                                ARRAY_SIZE(ar5416Common_9160), 2);
 739                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 740                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 741                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 742                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 743                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 744                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 745                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 746                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 747                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 748                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 749                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 750                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 751                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 752                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 753                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 754                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 755                 if (AR_SREV_9160_11(ah)) {
 756                         INIT_INI_ARRAY(&ah->iniAddac,
 757                                        ar5416Addac_91601_1,
 758                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 759                 } else {
 760                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 761                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 762                 }
 763         } else if (AR_SREV_9100_OR_LATER(ah)) {
 764                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 765                                ARRAY_SIZE(ar5416Modes_9100), 6);
 766                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 767                                ARRAY_SIZE(ar5416Common_9100), 2);
 768                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 769                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 770                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 771                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 772                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 773                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 774                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 775                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 776                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 777                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 778                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 779                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 780                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 781                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 782                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 783                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 784                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 785                                ARRAY_SIZE(ar5416Addac_9100), 2);
 786         } else {
 787                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 788                                ARRAY_SIZE(ar5416Modes), 6);
 789                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 790                                ARRAY_SIZE(ar5416Common), 2);
 791                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 792                                ARRAY_SIZE(ar5416Bank0), 2);
 793                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 794                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 795                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 796                                ARRAY_SIZE(ar5416Bank1), 2);
 797                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 798                                ARRAY_SIZE(ar5416Bank2), 2);
 799                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 800                                ARRAY_SIZE(ar5416Bank3), 3);
 801                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 802                                ARRAY_SIZE(ar5416Bank6), 3);
 803                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 804                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 805                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 806                                ARRAY_SIZE(ar5416Bank7), 2);
 807                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 808                                ARRAY_SIZE(ar5416Addac), 2);
 809         }
 810
 811         if (ah->is_pciexpress)
 812                 ath9k_hw_configpcipowersave(ah, 0);
 813         else
 814                 ath9k_hw_disablepcie(ah);
 815
 816         ecode = ath9k_hw_post_attach(ah);
 817         if (ecode != 0)
 818                 goto bad;
 819
 820         /* rxgain table */
 821         if (AR_SREV_9280_20(ah))
 822                 ath9k_hw_init_rxgain_ini(ah);
 823
 824         /* txgain table */
 825         if (AR_SREV_9280_20(ah))
 826                 ath9k_hw_init_txgain_ini(ah);
 827
 828         if (!ath9k_hw_fill_cap_info(ah)) {
 829                 DPRINTF(sc, ATH_DBG_RESET, "failed ath9k_hw_fill_cap_info\n");
 830                 ecode = -EINVAL;
 831                 goto bad;
 832         }
 833
 834         if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
 835             test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
 836
 837                 /* EEPROM Fixup */
 838                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
 839                         u32 reg = INI_RA(&ah->iniModes, i, 0);
 840
 841                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
 842                                 u32 val = INI_RA(&ah->iniModes, i, j);
 843
 844                                 INI_RA(&ah->iniModes, i, j) =
 845                                         ath9k_hw_ini_fixup(ah,
 846                                                            &ah->eeprom.def,
 847                                                            reg, val);
 848                         }
 849                 }
 850         }
 851
 852         ecode = ath9k_hw_init_macaddr(ah);
 853         if (ecode != 0) {
 854                 DPRINTF(sc, ATH_DBG_RESET,
 855                         "failed initializing mac address\n");
 856                 goto bad;
 857         }
 858
 859         if (AR_SREV_9285(ah))
 860                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 861         else
 862                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 863
 864         ath9k_init_nfcal_hist_buffer(ah);
 865
 866         return ah;
 867 bad:
 868         if (ah)
 869                 ath9k_hw_detach(ah);
 870         if (status)
 871                 *status = ecode;
 872
 873         return NULL;
 874 }
 875
 876 static void ath9k_hw_init_bb(struct ath_hw *ah,
 877                              struct ath9k_channel *chan)
 878 {
 879         u32 synthDelay;
 880
 881         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 882         if (IS_CHAN_B(chan))
 883                 synthDelay = (4 * synthDelay) / 22;
 884         else
 885                 synthDelay /= 10;
 886
 887         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 888
 889         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 890 }
 891
 892 static void ath9k_hw_init_qos(struct ath_hw *ah)
 893 {
 894         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 895         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 896
 897         REG_WRITE(ah, AR_QOS_NO_ACK,
 898                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 899                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 900                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 901
 902         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 903         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 904         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 905         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 906         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 907 }
 908
 909 static void ath9k_hw_init_pll(struct ath_hw *ah,
 910                               struct ath9k_channel *chan)
 911 {
 912         u32 pll;
 913
 914         if (AR_SREV_9100(ah)) {
 915                 if (chan && IS_CHAN_5GHZ(chan))
 916                         pll = 0x1450;
 917                 else
 918                         pll = 0x1458;
 919         } else {
 920                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 921                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 922
 923                         if (chan && IS_CHAN_HALF_RATE(chan))
 924                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 925                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 926                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 927
 928                         if (chan && IS_CHAN_5GHZ(chan)) {
 929                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
 930
 931
 932                                 if (AR_SREV_9280_20(ah)) {
 933                                         if (((chan->channel % 20) == 0)
 934                                             || ((chan->channel % 10) == 0))
 935                                                 pll = 0x2850;
 936                                         else
 937                                                 pll = 0x142c;
 938                                 }
 939                         } else {
 940                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
 941                         }
 942
 943                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 944
 945                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 946
 947                         if (chan && IS_CHAN_HALF_RATE(chan))
 948                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 949                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 950                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 951
 952                         if (chan && IS_CHAN_5GHZ(chan))
 953                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
 954                         else
 955                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
 956                 } else {
 957                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
 958
 959                         if (chan && IS_CHAN_HALF_RATE(chan))
 960                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
 961                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 962                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
 963
 964                         if (chan && IS_CHAN_5GHZ(chan))
 965                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
 966                         else
 967                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
 968                 }
 969         }
 970         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 971
 972         udelay(RTC_PLL_SETTLE_DELAY);
 973
 974         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
 975 }
 976
 977 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
 978 {
 979         int rx_chainmask, tx_chainmask;
 980
 981         rx_chainmask = ah->rxchainmask;
 982         tx_chainmask = ah->txchainmask;
 983
 984         switch (rx_chainmask) {
 985         case 0x5:
 986                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 987                             AR_PHY_SWAP_ALT_CHAIN);
 988         case 0x3:
 989                 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
 990                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
 991                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
 992                         break;
 993                 }
 994         case 0x1:
 995         case 0x2:
 996         case 0x7:
 997                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
 998                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
 999                 break;
1000         default:
1001                 break;
1002         }
1003
1004         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1005         if (tx_chainmask == 0x5) {
1006                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1007                             AR_PHY_SWAP_ALT_CHAIN);
1008         }
1009         if (AR_SREV_9100(ah))
1010                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1011                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1012 }
1013
1014 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1015                                           enum nl80211_iftype opmode)
1016 {
1017         ah->mask_reg = AR_IMR_TXERR |
1018                 AR_IMR_TXURN |
1019                 AR_IMR_RXERR |
1020                 AR_IMR_RXORN |
1021                 AR_IMR_BCNMISC;
1022
1023         if (ah->intr_mitigation)
1024                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1025         else
1026                 ah->mask_reg |= AR_IMR_RXOK;
1027
1028         ah->mask_reg |= AR_IMR_TXOK;
1029
1030         if (opmode == NL80211_IFTYPE_AP)
1031                 ah->mask_reg |= AR_IMR_MIB;
1032
1033         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1034         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1035
1036         if (!AR_SREV_9100(ah)) {
1037                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1038                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1039                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1040         }
1041 }
1042
1043 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1044 {
1045         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1046                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1047                 ah->acktimeout = (u32) -1;
1048                 return false;
1049         } else {
1050                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1051                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1052                 ah->acktimeout = us;
1053                 return true;
1054         }
1055 }
1056
1057 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1058 {
1059         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1060                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1061                 ah->ctstimeout = (u32) -1;
1062                 return false;
1063         } else {
1064                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1065                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1066                 ah->ctstimeout = us;
1067                 return true;
1068         }
1069 }
1070
1071 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1072 {
1073         if (tu > 0xFFFF) {
1074                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1075                         "bad global tx timeout %u\n", tu);
1076                 ah->globaltxtimeout = (u32) -1;
1077                 return false;
1078         } else {
1079                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1080                 ah->globaltxtimeout = tu;
1081                 return true;
1082         }
1083 }
1084
1085 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1086 {
1087         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1088                 ah->misc_mode);
1089
1090         if (ah->misc_mode != 0)
1091                 REG_WRITE(ah, AR_PCU_MISC,
1092                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1093         if (ah->slottime != (u32) -1)
1094                 ath9k_hw_setslottime(ah, ah->slottime);
1095         if (ah->acktimeout != (u32) -1)
1096                 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1097         if (ah->ctstimeout != (u32) -1)
1098                 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1099         if (ah->globaltxtimeout != (u32) -1)
1100                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1101 }
1102
1103 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1104 {
1105         return vendorid == ATHEROS_VENDOR_ID ?
1106                 ath9k_hw_devname(devid) : NULL;
1107 }
1108
1109 void ath9k_hw_detach(struct ath_hw *ah)
1110 {
1111         if (!AR_SREV_9100(ah))
1112                 ath9k_hw_ani_detach(ah);
1113
1114         ath9k_hw_rfdetach(ah);
1115         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1116         kfree(ah);
1117 }
1118
1119 struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1120 {
1121         struct ath_hw *ah = NULL;
1122
1123         switch (devid) {
1124         case AR5416_DEVID_PCI:
1125         case AR5416_DEVID_PCIE:
1126         case AR5416_AR9100_DEVID:
1127         case AR9160_DEVID_PCI:
1128         case AR9280_DEVID_PCI:
1129         case AR9280_DEVID_PCIE:
1130         case AR9285_DEVID_PCIE:
1131                 ah = ath9k_hw_do_attach(devid, sc, error);
1132                 break;
1133         default:
1134                 *error = -ENXIO;
1135                 break;
1136         }
1137
1138         return ah;
1139 }
1140
1141 /*******/
1142 /* INI */
1143 /*******/
1144
1145 static void ath9k_hw_override_ini(struct ath_hw *ah,
1146                                   struct ath9k_channel *chan)
1147 {
1148         /*
1149          * Set the RX_ABORT and RX_DIS and clear if off only after
1150          * RXE is set for MAC. This prevents frames with corrupted
1151          * descriptor status.
1152          */
1153         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1154
1155
1156         if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1157             AR_SREV_9280_10_OR_LATER(ah))
1158                 return;
1159
1160         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1161 }
1162
1163 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1164                               struct ar5416_eeprom_def *pEepData,
1165                               u32 reg, u32 value)
1166 {
1167         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1168
1169         switch (ah->hw_version.devid) {
1170         case AR9280_DEVID_PCI:
1171                 if (reg == 0x7894) {
1172                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1173                                 "ini VAL: %x  EEPROM: %x\n", value,
1174                                 (pBase->version & 0xff));
1175
1176                         if ((pBase->version & 0xff) > 0x0a) {
1177                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1178                                         "PWDCLKIND: %d\n",
1179                                         pBase->pwdclkind);
1180                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1181                                 value |= AR_AN_TOP2_PWDCLKIND &
1182                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1183                         } else {
1184                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1185                                         "PWDCLKIND Earlier Rev\n");
1186                         }
1187
1188                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1189                                 "final ini VAL: %x\n", value);
1190                 }
1191                 break;
1192         }
1193
1194         return value;
1195 }
1196
1197 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1198                               struct ar5416_eeprom_def *pEepData,
1199                               u32 reg, u32 value)
1200 {
1201         if (ah->eep_map == EEP_MAP_4KBITS)
1202                 return value;
1203         else
1204                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1205 }
1206
1207 static void ath9k_olc_init(struct ath_hw *ah)
1208 {
1209         u32 i;
1210
1211         for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1212                 ah->originalGain[i] =
1213                         MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1214                                         AR_PHY_TX_GAIN);
1215         ah->PDADCdelta = 0;
1216 }
1217
1218 static int ath9k_hw_process_ini(struct ath_hw *ah,
1219                                 struct ath9k_channel *chan,
1220                                 enum ath9k_ht_macmode macmode)
1221 {
1222 #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
1223                                 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1224         int i, regWrites = 0;
1225         struct ieee80211_channel *channel = chan->chan;
1226         u32 modesIndex, freqIndex;
1227         int status;
1228
1229         switch (chan->chanmode) {
1230         case CHANNEL_A:
1231         case CHANNEL_A_HT20:
1232                 modesIndex = 1;
1233                 freqIndex = 1;
1234                 break;
1235         case CHANNEL_A_HT40PLUS:
1236         case CHANNEL_A_HT40MINUS:
1237                 modesIndex = 2;
1238                 freqIndex = 1;
1239                 break;
1240         case CHANNEL_G:
1241         case CHANNEL_G_HT20:
1242         case CHANNEL_B:
1243                 modesIndex = 4;
1244                 freqIndex = 2;
1245                 break;
1246         case CHANNEL_G_HT40PLUS:
1247         case CHANNEL_G_HT40MINUS:
1248                 modesIndex = 3;
1249                 freqIndex = 2;
1250                 break;
1251
1252         default:
1253                 return -EINVAL;
1254         }
1255
1256         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1257         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1258         ah->eep_ops->set_addac(ah, chan);
1259
1260         if (AR_SREV_5416_V22_OR_LATER(ah)) {
1261                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1262         } else {
1263                 struct ar5416IniArray temp;
1264                 u32 addacSize =
1265                         sizeof(u32) * ah->iniAddac.ia_rows *
1266                         ah->iniAddac.ia_columns;
1267
1268                 memcpy(ah->addac5416_21,
1269                        ah->iniAddac.ia_array, addacSize);
1270
1271                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1272
1273                 temp.ia_array = ah->addac5416_21;
1274                 temp.ia_columns = ah->iniAddac.ia_columns;
1275                 temp.ia_rows = ah->iniAddac.ia_rows;
1276                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1277         }
1278
1279         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1280
1281         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1282                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1283                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1284
1285                 REG_WRITE(ah, reg, val);
1286
1287                 if (reg >= 0x7800 && reg < 0x78a0
1288                     && ah->config.analog_shiftreg) {
1289                         udelay(100);
1290                 }
1291
1292                 DO_DELAY(regWrites);
1293         }
1294
1295         if (AR_SREV_9280(ah))
1296                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1297
1298         if (AR_SREV_9280(ah))
1299                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1300
1301         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1302                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1303                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1304
1305                 REG_WRITE(ah, reg, val);
1306
1307                 if (reg >= 0x7800 && reg < 0x78a0
1308                     && ah->config.analog_shiftreg) {
1309                         udelay(100);
1310                 }
1311
1312                 DO_DELAY(regWrites);
1313         }
1314
1315         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1316
1317         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1318                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1319                                 regWrites);
1320         }
1321
1322         ath9k_hw_override_ini(ah, chan);
1323         ath9k_hw_set_regs(ah, chan, macmode);
1324         ath9k_hw_init_chain_masks(ah);
1325
1326         if (OLC_FOR_AR9280_20_LATER)
1327                 ath9k_olc_init(ah);
1328
1329         status = ah->eep_ops->set_txpower(ah, chan,
1330                                   ath9k_regd_get_ctl(ah, chan),
1331                                   channel->max_antenna_gain * 2,
1332                                   channel->max_power * 2,
1333                                   min((u32) MAX_RATE_POWER,
1334                                       (u32) ah->regulatory.power_limit));
1335         if (status != 0) {
1336                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1337                         "error init'ing transmit power\n");
1338                 return -EIO;
1339         }
1340
1341         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1342                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1343                         "ar5416SetRfRegs failed\n");
1344                 return -EIO;
1345         }
1346
1347         return 0;
1348 }
1349
1350 /****************************************/
1351 /* Reset and Channel Switching Routines */
1352 /****************************************/
1353
1354 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1355 {
1356         u32 rfMode = 0;
1357
1358         if (chan == NULL)
1359                 return;
1360
1361         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1362                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1363
1364         if (!AR_SREV_9280_10_OR_LATER(ah))
1365                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1366                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1367
1368         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1369                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1370
1371         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1372 }
1373
1374 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1375 {
1376         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1377 }
1378
1379 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1380 {
1381         u32 regval;
1382
1383         regval = REG_READ(ah, AR_AHB_MODE);
1384         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1385
1386         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1387         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1388
1389         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1390
1391         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1392         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1393
1394         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1395
1396         if (AR_SREV_9285(ah)) {
1397                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1398                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1399         } else {
1400                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1401                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1402         }
1403 }
1404
1405 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1406 {
1407         u32 val;
1408
1409         val = REG_READ(ah, AR_STA_ID1);
1410         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1411         switch (opmode) {
1412         case NL80211_IFTYPE_AP:
1413                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1414                           | AR_STA_ID1_KSRCH_MODE);
1415                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1416                 break;
1417         case NL80211_IFTYPE_ADHOC:
1418                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1419                           | AR_STA_ID1_KSRCH_MODE);
1420                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1421                 break;
1422         case NL80211_IFTYPE_STATION:
1423         case NL80211_IFTYPE_MONITOR:
1424                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1425                 break;
1426         }
1427 }
1428
1429 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1430                                                  u32 coef_scaled,
1431                                                  u32 *coef_mantissa,
1432                                                  u32 *coef_exponent)
1433 {
1434         u32 coef_exp, coef_man;
1435
1436         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1437                 if ((coef_scaled >> coef_exp) & 0x1)
1438                         break;
1439
1440         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1441
1442         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1443
1444         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1445         *coef_exponent = coef_exp - 16;
1446 }
1447
1448 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1449                                      struct ath9k_channel *chan)
1450 {
1451         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1452         u32 clockMhzScaled = 0x64000000;
1453         struct chan_centers centers;
1454
1455         if (IS_CHAN_HALF_RATE(chan))
1456                 clockMhzScaled = clockMhzScaled >> 1;
1457         else if (IS_CHAN_QUARTER_RATE(chan))
1458                 clockMhzScaled = clockMhzScaled >> 2;
1459
1460         ath9k_hw_get_channel_centers(ah, chan, &centers);
1461         coef_scaled = clockMhzScaled / centers.synth_center;
1462
1463         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1464                                       &ds_coef_exp);
1465
1466         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1467                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1468         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1469                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1470
1471         coef_scaled = (9 * coef_scaled) / 10;
1472
1473         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1474                                       &ds_coef_exp);
1475
1476         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1477                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1478         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1479                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1480 }
1481
1482 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1483 {
1484         u32 rst_flags;
1485         u32 tmpReg;
1486
1487         if (AR_SREV_9100(ah)) {
1488                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1489                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1490                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1491                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1492                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1493         }
1494
1495         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1496                   AR_RTC_FORCE_WAKE_ON_INT);
1497
1498         if (AR_SREV_9100(ah)) {
1499                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1500                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1501         } else {
1502                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1503                 if (tmpReg &
1504                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1505                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1506                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1507                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1508                 } else {
1509                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1510                 }
1511
1512                 rst_flags = AR_RTC_RC_MAC_WARM;
1513                 if (type == ATH9K_RESET_COLD)
1514                         rst_flags |= AR_RTC_RC_MAC_COLD;
1515         }
1516
1517         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1518         udelay(50);
1519
1520         REG_WRITE(ah, AR_RTC_RC, 0);
1521         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1522                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1523                         "RTC stuck in MAC reset\n");
1524                 return false;
1525         }
1526
1527         if (!AR_SREV_9100(ah))
1528                 REG_WRITE(ah, AR_RC, 0);
1529
1530         ath9k_hw_init_pll(ah, NULL);
1531
1532         if (AR_SREV_9100(ah))
1533                 udelay(50);
1534
1535         return true;
1536 }
1537
1538 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1539 {
1540         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1541                   AR_RTC_FORCE_WAKE_ON_INT);
1542
1543         REG_WRITE(ah, AR_RTC_RESET, 0);
1544         udelay(2);
1545         REG_WRITE(ah, AR_RTC_RESET, 1);
1546
1547         if (!ath9k_hw_wait(ah,
1548                            AR_RTC_STATUS,
1549                            AR_RTC_STATUS_M,
1550                            AR_RTC_STATUS_ON,
1551                            AH_WAIT_TIMEOUT)) {
1552                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1553                 return false;
1554         }
1555
1556         ath9k_hw_read_revisions(ah);
1557
1558         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1559 }
1560
1561 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1562 {
1563         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1564                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1565
1566         switch (type) {
1567         case ATH9K_RESET_POWER_ON:
1568                 return ath9k_hw_set_reset_power_on(ah);
1569                 break;
1570         case ATH9K_RESET_WARM:
1571         case ATH9K_RESET_COLD:
1572                 return ath9k_hw_set_reset(ah, type);
1573                 break;
1574         default:
1575                 return false;
1576         }
1577 }
1578
1579 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1580                               enum ath9k_ht_macmode macmode)
1581 {
1582         u32 phymode;
1583         u32 enableDacFifo = 0;
1584
1585         if (AR_SREV_9285_10_OR_LATER(ah))
1586                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1587                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1588
1589         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1590                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1591
1592         if (IS_CHAN_HT40(chan)) {
1593                 phymode |= AR_PHY_FC_DYN2040_EN;
1594
1595                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1596                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1597                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1598
1599                 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1600                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1601         }
1602         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1603
1604         ath9k_hw_set11nmac2040(ah, macmode);
1605
1606         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1607         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1608 }
1609
1610 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1611                                 struct ath9k_channel *chan)
1612 {
1613         if (OLC_FOR_AR9280_20_LATER) {
1614                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1615                         return false;
1616         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1617                 return false;
1618
1619         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1620                 return false;
1621
1622         ah->chip_fullsleep = false;
1623         ath9k_hw_init_pll(ah, chan);
1624         ath9k_hw_set_rfmode(ah, chan);
1625
1626         return true;
1627 }
1628
1629 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1630                                     struct ath9k_channel *chan,
1631                                     enum ath9k_ht_macmode macmode)
1632 {
1633         struct ieee80211_channel *channel = chan->chan;
1634         u32 synthDelay, qnum;
1635
1636         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1637                 if (ath9k_hw_numtxpending(ah, qnum)) {
1638                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1639                                 "Transmit frames pending on queue %d\n", qnum);
1640                         return false;
1641                 }
1642         }
1643
1644         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1645         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1646                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1647                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1648                         "Could not kill baseband RX\n");
1649                 return false;
1650         }
1651
1652         ath9k_hw_set_regs(ah, chan, macmode);
1653
1654         if (AR_SREV_9280_10_OR_LATER(ah)) {
1655                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1656                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1657                                 "failed to set channel\n");
1658                         return false;
1659                 }
1660         } else {
1661                 if (!(ath9k_hw_set_channel(ah, chan))) {
1662                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1663                                 "failed to set channel\n");
1664                         return false;
1665                 }
1666         }
1667
1668         if (ah->eep_ops->set_txpower(ah, chan,
1669                              ath9k_regd_get_ctl(ah, chan),
1670                              channel->max_antenna_gain * 2,
1671                              channel->max_power * 2,
1672                              min((u32) MAX_RATE_POWER,
1673                                  (u32) ah->regulatory.power_limit)) != 0) {
1674                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1675                         "error init'ing transmit power\n");
1676                 return false;
1677         }
1678
1679         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1680         if (IS_CHAN_B(chan))
1681                 synthDelay = (4 * synthDelay) / 22;
1682         else
1683                 synthDelay /= 10;
1684
1685         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1686
1687         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1688
1689         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1690                 ath9k_hw_set_delta_slope(ah, chan);
1691
1692         if (AR_SREV_9280_10_OR_LATER(ah))
1693                 ath9k_hw_9280_spur_mitigate(ah, chan);
1694         else
1695                 ath9k_hw_spur_mitigate(ah, chan);
1696
1697         if (!chan->oneTimeCalsDone)
1698                 chan->oneTimeCalsDone = true;
1699
1700         return true;
1701 }
1702
1703 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1704 {
1705         int bb_spur = AR_NO_SPUR;
1706         int freq;
1707         int bin, cur_bin;
1708         int bb_spur_off, spur_subchannel_sd;
1709         int spur_freq_sd;
1710         int spur_delta_phase;
1711         int denominator;
1712         int upper, lower, cur_vit_mask;
1713         int tmp, newVal;
1714         int i;
1715         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1716                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1717         };
1718         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1719                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1720         };
1721         int inc[4] = { 0, 100, 0, 0 };
1722         struct chan_centers centers;
1723
1724         int8_t mask_m[123];
1725         int8_t mask_p[123];
1726         int8_t mask_amt;
1727         int tmp_mask;
1728         int cur_bb_spur;
1729         bool is2GHz = IS_CHAN_2GHZ(chan);
1730
1731         memset(&mask_m, 0, sizeof(int8_t) * 123);
1732         memset(&mask_p, 0, sizeof(int8_t) * 123);
1733
1734         ath9k_hw_get_channel_centers(ah, chan, &centers);
1735         freq = centers.synth_center;
1736
1737         ah->config.spurmode = SPUR_ENABLE_EEPROM;
1738         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1739                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1740
1741                 if (is2GHz)
1742                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1743                 else
1744                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1745
1746                 if (AR_NO_SPUR == cur_bb_spur)
1747                         break;
1748                 cur_bb_spur = cur_bb_spur - freq;
1749
1750                 if (IS_CHAN_HT40(chan)) {
1751                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1752                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1753                                 bb_spur = cur_bb_spur;
1754                                 break;
1755                         }
1756                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1757                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1758                         bb_spur = cur_bb_spur;
1759                         break;
1760                 }
1761         }
1762
1763         if (AR_NO_SPUR == bb_spur) {
1764                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1765                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1766                 return;
1767         } else {
1768                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1769                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1770         }
1771
1772         bin = bb_spur * 320;
1773
1774         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1775
1776         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1777                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1778                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1779                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1780         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1781
1782         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1783                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1784                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1785                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1786                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1787         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1788
1789         if (IS_CHAN_HT40(chan)) {
1790                 if (bb_spur < 0) {
1791                         spur_subchannel_sd = 1;
1792                         bb_spur_off = bb_spur + 10;
1793                 } else {
1794                         spur_subchannel_sd = 0;
1795                         bb_spur_off = bb_spur - 10;
1796                 }
1797         } else {
1798                 spur_subchannel_sd = 0;
1799                 bb_spur_off = bb_spur;
1800         }
1801
1802         if (IS_CHAN_HT40(chan))
1803                 spur_delta_phase =
1804                         ((bb_spur * 262144) /
1805                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1806         else
1807                 spur_delta_phase =
1808                         ((bb_spur * 524288) /
1809                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1810
1811         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1812         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1813
1814         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1815                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1816                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1817         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1818
1819         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1820         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1821
1822         cur_bin = -6000;
1823         upper = bin + 100;
1824         lower = bin - 100;
1825
1826         for (i = 0; i < 4; i++) {
1827                 int pilot_mask = 0;
1828                 int chan_mask = 0;
1829                 int bp = 0;
1830                 for (bp = 0; bp < 30; bp++) {
1831                         if ((cur_bin > lower) && (cur_bin < upper)) {
1832                                 pilot_mask = pilot_mask | 0x1 << bp;
1833                                 chan_mask = chan_mask | 0x1 << bp;
1834                         }
1835                         cur_bin += 100;
1836                 }
1837                 cur_bin += inc[i];
1838                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1839                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1840         }
1841
1842         cur_vit_mask = 6100;
1843         upper = bin + 120;
1844         lower = bin - 120;
1845
1846         for (i = 0; i < 123; i++) {
1847                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1848
1849                         /* workaround for gcc bug #37014 */
1850                         volatile int tmp_v = abs(cur_vit_mask - bin);
1851
1852                         if (tmp_v < 75)
1853                                 mask_amt = 1;
1854                         else
1855                                 mask_amt = 0;
1856                         if (cur_vit_mask < 0)
1857                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1858                         else
1859                                 mask_p[cur_vit_mask / 100] = mask_amt;
1860                 }
1861                 cur_vit_mask -= 100;
1862         }
1863
1864         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1865                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1866                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1867                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1868                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1869                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1870                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1871                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1872         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1873         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1874
1875         tmp_mask = (mask_m[31] << 28)
1876                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1877                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1878                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1879                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1880                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1881                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1882                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1883         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1884         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1885
1886         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1887                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1888                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1889                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1890                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1891                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1892                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1893                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1894         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1895         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1896
1897         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1898                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1899                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1900                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1901                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1902                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1903                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1904                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1905         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1906         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1907
1908         tmp_mask = (mask_p[15] << 28)
1909                 | (mask_p[14] << 26) | (mask_p[13] << 24)
1910                 | (mask_p[12] << 22) | (mask_p[11] << 20)
1911                 | (mask_p[10] << 18) | (mask_p[9] << 16)
1912                 | (mask_p[8] << 14) | (mask_p[7] << 12)
1913                 | (mask_p[6] << 10) | (mask_p[5] << 8)
1914                 | (mask_p[4] << 6) | (mask_p[3] << 4)
1915                 | (mask_p[2] << 2) | (mask_p[1] << 0);
1916         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1917         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1918
1919         tmp_mask = (mask_p[30] << 28)
1920                 | (mask_p[29] << 26) | (mask_p[28] << 24)
1921                 | (mask_p[27] << 22) | (mask_p[26] << 20)
1922                 | (mask_p[25] << 18) | (mask_p[24] << 16)
1923                 | (mask_p[23] << 14) | (mask_p[22] << 12)
1924                 | (mask_p[21] << 10) | (mask_p[20] << 8)
1925                 | (mask_p[19] << 6) | (mask_p[18] << 4)
1926                 | (mask_p[17] << 2) | (mask_p[16] << 0);
1927         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1928         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1929
1930         tmp_mask = (mask_p[45] << 28)
1931                 | (mask_p[44] << 26) | (mask_p[43] << 24)
1932                 | (mask_p[42] << 22) | (mask_p[41] << 20)
1933                 | (mask_p[40] << 18) | (mask_p[39] << 16)
1934                 | (mask_p[38] << 14) | (mask_p[37] << 12)
1935                 | (mask_p[36] << 10) | (mask_p[35] << 8)
1936                 | (mask_p[34] << 6) | (mask_p[33] << 4)
1937                 | (mask_p[32] << 2) | (mask_p[31] << 0);
1938         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1939         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1940
1941         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1942                 | (mask_p[59] << 26) | (mask_p[58] << 24)
1943                 | (mask_p[57] << 22) | (mask_p[56] << 20)
1944                 | (mask_p[55] << 18) | (mask_p[54] << 16)
1945                 | (mask_p[53] << 14) | (mask_p[52] << 12)
1946                 | (mask_p[51] << 10) | (mask_p[50] << 8)
1947                 | (mask_p[49] << 6) | (mask_p[48] << 4)
1948                 | (mask_p[47] << 2) | (mask_p[46] << 0);
1949         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1950         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1951 }
1952
1953 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1954 {
1955         int bb_spur = AR_NO_SPUR;
1956         int bin, cur_bin;
1957         int spur_freq_sd;
1958         int spur_delta_phase;
1959         int denominator;
1960         int upper, lower, cur_vit_mask;
1961         int tmp, new;
1962         int i;
1963         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1964                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1965         };
1966         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1967                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1968         };
1969         int inc[4] = { 0, 100, 0, 0 };
1970
1971         int8_t mask_m[123];
1972         int8_t mask_p[123];
1973         int8_t mask_amt;
1974         int tmp_mask;
1975         int cur_bb_spur;
1976         bool is2GHz = IS_CHAN_2GHZ(chan);
1977
1978         memset(&mask_m, 0, sizeof(int8_t) * 123);
1979         memset(&mask_p, 0, sizeof(int8_t) * 123);
1980
1981         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1982                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1983                 if (AR_NO_SPUR == cur_bb_spur)
1984                         break;
1985                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
1986                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
1987                         bb_spur = cur_bb_spur;
1988                         break;
1989                 }
1990         }
1991
1992         if (AR_NO_SPUR == bb_spur)
1993                 return;
1994
1995         bin = bb_spur * 32;
1996
1997         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1998         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1999                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2000                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2001                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2002
2003         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2004
2005         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2006                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2007                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2008                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2009                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2010         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2011
2012         spur_delta_phase = ((bb_spur * 524288) / 100) &
2013                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2014
2015         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2016         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2017
2018         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2019                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2020                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2021         REG_WRITE(ah, AR_PHY_TIMING11, new);
2022
2023         cur_bin = -6000;
2024         upper = bin + 100;
2025         lower = bin - 100;
2026
2027         for (i = 0; i < 4; i++) {
2028                 int pilot_mask = 0;
2029                 int chan_mask = 0;
2030                 int bp = 0;
2031                 for (bp = 0; bp < 30; bp++) {
2032                         if ((cur_bin > lower) && (cur_bin < upper)) {
2033                                 pilot_mask = pilot_mask | 0x1 << bp;
2034                                 chan_mask = chan_mask | 0x1 << bp;
2035                         }
2036                         cur_bin += 100;
2037                 }
2038                 cur_bin += inc[i];
2039                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2040                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2041         }
2042
2043         cur_vit_mask = 6100;
2044         upper = bin + 120;
2045         lower = bin - 120;
2046
2047         for (i = 0; i < 123; i++) {
2048                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2049
2050                         /* workaround for gcc bug #37014 */
2051                         volatile int tmp_v = abs(cur_vit_mask - bin);
2052
2053                         if (tmp_v < 75)
2054                                 mask_amt = 1;
2055                         else
2056                                 mask_amt = 0;
2057                         if (cur_vit_mask < 0)
2058                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2059                         else
2060                                 mask_p[cur_vit_mask / 100] = mask_amt;
2061                 }
2062                 cur_vit_mask -= 100;
2063         }
2064
2065         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2066                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2067                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2068                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2069                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2070                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2071                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2072                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2073         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2074         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2075
2076         tmp_mask = (mask_m[31] << 28)
2077                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2078                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2079                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2080                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2081                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2082                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2083                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2084         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2085         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2086
2087         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2088                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2089                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2090                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2091                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2092                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2093                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2094                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2095         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2096         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2097
2098         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2099                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2100                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2101                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2102                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2103                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2104                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2105                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2106         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2107         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2108
2109         tmp_mask = (mask_p[15] << 28)
2110                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2111                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2112                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2113                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2114                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2115                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2116                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2117         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2118         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2119
2120         tmp_mask = (mask_p[30] << 28)
2121                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2122                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2123                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2124                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2125                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2126                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2127                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2128         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2129         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2130
2131         tmp_mask = (mask_p[45] << 28)
2132                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2133                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2134                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2135                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2136                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2137                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2138                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2139         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2140         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2141
2142         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2143                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2144                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2145                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2146                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2147                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2148                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2149                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2150         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2151         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2152 }
2153
2154 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2155                     bool bChannelChange)
2156 {
2157         u32 saveLedState;
2158         struct ath_softc *sc = ah->ah_sc;
2159         struct ath9k_channel *curchan = ah->curchan;
2160         u32 saveDefAntenna;
2161         u32 macStaId1;
2162         int i, rx_chainmask, r;
2163
2164         ah->extprotspacing = sc->ht_extprotspacing;
2165         ah->txchainmask = sc->tx_chainmask;
2166         ah->rxchainmask = sc->rx_chainmask;
2167
2168         if (AR_SREV_9285(ah)) {
2169                 ah->txchainmask &= 0x1;
2170                 ah->rxchainmask &= 0x1;
2171         } else if (AR_SREV_9280(ah)) {
2172                 ah->txchainmask &= 0x3;
2173                 ah->rxchainmask &= 0x3;
2174         }
2175
2176         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2177                 return -EIO;
2178
2179         if (curchan)
2180                 ath9k_hw_getnf(ah, curchan);
2181
2182         if (bChannelChange &&
2183             (ah->chip_fullsleep != true) &&
2184             (ah->curchan != NULL) &&
2185             (chan->channel != ah->curchan->channel) &&
2186             ((chan->channelFlags & CHANNEL_ALL) ==
2187              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2188             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2189                                    !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2190
2191                 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2192                         ath9k_hw_loadnf(ah, ah->curchan);
2193                         ath9k_hw_start_nfcal(ah);
2194                         return 0;
2195                 }
2196         }
2197
2198         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2199         if (saveDefAntenna == 0)
2200                 saveDefAntenna = 1;
2201
2202         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2203
2204         saveLedState = REG_READ(ah, AR_CFG_LED) &
2205                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2206                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2207
2208         ath9k_hw_mark_phy_inactive(ah);
2209
2210         if (!ath9k_hw_chip_reset(ah, chan)) {
2211                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2212                 return -EINVAL;
2213         }
2214
2215         if (AR_SREV_9280_10_OR_LATER(ah))
2216                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2217
2218         r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2219         if (r)
2220                 return r;
2221
2222         /* Setup MFP options for CCMP */
2223         if (AR_SREV_9280_20_OR_LATER(ah)) {
2224                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2225                  * frames when constructing CCMP AAD. */
2226                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2227                               0xc7ff);
2228                 ah->sw_mgmt_crypto = false;
2229         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2230                 /* Disable hardware crypto for management frames */
2231                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2232                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2233                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2234                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2235                 ah->sw_mgmt_crypto = true;
2236         } else
2237                 ah->sw_mgmt_crypto = true;
2238
2239         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2240                 ath9k_hw_set_delta_slope(ah, chan);
2241
2242         if (AR_SREV_9280_10_OR_LATER(ah))
2243                 ath9k_hw_9280_spur_mitigate(ah, chan);
2244         else
2245                 ath9k_hw_spur_mitigate(ah, chan);
2246
2247         if (!ah->eep_ops->set_board_values(ah, chan)) {
2248                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2249                         "error setting board options\n");
2250                 return -EIO;
2251         }
2252
2253         ath9k_hw_decrease_chain_power(ah, chan);
2254
2255         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2256         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2257                   | macStaId1
2258                   | AR_STA_ID1_RTS_USE_DEF
2259                   | (ah->config.
2260                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2261                   | ah->sta_id1_defaults);
2262         ath9k_hw_set_operating_mode(ah, ah->opmode);
2263
2264         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2265         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2266
2267         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2268
2269         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2270         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2271                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2272
2273         REG_WRITE(ah, AR_ISR, ~0);
2274
2275         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2276
2277         if (AR_SREV_9280_10_OR_LATER(ah)) {
2278                 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2279                         return -EIO;
2280         } else {
2281                 if (!(ath9k_hw_set_channel(ah, chan)))
2282                         return -EIO;
2283         }
2284
2285         for (i = 0; i < AR_NUM_DCU; i++)
2286                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2287
2288         ah->intr_txqs = 0;
2289         for (i = 0; i < ah->caps.total_queues; i++)
2290                 ath9k_hw_resettxqueue(ah, i);
2291
2292         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2293         ath9k_hw_init_qos(ah);
2294
2295 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2296         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2297                 ath9k_enable_rfkill(ah);
2298 #endif
2299         ath9k_hw_init_user_settings(ah);
2300
2301         REG_WRITE(ah, AR_STA_ID1,
2302                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2303
2304         ath9k_hw_set_dma(ah);
2305
2306         REG_WRITE(ah, AR_OBS, 8);
2307
2308         if (ah->intr_mitigation) {
2309
2310                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2311                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2312         }
2313
2314         ath9k_hw_init_bb(ah, chan);
2315
2316         if (!ath9k_hw_init_cal(ah, chan))
2317                 return -EIO;;
2318
2319         rx_chainmask = ah->rxchainmask;
2320         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2321                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2322                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2323         }
2324
2325         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2326
2327         if (AR_SREV_9100(ah)) {
2328                 u32 mask;
2329                 mask = REG_READ(ah, AR_CFG);
2330                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2331                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2332                                 "CFG Byte Swap Set 0x%x\n", mask);
2333                 } else {
2334                         mask =
2335                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2336                         REG_WRITE(ah, AR_CFG, mask);
2337                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2338                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2339                 }
2340         } else {
2341 #ifdef __BIG_ENDIAN
2342                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2343 #endif
2344         }
2345
2346         return 0;
2347 }
2348
2349 /************************/
2350 /* Key Cache Management */
2351 /************************/
2352
2353 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2354 {
2355         u32 keyType;
2356
2357         if (entry >= ah->caps.keycache_size) {
2358                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2359                         "entry %u out of range\n", entry);
2360                 return false;
2361         }
2362
2363         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2364
2365         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2366         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2367         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2368         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2369         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2370         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2371         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2372         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2373
2374         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2375                 u16 micentry = entry + 64;
2376
2377                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2378                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2379                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2380                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2381
2382         }
2383
2384         if (ah->curchan == NULL)
2385                 return true;
2386
2387         return true;
2388 }
2389
2390 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2391 {
2392         u32 macHi, macLo;
2393
2394         if (entry >= ah->caps.keycache_size) {
2395                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2396                         "entry %u out of range\n", entry);
2397                 return false;
2398         }
2399
2400         if (mac != NULL) {
2401                 macHi = (mac[5] << 8) | mac[4];
2402                 macLo = (mac[3] << 24) |
2403                         (mac[2] << 16) |
2404                         (mac[1] << 8) |
2405                         mac[0];
2406                 macLo >>= 1;
2407                 macLo |= (macHi & 1) << 31;
2408                 macHi >>= 1;
2409         } else {
2410                 macLo = macHi = 0;
2411         }
2412         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2413         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2414
2415         return true;
2416 }
2417
2418 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2419                                  const struct ath9k_keyval *k,
2420                                  const u8 *mac, int xorKey)
2421 {
2422         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2423         u32 key0, key1, key2, key3, key4;
2424         u32 keyType;
2425         u32 xorMask = xorKey ?
2426                 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2427                  | ATH9K_KEY_XOR) : 0;
2428
2429         if (entry >= pCap->keycache_size) {
2430                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2431                         "entry %u out of range\n", entry);
2432                 return false;
2433         }
2434
2435         switch (k->kv_type) {
2436         case ATH9K_CIPHER_AES_OCB:
2437                 keyType = AR_KEYTABLE_TYPE_AES;
2438                 break;
2439         case ATH9K_CIPHER_AES_CCM:
2440                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2441                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2442                                 "AES-CCM not supported by mac rev 0x%x\n",
2443                                 ah->hw_version.macRev);
2444                         return false;
2445                 }
2446                 keyType = AR_KEYTABLE_TYPE_CCM;
2447                 break;
2448         case ATH9K_CIPHER_TKIP:
2449                 keyType = AR_KEYTABLE_TYPE_TKIP;
2450                 if (ATH9K_IS_MIC_ENABLED(ah)
2451                     && entry + 64 >= pCap->keycache_size) {
2452                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2453                                 "entry %u inappropriate for TKIP\n", entry);
2454                         return false;
2455                 }
2456                 break;
2457         case ATH9K_CIPHER_WEP:
2458                 if (k->kv_len < LEN_WEP40) {
2459                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2460                                 "WEP key length %u too small\n", k->kv_len);
2461                         return false;
2462                 }
2463                 if (k->kv_len <= LEN_WEP40)
2464                         keyType = AR_KEYTABLE_TYPE_40;
2465                 else if (k->kv_len <= LEN_WEP104)
2466                         keyType = AR_KEYTABLE_TYPE_104;
2467                 else
2468                         keyType = AR_KEYTABLE_TYPE_128;
2469                 break;
2470         case ATH9K_CIPHER_CLR:
2471                 keyType = AR_KEYTABLE_TYPE_CLR;
2472                 break;
2473         default:
2474                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2475                         "cipher %u not supported\n", k->kv_type);
2476                 return false;
2477         }
2478
2479         key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2480         key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2481         key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2482         key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2483         key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2484         if (k->kv_len <= LEN_WEP104)
2485                 key4 &= 0xff;
2486
2487         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2488                 u16 micentry = entry + 64;
2489
2490                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2491                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2492                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2493                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2494                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2495                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2496                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2497
2498                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2499                         u32 mic0, mic1, mic2, mic3, mic4;
2500
2501                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2502                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2503                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2504                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2505                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2506                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2507                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2508                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2509                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2510                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2511                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2512                                   AR_KEYTABLE_TYPE_CLR);
2513
2514                 } else {
2515                         u32 mic0, mic2;
2516
2517                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2518                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2519                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2520                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2521                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2522                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2523                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2524                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2525                                   AR_KEYTABLE_TYPE_CLR);
2526                 }
2527                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2528                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2529                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2530                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2531         } else {
2532                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2533                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2534                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2535                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2536                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2537                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2538
2539                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2540         }
2541
2542         if (ah->curchan == NULL)
2543                 return true;
2544
2545         return true;
2546 }
2547
2548 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2549 {
2550         if (entry < ah->caps.keycache_size) {
2551                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2552                 if (val & AR_KEYTABLE_VALID)
2553                         return true;
2554         }
2555         return false;
2556 }
2557
2558 /******************************/
2559 /* Power Management (Chipset) */
2560 /******************************/
2561
2562 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2563 {
2564         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2565         if (setChip) {
2566                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2567                             AR_RTC_FORCE_WAKE_EN);
2568                 if (!AR_SREV_9100(ah))
2569                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2570
2571                 REG_CLR_BIT(ah, (AR_RTC_RESET),
2572                             AR_RTC_RESET_EN);
2573         }
2574 }
2575
2576 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2577 {
2578         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2579         if (setChip) {
2580                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2581
2582                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2583                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2584                                   AR_RTC_FORCE_WAKE_ON_INT);
2585                 } else {
2586                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2587                                     AR_RTC_FORCE_WAKE_EN);
2588                 }
2589         }
2590 }
2591
2592 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2593 {
2594         u32 val;
2595         int i;
2596
2597         if (setChip) {
2598                 if ((REG_READ(ah, AR_RTC_STATUS) &
2599                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2600                         if (ath9k_hw_set_reset_reg(ah,
2601                                            ATH9K_RESET_POWER_ON) != true) {
2602                                 return false;
2603                         }
2604                 }
2605                 if (AR_SREV_9100(ah))
2606                         REG_SET_BIT(ah, AR_RTC_RESET,
2607                                     AR_RTC_RESET_EN);
2608
2609                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2610                             AR_RTC_FORCE_WAKE_EN);
2611                 udelay(50);
2612
2613                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2614                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2615                         if (val == AR_RTC_STATUS_ON)
2616                                 break;
2617                         udelay(50);
2618                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2619                                     AR_RTC_FORCE_WAKE_EN);
2620                 }
2621                 if (i == 0) {
2622                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2623                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2624                         return false;
2625                 }
2626         }
2627
2628         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2629
2630         return true;
2631 }
2632
2633 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2634 {
2635         int status = true, setChip = true;
2636         static const char *modes[] = {
2637                 "AWAKE",
2638                 "FULL-SLEEP",
2639                 "NETWORK SLEEP",
2640                 "UNDEFINED"
2641         };
2642
2643         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2644                 modes[ah->power_mode], modes[mode],
2645                 setChip ? "set chip " : "");
2646
2647         switch (mode) {
2648         case ATH9K_PM_AWAKE:
2649                 status = ath9k_hw_set_power_awake(ah, setChip);
2650                 break;
2651         case ATH9K_PM_FULL_SLEEP:
2652                 ath9k_set_power_sleep(ah, setChip);
2653                 ah->chip_fullsleep = true;
2654                 break;
2655         case ATH9K_PM_NETWORK_SLEEP:
2656                 ath9k_set_power_network_sleep(ah, setChip);
2657                 break;
2658         default:
2659                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2660                         "Unknown power mode %u\n", mode);
2661                 return false;
2662         }
2663         ah->power_mode = mode;
2664
2665         return status;
2666 }
2667
2668 /*
2669  * Helper for ASPM support.
2670  *
2671  * Disable PLL when in L0s as well as receiver clock when in L1.
2672  * This power saving option must be enabled through the SerDes.
2673  *
2674  * Programming the SerDes must go through the same 288 bit serial shift
2675  * register as the other analog registers.  Hence the 9 writes.
2676  */
2677 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2678 {
2679         u8 i;
2680
2681         if (ah->is_pciexpress != true)
2682                 return;
2683
2684         /* Do not touch SerDes registers */
2685         if (ah->config.pcie_powersave_enable == 2)
2686                 return;
2687
2688         /* Nothing to do on restore for 11N */
2689         if (restore)
2690                 return;
2691
2692         if (AR_SREV_9280_20_OR_LATER(ah)) {
2693                 /*
2694                  * AR9280 2.0 or later chips use SerDes values from the
2695                  * initvals.h initialized depending on chipset during
2696                  * ath9k_hw_do_attach()
2697                  */
2698                 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2699                         REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2700                                   INI_RA(&ah->iniPcieSerdes, i, 1));
2701                 }
2702         } else if (AR_SREV_9280(ah) &&
2703                    (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2704                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2705                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2706
2707                 /* RX shut off when elecidle is asserted */
2708                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2709                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2710                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2711
2712                 /* Shut off CLKREQ active in L1 */
2713                 if (ah->config.pcie_clock_req)
2714                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2715                 else
2716                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2717
2718                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2719                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2720                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2721
2722                 /* Load the new settings */
2723                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2724
2725         } else {
2726                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2727                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2728
2729                 /* RX shut off when elecidle is asserted */
2730                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2731                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2732                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2733
2734                 /*
2735                  * Ignore ah->ah_config.pcie_clock_req setting for
2736                  * pre-AR9280 11n
2737                  */
2738                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2739
2740                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2741                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2742                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2743
2744                 /* Load the new settings */
2745                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2746         }
2747
2748         udelay(1000);
2749
2750         /* set bit 19 to allow forcing of pcie core into L1 state */
2751         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2752
2753         /* Several PCIe massages to ensure proper behaviour */
2754         if (ah->config.pcie_waen) {
2755                 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2756         } else {
2757                 if (AR_SREV_9285(ah))
2758                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2759                 /*
2760                  * On AR9280 chips bit 22 of 0x4004 needs to be set to
2761                  * otherwise card may disappear.
2762                  */
2763                 else if (AR_SREV_9280(ah))
2764                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2765                 else
2766                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2767         }
2768 }
2769
2770 /**********************/
2771 /* Interrupt Handling */
2772 /**********************/
2773
2774 bool ath9k_hw_intrpend(struct ath_hw *ah)
2775 {
2776         u32 host_isr;
2777
2778         if (AR_SREV_9100(ah))
2779                 return true;
2780
2781         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2782         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2783                 return true;
2784
2785         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2786         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2787             && (host_isr != AR_INTR_SPURIOUS))
2788                 return true;
2789
2790         return false;
2791 }
2792
2793 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2794 {
2795         u32 isr = 0;
2796         u32 mask2 = 0;
2797         struct ath9k_hw_capabilities *pCap = &ah->caps;
2798         u32 sync_cause = 0;
2799         bool fatal_int = false;
2800
2801         if (!AR_SREV_9100(ah)) {
2802                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2803                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2804                             == AR_RTC_STATUS_ON) {
2805                                 isr = REG_READ(ah, AR_ISR);
2806                         }
2807                 }
2808
2809                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2810                         AR_INTR_SYNC_DEFAULT;
2811
2812                 *masked = 0;
2813
2814                 if (!isr && !sync_cause)
2815                         return false;
2816         } else {
2817                 *masked = 0;
2818                 isr = REG_READ(ah, AR_ISR);
2819         }
2820
2821         if (isr) {
2822                 if (isr & AR_ISR_BCNMISC) {
2823                         u32 isr2;
2824                         isr2 = REG_READ(ah, AR_ISR_S2);
2825                         if (isr2 & AR_ISR_S2_TIM)
2826                                 mask2 |= ATH9K_INT_TIM;
2827                         if (isr2 & AR_ISR_S2_DTIM)
2828                                 mask2 |= ATH9K_INT_DTIM;
2829                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2830                                 mask2 |= ATH9K_INT_DTIMSYNC;
2831                         if (isr2 & (AR_ISR_S2_CABEND))
2832                                 mask2 |= ATH9K_INT_CABEND;
2833                         if (isr2 & AR_ISR_S2_GTT)
2834                                 mask2 |= ATH9K_INT_GTT;
2835                         if (isr2 & AR_ISR_S2_CST)
2836                                 mask2 |= ATH9K_INT_CST;
2837                         if (isr2 & AR_ISR_S2_TSFOOR)
2838                                 mask2 |= ATH9K_INT_TSFOOR;
2839                 }
2840
2841                 isr = REG_READ(ah, AR_ISR_RAC);
2842                 if (isr == 0xffffffff) {
2843                         *masked = 0;
2844                         return false;
2845                 }
2846
2847                 *masked = isr & ATH9K_INT_COMMON;
2848
2849                 if (ah->intr_mitigation) {
2850                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2851                                 *masked |= ATH9K_INT_RX;
2852                 }
2853
2854                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2855                         *masked |= ATH9K_INT_RX;
2856                 if (isr &
2857                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2858                      AR_ISR_TXEOL)) {
2859                         u32 s0_s, s1_s;
2860
2861                         *masked |= ATH9K_INT_TX;
2862
2863                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2864                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2865                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2866
2867                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2868                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2869                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2870                 }
2871
2872                 if (isr & AR_ISR_RXORN) {
2873                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2874                                 "receive FIFO overrun interrupt\n");
2875                 }
2876
2877                 if (!AR_SREV_9100(ah)) {
2878                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2879                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2880                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2881                                         *masked |= ATH9K_INT_TIM_TIMER;
2882                         }
2883                 }
2884
2885                 *masked |= mask2;
2886         }
2887
2888         if (AR_SREV_9100(ah))
2889                 return true;
2890
2891         if (sync_cause) {
2892                 fatal_int =
2893                         (sync_cause &
2894                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2895                         ? true : false;
2896
2897                 if (fatal_int) {
2898                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2899                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2900                                         "received PCI FATAL interrupt\n");
2901                         }
2902                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2903                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2904                                         "received PCI PERR interrupt\n");
2905                         }
2906                 }
2907                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2908                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2909                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2910                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2911                         REG_WRITE(ah, AR_RC, 0);
2912                         *masked |= ATH9K_INT_FATAL;
2913                 }
2914                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2915                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2916                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2917                 }
2918
2919                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2920                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2921         }
2922
2923         return true;
2924 }
2925
2926 enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
2927 {
2928         return ah->mask_reg;
2929 }
2930
2931 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2932 {
2933         u32 omask = ah->mask_reg;
2934         u32 mask, mask2;
2935         struct ath9k_hw_capabilities *pCap = &ah->caps;
2936
2937         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2938
2939         if (omask & ATH9K_INT_GLOBAL) {
2940                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
2941                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2942                 (void) REG_READ(ah, AR_IER);
2943                 if (!AR_SREV_9100(ah)) {
2944                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2945                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2946
2947                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2948                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2949                 }
2950         }
2951
2952         mask = ints & ATH9K_INT_COMMON;
2953         mask2 = 0;
2954
2955         if (ints & ATH9K_INT_TX) {
2956                 if (ah->txok_interrupt_mask)
2957                         mask |= AR_IMR_TXOK;
2958                 if (ah->txdesc_interrupt_mask)
2959                         mask |= AR_IMR_TXDESC;
2960                 if (ah->txerr_interrupt_mask)
2961                         mask |= AR_IMR_TXERR;
2962                 if (ah->txeol_interrupt_mask)
2963                         mask |= AR_IMR_TXEOL;
2964         }
2965         if (ints & ATH9K_INT_RX) {
2966                 mask |= AR_IMR_RXERR;
2967                 if (ah->intr_mitigation)
2968                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2969                 else
2970                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2971                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2972                         mask |= AR_IMR_GENTMR;
2973         }
2974
2975         if (ints & (ATH9K_INT_BMISC)) {
2976                 mask |= AR_IMR_BCNMISC;
2977                 if (ints & ATH9K_INT_TIM)
2978                         mask2 |= AR_IMR_S2_TIM;
2979                 if (ints & ATH9K_INT_DTIM)
2980                         mask2 |= AR_IMR_S2_DTIM;
2981                 if (ints & ATH9K_INT_DTIMSYNC)
2982                         mask2 |= AR_IMR_S2_DTIMSYNC;
2983                 if (ints & ATH9K_INT_CABEND)
2984                         mask2 |= AR_IMR_S2_CABEND;
2985                 if (ints & ATH9K_INT_TSFOOR)
2986                         mask2 |= AR_IMR_S2_TSFOOR;
2987         }
2988
2989         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2990                 mask |= AR_IMR_BCNMISC;
2991                 if (ints & ATH9K_INT_GTT)
2992                         mask2 |= AR_IMR_S2_GTT;
2993                 if (ints & ATH9K_INT_CST)
2994                         mask2 |= AR_IMR_S2_CST;
2995         }
2996
2997         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2998         REG_WRITE(ah, AR_IMR, mask);
2999         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3000                                            AR_IMR_S2_DTIM |
3001                                            AR_IMR_S2_DTIMSYNC |
3002                                            AR_IMR_S2_CABEND |
3003                                            AR_IMR_S2_CABTO |
3004                                            AR_IMR_S2_TSFOOR |
3005                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3006         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3007         ah->mask_reg = ints;
3008
3009         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3010                 if (ints & ATH9K_INT_TIM_TIMER)
3011                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3012                 else
3013                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3014         }
3015
3016         if (ints & ATH9K_INT_GLOBAL) {
3017                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3018                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3019                 if (!AR_SREV_9100(ah)) {
3020                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3021                                   AR_INTR_MAC_IRQ);
3022                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3023
3024
3025                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3026                                   AR_INTR_SYNC_DEFAULT);
3027                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3028                                   AR_INTR_SYNC_DEFAULT);
3029                 }
3030                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3031                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3032         }
3033
3034         return omask;
3035 }
3036
3037 /*******************/
3038 /* Beacon Handling */
3039 /*******************/
3040
3041 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3042 {
3043         int flags = 0;
3044
3045         ah->beacon_interval = beacon_period;
3046
3047         switch (ah->opmode) {
3048         case NL80211_IFTYPE_STATION:
3049         case NL80211_IFTYPE_MONITOR:
3050                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3051                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3052                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3053                 flags |= AR_TBTT_TIMER_EN;
3054                 break;
3055         case NL80211_IFTYPE_ADHOC:
3056                 REG_SET_BIT(ah, AR_TXCFG,
3057                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3058                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3059                           TU_TO_USEC(next_beacon +
3060                                      (ah->atim_window ? ah->
3061                                       atim_window : 1)));
3062                 flags |= AR_NDP_TIMER_EN;
3063         case NL80211_IFTYPE_AP:
3064                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3065                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3066                           TU_TO_USEC(next_beacon -
3067                                      ah->config.
3068                                      dma_beacon_response_time));
3069                 REG_WRITE(ah, AR_NEXT_SWBA,
3070                           TU_TO_USEC(next_beacon -
3071                                      ah->config.
3072                                      sw_beacon_response_time));
3073                 flags |=
3074                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3075                 break;
3076         default:
3077                 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3078                         "%s: unsupported opmode: %d\n",
3079                         __func__, ah->opmode);
3080                 return;
3081                 break;
3082         }
3083
3084         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3085         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3086         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3087         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3088
3089         beacon_period &= ~ATH9K_BEACON_ENA;
3090         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3091                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3092                 ath9k_hw_reset_tsf(ah);
3093         }
3094
3095         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3096 }
3097
3098 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3099                                     const struct ath9k_beacon_state *bs)
3100 {
3101         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3102         struct ath9k_hw_capabilities *pCap = &ah->caps;
3103
3104         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3105
3106         REG_WRITE(ah, AR_BEACON_PERIOD,
3107                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3108         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3109                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3110
3111         REG_RMW_FIELD(ah, AR_RSSI_THR,
3112                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3113
3114         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3115
3116         if (bs->bs_sleepduration > beaconintval)
3117                 beaconintval = bs->bs_sleepduration;
3118
3119         dtimperiod = bs->bs_dtimperiod;
3120         if (bs->bs_sleepduration > dtimperiod)
3121                 dtimperiod = bs->bs_sleepduration;
3122
3123         if (beaconintval == dtimperiod)
3124                 nextTbtt = bs->bs_nextdtim;
3125         else
3126                 nextTbtt = bs->bs_nexttbtt;
3127
3128         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3129         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3130         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3131         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3132
3133         REG_WRITE(ah, AR_NEXT_DTIM,
3134                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3135         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3136
3137         REG_WRITE(ah, AR_SLEEP1,
3138                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3139                   | AR_SLEEP1_ASSUME_DTIM);
3140
3141         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3142                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3143         else
3144                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3145
3146         REG_WRITE(ah, AR_SLEEP2,
3147                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3148
3149         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3150         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3151
3152         REG_SET_BIT(ah, AR_TIMER_MODE,
3153                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3154                     AR_DTIM_TIMER_EN);
3155
3156         /* TSF Out of Range Threshold */
3157         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3158 }
3159
3160 /*******************/
3161 /* HW Capabilities */
3162 /*******************/
3163
3164 bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
3165 {
3166         struct ath9k_hw_capabilities *pCap = &ah->caps;
3167         u16 capField = 0, eeval;
3168
3169         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3170         ah->regulatory.current_rd = eeval;
3171
3172         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3173         if (AR_SREV_9285_10_OR_LATER(ah))
3174                 eeval |= AR9285_RDEXT_DEFAULT;
3175         ah->regulatory.current_rd_ext = eeval;
3176
3177         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3178
3179         if (ah->opmode != NL80211_IFTYPE_AP &&
3180             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3181                 if (ah->regulatory.current_rd == 0x64 ||
3182                     ah->regulatory.current_rd == 0x65)
3183                         ah->regulatory.current_rd += 5;
3184                 else if (ah->regulatory.current_rd == 0x41)
3185                         ah->regulatory.current_rd = 0x43;
3186                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3187                         "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3188         }
3189
3190         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3191         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3192
3193         if (eeval & AR5416_OPFLAGS_11A) {
3194                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3195                 if (ah->config.ht_enable) {
3196                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3197                                 set_bit(ATH9K_MODE_11NA_HT20,
3198                                         pCap->wireless_modes);
3199                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3200                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3201                                         pCap->wireless_modes);
3202                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3203                                         pCap->wireless_modes);
3204                         }
3205                 }
3206         }
3207
3208         if (eeval & AR5416_OPFLAGS_11G) {
3209                 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3210                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3211                 if (ah->config.ht_enable) {
3212                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3213                                 set_bit(ATH9K_MODE_11NG_HT20,
3214                                         pCap->wireless_modes);
3215                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3216                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3217                                         pCap->wireless_modes);
3218                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3219                                         pCap->wireless_modes);
3220                         }
3221                 }
3222         }
3223
3224         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3225         if ((ah->is_pciexpress)
3226             || (eeval & AR5416_OPFLAGS_11A)) {
3227                 pCap->rx_chainmask =
3228                         ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3229         } else {
3230                 pCap->rx_chainmask =
3231                         (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3232         }
3233
3234         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3235                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3236
3237         pCap->low_2ghz_chan = 2312;
3238         pCap->high_2ghz_chan = 2732;
3239
3240         pCap->low_5ghz_chan = 4920;
3241         pCap->high_5ghz_chan = 6100;
3242
3243         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3244         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3245         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3246
3247         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3248         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3249         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3250
3251         pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3252
3253         if (ah->config.ht_enable)
3254                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3255         else
3256                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3257
3258         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3259         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3260         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3261         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3262
3263         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3264                 pCap->total_queues =
3265                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3266         else
3267                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3268
3269         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3270                 pCap->keycache_size =
3271                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3272         else
3273                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3274
3275         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3276         pCap->num_mr_retries = 4;
3277         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3278
3279         if (AR_SREV_9285_10_OR_LATER(ah))
3280                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3281         else if (AR_SREV_9280_10_OR_LATER(ah))
3282                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3283         else
3284                 pCap->num_gpio_pins = AR_NUM_GPIO;
3285
3286         if (AR_SREV_9280_10_OR_LATER(ah)) {
3287                 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3288                 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3289         } else {
3290                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3291                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3292         }
3293
3294         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3295                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3296                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3297         } else {
3298                 pCap->rts_aggr_limit = (8 * 1024);
3299         }
3300
3301         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3302
3303 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3304         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3305         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3306                 ah->rfkill_gpio =
3307                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3308                 ah->rfkill_polarity =
3309                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3310
3311                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3312         }
3313 #endif
3314
3315         if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3316             (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3317             (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3318             (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3319             (ah->hw_version.macVersion == AR_SREV_VERSION_9280))
3320                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3321         else
3322                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3323
3324         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3325                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3326         else
3327                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3328
3329         if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3330                 pCap->reg_cap =
3331                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3332                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3333                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3334                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3335         } else {
3336                 pCap->reg_cap =
3337                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3338                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3339         }
3340
3341         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3342
3343         pCap->num_antcfg_5ghz =
3344                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3345         pCap->num_antcfg_2ghz =
3346                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3347
3348         if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3349                 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3350                 ah->btactive_gpio = 6;
3351                 ah->wlanactive_gpio = 5;
3352         }
3353
3354         return true;
3355 }
3356
3357 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3358                             u32 capability, u32 *result)
3359 {
3360         switch (type) {
3361         case ATH9K_CAP_CIPHER:
3362                 switch (capability) {
3363                 case ATH9K_CIPHER_AES_CCM:
3364                 case ATH9K_CIPHER_AES_OCB:
3365                 case ATH9K_CIPHER_TKIP:
3366                 case ATH9K_CIPHER_WEP:
3367                 case ATH9K_CIPHER_MIC:
3368                 case ATH9K_CIPHER_CLR:
3369                         return true;
3370                 default:
3371                         return false;
3372                 }
3373         case ATH9K_CAP_TKIP_MIC:
3374                 switch (capability) {
3375                 case 0:
3376                         return true;
3377                 case 1:
3378                         return (ah->sta_id1_defaults &
3379                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3380                         false;
3381                 }
3382         case ATH9K_CAP_TKIP_SPLIT:
3383                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3384                         false : true;
3385         case ATH9K_CAP_DIVERSITY:
3386                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3387                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3388                         true : false;
3389         case ATH9K_CAP_MCAST_KEYSRCH:
3390                 switch (capability) {
3391                 case 0:
3392                         return true;
3393                 case 1:
3394                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3395                                 return false;
3396                         } else {
3397                                 return (ah->sta_id1_defaults &
3398                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3399                                         false;
3400                         }
3401                 }
3402                 return false;
3403         case ATH9K_CAP_TXPOW:
3404                 switch (capability) {
3405                 case 0:
3406                         return 0;
3407                 case 1:
3408                         *result = ah->regulatory.power_limit;
3409                         return 0;
3410                 case 2:
3411                         *result = ah->regulatory.max_power_level;
3412                         return 0;
3413                 case 3:
3414                         *result = ah->regulatory.tp_scale;
3415                         return 0;
3416                 }
3417                 return false;
3418         case ATH9K_CAP_DS:
3419                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3420                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3421                         ? false : true;
3422         default:
3423                 return false;
3424         }
3425 }
3426
3427 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3428                             u32 capability, u32 setting, int *status)
3429 {
3430         u32 v;
3431
3432         switch (type) {
3433         case ATH9K_CAP_TKIP_MIC:
3434                 if (setting)
3435                         ah->sta_id1_defaults |=
3436                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3437                 else
3438                         ah->sta_id1_defaults &=
3439                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3440                 return true;
3441         case ATH9K_CAP_DIVERSITY:
3442                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3443                 if (setting)
3444                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3445                 else
3446                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3447                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3448                 return true;
3449         case ATH9K_CAP_MCAST_KEYSRCH:
3450                 if (setting)
3451                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3452                 else
3453                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3454                 return true;
3455         default:
3456                 return false;
3457         }
3458 }
3459
3460 /****************************/
3461 /* GPIO / RFKILL / Antennae */
3462 /****************************/
3463
3464 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3465                                          u32 gpio, u32 type)
3466 {
3467         int addr;
3468         u32 gpio_shift, tmp;
3469
3470         if (gpio > 11)
3471                 addr = AR_GPIO_OUTPUT_MUX3;
3472         else if (gpio > 5)
3473                 addr = AR_GPIO_OUTPUT_MUX2;
3474         else
3475                 addr = AR_GPIO_OUTPUT_MUX1;
3476
3477         gpio_shift = (gpio % 6) * 5;
3478
3479         if (AR_SREV_9280_20_OR_LATER(ah)
3480             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3481                 REG_RMW(ah, addr, (type << gpio_shift),
3482                         (0x1f << gpio_shift));
3483         } else {
3484                 tmp = REG_READ(ah, addr);
3485                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3486                 tmp &= ~(0x1f << gpio_shift);
3487                 tmp |= (type << gpio_shift);
3488                 REG_WRITE(ah, addr, tmp);
3489         }
3490 }
3491
3492 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3493 {
3494         u32 gpio_shift;
3495
3496         ASSERT(gpio < ah->caps.num_gpio_pins);
3497
3498         gpio_shift = gpio << 1;
3499
3500         REG_RMW(ah,
3501                 AR_GPIO_OE_OUT,
3502                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3503                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3504 }
3505
3506 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3507 {
3508 #define MS_REG_READ(x, y) \
3509         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3510
3511         if (gpio >= ah->caps.num_gpio_pins)
3512                 return 0xffffffff;
3513
3514         if (AR_SREV_9285_10_OR_LATER(ah))
3515                 return MS_REG_READ(AR9285, gpio) != 0;
3516         else if (AR_SREV_9280_10_OR_LATER(ah))
3517                 return MS_REG_READ(AR928X, gpio) != 0;
3518         else
3519                 return MS_REG_READ(AR, gpio) != 0;
3520 }
3521
3522 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3523                          u32 ah_signal_type)
3524 {
3525         u32 gpio_shift;
3526
3527         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3528
3529         gpio_shift = 2 * gpio;
3530
3531         REG_RMW(ah,
3532                 AR_GPIO_OE_OUT,
3533                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3534                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3535 }
3536
3537 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3538 {
3539         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3540                 AR_GPIO_BIT(gpio));
3541 }
3542
3543 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3544 void ath9k_enable_rfkill(struct ath_hw *ah)
3545 {
3546         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3547                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3548
3549         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3550                     AR_GPIO_INPUT_MUX2_RFSILENT);
3551
3552         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3553         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3554 }
3555 #endif
3556
3557 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3558 {
3559         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3560 }
3561
3562 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3563 {
3564         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3565 }
3566
3567 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3568                                enum ath9k_ant_setting settings,
3569                                struct ath9k_channel *chan,
3570                                u8 *tx_chainmask,
3571                                u8 *rx_chainmask,
3572                                u8 *antenna_cfgd)
3573 {
3574         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3575
3576         if (AR_SREV_9280(ah)) {
3577                 if (!tx_chainmask_cfg) {
3578
3579                         tx_chainmask_cfg = *tx_chainmask;
3580                         rx_chainmask_cfg = *rx_chainmask;
3581                 }
3582
3583                 switch (settings) {
3584                 case ATH9K_ANT_FIXED_A:
3585                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3586                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3587                         *antenna_cfgd = true;
3588                         break;
3589                 case ATH9K_ANT_FIXED_B:
3590                         if (ah->caps.tx_chainmask >
3591                             ATH9K_ANTENNA1_CHAINMASK) {
3592                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3593                         }
3594                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3595                         *antenna_cfgd = true;
3596                         break;
3597                 case ATH9K_ANT_VARIABLE:
3598                         *tx_chainmask = tx_chainmask_cfg;
3599                         *rx_chainmask = rx_chainmask_cfg;
3600                         *antenna_cfgd = true;
3601                         break;
3602                 default:
3603                         break;
3604                 }
3605         } else {
3606                 ah->diversity_control = settings;
3607         }
3608
3609         return true;
3610 }
3611
3612 /*********************/
3613 /* General Operation */
3614 /*********************/
3615
3616 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3617 {
3618         u32 bits = REG_READ(ah, AR_RX_FILTER);
3619         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3620
3621         if (phybits & AR_PHY_ERR_RADAR)
3622                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3623         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3624                 bits |= ATH9K_RX_FILTER_PHYERR;
3625
3626         return bits;
3627 }
3628
3629 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3630 {
3631         u32 phybits;
3632
3633         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3634         phybits = 0;
3635         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3636                 phybits |= AR_PHY_ERR_RADAR;
3637         if (bits & ATH9K_RX_FILTER_PHYERR)
3638                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3639         REG_WRITE(ah, AR_PHY_ERR, phybits);
3640
3641         if (phybits)
3642                 REG_WRITE(ah, AR_RXCFG,
3643                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3644         else
3645                 REG_WRITE(ah, AR_RXCFG,
3646                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3647 }
3648
3649 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3650 {
3651         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3652 }
3653
3654 bool ath9k_hw_disable(struct ath_hw *ah)
3655 {
3656         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3657                 return false;
3658
3659         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3660 }
3661
3662 bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3663 {
3664         struct ath9k_channel *chan = ah->curchan;
3665         struct ieee80211_channel *channel = chan->chan;
3666
3667         ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3668
3669         if (ah->eep_ops->set_txpower(ah, chan,
3670                              ath9k_regd_get_ctl(ah, chan),
3671                              channel->max_antenna_gain * 2,
3672                              channel->max_power * 2,
3673                              min((u32) MAX_RATE_POWER,
3674                                  (u32) ah->regulatory.power_limit)) != 0)
3675                 return false;
3676
3677         return true;
3678 }
3679
3680 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3681 {
3682         memcpy(ah->macaddr, mac, ETH_ALEN);
3683 }
3684
3685 void ath9k_hw_setopmode(struct ath_hw *ah)
3686 {
3687         ath9k_hw_set_operating_mode(ah, ah->opmode);
3688 }
3689
3690 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3691 {
3692         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3693         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3694 }
3695
3696 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3697 {
3698         REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3699         REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3700 }
3701
3702 void ath9k_hw_write_associd(struct ath_softc *sc)
3703 {
3704         REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3705         REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3706                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3707 }
3708
3709 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3710 {
3711         u64 tsf;
3712
3713         tsf = REG_READ(ah, AR_TSF_U32);
3714         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3715
3716         return tsf;
3717 }
3718
3719 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3720 {
3721         REG_WRITE(ah, AR_TSF_L32, 0x00000000);
3722         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3723         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3724 }
3725
3726 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3727 {
3728         int count;
3729
3730         count = 0;
3731         while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3732                 count++;
3733                 if (count > 10) {
3734                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3735                                 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3736                         break;
3737                 }
3738                 udelay(10);
3739         }
3740         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3741 }
3742
3743 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3744 {
3745         if (setting)
3746                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3747         else
3748                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3749
3750         return true;
3751 }
3752
3753 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3754 {
3755         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3756                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3757                 ah->slottime = (u32) -1;
3758                 return false;
3759         } else {
3760                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3761                 ah->slottime = us;
3762                 return true;
3763         }
3764 }
3765
3766 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3767 {
3768         u32 macmode;
3769
3770         if (mode == ATH9K_HT_MACMODE_2040 &&
3771             !ah->config.cwm_ignore_extcca)
3772                 macmode = AR_2040_JOINED_RX_CLEAR;
3773         else
3774                 macmode = 0;
3775
3776         REG_WRITE(ah, AR_2040_MODE, macmode);
3777 }
3778
3779 /***************************/
3780 /*  Bluetooth Coexistence  */
3781 /***************************/
3782
3783 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3784 {
3785         /* connect bt_active to baseband */
3786         REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3787                         (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3788                          AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3789
3790         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3791                         AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3792
3793         /* Set input mux for bt_active to gpio pin */
3794         REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3795                         AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3796                         ah->btactive_gpio);
3797
3798         /* Configure the desired gpio port for input */
3799         ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3800
3801         /* Configure the desired GPIO port for TX_FRAME output */
3802         ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3803                             AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3804 }