2 * linux/drivers/ide/pci/sc1200.c Version 0.95 Jun 16 2007
4 * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com>
5 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
7 * May be copied or modified under the terms of the GNU General Public License
9 * Development of this chipset driver was funded
10 * by the nice folks at National Semiconductor.
13 * Available from National Semiconductor
16 #include <linux/module.h>
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/delay.h>
20 #include <linux/timer.h>
22 #include <linux/ioport.h>
23 #include <linux/blkdev.h>
24 #include <linux/hdreg.h>
25 #include <linux/interrupt.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/ide.h>
33 #define SC1200_REV_A 0x00
34 #define SC1200_REV_B1 0x01
35 #define SC1200_REV_B3 0x02
36 #define SC1200_REV_C1 0x03
37 #define SC1200_REV_D1 0x04
39 #define PCI_CLK_33 0x00
40 #define PCI_CLK_48 0x01
41 #define PCI_CLK_66 0x02
42 #define PCI_CLK_33A 0x03
44 static unsigned short sc1200_get_pci_clock (void)
46 unsigned char chip_id, silicon_revision;
47 unsigned int pci_clock;
49 * Check the silicon revision, as not all versions of the chip
50 * have the register with the fast PCI bus timings.
52 chip_id = inb (0x903c);
53 silicon_revision = inb (0x903d);
55 // Read the fast pci clock frequency
56 if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) {
57 pci_clock = PCI_CLK_33;
59 // check clock generator configuration (cfcc)
60 // the clock is in bits 8 and 9 of this word
62 pci_clock = inw (0x901e);
65 if (pci_clock == PCI_CLK_33A)
66 pci_clock = PCI_CLK_33;
71 extern char *ide_xfer_verbose (byte xfer_rate);
74 * Set a new transfer mode at the drive
76 static int sc1200_set_xfer_mode (ide_drive_t *drive, byte mode)
78 printk("%s: sc1200_set_xfer_mode(%s)\n", drive->name, ide_xfer_verbose(mode));
79 return ide_config_drive_speed(drive, mode);
83 * Here are the standard PIO mode 0-4 timings for each "format".
84 * Format-0 uses fast data reg timings, with slower command reg timings.
85 * Format-1 uses fast timings for all registers, but won't work with all drives.
87 static const unsigned int sc1200_pio_timings[4][5] =
88 {{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz
89 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz
90 {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz
91 {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz
94 * After chip reset, the PIO timings are set to 0x00009172, which is not valid.
96 //#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)
98 static void sc1200_tunepio(ide_drive_t *drive, u8 pio)
100 ide_hwif_t *hwif = drive->hwif;
101 struct pci_dev *pdev = hwif->pci_dev;
102 unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0;
104 pci_read_config_dword(pdev, basereg + 4, &format);
105 format = (format >> 31) & 1;
107 format += sc1200_get_pci_clock();
108 pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3),
109 sc1200_pio_timings[format][pio]);
113 * The SC1200 specifies that two drives sharing a cable cannot mix
114 * UDMA/MDMA. It has to be one or the other, for the pair, though
115 * different timings can still be chosen for each drive. We could
116 * set the appropriate timing bits on the fly, but that might be
117 * a bit confusing. So, for now we statically handle this requirement
118 * by looking at our mate drive to see what it is capable of, before
119 * choosing a mode for our own drive.
121 static u8 sc1200_udma_filter(ide_drive_t *drive)
123 ide_hwif_t *hwif = drive->hwif;
124 ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
125 struct hd_driveid *mateid = mate->id;
126 u8 mask = hwif->ultra_mask;
128 if (mate->present == 0)
131 if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
132 if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
134 if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
141 static int sc1200_tune_chipset(ide_drive_t *drive, const u8 mode)
143 ide_hwif_t *hwif = HWIF(drive);
144 int unit = drive->select.b.unit;
145 unsigned int reg, timings;
146 unsigned short pci_clock;
147 unsigned int basereg = hwif->channel ? 0x50 : 0x40;
150 * Tell the drive to switch to the new mode; abort on failure.
152 if (sc1200_set_xfer_mode(drive, mode))
153 return 1; /* failure */
155 pci_clock = sc1200_get_pci_clock();
158 * Now tune the chipset to match the drive:
160 * Note that each DMA mode has several timings associated with it.
161 * The correct timing depends on the fast PCI clock freq.
167 case PCI_CLK_33: timings = 0x00921250; break;
168 case PCI_CLK_48: timings = 0x00932470; break;
169 case PCI_CLK_66: timings = 0x009436a1; break;
174 case PCI_CLK_33: timings = 0x00911140; break;
175 case PCI_CLK_48: timings = 0x00922260; break;
176 case PCI_CLK_66: timings = 0x00933481; break;
181 case PCI_CLK_33: timings = 0x00911030; break;
182 case PCI_CLK_48: timings = 0x00922140; break;
183 case PCI_CLK_66: timings = 0x00923261; break;
188 case PCI_CLK_33: timings = 0x00077771; break;
189 case PCI_CLK_48: timings = 0x000bbbb2; break;
190 case PCI_CLK_66: timings = 0x000ffff3; break;
195 case PCI_CLK_33: timings = 0x00012121; break;
196 case PCI_CLK_48: timings = 0x00024241; break;
197 case PCI_CLK_66: timings = 0x00035352; break;
202 case PCI_CLK_33: timings = 0x00002020; break;
203 case PCI_CLK_48: timings = 0x00013131; break;
204 case PCI_CLK_66: timings = 0x00015151; break;
212 if (unit == 0) { /* are we configuring drive0? */
213 pci_read_config_dword(hwif->pci_dev, basereg+4, ®);
214 timings |= reg & 0x80000000; /* preserve PIO format bit */
215 pci_write_config_dword(hwif->pci_dev, basereg+4, timings);
217 pci_write_config_dword(hwif->pci_dev, basereg+12, timings);
220 return 0; /* success */
224 * sc1200_config_dma() handles selection/setting of DMA/UDMA modes
225 * for both the chipset and drive.
227 static int sc1200_config_dma (ide_drive_t *drive)
229 if (ide_tune_dma(drive))
236 /* Replacement for the standard ide_dma_end action in
239 * returns 1 on error, 0 otherwise
241 static int sc1200_ide_dma_end (ide_drive_t *drive)
243 ide_hwif_t *hwif = HWIF(drive);
244 unsigned long dma_base = hwif->dma_base;
247 dma_stat = inb(dma_base+2); /* get DMA status */
250 printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
251 dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2));
253 outb(dma_stat|0x1b, dma_base+2); /* clear the INTR & ERROR bits */
254 outb(inb(dma_base)&~1, dma_base); /* !! DO THIS HERE !! stop DMA */
256 drive->waiting_for_dma = 0;
257 ide_destroy_dmatable(drive); /* purge DMA mappings */
259 return (dma_stat & 7) != 4; /* verify good DMA status */
263 * sc1200_set_pio_mode() handles setting of PIO modes
264 * for both the chipset and drive.
266 * All existing BIOSs for this chipset guarantee that all drives
267 * will have valid default PIO timings set up before we get here.
270 static void sc1200_set_pio_mode(ide_drive_t *drive, const u8 pio)
272 ide_hwif_t *hwif = HWIF(drive);
276 * bad abuse of ->set_pio_mode interface
279 case 200: mode = XFER_UDMA_0; break;
280 case 201: mode = XFER_UDMA_1; break;
281 case 202: mode = XFER_UDMA_2; break;
282 case 100: mode = XFER_MW_DMA_0; break;
283 case 101: mode = XFER_MW_DMA_1; break;
284 case 102: mode = XFER_MW_DMA_2; break;
287 printk("SC1200: %s: changing (U)DMA mode\n", drive->name);
288 hwif->dma_off_quietly(drive);
289 if (sc1200_tune_chipset(drive, mode) == 0)
290 hwif->dma_host_on(drive);
294 if (sc1200_set_xfer_mode(drive, XFER_PIO_0 + pio) == 0)
295 sc1200_tunepio(drive, pio);
299 static ide_hwif_t *lookup_pci_dev (ide_hwif_t *prev, struct pci_dev *dev)
303 for (h = 0; h < MAX_HWIFS; h++) {
304 ide_hwif_t *hwif = &ide_hwifs[h];
307 prev = NULL; // found previous, now look for next match
309 if (hwif && hwif->pci_dev == dev)
310 return hwif; // found next match
313 return NULL; // not found
316 typedef struct sc1200_saved_state_s {
318 } sc1200_saved_state_t;
321 static int sc1200_suspend (struct pci_dev *dev, pm_message_t state)
323 ide_hwif_t *hwif = NULL;
325 printk("SC1200: suspend(%u)\n", state.event);
327 if (state.event == PM_EVENT_ON) {
328 // we only save state when going from full power to less
331 // Loop over all interfaces that are part of this PCI device:
333 while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) {
334 sc1200_saved_state_t *ss;
335 unsigned int basereg, r;
337 // allocate a permanent save area, if not already allocated
339 ss = (sc1200_saved_state_t *)hwif->config_data;
341 ss = kmalloc(sizeof(sc1200_saved_state_t), GFP_KERNEL);
344 hwif->config_data = (unsigned long)ss;
346 ss = (sc1200_saved_state_t *)hwif->config_data;
348 // Save timing registers: this may be unnecessary if
351 basereg = hwif->channel ? 0x50 : 0x40;
352 for (r = 0; r < 4; ++r) {
353 pci_read_config_dword (hwif->pci_dev, basereg + (r<<2), &ss->regs[r]);
358 /* You don't need to iterate over disks -- sysfs should have done that for you already */
360 pci_disable_device(dev);
361 pci_set_power_state(dev, pci_choose_state(dev, state));
362 dev->current_state = state.event;
366 static int sc1200_resume (struct pci_dev *dev)
368 ide_hwif_t *hwif = NULL;
370 pci_set_power_state(dev, PCI_D0); // bring chip back from sleep state
371 dev->current_state = PM_EVENT_ON;
372 pci_enable_device(dev);
374 // loop over all interfaces that are part of this pci device:
376 while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) {
377 unsigned int basereg, r;
378 sc1200_saved_state_t *ss = (sc1200_saved_state_t *)hwif->config_data;
381 // Restore timing registers: this may be unnecessary if BIOS also does it
383 basereg = hwif->channel ? 0x50 : 0x40;
385 for (r = 0; r < 4; ++r) {
386 pci_write_config_dword(hwif->pci_dev, basereg + (r<<2), ss->regs[r]);
395 * This gets invoked by the IDE driver once for each channel,
396 * and performs channel-specific pre-initialization before drive probing.
398 static void __devinit init_hwif_sc1200 (ide_hwif_t *hwif)
401 hwif->serialized = hwif->mate->serialized = 1;
403 if (hwif->dma_base) {
404 hwif->udma_filter = sc1200_udma_filter;
405 hwif->ide_dma_check = &sc1200_config_dma;
406 hwif->ide_dma_end = &sc1200_ide_dma_end;
410 hwif->set_pio_mode = &sc1200_set_pio_mode;
411 hwif->speedproc = &sc1200_tune_chipset;
414 hwif->ultra_mask = 0x07;
415 hwif->mwdma_mask = 0x07;
417 hwif->drives[0].autodma = hwif->autodma;
418 hwif->drives[1].autodma = hwif->autodma;
421 static ide_pci_device_t sc1200_chipset __devinitdata = {
423 .init_hwif = init_hwif_sc1200,
425 .bootable = ON_BOARD,
426 .host_flags = IDE_HFLAG_ABUSE_DMA_MODES,
427 .pio_mask = ATA_PIO4,
430 static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
432 return ide_setup_pci_device(dev, &sc1200_chipset);
435 static struct pci_device_id sc1200_pci_tbl[] = {
436 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0},
439 MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl);
441 static struct pci_driver driver = {
442 .name = "SC1200_IDE",
443 .id_table = sc1200_pci_tbl,
444 .probe = sc1200_init_one,
446 .suspend = sc1200_suspend,
447 .resume = sc1200_resume,
451 static int __init sc1200_ide_init(void)
453 return ide_pci_register_driver(&driver);
456 module_init(sc1200_ide_init);
458 MODULE_AUTHOR("Mark Lord");
459 MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
460 MODULE_LICENSE("GPL");