fix build bug in "x86: add PCI extended config space access for AMD Barcelona"
[linux-2.6] / arch / x86 / kernel / cpu / amd.c
1 #include <linux/init.h>
2 #include <linux/bitops.h>
3 #include <linux/mm.h>
4 #include <asm/io.h>
5 #include <asm/processor.h>
6 #include <asm/apic.h>
7 #include <asm/mmconfig.h>
8
9 #include <mach_apic.h>
10 #include "../setup.h"
11 #include "cpu.h"
12
13 /*
14  *      B step AMD K6 before B 9730xxxx have hardware bugs that can cause
15  *      misexecution of code under Linux. Owners of such processors should
16  *      contact AMD for precise details and a CPU swap.
17  *
18  *      See     http://www.multimania.com/poulot/k6bug.html
19  *              http://www.amd.com/K6/k6docs/revgd.html
20  *
21  *      The following test is erm.. interesting. AMD neglected to up
22  *      the chip setting when fixing the bug but they also tweaked some
23  *      performance at the same time..
24  */
25
26 extern void vide(void);
27 __asm__(".align 4\nvide: ret");
28
29 #ifdef CONFIG_X86_LOCAL_APIC
30 #define ENABLE_C1E_MASK         0x18000000
31 #define CPUID_PROCESSOR_SIGNATURE       1
32 #define CPUID_XFAM              0x0ff00000
33 #define CPUID_XFAM_K8           0x00000000
34 #define CPUID_XFAM_10H          0x00100000
35 #define CPUID_XFAM_11H          0x00200000
36 #define CPUID_XMOD              0x000f0000
37 #define CPUID_XMOD_REV_F        0x00040000
38
39 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
40 static __cpuinit int amd_apic_timer_broken(void)
41 {
42         u32 lo, hi;
43         u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
44         switch (eax & CPUID_XFAM) {
45         case CPUID_XFAM_K8:
46                 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
47                         break;
48         case CPUID_XFAM_10H:
49         case CPUID_XFAM_11H:
50                 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
51                 if (lo & ENABLE_C1E_MASK) {
52                         if (smp_processor_id() != boot_cpu_physical_apicid)
53                                 printk(KERN_INFO "AMD C1E detected late. "
54                                        "        Force timer broadcast.\n");
55                         return 1;
56                 }
57                 break;
58         default:
59                 /* err on the side of caution */
60                 return 1;
61         }
62         return 0;
63 }
64 #endif
65
66 int force_mwait __cpuinitdata;
67
68 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
69 {
70         if (cpuid_eax(0x80000000) >= 0x80000007) {
71                 c->x86_power = cpuid_edx(0x80000007);
72                 if (c->x86_power & (1<<8))
73                         set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
74         }
75 }
76
77 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
78 {
79         u32 l, h;
80         int mbytes = num_physpages >> (20-PAGE_SHIFT);
81         int r;
82
83 #ifdef CONFIG_SMP
84         unsigned long long value;
85
86         /*
87          * Disable TLB flush filter by setting HWCR.FFDIS on K8
88          * bit 6 of msr C001_0015
89          *
90          * Errata 63 for SH-B3 steppings
91          * Errata 122 for all steppings (F+ have it disabled by default)
92          */
93         if (c->x86 == 15) {
94                 rdmsrl(MSR_K7_HWCR, value);
95                 value |= 1 << 6;
96                 wrmsrl(MSR_K7_HWCR, value);
97         }
98 #endif
99
100         early_init_amd(c);
101
102         /*
103          *      FIXME: We should handle the K5 here. Set up the write
104          *      range and also turn on MSR 83 bits 4 and 31 (write alloc,
105          *      no bus pipeline)
106          */
107
108         /*
109          * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
110          * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
111          */
112         clear_cpu_cap(c, 0*32+31);
113
114         r = get_model_name(c);
115
116         switch (c->x86) {
117         case 4:
118                 /*
119                  * General Systems BIOSen alias the cpu frequency registers
120                  * of the Elan at 0x000df000. Unfortuantly, one of the Linux
121                  * drivers subsequently pokes it, and changes the CPU speed.
122                  * Workaround : Remove the unneeded alias.
123                  */
124 #define CBAR            (0xfffc) /* Configuration Base Address  (32-bit) */
125 #define CBAR_ENB        (0x80000000)
126 #define CBAR_KEY        (0X000000CB)
127                         if (c->x86_model == 9 || c->x86_model == 10) {
128                                 if (inl (CBAR) & CBAR_ENB)
129                                         outl (0 | CBAR_KEY, CBAR);
130                         }
131                         break;
132         case 5:
133                         if (c->x86_model < 6) {
134                                 /* Based on AMD doc 20734R - June 2000 */
135                                 if (c->x86_model == 0) {
136                                         clear_cpu_cap(c, X86_FEATURE_APIC);
137                                         set_cpu_cap(c, X86_FEATURE_PGE);
138                                 }
139                                 break;
140                         }
141
142                         if (c->x86_model == 6 && c->x86_mask == 1) {
143                                 const int K6_BUG_LOOP = 1000000;
144                                 int n;
145                                 void (*f_vide)(void);
146                                 unsigned long d, d2;
147
148                                 printk(KERN_INFO "AMD K6 stepping B detected - ");
149
150                                 /*
151                                  * It looks like AMD fixed the 2.6.2 bug and improved indirect
152                                  * calls at the same time.
153                                  */
154
155                                 n = K6_BUG_LOOP;
156                                 f_vide = vide;
157                                 rdtscl(d);
158                                 while (n--)
159                                         f_vide();
160                                 rdtscl(d2);
161                                 d = d2-d;
162
163                                 if (d > 20*K6_BUG_LOOP)
164                                         printk("system stability may be impaired when more than 32 MB are used.\n");
165                                 else
166                                         printk("probably OK (after B9730xxxx).\n");
167                                 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
168                         }
169
170                         /* K6 with old style WHCR */
171                         if (c->x86_model < 8 ||
172                            (c->x86_model == 8 && c->x86_mask < 8)) {
173                                 /* We can only write allocate on the low 508Mb */
174                                 if (mbytes > 508)
175                                         mbytes = 508;
176
177                                 rdmsr(MSR_K6_WHCR, l, h);
178                                 if ((l&0x0000FFFF) == 0) {
179                                         unsigned long flags;
180                                         l = (1<<0)|((mbytes/4)<<1);
181                                         local_irq_save(flags);
182                                         wbinvd();
183                                         wrmsr(MSR_K6_WHCR, l, h);
184                                         local_irq_restore(flags);
185                                         printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
186                                                 mbytes);
187                                 }
188                                 break;
189                         }
190
191                         if ((c->x86_model == 8 && c->x86_mask > 7) ||
192                              c->x86_model == 9 || c->x86_model == 13) {
193                                 /* The more serious chips .. */
194
195                                 if (mbytes > 4092)
196                                         mbytes = 4092;
197
198                                 rdmsr(MSR_K6_WHCR, l, h);
199                                 if ((l&0xFFFF0000) == 0) {
200                                         unsigned long flags;
201                                         l = ((mbytes>>2)<<22)|(1<<16);
202                                         local_irq_save(flags);
203                                         wbinvd();
204                                         wrmsr(MSR_K6_WHCR, l, h);
205                                         local_irq_restore(flags);
206                                         printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
207                                                 mbytes);
208                                 }
209
210                                 /*  Set MTRR capability flag if appropriate */
211                                 if (c->x86_model == 13 || c->x86_model == 9 ||
212                                    (c->x86_model == 8 && c->x86_mask >= 8))
213                                         set_cpu_cap(c, X86_FEATURE_K6_MTRR);
214                                 break;
215                         }
216
217                         if (c->x86_model == 10) {
218                                 /* AMD Geode LX is model 10 */
219                                 /* placeholder for any needed mods */
220                                 break;
221                         }
222                         break;
223         case 6: /* An Athlon/Duron */
224
225                         /*
226                          * Bit 15 of Athlon specific MSR 15, needs to be 0
227                          * to enable SSE on Palomino/Morgan/Barton CPU's.
228                          * If the BIOS didn't enable it already, enable it here.
229                          */
230                         if (c->x86_model >= 6 && c->x86_model <= 10) {
231                                 if (!cpu_has(c, X86_FEATURE_XMM)) {
232                                         printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
233                                         rdmsr(MSR_K7_HWCR, l, h);
234                                         l &= ~0x00008000;
235                                         wrmsr(MSR_K7_HWCR, l, h);
236                                         set_cpu_cap(c, X86_FEATURE_XMM);
237                                 }
238                         }
239
240                         /*
241                          * It's been determined by AMD that Athlons since model 8 stepping 1
242                          * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
243                          * As per AMD technical note 27212 0.2
244                          */
245                         if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
246                                 rdmsr(MSR_K7_CLK_CTL, l, h);
247                                 if ((l & 0xfff00000) != 0x20000000) {
248                                         printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
249                                                 ((l & 0x000fffff)|0x20000000));
250                                         wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
251                                 }
252                         }
253                         break;
254         }
255
256         switch (c->x86) {
257         case 15:
258         /* Use K8 tuning for Fam10h and Fam11h */
259         case 0x10:
260         case 0x11:
261                 set_cpu_cap(c, X86_FEATURE_K8);
262                 break;
263         case 6:
264                 set_cpu_cap(c, X86_FEATURE_K7);
265                 break;
266         }
267         if (c->x86 >= 6)
268                 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
269
270         display_cacheinfo(c);
271
272         if (cpuid_eax(0x80000000) >= 0x80000008)
273                 c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
274
275 #ifdef CONFIG_X86_HT
276         /*
277          * On a AMD multi core setup the lower bits of the APIC id
278          * distinguish the cores.
279          */
280         if (c->x86_max_cores > 1) {
281                 int cpu = smp_processor_id();
282                 unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;
283
284                 if (bits == 0) {
285                         while ((1 << bits) < c->x86_max_cores)
286                                 bits++;
287                 }
288                 c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
289                 c->phys_proc_id >>= bits;
290                 printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
291                        cpu, c->x86_max_cores, c->cpu_core_id);
292         }
293 #endif
294
295         if (cpuid_eax(0x80000000) >= 0x80000006) {
296                 if ((c->x86 == 0x10) && (cpuid_edx(0x80000006) & 0xf000))
297                         num_cache_leaves = 4;
298                 else
299                         num_cache_leaves = 3;
300         }
301
302 #ifdef CONFIG_X86_LOCAL_APIC
303         if (amd_apic_timer_broken())
304                 local_apic_timer_disabled = 1;
305 #endif
306
307         /* K6s reports MCEs but don't actually have all the MSRs */
308         if (c->x86 < 6)
309                 clear_cpu_cap(c, X86_FEATURE_MCE);
310
311         if (cpu_has_xmm2)
312                 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
313
314         if (c->x86 == 0x10)
315                 amd_enable_pci_ext_cfg(c);
316 }
317
318 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
319 {
320         /* AMD errata T13 (order #21922) */
321         if ((c->x86 == 6)) {
322                 if (c->x86_model == 3 && c->x86_mask == 0)      /* Duron Rev A0 */
323                         size = 64;
324                 if (c->x86_model == 4 &&
325                     (c->x86_mask == 0 || c->x86_mask == 1))     /* Tbird rev A1/A2 */
326                         size = 256;
327         }
328         return size;
329 }
330
331 static struct cpu_dev amd_cpu_dev __cpuinitdata = {
332         .c_vendor       = "AMD",
333         .c_ident        = { "AuthenticAMD" },
334         .c_models = {
335                 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
336                   {
337                           [3] = "486 DX/2",
338                           [7] = "486 DX/2-WB",
339                           [8] = "486 DX/4",
340                           [9] = "486 DX/4-WB",
341                           [14] = "Am5x86-WT",
342                           [15] = "Am5x86-WB"
343                   }
344                 },
345         },
346         .c_early_init   = early_init_amd,
347         .c_init         = init_amd,
348         .c_size_cache   = amd_size_cache,
349 };
350
351 cpu_vendor_dev_register(X86_VENDOR_AMD, &amd_cpu_dev);