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   1 /*
   2  *  arch/ppc64/kernel/cputable.c
   3  *
   4  *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
   5  *
   6  *  Modifications for ppc64:
   7  *      Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
   8  *
   9  *  This program is free software; you can redistribute it and/or
  10  *  modify it under the terms of the GNU General Public License
  11  *  as published by the Free Software Foundation; either version
  12  *  2 of the License, or (at your option) any later version.
  13  */
  14
  15 #include <linux/config.h>
  16 #include <linux/string.h>
  17 #include <linux/sched.h>
  18 #include <linux/threads.h>
  19 #include <linux/init.h>
  20 #include <linux/module.h>
  21
  22 #include <asm/cputable.h>
  23 #include <asm/firmware.h>
  24
  25 struct cpu_spec* cur_cpu_spec = NULL;
  26 EXPORT_SYMBOL(cur_cpu_spec);
  27 unsigned long ppc64_firmware_features;
  28
  29 /* NOTE:
  30  * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  31  * the responsibility of the appropriate CPU save/restore functions to
  32  * eventually copy these settings over. Those save/restore aren't yet
  33  * part of the cputable though. That has to be fixed for both ppc32
  34  * and ppc64
  35  */
  36 extern void __setup_cpu_power3(unsigned long offset, struct cpu_spec* spec);
  37 extern void __setup_cpu_power4(unsigned long offset, struct cpu_spec* spec);
  38 extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  39 extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
  40
  41
  42 /* We only set the altivec features if the kernel was compiled with altivec
  43  * support
  44  */
  45 #ifdef CONFIG_ALTIVEC
  46 #define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
  47 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
  48 #else
  49 #define CPU_FTR_ALTIVEC_COMP    0
  50 #define PPC_FEATURE_HAS_ALTIVEC_COMP    0
  51 #endif
  52
  53 struct cpu_spec cpu_specs[] = {
  54         {       /* Power3 */
  55                 .pvr_mask               = 0xffff0000,
  56                 .pvr_value              = 0x00400000,
  57                 .cpu_name               = "POWER3 (630)",
  58                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
  59                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
  60                         CPU_FTR_PMC8,
  61                 .cpu_user_features = COMMON_USER_PPC64,
  62                 .icache_bsize           = 128,
  63                 .dcache_bsize           = 128,
  64                 .cpu_setup              = __setup_cpu_power3,
  65         },
  66         {       /* Power3+ */
  67                 .pvr_mask               = 0xffff0000,
  68                 .pvr_value              = 0x00410000,
  69                 .cpu_name               = "POWER3 (630+)",
  70                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
  71                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
  72                         CPU_FTR_PMC8,
  73                 .cpu_user_features      = COMMON_USER_PPC64,
  74                 .icache_bsize           = 128,
  75                 .dcache_bsize           = 128,
  76                 .cpu_setup              = __setup_cpu_power3,
  77         },
  78         {       /* Northstar */
  79                 .pvr_mask               = 0xffff0000,
  80                 .pvr_value              = 0x00330000,
  81                 .cpu_name               = "RS64-II (northstar)",
  82                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
  83                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
  84                         CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
  85                 .cpu_user_features      = COMMON_USER_PPC64,
  86                 .icache_bsize           = 128,
  87                 .dcache_bsize           = 128,
  88                 .cpu_setup              = __setup_cpu_power3,
  89         },
  90         {       /* Pulsar */
  91                 .pvr_mask               = 0xffff0000,
  92                 .pvr_value              = 0x00340000,
  93                 .cpu_name               = "RS64-III (pulsar)",
  94                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
  95                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
  96                         CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
  97                 .cpu_user_features      = COMMON_USER_PPC64,
  98                 .icache_bsize           = 128,
  99                 .dcache_bsize           = 128,
 100                 .cpu_setup              = __setup_cpu_power3,
 101         },
 102         {       /* I-star */
 103                 .pvr_mask               = 0xffff0000,
 104                 .pvr_value              = 0x00360000,
 105                 .cpu_name               = "RS64-III (icestar)",
 106                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 107                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
 108                         CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
 109                 .cpu_user_features      = COMMON_USER_PPC64,
 110                 .icache_bsize           = 128,
 111                 .dcache_bsize           = 128,
 112                 .cpu_setup              = __setup_cpu_power3,
 113         },
 114         {       /* S-star */
 115                 .pvr_mask               = 0xffff0000,
 116                 .pvr_value              = 0x00370000,
 117                 .cpu_name               = "RS64-IV (sstar)",
 118                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 119                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
 120                         CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
 121                 .cpu_user_features      = COMMON_USER_PPC64,
 122                 .icache_bsize           = 128,
 123                 .dcache_bsize           = 128,
 124                 .cpu_setup              = __setup_cpu_power3,
 125         },
 126         {       /* Power4 */
 127                 .pvr_mask               = 0xffff0000,
 128                 .pvr_value              = 0x00350000,
 129                 .cpu_name               = "POWER4 (gp)",
 130                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 131                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 132                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 133                 .cpu_user_features      = COMMON_USER_PPC64,
 134                 .icache_bsize           = 128,
 135                 .dcache_bsize           = 128,
 136                 .cpu_setup              = __setup_cpu_power4,
 137         },
 138         {       /* Power4+ */
 139                 .pvr_mask               = 0xffff0000,
 140                 .pvr_value              = 0x00380000,
 141                 .cpu_name               = "POWER4+ (gq)",
 142                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 143                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 144                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 145                 .cpu_user_features      = COMMON_USER_PPC64,
 146                 .icache_bsize           = 128,
 147                 .dcache_bsize           = 128,
 148                 .cpu_setup              = __setup_cpu_power4,
 149         },
 150         {       /* PPC970 */
 151                 .pvr_mask               = 0xffff0000,
 152                 .pvr_value              = 0x00390000,
 153                 .cpu_name               = "PPC970",
 154                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 155                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 156                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
 157                         CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 158                 .cpu_user_features      = COMMON_USER_PPC64 |
 159                         PPC_FEATURE_HAS_ALTIVEC_COMP,
 160                 .icache_bsize           = 128,
 161                 .dcache_bsize           = 128,
 162                 .cpu_setup              = __setup_cpu_ppc970,
 163         },
 164         {       /* PPC970FX */
 165                 .pvr_mask               = 0xffff0000,
 166                 .pvr_value              = 0x003c0000,
 167                 .cpu_name               = "PPC970FX",
 168                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 169                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 170                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
 171                         CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 172                 .cpu_user_features      = COMMON_USER_PPC64 |
 173                         PPC_FEATURE_HAS_ALTIVEC_COMP,
 174                 .icache_bsize           = 128,
 175                 .dcache_bsize           = 128,
 176                 .cpu_setup              = __setup_cpu_ppc970,
 177         },
 178         {       /* PPC970MP */
 179                 .pvr_mask               = 0xffff0000,
 180                 .pvr_value              = 0x00440000,
 181                 .cpu_name               = "PPC970MP",
 182                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 183                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 184                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
 185                         CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 186                 .cpu_user_features      = COMMON_USER_PPC64 |
 187                         PPC_FEATURE_HAS_ALTIVEC_COMP,
 188                 .icache_bsize           = 128,
 189                 .dcache_bsize           = 128,
 190                 .cpu_setup              = __setup_cpu_ppc970,
 191         },
 192         {       /* Power5 */
 193                 .pvr_mask               = 0xffff0000,
 194                 .pvr_value              = 0x003a0000,
 195                 .cpu_name               = "POWER5 (gr)",
 196                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 197                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 198                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
 199                         CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
 200                         CPU_FTR_MMCRA_SIHV,
 201                 .cpu_user_features      = COMMON_USER_PPC64,
 202                 .icache_bsize           = 128,
 203                 .dcache_bsize           = 128,
 204                 .cpu_setup              = __setup_cpu_power4,
 205         },
 206         {       /* Power5 */
 207                 .pvr_mask               = 0xffff0000,
 208                 .pvr_value              = 0x003b0000,
 209                 .cpu_name               = "POWER5 (gs)",
 210                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 211                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 212                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
 213                         CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
 214                         CPU_FTR_MMCRA_SIHV,
 215                 .cpu_user_features      = COMMON_USER_PPC64,
 216                 .icache_bsize           = 128,
 217                 .dcache_bsize           = 128,
 218                 .cpu_setup              = __setup_cpu_power4,
 219         },
 220         {       /* BE DD1.x */
 221                 .pvr_mask               = 0xffff0000,
 222                 .pvr_value              = 0x00700000,
 223                 .cpu_name               = "Broadband Engine",
 224                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 225                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 226                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
 227                         CPU_FTR_SMT,
 228                 .cpu_user_features      = COMMON_USER_PPC64 |
 229                         PPC_FEATURE_HAS_ALTIVEC_COMP,
 230                 .icache_bsize           = 128,
 231                 .dcache_bsize           = 128,
 232                 .cpu_setup              = __setup_cpu_be,
 233         },
 234         {       /* default match */
 235                 .pvr_mask               = 0x00000000,
 236                 .pvr_value              = 0x00000000,
 237                 .cpu_name               = "POWER4 (compatible)",
 238                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 239                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 240                         CPU_FTR_PPCAS_ARCH_V2,
 241                 .cpu_user_features      = COMMON_USER_PPC64,
 242                 .icache_bsize           = 128,
 243                 .dcache_bsize           = 128,
 244                 .cpu_setup              = __setup_cpu_power4,
 245         }
 246 };
 247
 248 firmware_feature_t firmware_features_table[FIRMWARE_MAX_FEATURES] = {
 249         {FW_FEATURE_PFT,                "hcall-pft"},
 250         {FW_FEATURE_TCE,                "hcall-tce"},
 251         {FW_FEATURE_SPRG0,              "hcall-sprg0"},
 252         {FW_FEATURE_DABR,               "hcall-dabr"},
 253         {FW_FEATURE_COPY,               "hcall-copy"},
 254         {FW_FEATURE_ASR,                "hcall-asr"},
 255         {FW_FEATURE_DEBUG,              "hcall-debug"},
 256         {FW_FEATURE_PERF,               "hcall-perf"},
 257         {FW_FEATURE_DUMP,               "hcall-dump"},
 258         {FW_FEATURE_INTERRUPT,          "hcall-interrupt"},
 259         {FW_FEATURE_MIGRATE,            "hcall-migrate"},
 260         {FW_FEATURE_PERFMON,            "hcall-perfmon"},
 261         {FW_FEATURE_CRQ,                "hcall-crq"},
 262         {FW_FEATURE_VIO,                "hcall-vio"},
 263         {FW_FEATURE_RDMA,               "hcall-rdma"},
 264         {FW_FEATURE_LLAN,               "hcall-lLAN"},
 265         {FW_FEATURE_BULK,               "hcall-bulk"},
 266         {FW_FEATURE_XDABR,              "hcall-xdabr"},
 267         {FW_FEATURE_MULTITCE,           "hcall-multi-tce"},
 268         {FW_FEATURE_SPLPAR,             "hcall-splpar"},
 269 };