1 /***************************************************************************
2 * Plug-in for PAS202BCB image sensor connected to the SN9C1xx PC Camera *
5 * Copyright (C) 2004 by Carlos Eduardo Medaglia Dyonisio *
6 * <medaglia@undl.org.br> *
7 * http://cadu.homelinux.com:8080/ *
9 * Support for SN9C103, DAC Magnitude, exposure and green gain controls *
10 * added by Luca Risolia <luca.risolia@studio.unibo.it> *
12 * This program is free software; you can redistribute it and/or modify *
13 * it under the terms of the GNU General Public License as published by *
14 * the Free Software Foundation; either version 2 of the License, or *
15 * (at your option) any later version. *
17 * This program is distributed in the hope that it will be useful, *
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
20 * GNU General Public License for more details. *
22 * You should have received a copy of the GNU General Public License *
23 * along with this program; if not, write to the Free Software *
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
25 ***************************************************************************/
27 #include <linux/delay.h>
28 #include "sn9c102_sensor.h"
31 static struct sn9c102_sensor pas202bcb;
34 static int pas202bcb_init(struct sn9c102_device* cam)
38 switch (sn9c102_get_bridge(cam)) {
41 err += sn9c102_write_reg(cam, 0x00, 0x10);
42 err += sn9c102_write_reg(cam, 0x00, 0x11);
43 err += sn9c102_write_reg(cam, 0x00, 0x14);
44 err += sn9c102_write_reg(cam, 0x20, 0x17);
45 err += sn9c102_write_reg(cam, 0x30, 0x19);
46 err += sn9c102_write_reg(cam, 0x09, 0x18);
49 err += sn9c102_write_reg(cam, 0x00, 0x02);
50 err += sn9c102_write_reg(cam, 0x00, 0x03);
51 err += sn9c102_write_reg(cam, 0x1a, 0x04);
52 err += sn9c102_write_reg(cam, 0x20, 0x05);
53 err += sn9c102_write_reg(cam, 0x20, 0x06);
54 err += sn9c102_write_reg(cam, 0x20, 0x07);
55 err += sn9c102_write_reg(cam, 0x00, 0x10);
56 err += sn9c102_write_reg(cam, 0x00, 0x11);
57 err += sn9c102_write_reg(cam, 0x00, 0x14);
58 err += sn9c102_write_reg(cam, 0x20, 0x17);
59 err += sn9c102_write_reg(cam, 0x30, 0x19);
60 err += sn9c102_write_reg(cam, 0x09, 0x18);
61 err += sn9c102_write_reg(cam, 0x02, 0x1c);
62 err += sn9c102_write_reg(cam, 0x03, 0x1d);
63 err += sn9c102_write_reg(cam, 0x0f, 0x1e);
64 err += sn9c102_write_reg(cam, 0x0c, 0x1f);
65 err += sn9c102_write_reg(cam, 0x00, 0x20);
66 err += sn9c102_write_reg(cam, 0x10, 0x21);
67 err += sn9c102_write_reg(cam, 0x20, 0x22);
68 err += sn9c102_write_reg(cam, 0x30, 0x23);
69 err += sn9c102_write_reg(cam, 0x40, 0x24);
70 err += sn9c102_write_reg(cam, 0x50, 0x25);
71 err += sn9c102_write_reg(cam, 0x60, 0x26);
72 err += sn9c102_write_reg(cam, 0x70, 0x27);
73 err += sn9c102_write_reg(cam, 0x80, 0x28);
74 err += sn9c102_write_reg(cam, 0x90, 0x29);
75 err += sn9c102_write_reg(cam, 0xa0, 0x2a);
76 err += sn9c102_write_reg(cam, 0xb0, 0x2b);
77 err += sn9c102_write_reg(cam, 0xc0, 0x2c);
78 err += sn9c102_write_reg(cam, 0xd0, 0x2d);
79 err += sn9c102_write_reg(cam, 0xe0, 0x2e);
80 err += sn9c102_write_reg(cam, 0xf0, 0x2f);
81 err += sn9c102_write_reg(cam, 0xff, 0x30);
87 err += sn9c102_i2c_write(cam, 0x02, 0x14);
88 err += sn9c102_i2c_write(cam, 0x03, 0x40);
89 err += sn9c102_i2c_write(cam, 0x0d, 0x2c);
90 err += sn9c102_i2c_write(cam, 0x0e, 0x01);
91 err += sn9c102_i2c_write(cam, 0x0f, 0xa9);
92 err += sn9c102_i2c_write(cam, 0x10, 0x08);
93 err += sn9c102_i2c_write(cam, 0x13, 0x63);
94 err += sn9c102_i2c_write(cam, 0x15, 0x70);
95 err += sn9c102_i2c_write(cam, 0x11, 0x01);
103 static int pas202bcb_get_ctrl(struct sn9c102_device* cam,
104 struct v4l2_control* ctrl)
107 case V4L2_CID_EXPOSURE:
109 int r1 = sn9c102_i2c_read(cam, 0x04),
110 r2 = sn9c102_i2c_read(cam, 0x05);
111 if (r1 < 0 || r2 < 0)
113 ctrl->value = (r1 << 6) | (r2 & 0x3f);
116 case V4L2_CID_RED_BALANCE:
117 if ((ctrl->value = sn9c102_i2c_read(cam, 0x09)) < 0)
121 case V4L2_CID_BLUE_BALANCE:
122 if ((ctrl->value = sn9c102_i2c_read(cam, 0x07)) < 0)
127 if ((ctrl->value = sn9c102_i2c_read(cam, 0x10)) < 0)
131 case SN9C102_V4L2_CID_GREEN_BALANCE:
132 if ((ctrl->value = sn9c102_i2c_read(cam, 0x08)) < 0)
136 case SN9C102_V4L2_CID_DAC_MAGNITUDE:
137 if ((ctrl->value = sn9c102_i2c_read(cam, 0x0c)) < 0)
146 static int pas202bcb_set_pix_format(struct sn9c102_device* cam,
147 const struct v4l2_pix_format* pix)
151 if (pix->pixelformat == V4L2_PIX_FMT_SN9C10X)
152 err += sn9c102_write_reg(cam, 0x28, 0x17);
154 err += sn9c102_write_reg(cam, 0x20, 0x17);
160 static int pas202bcb_set_ctrl(struct sn9c102_device* cam,
161 const struct v4l2_control* ctrl)
166 case V4L2_CID_EXPOSURE:
167 err += sn9c102_i2c_write(cam, 0x04, ctrl->value >> 6);
168 err += sn9c102_i2c_write(cam, 0x05, ctrl->value & 0x3f);
170 case V4L2_CID_RED_BALANCE:
171 err += sn9c102_i2c_write(cam, 0x09, ctrl->value);
173 case V4L2_CID_BLUE_BALANCE:
174 err += sn9c102_i2c_write(cam, 0x07, ctrl->value);
177 err += sn9c102_i2c_write(cam, 0x10, ctrl->value);
179 case SN9C102_V4L2_CID_GREEN_BALANCE:
180 err += sn9c102_i2c_write(cam, 0x08, ctrl->value);
182 case SN9C102_V4L2_CID_DAC_MAGNITUDE:
183 err += sn9c102_i2c_write(cam, 0x0c, ctrl->value);
188 err += sn9c102_i2c_write(cam, 0x11, 0x01);
190 return err ? -EIO : 0;
194 static int pas202bcb_set_crop(struct sn9c102_device* cam,
195 const struct v4l2_rect* rect)
197 struct sn9c102_sensor* s = sn9c102_get_sensor(cam);
200 v_start = (u8)(rect->top - s->cropcap.bounds.top) + 3;
202 switch (sn9c102_get_bridge(cam)) {
205 h_start = (u8)(rect->left - s->cropcap.bounds.left) + 4;
208 h_start = (u8)(rect->left - s->cropcap.bounds.left) + 3;
214 err += sn9c102_write_reg(cam, h_start, 0x12);
215 err += sn9c102_write_reg(cam, v_start, 0x13);
221 static struct sn9c102_sensor pas202bcb = {
223 .maintainer = "Luca Risolia <luca.risolia@studio.unibo.it>",
224 .supported_bridge = BRIDGE_SN9C101 | BRIDGE_SN9C102 | BRIDGE_SN9C103,
225 .sysfs_ops = SN9C102_I2C_READ | SN9C102_I2C_WRITE,
226 .frequency = SN9C102_I2C_400KHZ | SN9C102_I2C_100KHZ,
227 .interface = SN9C102_I2C_2WIRES,
228 .i2c_slave_id = 0x40,
229 .init = &pas202bcb_init,
232 .id = V4L2_CID_EXPOSURE,
233 .type = V4L2_CTRL_TYPE_INTEGER,
238 .default_value = 0x01e5,
243 .type = V4L2_CTRL_TYPE_INTEGER,
244 .name = "global gain",
248 .default_value = 0x0b,
252 .id = V4L2_CID_RED_BALANCE,
253 .type = V4L2_CTRL_TYPE_INTEGER,
254 .name = "red balance",
258 .default_value = 0x00,
262 .id = V4L2_CID_BLUE_BALANCE,
263 .type = V4L2_CTRL_TYPE_INTEGER,
264 .name = "blue balance",
268 .default_value = 0x05,
272 .id = SN9C102_V4L2_CID_GREEN_BALANCE,
273 .type = V4L2_CTRL_TYPE_INTEGER,
274 .name = "green balance",
278 .default_value = 0x00,
282 .id = SN9C102_V4L2_CID_DAC_MAGNITUDE,
283 .type = V4L2_CTRL_TYPE_INTEGER,
284 .name = "DAC magnitude",
288 .default_value = 0x04,
292 .get_ctrl = &pas202bcb_get_ctrl,
293 .set_ctrl = &pas202bcb_set_ctrl,
308 .set_crop = &pas202bcb_set_crop,
312 .pixelformat = V4L2_PIX_FMT_SBGGR8,
315 .set_pix_format = &pas202bcb_set_pix_format
319 int sn9c102_probe_pas202bcb(struct sn9c102_device* cam)
321 int r0 = 0, r1 = 0, err = 0;
322 unsigned int pid = 0;
325 * Minimal initialization to enable the I2C communication
326 * NOTE: do NOT change the values!
328 switch (sn9c102_get_bridge(cam)) {
331 err += sn9c102_write_reg(cam, 0x01, 0x01); /* power down */
332 err += sn9c102_write_reg(cam, 0x40, 0x01); /* power on */
333 err += sn9c102_write_reg(cam, 0x28, 0x17); /* clock 24 MHz */
335 case BRIDGE_SN9C103: /* do _not_ change anything! */
336 err += sn9c102_write_reg(cam, 0x09, 0x01);
337 err += sn9c102_write_reg(cam, 0x44, 0x01);
338 err += sn9c102_write_reg(cam, 0x44, 0x02);
339 err += sn9c102_write_reg(cam, 0x29, 0x17);
345 r0 = sn9c102_i2c_try_read(cam, &pas202bcb, 0x00);
346 r1 = sn9c102_i2c_try_read(cam, &pas202bcb, 0x01);
348 if (err || r0 < 0 || r1 < 0)
351 pid = (r0 << 4) | ((r1 & 0xf0) >> 4);
355 sn9c102_attach_sensor(cam, &pas202bcb);