Merge git://git.kernel.org/pub/scm/linux/kernel/git/sam/kbuild-fixes
[linux-2.6] / drivers / video / pxafb.c
1 /*
2  *  linux/drivers/video/pxafb.c
3  *
4  *  Copyright (C) 1999 Eric A. Thomas.
5  *  Copyright (C) 2004 Jean-Frederic Clere.
6  *  Copyright (C) 2004 Ian Campbell.
7  *  Copyright (C) 2004 Jeff Lackey.
8  *   Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
9  *  which in turn is
10  *   Based on acornfb.c Copyright (C) Russell King.
11  *
12  * This file is subject to the terms and conditions of the GNU General Public
13  * License.  See the file COPYING in the main directory of this archive for
14  * more details.
15  *
16  *              Intel PXA250/210 LCD Controller Frame Buffer Driver
17  *
18  * Please direct your questions and comments on this driver to the following
19  * email address:
20  *
21  *      linux-arm-kernel@lists.arm.linux.org.uk
22  *
23  */
24
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/kernel.h>
28 #include <linux/sched.h>
29 #include <linux/errno.h>
30 #include <linux/string.h>
31 #include <linux/interrupt.h>
32 #include <linux/slab.h>
33 #include <linux/fb.h>
34 #include <linux/delay.h>
35 #include <linux/init.h>
36 #include <linux/ioport.h>
37 #include <linux/cpufreq.h>
38 #include <linux/platform_device.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/clk.h>
41 #include <linux/err.h>
42 #include <linux/completion.h>
43 #include <linux/kthread.h>
44 #include <linux/freezer.h>
45
46 #include <asm/hardware.h>
47 #include <asm/io.h>
48 #include <asm/irq.h>
49 #include <asm/div64.h>
50 #include <asm/arch/pxa-regs.h>
51 #include <asm/arch/pxa2xx-gpio.h>
52 #include <asm/arch/bitfield.h>
53 #include <asm/arch/pxafb.h>
54
55 /*
56  * Complain if VAR is out of range.
57  */
58 #define DEBUG_VAR 1
59
60 #include "pxafb.h"
61
62 /* Bits which should not be set in machine configuration structures */
63 #define LCCR0_INVALID_CONFIG_MASK       (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
64                                          LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
65                                          LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
66
67 #define LCCR3_INVALID_CONFIG_MASK       (LCCR3_HSP | LCCR3_VSP |\
68                                          LCCR3_PCD | LCCR3_BPP)
69
70 static void (*pxafb_backlight_power)(int);
71 static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
72
73 static int pxafb_activate_var(struct fb_var_screeninfo *var,
74                                 struct pxafb_info *);
75 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
76
77 static inline unsigned long
78 lcd_readl(struct pxafb_info *fbi, unsigned int off)
79 {
80         return __raw_readl(fbi->mmio_base + off);
81 }
82
83 static inline void
84 lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
85 {
86         __raw_writel(val, fbi->mmio_base + off);
87 }
88
89 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
90 {
91         unsigned long flags;
92
93         local_irq_save(flags);
94         /*
95          * We need to handle two requests being made at the same time.
96          * There are two important cases:
97          *  1. When we are changing VT (C_REENABLE) while unblanking
98          *     (C_ENABLE) We must perform the unblanking, which will
99          *     do our REENABLE for us.
100          *  2. When we are blanking, but immediately unblank before
101          *     we have blanked.  We do the "REENABLE" thing here as
102          *     well, just to be sure.
103          */
104         if (fbi->task_state == C_ENABLE && state == C_REENABLE)
105                 state = (u_int) -1;
106         if (fbi->task_state == C_DISABLE && state == C_ENABLE)
107                 state = C_REENABLE;
108
109         if (state != (u_int)-1) {
110                 fbi->task_state = state;
111                 schedule_work(&fbi->task);
112         }
113         local_irq_restore(flags);
114 }
115
116 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
117 {
118         chan &= 0xffff;
119         chan >>= 16 - bf->length;
120         return chan << bf->offset;
121 }
122
123 static int
124 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
125                        u_int trans, struct fb_info *info)
126 {
127         struct pxafb_info *fbi = (struct pxafb_info *)info;
128         u_int val;
129
130         if (regno >= fbi->palette_size)
131                 return 1;
132
133         if (fbi->fb.var.grayscale) {
134                 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
135                 return 0;
136         }
137
138         switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
139         case LCCR4_PAL_FOR_0:
140                 val  = ((red   >>  0) & 0xf800);
141                 val |= ((green >>  5) & 0x07e0);
142                 val |= ((blue  >> 11) & 0x001f);
143                 fbi->palette_cpu[regno] = val;
144                 break;
145         case LCCR4_PAL_FOR_1:
146                 val  = ((red   << 8) & 0x00f80000);
147                 val |= ((green >> 0) & 0x0000fc00);
148                 val |= ((blue  >> 8) & 0x000000f8);
149                 ((u32 *)(fbi->palette_cpu))[regno] = val;
150                 break;
151         case LCCR4_PAL_FOR_2:
152                 val  = ((red   << 8) & 0x00fc0000);
153                 val |= ((green >> 0) & 0x0000fc00);
154                 val |= ((blue  >> 8) & 0x000000fc);
155                 ((u32 *)(fbi->palette_cpu))[regno] = val;
156                 break;
157         }
158
159         return 0;
160 }
161
162 static int
163 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
164                    u_int trans, struct fb_info *info)
165 {
166         struct pxafb_info *fbi = (struct pxafb_info *)info;
167         unsigned int val;
168         int ret = 1;
169
170         /*
171          * If inverse mode was selected, invert all the colours
172          * rather than the register number.  The register number
173          * is what you poke into the framebuffer to produce the
174          * colour you requested.
175          */
176         if (fbi->cmap_inverse) {
177                 red   = 0xffff - red;
178                 green = 0xffff - green;
179                 blue  = 0xffff - blue;
180         }
181
182         /*
183          * If greyscale is true, then we convert the RGB value
184          * to greyscale no matter what visual we are using.
185          */
186         if (fbi->fb.var.grayscale)
187                 red = green = blue = (19595 * red + 38470 * green +
188                                         7471 * blue) >> 16;
189
190         switch (fbi->fb.fix.visual) {
191         case FB_VISUAL_TRUECOLOR:
192                 /*
193                  * 16-bit True Colour.  We encode the RGB value
194                  * according to the RGB bitfield information.
195                  */
196                 if (regno < 16) {
197                         u32 *pal = fbi->fb.pseudo_palette;
198
199                         val  = chan_to_field(red, &fbi->fb.var.red);
200                         val |= chan_to_field(green, &fbi->fb.var.green);
201                         val |= chan_to_field(blue, &fbi->fb.var.blue);
202
203                         pal[regno] = val;
204                         ret = 0;
205                 }
206                 break;
207
208         case FB_VISUAL_STATIC_PSEUDOCOLOR:
209         case FB_VISUAL_PSEUDOCOLOR:
210                 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
211                 break;
212         }
213
214         return ret;
215 }
216
217 /*
218  *  pxafb_bpp_to_lccr3():
219  *    Convert a bits per pixel value to the correct bit pattern for LCCR3
220  */
221 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
222 {
223         int ret = 0;
224         switch (var->bits_per_pixel) {
225         case 1:  ret = LCCR3_1BPP; break;
226         case 2:  ret = LCCR3_2BPP; break;
227         case 4:  ret = LCCR3_4BPP; break;
228         case 8:  ret = LCCR3_8BPP; break;
229         case 16: ret = LCCR3_16BPP; break;
230         }
231         return ret;
232 }
233
234 #ifdef CONFIG_CPU_FREQ
235 /*
236  *  pxafb_display_dma_period()
237  *    Calculate the minimum period (in picoseconds) between two DMA
238  *    requests for the LCD controller.  If we hit this, it means we're
239  *    doing nothing but LCD DMA.
240  */
241 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
242 {
243         /*
244          * Period = pixclock * bits_per_byte * bytes_per_transfer
245          *              / memory_bits_per_pixel;
246          */
247         return var->pixclock * 8 * 16 / var->bits_per_pixel;
248 }
249 #endif
250
251 /*
252  * Select the smallest mode that allows the desired resolution to be
253  * displayed. If desired parameters can be rounded up.
254  */
255 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
256                                              struct fb_var_screeninfo *var)
257 {
258         struct pxafb_mode_info *mode = NULL;
259         struct pxafb_mode_info *modelist = mach->modes;
260         unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
261         unsigned int i;
262
263         for (i = 0; i < mach->num_modes; i++) {
264                 if (modelist[i].xres >= var->xres &&
265                     modelist[i].yres >= var->yres &&
266                     modelist[i].xres < best_x &&
267                     modelist[i].yres < best_y &&
268                     modelist[i].bpp >= var->bits_per_pixel) {
269                         best_x = modelist[i].xres;
270                         best_y = modelist[i].yres;
271                         mode = &modelist[i];
272                 }
273         }
274
275         return mode;
276 }
277
278 static void pxafb_setmode(struct fb_var_screeninfo *var,
279                           struct pxafb_mode_info *mode)
280 {
281         var->xres               = mode->xres;
282         var->yres               = mode->yres;
283         var->bits_per_pixel     = mode->bpp;
284         var->pixclock           = mode->pixclock;
285         var->hsync_len          = mode->hsync_len;
286         var->left_margin        = mode->left_margin;
287         var->right_margin       = mode->right_margin;
288         var->vsync_len          = mode->vsync_len;
289         var->upper_margin       = mode->upper_margin;
290         var->lower_margin       = mode->lower_margin;
291         var->sync               = mode->sync;
292         var->grayscale          = mode->cmap_greyscale;
293         var->xres_virtual       = var->xres;
294         var->yres_virtual       = var->yres;
295 }
296
297 /*
298  *  pxafb_check_var():
299  *    Get the video params out of 'var'. If a value doesn't fit, round it up,
300  *    if it's too big, return -EINVAL.
301  *
302  *    Round up in the following order: bits_per_pixel, xres,
303  *    yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
304  *    bitfields, horizontal timing, vertical timing.
305  */
306 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
307 {
308         struct pxafb_info *fbi = (struct pxafb_info *)info;
309         struct pxafb_mach_info *inf = fbi->dev->platform_data;
310
311         if (var->xres < MIN_XRES)
312                 var->xres = MIN_XRES;
313         if (var->yres < MIN_YRES)
314                 var->yres = MIN_YRES;
315
316         if (inf->fixed_modes) {
317                 struct pxafb_mode_info *mode;
318
319                 mode = pxafb_getmode(inf, var);
320                 if (!mode)
321                         return -EINVAL;
322                 pxafb_setmode(var, mode);
323         } else {
324                 if (var->xres > inf->modes->xres)
325                         return -EINVAL;
326                 if (var->yres > inf->modes->yres)
327                         return -EINVAL;
328                 if (var->bits_per_pixel > inf->modes->bpp)
329                         return -EINVAL;
330         }
331
332         var->xres_virtual =
333                 max(var->xres_virtual, var->xres);
334         var->yres_virtual =
335                 max(var->yres_virtual, var->yres);
336
337         /*
338          * Setup the RGB parameters for this display.
339          *
340          * The pixel packing format is described on page 7-11 of the
341          * PXA2XX Developer's Manual.
342          */
343         if (var->bits_per_pixel == 16) {
344                 var->red.offset   = 11; var->red.length   = 5;
345                 var->green.offset = 5;  var->green.length = 6;
346                 var->blue.offset  = 0;  var->blue.length  = 5;
347                 var->transp.offset = var->transp.length = 0;
348         } else {
349                 var->red.offset = var->green.offset = 0;
350                 var->blue.offset = var->transp.offset = 0;
351                 var->red.length   = 8;
352                 var->green.length = 8;
353                 var->blue.length  = 8;
354                 var->transp.length = 0;
355         }
356
357 #ifdef CONFIG_CPU_FREQ
358         pr_debug("pxafb: dma period = %d ps\n",
359                  pxafb_display_dma_period(var));
360 #endif
361
362         return 0;
363 }
364
365 static inline void pxafb_set_truecolor(u_int is_true_color)
366 {
367         /* do your machine-specific setup if needed */
368 }
369
370 /*
371  * pxafb_set_par():
372  *      Set the user defined part of the display for the specified console
373  */
374 static int pxafb_set_par(struct fb_info *info)
375 {
376         struct pxafb_info *fbi = (struct pxafb_info *)info;
377         struct fb_var_screeninfo *var = &info->var;
378
379         if (var->bits_per_pixel == 16)
380                 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
381         else if (!fbi->cmap_static)
382                 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
383         else {
384                 /*
385                  * Some people have weird ideas about wanting static
386                  * pseudocolor maps.  I suspect their user space
387                  * applications are broken.
388                  */
389                 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
390         }
391
392         fbi->fb.fix.line_length = var->xres_virtual *
393                                   var->bits_per_pixel / 8;
394         if (var->bits_per_pixel == 16)
395                 fbi->palette_size = 0;
396         else
397                 fbi->palette_size = var->bits_per_pixel == 1 ?
398                                         4 : 1 << var->bits_per_pixel;
399
400         fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
401
402         /*
403          * Set (any) board control register to handle new color depth
404          */
405         pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
406
407         if (fbi->fb.var.bits_per_pixel == 16)
408                 fb_dealloc_cmap(&fbi->fb.cmap);
409         else
410                 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
411
412         pxafb_activate_var(var, fbi);
413
414         return 0;
415 }
416
417 /*
418  * pxafb_blank():
419  *      Blank the display by setting all palette values to zero.  Note, the
420  *      16 bpp mode does not really use the palette, so this will not
421  *      blank the display in all modes.
422  */
423 static int pxafb_blank(int blank, struct fb_info *info)
424 {
425         struct pxafb_info *fbi = (struct pxafb_info *)info;
426         int i;
427
428         switch (blank) {
429         case FB_BLANK_POWERDOWN:
430         case FB_BLANK_VSYNC_SUSPEND:
431         case FB_BLANK_HSYNC_SUSPEND:
432         case FB_BLANK_NORMAL:
433                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
434                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
435                         for (i = 0; i < fbi->palette_size; i++)
436                                 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
437
438                 pxafb_schedule_work(fbi, C_DISABLE);
439                 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
440                 break;
441
442         case FB_BLANK_UNBLANK:
443                 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
444                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
445                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
446                         fb_set_cmap(&fbi->fb.cmap, info);
447                 pxafb_schedule_work(fbi, C_ENABLE);
448         }
449         return 0;
450 }
451
452 static int pxafb_mmap(struct fb_info *info,
453                       struct vm_area_struct *vma)
454 {
455         struct pxafb_info *fbi = (struct pxafb_info *)info;
456         unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
457
458         if (off < info->fix.smem_len) {
459                 vma->vm_pgoff += fbi->video_offset / PAGE_SIZE;
460                 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
461                                              fbi->map_dma, fbi->map_size);
462         }
463         return -EINVAL;
464 }
465
466 static struct fb_ops pxafb_ops = {
467         .owner          = THIS_MODULE,
468         .fb_check_var   = pxafb_check_var,
469         .fb_set_par     = pxafb_set_par,
470         .fb_setcolreg   = pxafb_setcolreg,
471         .fb_fillrect    = cfb_fillrect,
472         .fb_copyarea    = cfb_copyarea,
473         .fb_imageblit   = cfb_imageblit,
474         .fb_blank       = pxafb_blank,
475         .fb_mmap        = pxafb_mmap,
476 };
477
478 /*
479  * Calculate the PCD value from the clock rate (in picoseconds).
480  * We take account of the PPCR clock setting.
481  * From PXA Developer's Manual:
482  *
483  *   PixelClock =      LCLK
484  *                -------------
485  *                2 ( PCD + 1 )
486  *
487  *   PCD =      LCLK
488  *         ------------- - 1
489  *         2(PixelClock)
490  *
491  * Where:
492  *   LCLK = LCD/Memory Clock
493  *   PCD = LCCR3[7:0]
494  *
495  * PixelClock here is in Hz while the pixclock argument given is the
496  * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
497  *
498  * The function get_lclk_frequency_10khz returns LCLK in units of
499  * 10khz. Calling the result of this function lclk gives us the
500  * following
501  *
502  *    PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
503  *          -------------------------------------- - 1
504  *                          2
505  *
506  * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
507  */
508 static inline unsigned int get_pcd(struct pxafb_info *fbi,
509                                    unsigned int pixclock)
510 {
511         unsigned long long pcd;
512
513         /* FIXME: Need to take into account Double Pixel Clock mode
514          * (DPC) bit? or perhaps set it based on the various clock
515          * speeds */
516         pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
517         pcd *= pixclock;
518         do_div(pcd, 100000000 * 2);
519         /* no need for this, since we should subtract 1 anyway. they cancel */
520         /* pcd += 1; */ /* make up for integer math truncations */
521         return (unsigned int)pcd;
522 }
523
524 /*
525  * Some touchscreens need hsync information from the video driver to
526  * function correctly. We export it here.  Note that 'hsync_time' and
527  * the value returned from pxafb_get_hsync_time() is the *reciprocal*
528  * of the hsync period in seconds.
529  */
530 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
531 {
532         unsigned long htime;
533
534         if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
535                 fbi->hsync_time = 0;
536                 return;
537         }
538
539         htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
540
541         fbi->hsync_time = htime;
542 }
543
544 unsigned long pxafb_get_hsync_time(struct device *dev)
545 {
546         struct pxafb_info *fbi = dev_get_drvdata(dev);
547
548         /* If display is blanked/suspended, hsync isn't active */
549         if (!fbi || (fbi->state != C_ENABLE))
550                 return 0;
551
552         return fbi->hsync_time;
553 }
554 EXPORT_SYMBOL(pxafb_get_hsync_time);
555
556 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
557                 unsigned int offset, size_t size)
558 {
559         struct pxafb_dma_descriptor *dma_desc, *pal_desc;
560         unsigned int dma_desc_off, pal_desc_off;
561
562         if (dma < 0 || dma >= DMA_MAX)
563                 return -EINVAL;
564
565         dma_desc = &fbi->dma_buff->dma_desc[dma];
566         dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
567
568         dma_desc->fsadr = fbi->screen_dma + offset;
569         dma_desc->fidr  = 0;
570         dma_desc->ldcmd = size;
571
572         if (pal < 0 || pal >= PAL_MAX) {
573                 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
574                 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
575         } else {
576                 pal_desc = &fbi->dma_buff->pal_desc[dma];
577                 pal_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[pal]);
578
579                 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
580                 pal_desc->fidr  = 0;
581
582                 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
583                         pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
584                 else
585                         pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
586
587                 pal_desc->ldcmd |= LDCMD_PAL;
588
589                 /* flip back and forth between palette and frame buffer */
590                 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
591                 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
592                 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
593         }
594
595         return 0;
596 }
597
598 #ifdef CONFIG_FB_PXA_SMARTPANEL
599 static int setup_smart_dma(struct pxafb_info *fbi)
600 {
601         struct pxafb_dma_descriptor *dma_desc;
602         unsigned long dma_desc_off, cmd_buff_off;
603
604         dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
605         dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
606         cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
607
608         dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
609         dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
610         dma_desc->fidr  = 0;
611         dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
612
613         fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
614         return 0;
615 }
616
617 int pxafb_smart_flush(struct fb_info *info)
618 {
619         struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
620         uint32_t prsr;
621         int ret = 0;
622
623         /* disable controller until all registers are set up */
624         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
625
626         /* 1. make it an even number of commands to align on 32-bit boundary
627          * 2. add the interrupt command to the end of the chain so we can
628          *    keep track of the end of the transfer
629          */
630
631         while (fbi->n_smart_cmds & 1)
632                 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
633
634         fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
635         fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
636         setup_smart_dma(fbi);
637
638         /* continue to execute next command */
639         prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
640         lcd_writel(fbi, PRSR, prsr);
641
642         /* stop the processor in case it executed "wait for sync" cmd */
643         lcd_writel(fbi, CMDCR, 0x0001);
644
645         /* don't send interrupts for fifo underruns on channel 6 */
646         lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
647
648         lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
649         lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
650         lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
651         lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
652         lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
653
654         /* begin sending */
655         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
656
657         if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
658                 pr_warning("%s: timeout waiting for command done\n",
659                                 __func__);
660                 ret = -ETIMEDOUT;
661         }
662
663         /* quick disable */
664         prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
665         lcd_writel(fbi, PRSR, prsr);
666         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
667         lcd_writel(fbi, FDADR6, 0);
668         fbi->n_smart_cmds = 0;
669         return ret;
670 }
671
672 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
673 {
674         int i;
675         struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
676
677         /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
678         for (i = 0; i < n_cmds; i++) {
679                 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
680                         pxafb_smart_flush(info);
681
682                 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds++;
683         }
684
685         return 0;
686 }
687
688 static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
689 {
690         unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
691         return (t == 0) ? 1 : t;
692 }
693
694 static void setup_smart_timing(struct pxafb_info *fbi,
695                                 struct fb_var_screeninfo *var)
696 {
697         struct pxafb_mach_info *inf = fbi->dev->platform_data;
698         struct pxafb_mode_info *mode = &inf->modes[0];
699         unsigned long lclk = clk_get_rate(fbi->clk);
700         unsigned t1, t2, t3, t4;
701
702         t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
703         t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
704         t3 = mode->op_hold_time;
705         t4 = mode->cmd_inh_time;
706
707         fbi->reg_lccr1 =
708                 LCCR1_DisWdth(var->xres) |
709                 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
710                 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
711                 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
712
713         fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
714         fbi->reg_lccr3 = LCCR3_PixClkDiv(__smart_timing(t4, lclk));
715
716         /* FIXME: make this configurable */
717         fbi->reg_cmdcr = 1;
718 }
719
720 static int pxafb_smart_thread(void *arg)
721 {
722         struct pxafb_info *fbi = arg;
723         struct pxafb_mach_info *inf = fbi->dev->platform_data;
724
725         if (!fbi || !inf->smart_update) {
726                 pr_err("%s: not properly initialized, thread terminated\n",
727                                 __func__);
728                 return -EINVAL;
729         }
730
731         pr_debug("%s(): task starting\n", __func__);
732
733         set_freezable();
734         while (!kthread_should_stop()) {
735
736                 if (try_to_freeze())
737                         continue;
738
739                 if (fbi->state == C_ENABLE) {
740                         inf->smart_update(&fbi->fb);
741                         complete(&fbi->refresh_done);
742                 }
743
744                 set_current_state(TASK_INTERRUPTIBLE);
745                 schedule_timeout(30 * HZ / 1000);
746         }
747
748         pr_debug("%s(): task ending\n", __func__);
749         return 0;
750 }
751
752 static int pxafb_smart_init(struct pxafb_info *fbi)
753 {
754         fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
755                                         "lcd_refresh");
756         if (IS_ERR(fbi->smart_thread)) {
757                 printk(KERN_ERR "%s: unable to create kernel thread\n",
758                                 __func__);
759                 return PTR_ERR(fbi->smart_thread);
760         }
761         return 0;
762 }
763 #else
764 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
765 {
766         return 0;
767 }
768
769 int pxafb_smart_flush(struct fb_info *info)
770 {
771         return 0;
772 }
773 #endif /* CONFIG_FB_SMART_PANEL */
774
775 static void setup_parallel_timing(struct pxafb_info *fbi,
776                                   struct fb_var_screeninfo *var)
777 {
778         unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
779
780         fbi->reg_lccr1 =
781                 LCCR1_DisWdth(var->xres) +
782                 LCCR1_HorSnchWdth(var->hsync_len) +
783                 LCCR1_BegLnDel(var->left_margin) +
784                 LCCR1_EndLnDel(var->right_margin);
785
786         /*
787          * If we have a dual scan LCD, we need to halve
788          * the YRES parameter.
789          */
790         lines_per_panel = var->yres;
791         if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
792                 lines_per_panel /= 2;
793
794         fbi->reg_lccr2 =
795                 LCCR2_DisHght(lines_per_panel) +
796                 LCCR2_VrtSnchWdth(var->vsync_len) +
797                 LCCR2_BegFrmDel(var->upper_margin) +
798                 LCCR2_EndFrmDel(var->lower_margin);
799
800         fbi->reg_lccr3 = fbi->lccr3 |
801                 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
802                  LCCR3_HorSnchH : LCCR3_HorSnchL) |
803                 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
804                  LCCR3_VrtSnchH : LCCR3_VrtSnchL);
805
806         if (pcd) {
807                 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
808                 set_hsync_time(fbi, pcd);
809         }
810 }
811
812 /*
813  * pxafb_activate_var():
814  *      Configures LCD Controller based on entries in var parameter.
815  *      Settings are only written to the controller if changes were made.
816  */
817 static int pxafb_activate_var(struct fb_var_screeninfo *var,
818                               struct pxafb_info *fbi)
819 {
820         u_long flags;
821         size_t nbytes;
822
823 #if DEBUG_VAR
824         if (!(fbi->lccr0 & LCCR0_LCDT)) {
825                 if (var->xres < 16 || var->xres > 1024)
826                         printk(KERN_ERR "%s: invalid xres %d\n",
827                                 fbi->fb.fix.id, var->xres);
828                 switch (var->bits_per_pixel) {
829                 case 1:
830                 case 2:
831                 case 4:
832                 case 8:
833                 case 16:
834                         break;
835                 default:
836                         printk(KERN_ERR "%s: invalid bit depth %d\n",
837                                fbi->fb.fix.id, var->bits_per_pixel);
838                         break;
839                 }
840
841                 if (var->hsync_len < 1 || var->hsync_len > 64)
842                         printk(KERN_ERR "%s: invalid hsync_len %d\n",
843                                 fbi->fb.fix.id, var->hsync_len);
844                 if (var->left_margin < 1 || var->left_margin > 255)
845                         printk(KERN_ERR "%s: invalid left_margin %d\n",
846                                 fbi->fb.fix.id, var->left_margin);
847                 if (var->right_margin < 1 || var->right_margin > 255)
848                         printk(KERN_ERR "%s: invalid right_margin %d\n",
849                                 fbi->fb.fix.id, var->right_margin);
850                 if (var->yres < 1 || var->yres > 1024)
851                         printk(KERN_ERR "%s: invalid yres %d\n",
852                                 fbi->fb.fix.id, var->yres);
853                 if (var->vsync_len < 1 || var->vsync_len > 64)
854                         printk(KERN_ERR "%s: invalid vsync_len %d\n",
855                                 fbi->fb.fix.id, var->vsync_len);
856                 if (var->upper_margin < 0 || var->upper_margin > 255)
857                         printk(KERN_ERR "%s: invalid upper_margin %d\n",
858                                 fbi->fb.fix.id, var->upper_margin);
859                 if (var->lower_margin < 0 || var->lower_margin > 255)
860                         printk(KERN_ERR "%s: invalid lower_margin %d\n",
861                                 fbi->fb.fix.id, var->lower_margin);
862         }
863 #endif
864         /* Update shadow copy atomically */
865         local_irq_save(flags);
866
867 #ifdef CONFIG_FB_PXA_SMARTPANEL
868         if (fbi->lccr0 & LCCR0_LCDT)
869                 setup_smart_timing(fbi, var);
870         else
871 #endif
872                 setup_parallel_timing(fbi, var);
873
874         fbi->reg_lccr0 = fbi->lccr0 |
875                 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
876                  LCCR0_QDM | LCCR0_BM  | LCCR0_OUM);
877
878         fbi->reg_lccr3 |= pxafb_bpp_to_lccr3(var);
879
880         nbytes = var->yres * fbi->fb.fix.line_length;
881
882         if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) {
883                 nbytes = nbytes / 2;
884                 setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, nbytes, nbytes);
885         }
886
887         if ((var->bits_per_pixel >= 16) || (fbi->lccr0 & LCCR0_LCDT))
888                 setup_frame_dma(fbi, DMA_BASE, PAL_NONE, 0, nbytes);
889         else
890                 setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes);
891
892         fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
893         fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
894         local_irq_restore(flags);
895
896         /*
897          * Only update the registers if the controller is enabled
898          * and something has changed.
899          */
900         if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
901             (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
902             (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
903             (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
904             (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
905             (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
906                 pxafb_schedule_work(fbi, C_REENABLE);
907
908         return 0;
909 }
910
911 /*
912  * NOTE!  The following functions are purely helpers for set_ctrlr_state.
913  * Do not call them directly; set_ctrlr_state does the correct serialisation
914  * to ensure that things happen in the right way 100% of time time.
915  *      -- rmk
916  */
917 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
918 {
919         pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
920
921         if (pxafb_backlight_power)
922                 pxafb_backlight_power(on);
923 }
924
925 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
926 {
927         pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
928
929         if (pxafb_lcd_power)
930                 pxafb_lcd_power(on, &fbi->fb.var);
931 }
932
933 static void pxafb_setup_gpio(struct pxafb_info *fbi)
934 {
935         int gpio, ldd_bits;
936         unsigned int lccr0 = fbi->lccr0;
937
938         /*
939          * setup is based on type of panel supported
940          */
941
942         /* 4 bit interface */
943         if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
944             (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
945             (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
946                 ldd_bits = 4;
947
948         /* 8 bit interface */
949         else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
950                   ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
951                    (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
952                  ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
953                   (lccr0 & LCCR0_PAS) == LCCR0_Pas &&
954                   (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
955                 ldd_bits = 8;
956
957         /* 16 bit interface */
958         else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
959                  ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
960                   (lccr0 & LCCR0_PAS) == LCCR0_Act))
961                 ldd_bits = 16;
962
963         else {
964                 printk(KERN_ERR "pxafb_setup_gpio: unable to determine "
965                                "bits per pixel\n");
966                 return;
967         }
968
969         for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
970                 pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
971         pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
972         pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
973         pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
974         pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
975 }
976
977 static void pxafb_enable_controller(struct pxafb_info *fbi)
978 {
979         pr_debug("pxafb: Enabling LCD controller\n");
980         pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
981         pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
982         pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
983         pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
984         pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
985         pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
986
987         /* enable LCD controller clock */
988         clk_enable(fbi->clk);
989
990         if (fbi->lccr0 & LCCR0_LCDT)
991                 return;
992
993         /* Sequence from 11.7.10 */
994         lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
995         lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
996         lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
997         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
998
999         lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1000         lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1001         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1002 }
1003
1004 static void pxafb_disable_controller(struct pxafb_info *fbi)
1005 {
1006         uint32_t lccr0;
1007
1008 #ifdef CONFIG_FB_PXA_SMARTPANEL
1009         if (fbi->lccr0 & LCCR0_LCDT) {
1010                 wait_for_completion_timeout(&fbi->refresh_done,
1011                                 200 * HZ / 1000);
1012                 return;
1013         }
1014 #endif
1015
1016         /* Clear LCD Status Register */
1017         lcd_writel(fbi, LCSR, 0xffffffff);
1018
1019         lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1020         lcd_writel(fbi, LCCR0, lccr0);
1021         lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1022
1023         wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
1024
1025         /* disable LCD controller clock */
1026         clk_disable(fbi->clk);
1027 }
1028
1029 /*
1030  *  pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1031  */
1032 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1033 {
1034         struct pxafb_info *fbi = dev_id;
1035         unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR);
1036
1037         if (lcsr & LCSR_LDD) {
1038                 lccr0 = lcd_readl(fbi, LCCR0);
1039                 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
1040                 complete(&fbi->disable_done);
1041         }
1042
1043 #ifdef CONFIG_FB_PXA_SMARTPANEL
1044         if (lcsr & LCSR_CMD_INT)
1045                 complete(&fbi->command_done);
1046 #endif
1047
1048         lcd_writel(fbi, LCSR, lcsr);
1049         return IRQ_HANDLED;
1050 }
1051
1052 /*
1053  * This function must be called from task context only, since it will
1054  * sleep when disabling the LCD controller, or if we get two contending
1055  * processes trying to alter state.
1056  */
1057 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1058 {
1059         u_int old_state;
1060
1061         down(&fbi->ctrlr_sem);
1062
1063         old_state = fbi->state;
1064
1065         /*
1066          * Hack around fbcon initialisation.
1067          */
1068         if (old_state == C_STARTUP && state == C_REENABLE)
1069                 state = C_ENABLE;
1070
1071         switch (state) {
1072         case C_DISABLE_CLKCHANGE:
1073                 /*
1074                  * Disable controller for clock change.  If the
1075                  * controller is already disabled, then do nothing.
1076                  */
1077                 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1078                         fbi->state = state;
1079                         /* TODO __pxafb_lcd_power(fbi, 0); */
1080                         pxafb_disable_controller(fbi);
1081                 }
1082                 break;
1083
1084         case C_DISABLE_PM:
1085         case C_DISABLE:
1086                 /*
1087                  * Disable controller
1088                  */
1089                 if (old_state != C_DISABLE) {
1090                         fbi->state = state;
1091                         __pxafb_backlight_power(fbi, 0);
1092                         __pxafb_lcd_power(fbi, 0);
1093                         if (old_state != C_DISABLE_CLKCHANGE)
1094                                 pxafb_disable_controller(fbi);
1095                 }
1096                 break;
1097
1098         case C_ENABLE_CLKCHANGE:
1099                 /*
1100                  * Enable the controller after clock change.  Only
1101                  * do this if we were disabled for the clock change.
1102                  */
1103                 if (old_state == C_DISABLE_CLKCHANGE) {
1104                         fbi->state = C_ENABLE;
1105                         pxafb_enable_controller(fbi);
1106                         /* TODO __pxafb_lcd_power(fbi, 1); */
1107                 }
1108                 break;
1109
1110         case C_REENABLE:
1111                 /*
1112                  * Re-enable the controller only if it was already
1113                  * enabled.  This is so we reprogram the control
1114                  * registers.
1115                  */
1116                 if (old_state == C_ENABLE) {
1117                         __pxafb_lcd_power(fbi, 0);
1118                         pxafb_disable_controller(fbi);
1119                         pxafb_setup_gpio(fbi);
1120                         pxafb_enable_controller(fbi);
1121                         __pxafb_lcd_power(fbi, 1);
1122                 }
1123                 break;
1124
1125         case C_ENABLE_PM:
1126                 /*
1127                  * Re-enable the controller after PM.  This is not
1128                  * perfect - think about the case where we were doing
1129                  * a clock change, and we suspended half-way through.
1130                  */
1131                 if (old_state != C_DISABLE_PM)
1132                         break;
1133                 /* fall through */
1134
1135         case C_ENABLE:
1136                 /*
1137                  * Power up the LCD screen, enable controller, and
1138                  * turn on the backlight.
1139                  */
1140                 if (old_state != C_ENABLE) {
1141                         fbi->state = C_ENABLE;
1142                         pxafb_setup_gpio(fbi);
1143                         pxafb_enable_controller(fbi);
1144                         __pxafb_lcd_power(fbi, 1);
1145                         __pxafb_backlight_power(fbi, 1);
1146                 }
1147                 break;
1148         }
1149         up(&fbi->ctrlr_sem);
1150 }
1151
1152 /*
1153  * Our LCD controller task (which is called when we blank or unblank)
1154  * via keventd.
1155  */
1156 static void pxafb_task(struct work_struct *work)
1157 {
1158         struct pxafb_info *fbi =
1159                 container_of(work, struct pxafb_info, task);
1160         u_int state = xchg(&fbi->task_state, -1);
1161
1162         set_ctrlr_state(fbi, state);
1163 }
1164
1165 #ifdef CONFIG_CPU_FREQ
1166 /*
1167  * CPU clock speed change handler.  We need to adjust the LCD timing
1168  * parameters when the CPU clock is adjusted by the power management
1169  * subsystem.
1170  *
1171  * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1172  */
1173 static int
1174 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1175 {
1176         struct pxafb_info *fbi = TO_INF(nb, freq_transition);
1177         /* TODO struct cpufreq_freqs *f = data; */
1178         u_int pcd;
1179
1180         switch (val) {
1181         case CPUFREQ_PRECHANGE:
1182                 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1183                 break;
1184
1185         case CPUFREQ_POSTCHANGE:
1186                 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
1187                 set_hsync_time(fbi, pcd);
1188                 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1189                                   LCCR3_PixClkDiv(pcd);
1190                 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1191                 break;
1192         }
1193         return 0;
1194 }
1195
1196 static int
1197 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1198 {
1199         struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1200         struct fb_var_screeninfo *var = &fbi->fb.var;
1201         struct cpufreq_policy *policy = data;
1202
1203         switch (val) {
1204         case CPUFREQ_ADJUST:
1205         case CPUFREQ_INCOMPATIBLE:
1206                 pr_debug("min dma period: %d ps, "
1207                         "new clock %d kHz\n", pxafb_display_dma_period(var),
1208                         policy->max);
1209                 /* TODO: fill in min/max values */
1210                 break;
1211         }
1212         return 0;
1213 }
1214 #endif
1215
1216 #ifdef CONFIG_PM
1217 /*
1218  * Power management hooks.  Note that we won't be called from IRQ context,
1219  * unlike the blank functions above, so we may sleep.
1220  */
1221 static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1222 {
1223         struct pxafb_info *fbi = platform_get_drvdata(dev);
1224
1225         set_ctrlr_state(fbi, C_DISABLE_PM);
1226         return 0;
1227 }
1228
1229 static int pxafb_resume(struct platform_device *dev)
1230 {
1231         struct pxafb_info *fbi = platform_get_drvdata(dev);
1232
1233         set_ctrlr_state(fbi, C_ENABLE_PM);
1234         return 0;
1235 }
1236 #else
1237 #define pxafb_suspend   NULL
1238 #define pxafb_resume    NULL
1239 #endif
1240
1241 /*
1242  * pxafb_map_video_memory():
1243  *      Allocates the DRAM memory for the frame buffer.  This buffer is
1244  *      remapped into a non-cached, non-buffered, memory region to
1245  *      allow palette and pixel writes to occur without flushing the
1246  *      cache.  Once this area is remapped, all virtual memory
1247  *      access to the video memory should occur at the new region.
1248  */
1249 static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
1250 {
1251         /*
1252          * We reserve one page for the palette, plus the size
1253          * of the framebuffer.
1254          */
1255         fbi->video_offset = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
1256         fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + fbi->video_offset);
1257         fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1258                                               &fbi->map_dma, GFP_KERNEL);
1259
1260         if (fbi->map_cpu) {
1261                 /* prevent initial garbage on screen */
1262                 memset(fbi->map_cpu, 0, fbi->map_size);
1263                 fbi->fb.screen_base = fbi->map_cpu + fbi->video_offset;
1264                 fbi->screen_dma = fbi->map_dma + fbi->video_offset;
1265
1266                 /*
1267                  * FIXME: this is actually the wrong thing to place in
1268                  * smem_start.  But fbdev suffers from the problem that
1269                  * it needs an API which doesn't exist (in this case,
1270                  * dma_writecombine_mmap)
1271                  */
1272                 fbi->fb.fix.smem_start = fbi->screen_dma;
1273                 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1274
1275                 fbi->dma_buff = (void *) fbi->map_cpu;
1276                 fbi->dma_buff_phys = fbi->map_dma;
1277                 fbi->palette_cpu = (u16 *) fbi->dma_buff->palette;
1278
1279 #ifdef CONFIG_FB_PXA_SMARTPANEL
1280                 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
1281                 fbi->n_smart_cmds = 0;
1282 #endif
1283         }
1284
1285         return fbi->map_cpu ? 0 : -ENOMEM;
1286 }
1287
1288 static void pxafb_decode_mode_info(struct pxafb_info *fbi,
1289                                    struct pxafb_mode_info *modes,
1290                                    unsigned int num_modes)
1291 {
1292         unsigned int i, smemlen;
1293
1294         pxafb_setmode(&fbi->fb.var, &modes[0]);
1295
1296         for (i = 0; i < num_modes; i++) {
1297                 smemlen = modes[i].xres * modes[i].yres * modes[i].bpp / 8;
1298                 if (smemlen > fbi->fb.fix.smem_len)
1299                         fbi->fb.fix.smem_len = smemlen;
1300         }
1301 }
1302
1303 static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1304                                    struct pxafb_mach_info *inf)
1305 {
1306         unsigned int lcd_conn = inf->lcd_conn;
1307
1308         fbi->cmap_inverse       = inf->cmap_inverse;
1309         fbi->cmap_static        = inf->cmap_static;
1310
1311         switch (lcd_conn & 0xf) {
1312         case LCD_TYPE_MONO_STN:
1313                 fbi->lccr0 = LCCR0_CMS;
1314                 break;
1315         case LCD_TYPE_MONO_DSTN:
1316                 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1317                 break;
1318         case LCD_TYPE_COLOR_STN:
1319                 fbi->lccr0 = 0;
1320                 break;
1321         case LCD_TYPE_COLOR_DSTN:
1322                 fbi->lccr0 = LCCR0_SDS;
1323                 break;
1324         case LCD_TYPE_COLOR_TFT:
1325                 fbi->lccr0 = LCCR0_PAS;
1326                 break;
1327         case LCD_TYPE_SMART_PANEL:
1328                 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1329                 break;
1330         default:
1331                 /* fall back to backward compatibility way */
1332                 fbi->lccr0 = inf->lccr0;
1333                 fbi->lccr3 = inf->lccr3;
1334                 fbi->lccr4 = inf->lccr4;
1335                 goto decode_mode;
1336         }
1337
1338         if (lcd_conn == LCD_MONO_STN_8BPP)
1339                 fbi->lccr0 |= LCCR0_DPD;
1340
1341         fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1342         fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1343         fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL)  ? LCCR3_PCP : 0;
1344
1345 decode_mode:
1346         pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes);
1347 }
1348
1349 static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
1350 {
1351         struct pxafb_info *fbi;
1352         void *addr;
1353         struct pxafb_mach_info *inf = dev->platform_data;
1354         struct pxafb_mode_info *mode = inf->modes;
1355
1356         /* Alloc the pxafb_info and pseudo_palette in one step */
1357         fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1358         if (!fbi)
1359                 return NULL;
1360
1361         memset(fbi, 0, sizeof(struct pxafb_info));
1362         fbi->dev = dev;
1363
1364         fbi->clk = clk_get(dev, "LCDCLK");
1365         if (IS_ERR(fbi->clk)) {
1366                 kfree(fbi);
1367                 return NULL;
1368         }
1369
1370         strcpy(fbi->fb.fix.id, PXA_NAME);
1371
1372         fbi->fb.fix.type        = FB_TYPE_PACKED_PIXELS;
1373         fbi->fb.fix.type_aux    = 0;
1374         fbi->fb.fix.xpanstep    = 0;
1375         fbi->fb.fix.ypanstep    = 0;
1376         fbi->fb.fix.ywrapstep   = 0;
1377         fbi->fb.fix.accel       = FB_ACCEL_NONE;
1378
1379         fbi->fb.var.nonstd      = 0;
1380         fbi->fb.var.activate    = FB_ACTIVATE_NOW;
1381         fbi->fb.var.height      = -1;
1382         fbi->fb.var.width       = -1;
1383         fbi->fb.var.accel_flags = 0;
1384         fbi->fb.var.vmode       = FB_VMODE_NONINTERLACED;
1385
1386         fbi->fb.fbops           = &pxafb_ops;
1387         fbi->fb.flags           = FBINFO_DEFAULT;
1388         fbi->fb.node            = -1;
1389
1390         addr = fbi;
1391         addr = addr + sizeof(struct pxafb_info);
1392         fbi->fb.pseudo_palette  = addr;
1393
1394         fbi->state              = C_STARTUP;
1395         fbi->task_state         = (u_char)-1;
1396
1397         pxafb_decode_mach_info(fbi, inf);
1398
1399         init_waitqueue_head(&fbi->ctrlr_wait);
1400         INIT_WORK(&fbi->task, pxafb_task);
1401         init_MUTEX(&fbi->ctrlr_sem);
1402         init_completion(&fbi->disable_done);
1403 #ifdef CONFIG_FB_PXA_SMARTPANEL
1404         init_completion(&fbi->command_done);
1405         init_completion(&fbi->refresh_done);
1406 #endif
1407
1408         return fbi;
1409 }
1410
1411 #ifdef CONFIG_FB_PXA_PARAMETERS
1412 static int __init parse_opt_mode(struct device *dev, const char *this_opt)
1413 {
1414         struct pxafb_mach_info *inf = dev->platform_data;
1415
1416         const char *name = this_opt+5;
1417         unsigned int namelen = strlen(name);
1418         int res_specified = 0, bpp_specified = 0;
1419         unsigned int xres = 0, yres = 0, bpp = 0;
1420         int yres_specified = 0;
1421         int i;
1422         for (i = namelen-1; i >= 0; i--) {
1423                 switch (name[i]) {
1424                 case '-':
1425                         namelen = i;
1426                         if (!bpp_specified && !yres_specified) {
1427                                 bpp = simple_strtoul(&name[i+1], NULL, 0);
1428                                 bpp_specified = 1;
1429                         } else
1430                                 goto done;
1431                         break;
1432                 case 'x':
1433                         if (!yres_specified) {
1434                                 yres = simple_strtoul(&name[i+1], NULL, 0);
1435                                 yres_specified = 1;
1436                         } else
1437                                 goto done;
1438                         break;
1439                 case '0' ... '9':
1440                         break;
1441                 default:
1442                         goto done;
1443                 }
1444         }
1445         if (i < 0 && yres_specified) {
1446                 xres = simple_strtoul(name, NULL, 0);
1447                 res_specified = 1;
1448         }
1449 done:
1450         if (res_specified) {
1451                 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1452                 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1453         }
1454         if (bpp_specified)
1455                 switch (bpp) {
1456                 case 1:
1457                 case 2:
1458                 case 4:
1459                 case 8:
1460                 case 16:
1461                         inf->modes[0].bpp = bpp;
1462                         dev_info(dev, "overriding bit depth: %d\n", bpp);
1463                         break;
1464                 default:
1465                         dev_err(dev, "Depth %d is not valid\n", bpp);
1466                         return -EINVAL;
1467                 }
1468         return 0;
1469 }
1470
1471 static int __init parse_opt(struct device *dev, char *this_opt)
1472 {
1473         struct pxafb_mach_info *inf = dev->platform_data;
1474         struct pxafb_mode_info *mode = &inf->modes[0];
1475         char s[64];
1476
1477         s[0] = '\0';
1478
1479         if (!strncmp(this_opt, "mode:", 5)) {
1480                 return parse_opt_mode(dev, this_opt);
1481         } else if (!strncmp(this_opt, "pixclock:", 9)) {
1482                 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1483                 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1484         } else if (!strncmp(this_opt, "left:", 5)) {
1485                 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1486                 sprintf(s, "left: %u\n", mode->left_margin);
1487         } else if (!strncmp(this_opt, "right:", 6)) {
1488                 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1489                 sprintf(s, "right: %u\n", mode->right_margin);
1490         } else if (!strncmp(this_opt, "upper:", 6)) {
1491                 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1492                 sprintf(s, "upper: %u\n", mode->upper_margin);
1493         } else if (!strncmp(this_opt, "lower:", 6)) {
1494                 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1495                 sprintf(s, "lower: %u\n", mode->lower_margin);
1496         } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1497                 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1498                 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1499         } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1500                 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1501                 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1502         } else if (!strncmp(this_opt, "hsync:", 6)) {
1503                 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1504                         sprintf(s, "hsync: Active Low\n");
1505                         mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1506                 } else {
1507                         sprintf(s, "hsync: Active High\n");
1508                         mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1509                 }
1510         } else if (!strncmp(this_opt, "vsync:", 6)) {
1511                 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1512                         sprintf(s, "vsync: Active Low\n");
1513                         mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1514                 } else {
1515                         sprintf(s, "vsync: Active High\n");
1516                         mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1517                 }
1518         } else if (!strncmp(this_opt, "dpc:", 4)) {
1519                 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1520                         sprintf(s, "double pixel clock: false\n");
1521                         inf->lccr3 &= ~LCCR3_DPC;
1522                 } else {
1523                         sprintf(s, "double pixel clock: true\n");
1524                         inf->lccr3 |= LCCR3_DPC;
1525                 }
1526         } else if (!strncmp(this_opt, "outputen:", 9)) {
1527                 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1528                         sprintf(s, "output enable: active low\n");
1529                         inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1530                 } else {
1531                         sprintf(s, "output enable: active high\n");
1532                         inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1533                 }
1534         } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1535                 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1536                         sprintf(s, "pixel clock polarity: falling edge\n");
1537                         inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1538                 } else {
1539                         sprintf(s, "pixel clock polarity: rising edge\n");
1540                         inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1541                 }
1542         } else if (!strncmp(this_opt, "color", 5)) {
1543                 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1544         } else if (!strncmp(this_opt, "mono", 4)) {
1545                 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1546         } else if (!strncmp(this_opt, "active", 6)) {
1547                 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1548         } else if (!strncmp(this_opt, "passive", 7)) {
1549                 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1550         } else if (!strncmp(this_opt, "single", 6)) {
1551                 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1552         } else if (!strncmp(this_opt, "dual", 4)) {
1553                 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1554         } else if (!strncmp(this_opt, "4pix", 4)) {
1555                 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1556         } else if (!strncmp(this_opt, "8pix", 4)) {
1557                 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1558         } else {
1559                 dev_err(dev, "unknown option: %s\n", this_opt);
1560                 return -EINVAL;
1561         }
1562
1563         if (s[0] != '\0')
1564                 dev_info(dev, "override %s", s);
1565
1566         return 0;
1567 }
1568
1569 static int __init pxafb_parse_options(struct device *dev, char *options)
1570 {
1571         char *this_opt;
1572         int ret;
1573
1574         if (!options || !*options)
1575                 return 0;
1576
1577         dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1578
1579         /* could be made table driven or similar?... */
1580         while ((this_opt = strsep(&options, ",")) != NULL) {
1581                 ret = parse_opt(dev, this_opt);
1582                 if (ret)
1583                         return ret;
1584         }
1585         return 0;
1586 }
1587
1588 static char g_options[256] __devinitdata = "";
1589
1590 #ifndef CONFIG_MODULES
1591 static int __devinit pxafb_setup_options(void)
1592 {
1593         char *options = NULL;
1594
1595         if (fb_get_options("pxafb", &options))
1596                 return -ENODEV;
1597
1598         if (options)
1599                 strlcpy(g_options, options, sizeof(g_options));
1600
1601         return 0;
1602 }
1603 #else
1604 #define pxafb_setup_options()           (0)
1605
1606 module_param_string(options, g_options, sizeof(g_options), 0);
1607 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1608 #endif
1609
1610 #else
1611 #define pxafb_parse_options(...)        (0)
1612 #define pxafb_setup_options()           (0)
1613 #endif
1614
1615 static int __init pxafb_probe(struct platform_device *dev)
1616 {
1617         struct pxafb_info *fbi;
1618         struct pxafb_mach_info *inf;
1619         struct resource *r;
1620         int irq, ret;
1621
1622         dev_dbg(&dev->dev, "pxafb_probe\n");
1623
1624         inf = dev->dev.platform_data;
1625         ret = -ENOMEM;
1626         fbi = NULL;
1627         if (!inf)
1628                 goto failed;
1629
1630         ret = pxafb_parse_options(&dev->dev, g_options);
1631         if (ret < 0)
1632                 goto failed;
1633
1634 #ifdef DEBUG_VAR
1635         /* Check for various illegal bit-combinations. Currently only
1636          * a warning is given. */
1637
1638         if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1639                 dev_warn(&dev->dev, "machine LCCR0 setting contains "
1640                                 "illegal bits: %08x\n",
1641                         inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1642         if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1643                 dev_warn(&dev->dev, "machine LCCR3 setting contains "
1644                                 "illegal bits: %08x\n",
1645                         inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1646         if (inf->lccr0 & LCCR0_DPD &&
1647             ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1648              (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1649              (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
1650                 dev_warn(&dev->dev, "Double Pixel Data (DPD) mode is "
1651                                 "only valid in passive mono"
1652                                 " single panel mode\n");
1653         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1654             (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1655                 dev_warn(&dev->dev, "Dual panel only valid in passive mode\n");
1656         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1657              (inf->modes->upper_margin || inf->modes->lower_margin))
1658                 dev_warn(&dev->dev, "Upper and lower margins must be 0 in "
1659                                 "passive mode\n");
1660 #endif
1661
1662         dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
1663                         inf->modes->xres,
1664                         inf->modes->yres,
1665                         inf->modes->bpp);
1666         if (inf->modes->xres == 0 ||
1667             inf->modes->yres == 0 ||
1668             inf->modes->bpp == 0) {
1669                 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1670                 ret = -EINVAL;
1671                 goto failed;
1672         }
1673         pxafb_backlight_power = inf->pxafb_backlight_power;
1674         pxafb_lcd_power = inf->pxafb_lcd_power;
1675         fbi = pxafb_init_fbinfo(&dev->dev);
1676         if (!fbi) {
1677                 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
1678                 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
1679                 ret = -ENOMEM;
1680                 goto failed;
1681         }
1682
1683         r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1684         if (r == NULL) {
1685                 dev_err(&dev->dev, "no I/O memory resource defined\n");
1686                 ret = -ENODEV;
1687                 goto failed;
1688         }
1689
1690         r = request_mem_region(r->start, r->end - r->start + 1, dev->name);
1691         if (r == NULL) {
1692                 dev_err(&dev->dev, "failed to request I/O memory\n");
1693                 ret = -EBUSY;
1694                 goto failed;
1695         }
1696
1697         fbi->mmio_base = ioremap(r->start, r->end - r->start + 1);
1698         if (fbi->mmio_base == NULL) {
1699                 dev_err(&dev->dev, "failed to map I/O memory\n");
1700                 ret = -EBUSY;
1701                 goto failed_free_res;
1702         }
1703
1704         /* Initialize video memory */
1705         ret = pxafb_map_video_memory(fbi);
1706         if (ret) {
1707                 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1708                 ret = -ENOMEM;
1709                 goto failed_free_io;
1710         }
1711
1712         irq = platform_get_irq(dev, 0);
1713         if (irq < 0) {
1714                 dev_err(&dev->dev, "no IRQ defined\n");
1715                 ret = -ENODEV;
1716                 goto failed_free_mem;
1717         }
1718
1719         ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1720         if (ret) {
1721                 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1722                 ret = -EBUSY;
1723                 goto failed_free_mem;
1724         }
1725
1726 #ifdef CONFIG_FB_PXA_SMARTPANEL
1727         ret = pxafb_smart_init(fbi);
1728         if (ret) {
1729                 dev_err(&dev->dev, "failed to initialize smartpanel\n");
1730                 goto failed_free_irq;
1731         }
1732 #endif
1733         /*
1734          * This makes sure that our colour bitfield
1735          * descriptors are correctly initialised.
1736          */
1737         pxafb_check_var(&fbi->fb.var, &fbi->fb);
1738         pxafb_set_par(&fbi->fb);
1739
1740         platform_set_drvdata(dev, fbi);
1741
1742         ret = register_framebuffer(&fbi->fb);
1743         if (ret < 0) {
1744                 dev_err(&dev->dev,
1745                         "Failed to register framebuffer device: %d\n", ret);
1746                 goto failed_free_irq;
1747         }
1748
1749 #ifdef CONFIG_CPU_FREQ
1750         fbi->freq_transition.notifier_call = pxafb_freq_transition;
1751         fbi->freq_policy.notifier_call = pxafb_freq_policy;
1752         cpufreq_register_notifier(&fbi->freq_transition,
1753                                 CPUFREQ_TRANSITION_NOTIFIER);
1754         cpufreq_register_notifier(&fbi->freq_policy,
1755                                 CPUFREQ_POLICY_NOTIFIER);
1756 #endif
1757
1758         /*
1759          * Ok, now enable the LCD controller
1760          */
1761         set_ctrlr_state(fbi, C_ENABLE);
1762
1763         return 0;
1764
1765 failed_free_irq:
1766         free_irq(irq, fbi);
1767 failed_free_res:
1768         release_mem_region(r->start, r->end - r->start + 1);
1769 failed_free_io:
1770         iounmap(fbi->mmio_base);
1771 failed_free_mem:
1772         dma_free_writecombine(&dev->dev, fbi->map_size,
1773                         fbi->map_cpu, fbi->map_dma);
1774 failed:
1775         platform_set_drvdata(dev, NULL);
1776         kfree(fbi);
1777         return ret;
1778 }
1779
1780 static struct platform_driver pxafb_driver = {
1781         .probe          = pxafb_probe,
1782         .suspend        = pxafb_suspend,
1783         .resume         = pxafb_resume,
1784         .driver         = {
1785                 .name   = "pxa2xx-fb",
1786         },
1787 };
1788
1789 static int __devinit pxafb_init(void)
1790 {
1791         if (pxafb_setup_options())
1792                 return -EINVAL;
1793
1794         return platform_driver_register(&pxafb_driver);
1795 }
1796
1797 module_init(pxafb_init);
1798
1799 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1800 MODULE_LICENSE("GPL");