git.oblomov.eu Git - linux-2.6/blob - drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *  $Id$
   4  *
   5  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  *
  20  */
  21
  22 #include <linux/errno.h>
  23 #include <linux/string.h>
  24 #include <linux/slab.h>
  25 #include <linux/firmware.h>
  26 #include <linux/videodev2.h>
  27 #include <media/v4l2-common.h>
  28 #include <asm/semaphore.h>
  29 #include "pvrusb2.h"
  30 #include "pvrusb2-std.h"
  31 #include "pvrusb2-util.h"
  32 #include "pvrusb2-hdw.h"
  33 #include "pvrusb2-i2c-core.h"
  34 #include "pvrusb2-tuner.h"
  35 #include "pvrusb2-eeprom.h"
  36 #include "pvrusb2-hdw-internal.h"
  37 #include "pvrusb2-encoder.h"
  38 #include "pvrusb2-debug.h"
  39
  40 struct usb_device_id pvr2_device_table[] = {
  41         [PVR2_HDW_TYPE_29XXX] = { USB_DEVICE(0x2040, 0x2900) },
  42         [PVR2_HDW_TYPE_24XXX] = { USB_DEVICE(0x2040, 0x2400) },
  43         { }
  44 };
  45
  46 MODULE_DEVICE_TABLE(usb, pvr2_device_table);
  47
  48 static const char *pvr2_device_names[] = {
  49         [PVR2_HDW_TYPE_29XXX] = "WinTV PVR USB2 Model Category 29xxxx",
  50         [PVR2_HDW_TYPE_24XXX] = "WinTV PVR USB2 Model Category 24xxxx",
  51 };
  52
  53 struct pvr2_string_table {
  54         const char **lst;
  55         unsigned int cnt;
  56 };
  57
  58 // Names of other client modules to request for 24xxx model hardware
  59 static const char *pvr2_client_24xxx[] = {
  60         "cx25840",
  61         "tuner",
  62         "wm8775",
  63 };
  64
  65 // Names of other client modules to request for 29xxx model hardware
  66 static const char *pvr2_client_29xxx[] = {
  67         "msp3400",
  68         "saa7115",
  69         "tuner",
  70 };
  71
  72 static struct pvr2_string_table pvr2_client_lists[] = {
  73         [PVR2_HDW_TYPE_29XXX] = {
  74                 pvr2_client_29xxx,
  75                 sizeof(pvr2_client_29xxx)/sizeof(pvr2_client_29xxx[0]),
  76         },
  77         [PVR2_HDW_TYPE_24XXX] = {
  78                 pvr2_client_24xxx,
  79                 sizeof(pvr2_client_24xxx)/sizeof(pvr2_client_24xxx[0]),
  80         },
  81 };
  82
  83 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  84 static DECLARE_MUTEX(pvr2_unit_sem);
  85
  86 static int ctlchg = 0;
  87 static int initusbreset = 1;
  88 static int procreload = 0;
  89 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  90 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  91 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  92 static int init_pause_msec = 0;
  93
  94 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  95 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  96 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  97 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  98 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
  99 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
 100 module_param(procreload, int, S_IRUGO|S_IWUSR);
 101 MODULE_PARM_DESC(procreload,
 102                  "Attempt init failure recovery with firmware reload");
 103 module_param_array(tuner,    int, NULL, 0444);
 104 MODULE_PARM_DESC(tuner,"specify installed tuner type");
 105 module_param_array(video_std,    int, NULL, 0444);
 106 MODULE_PARM_DESC(video_std,"specify initial video standard");
 107 module_param_array(tolerance,    int, NULL, 0444);
 108 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
 109
 110 #define PVR2_CTL_WRITE_ENDPOINT  0x01
 111 #define PVR2_CTL_READ_ENDPOINT   0x81
 112
 113 #define PVR2_GPIO_IN 0x9008
 114 #define PVR2_GPIO_OUT 0x900c
 115 #define PVR2_GPIO_DIR 0x9020
 116
 117 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 118
 119 #define PVR2_FIRMWARE_ENDPOINT   0x02
 120
 121 /* size of a firmware chunk */
 122 #define FIRMWARE_CHUNK_SIZE 0x2000
 123
 124 /* Define the list of additional controls we'll dynamically construct based
 125    on query of the cx2341x module. */
 126 struct pvr2_mpeg_ids {
 127         const char *strid;
 128         int id;
 129 };
 130 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 131         {
 132                 .strid = "audio_layer",
 133                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 134         },{
 135                 .strid = "audio_bitrate",
 136                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 137         },{
 138                 /* Already using audio_mode elsewhere :-( */
 139                 .strid = "mpeg_audio_mode",
 140                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 141         },{
 142                 .strid = "mpeg_audio_mode_extension",
 143                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 144         },{
 145                 .strid = "audio_emphasis",
 146                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 147         },{
 148                 .strid = "audio_crc",
 149                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 150         },{
 151                 .strid = "video_aspect",
 152                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 153         },{
 154                 .strid = "video_b_frames",
 155                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 156         },{
 157                 .strid = "video_gop_size",
 158                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 159         },{
 160                 .strid = "video_gop_closure",
 161                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 162         },{
 163                 .strid = "video_pulldown",
 164                 .id = V4L2_CID_MPEG_VIDEO_PULLDOWN,
 165         },{
 166                 .strid = "video_bitrate_mode",
 167                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 168         },{
 169                 .strid = "video_bitrate",
 170                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 171         },{
 172                 .strid = "video_bitrate_peak",
 173                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 174         },{
 175                 .strid = "video_temporal_decimation",
 176                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 177         },{
 178                 .strid = "stream_type",
 179                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 180         },{
 181                 .strid = "video_spatial_filter_mode",
 182                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 183         },{
 184                 .strid = "video_spatial_filter",
 185                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 186         },{
 187                 .strid = "video_luma_spatial_filter_type",
 188                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 189         },{
 190                 .strid = "video_chroma_spatial_filter_type",
 191                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 192         },{
 193                 .strid = "video_temporal_filter_mode",
 194                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 195         },{
 196                 .strid = "video_temporal_filter",
 197                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 198         },{
 199                 .strid = "video_median_filter_type",
 200                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 201         },{
 202                 .strid = "video_luma_median_filter_top",
 203                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 204         },{
 205                 .strid = "video_luma_median_filter_bottom",
 206                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 207         },{
 208                 .strid = "video_chroma_median_filter_top",
 209                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 210         },{
 211                 .strid = "video_chroma_median_filter_bottom",
 212                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 213         }
 214 };
 215 #define MPEGDEF_COUNT (sizeof(mpeg_ids)/sizeof(mpeg_ids[0]))
 216
 217
 218 static const char *control_values_srate[] = {
 219         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 220         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 221         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 222 };
 223
 224
 225
 226 static const char *control_values_input[] = {
 227         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 228         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 229         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 230         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 231 };
 232
 233
 234 static const char *control_values_audiomode[] = {
 235         [V4L2_TUNER_MODE_MONO]   = "Mono",
 236         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 237         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 238         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 239         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 240 };
 241
 242
 243 static const char *control_values_hsm[] = {
 244         [PVR2_CVAL_HSM_FAIL] = "Fail",
 245         [PVR2_CVAL_HSM_HIGH] = "High",
 246         [PVR2_CVAL_HSM_FULL] = "Full",
 247 };
 248
 249
 250 static const char *control_values_subsystem[] = {
 251         [PVR2_SUBSYS_B_ENC_FIRMWARE]  = "enc_firmware",
 252         [PVR2_SUBSYS_B_ENC_CFG] = "enc_config",
 253         [PVR2_SUBSYS_B_DIGITIZER_RUN] = "digitizer_run",
 254         [PVR2_SUBSYS_B_USBSTREAM_RUN] = "usbstream_run",
 255         [PVR2_SUBSYS_B_ENC_RUN] = "enc_run",
 256 };
 257
 258 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 259 static int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw);
 260 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 261 static unsigned int pvr2_hdw_get_signal_status_internal(struct pvr2_hdw *hdw);
 262 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 263 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 264 static void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw);
 265 static void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
 266                                             unsigned long msk,
 267                                             unsigned long val);
 268 static void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
 269                                                    unsigned long msk,
 270                                                    unsigned long val);
 271 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 272                                 unsigned int timeout,int probe_fl,
 273                                 void *write_data,unsigned int write_len,
 274                                 void *read_data,unsigned int read_len);
 275 static int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res);
 276 static int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res);
 277
 278 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 279 {
 280         struct pvr2_hdw *hdw = cptr->hdw;
 281         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 282                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 283         } else {
 284                 *vp = 0;
 285         }
 286         return 0;
 287 }
 288
 289 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 290 {
 291         struct pvr2_hdw *hdw = cptr->hdw;
 292         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 293                 hdw->freqTable[hdw->freqProgSlot-1] = v;
 294         }
 295         return 0;
 296 }
 297
 298 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 299 {
 300         *vp = cptr->hdw->freqProgSlot;
 301         return 0;
 302 }
 303
 304 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 305 {
 306         struct pvr2_hdw *hdw = cptr->hdw;
 307         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 308                 hdw->freqProgSlot = v;
 309         }
 310         return 0;
 311 }
 312
 313 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 314 {
 315         *vp = cptr->hdw->freqSlot;
 316         return 0;
 317 }
 318
 319 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int v)
 320 {
 321         unsigned freq = 0;
 322         struct pvr2_hdw *hdw = cptr->hdw;
 323         hdw->freqSlot = v;
 324         if ((hdw->freqSlot > 0) && (hdw->freqSlot <= FREQTABLE_SIZE)) {
 325                 freq = hdw->freqTable[hdw->freqSlot-1];
 326         }
 327         if (freq && (freq != hdw->freqVal)) {
 328                 hdw->freqVal = freq;
 329                 hdw->freqDirty = !0;
 330         }
 331         return 0;
 332 }
 333
 334 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 335 {
 336         *vp = cptr->hdw->freqVal;
 337         return 0;
 338 }
 339
 340 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 341 {
 342         return cptr->hdw->freqDirty != 0;
 343 }
 344
 345 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 346 {
 347         cptr->hdw->freqDirty = 0;
 348 }
 349
 350 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 351 {
 352         struct pvr2_hdw *hdw = cptr->hdw;
 353         hdw->freqVal = v;
 354         hdw->freqDirty = !0;
 355         hdw->freqSlot = 0;
 356         return 0;
 357 }
 358
 359 static int ctrl_hres_max_get(struct pvr2_ctrl *cptr,int *vp)
 360 {
 361         /* If we're dealing with a 24xxx device, force the horizontal
 362            maximum to be 720 no matter what, since we can't get the device
 363            to work properly with any other value.  Otherwise just return
 364            the normal value. */
 365         *vp = cptr->info->def.type_int.max_value;
 366         if (cptr->hdw->hdw_type == PVR2_HDW_TYPE_24XXX) *vp = 720;
 367         return 0;
 368 }
 369
 370 static int ctrl_hres_min_get(struct pvr2_ctrl *cptr,int *vp)
 371 {
 372         /* If we're dealing with a 24xxx device, force the horizontal
 373            minimum to be 720 no matter what, since we can't get the device
 374            to work properly with any other value.  Otherwise just return
 375            the normal value. */
 376         *vp = cptr->info->def.type_int.min_value;
 377         if (cptr->hdw->hdw_type == PVR2_HDW_TYPE_24XXX) *vp = 720;
 378         return 0;
 379 }
 380
 381 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 382 {
 383         /* Actual maximum depends on the video standard in effect. */
 384         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 385                 *vp = 480;
 386         } else {
 387                 *vp = 576;
 388         }
 389         return 0;
 390 }
 391
 392 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 393 {
 394         /* Actual minimum depends on device type. */
 395         if (cptr->hdw->hdw_type == PVR2_HDW_TYPE_24XXX) {
 396                 *vp = 75;
 397         } else {
 398                 *vp = 17;
 399         }
 400         return 0;
 401 }
 402
 403 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 404 {
 405         return cptr->hdw->enc_stale != 0;
 406 }
 407
 408 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 409 {
 410         cptr->hdw->enc_stale = 0;
 411 }
 412
 413 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 414 {
 415         int ret;
 416         struct v4l2_ext_controls cs;
 417         struct v4l2_ext_control c1;
 418         memset(&cs,0,sizeof(cs));
 419         memset(&c1,0,sizeof(c1));
 420         cs.controls = &c1;
 421         cs.count = 1;
 422         c1.id = cptr->info->v4l_id;
 423         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state,&cs,
 424                                 VIDIOC_G_EXT_CTRLS);
 425         if (ret) return ret;
 426         *vp = c1.value;
 427         return 0;
 428 }
 429
 430 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 431 {
 432         int ret;
 433         struct v4l2_ext_controls cs;
 434         struct v4l2_ext_control c1;
 435         memset(&cs,0,sizeof(cs));
 436         memset(&c1,0,sizeof(c1));
 437         cs.controls = &c1;
 438         cs.count = 1;
 439         c1.id = cptr->info->v4l_id;
 440         c1.value = v;
 441         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state,&cs,
 442                                 VIDIOC_S_EXT_CTRLS);
 443         if (ret) return ret;
 444         cptr->hdw->enc_stale = !0;
 445         return 0;
 446 }
 447
 448 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 449 {
 450         struct v4l2_queryctrl qctrl;
 451         struct pvr2_ctl_info *info;
 452         qctrl.id = cptr->info->v4l_id;
 453         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 454         /* Strip out the const so we can adjust a function pointer.  It's
 455            OK to do this here because we know this is a dynamically created
 456            control, so the underlying storage for the info pointer is (a)
 457            private to us, and (b) not in read-only storage.  Either we do
 458            this or we significantly complicate the underlying control
 459            implementation. */
 460         info = (struct pvr2_ctl_info *)(cptr->info);
 461         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 462                 if (info->set_value) {
 463                         info->set_value = NULL;
 464                 }
 465         } else {
 466                 if (!(info->set_value)) {
 467                         info->set_value = ctrl_cx2341x_set;
 468                 }
 469         }
 470         return qctrl.flags;
 471 }
 472
 473 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 474 {
 475         *vp = cptr->hdw->flag_streaming_enabled;
 476         return 0;
 477 }
 478
 479 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 480 {
 481         int result = pvr2_hdw_is_hsm(cptr->hdw);
 482         *vp = PVR2_CVAL_HSM_FULL;
 483         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 484         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 485         return 0;
 486 }
 487
 488 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 489 {
 490         *vp = cptr->hdw->std_mask_avail;
 491         return 0;
 492 }
 493
 494 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 495 {
 496         struct pvr2_hdw *hdw = cptr->hdw;
 497         v4l2_std_id ns;
 498         ns = hdw->std_mask_avail;
 499         ns = (ns & ~m) | (v & m);
 500         if (ns == hdw->std_mask_avail) return 0;
 501         hdw->std_mask_avail = ns;
 502         pvr2_hdw_internal_set_std_avail(hdw);
 503         pvr2_hdw_internal_find_stdenum(hdw);
 504         return 0;
 505 }
 506
 507 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 508                                char *bufPtr,unsigned int bufSize,
 509                                unsigned int *len)
 510 {
 511         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 512         return 0;
 513 }
 514
 515 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 516                                const char *bufPtr,unsigned int bufSize,
 517                                int *mskp,int *valp)
 518 {
 519         int ret;
 520         v4l2_std_id id;
 521         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 522         if (ret < 0) return ret;
 523         if (mskp) *mskp = id;
 524         if (valp) *valp = id;
 525         return 0;
 526 }
 527
 528 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 529 {
 530         *vp = cptr->hdw->std_mask_cur;
 531         return 0;
 532 }
 533
 534 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 535 {
 536         struct pvr2_hdw *hdw = cptr->hdw;
 537         v4l2_std_id ns;
 538         ns = hdw->std_mask_cur;
 539         ns = (ns & ~m) | (v & m);
 540         if (ns == hdw->std_mask_cur) return 0;
 541         hdw->std_mask_cur = ns;
 542         hdw->std_dirty = !0;
 543         pvr2_hdw_internal_find_stdenum(hdw);
 544         return 0;
 545 }
 546
 547 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 548 {
 549         return cptr->hdw->std_dirty != 0;
 550 }
 551
 552 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 553 {
 554         cptr->hdw->std_dirty = 0;
 555 }
 556
 557 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 558 {
 559         *vp = ((pvr2_hdw_get_signal_status_internal(cptr->hdw) &
 560                 PVR2_SIGNAL_OK) ? 1 : 0);
 561         return 0;
 562 }
 563
 564 static int ctrl_subsys_get(struct pvr2_ctrl *cptr,int *vp)
 565 {
 566         *vp = cptr->hdw->subsys_enabled_mask;
 567         return 0;
 568 }
 569
 570 static int ctrl_subsys_set(struct pvr2_ctrl *cptr,int m,int v)
 571 {
 572         pvr2_hdw_subsys_bit_chg_no_lock(cptr->hdw,m,v);
 573         return 0;
 574 }
 575
 576 static int ctrl_subsys_stream_get(struct pvr2_ctrl *cptr,int *vp)
 577 {
 578         *vp = cptr->hdw->subsys_stream_mask;
 579         return 0;
 580 }
 581
 582 static int ctrl_subsys_stream_set(struct pvr2_ctrl *cptr,int m,int v)
 583 {
 584         pvr2_hdw_subsys_stream_bit_chg_no_lock(cptr->hdw,m,v);
 585         return 0;
 586 }
 587
 588 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 589 {
 590         struct pvr2_hdw *hdw = cptr->hdw;
 591         if (v < 0) return -EINVAL;
 592         if (v > hdw->std_enum_cnt) return -EINVAL;
 593         hdw->std_enum_cur = v;
 594         if (!v) return 0;
 595         v--;
 596         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 597         hdw->std_mask_cur = hdw->std_defs[v].id;
 598         hdw->std_dirty = !0;
 599         return 0;
 600 }
 601
 602
 603 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 604 {
 605         *vp = cptr->hdw->std_enum_cur;
 606         return 0;
 607 }
 608
 609
 610 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 611 {
 612         return cptr->hdw->std_dirty != 0;
 613 }
 614
 615
 616 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 617 {
 618         cptr->hdw->std_dirty = 0;
 619 }
 620
 621
 622 #define DEFINT(vmin,vmax) \
 623         .type = pvr2_ctl_int, \
 624         .def.type_int.min_value = vmin, \
 625         .def.type_int.max_value = vmax
 626
 627 #define DEFENUM(tab) \
 628         .type = pvr2_ctl_enum, \
 629         .def.type_enum.count = (sizeof(tab)/sizeof((tab)[0])), \
 630         .def.type_enum.value_names = tab
 631
 632 #define DEFBOOL \
 633         .type = pvr2_ctl_bool
 634
 635 #define DEFMASK(msk,tab) \
 636         .type = pvr2_ctl_bitmask, \
 637         .def.type_bitmask.valid_bits = msk, \
 638         .def.type_bitmask.bit_names = tab
 639
 640 #define DEFREF(vname) \
 641         .set_value = ctrl_set_##vname, \
 642         .get_value = ctrl_get_##vname, \
 643         .is_dirty = ctrl_isdirty_##vname, \
 644         .clear_dirty = ctrl_cleardirty_##vname
 645
 646
 647 #define VCREATE_FUNCS(vname) \
 648 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 649 {*vp = cptr->hdw->vname##_val; return 0;} \
 650 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 651 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 652 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 653 {return cptr->hdw->vname##_dirty != 0;} \
 654 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 655 {cptr->hdw->vname##_dirty = 0;}
 656
 657 VCREATE_FUNCS(brightness)
 658 VCREATE_FUNCS(contrast)
 659 VCREATE_FUNCS(saturation)
 660 VCREATE_FUNCS(hue)
 661 VCREATE_FUNCS(volume)
 662 VCREATE_FUNCS(balance)
 663 VCREATE_FUNCS(bass)
 664 VCREATE_FUNCS(treble)
 665 VCREATE_FUNCS(mute)
 666 VCREATE_FUNCS(input)
 667 VCREATE_FUNCS(audiomode)
 668 VCREATE_FUNCS(res_hor)
 669 VCREATE_FUNCS(res_ver)
 670 VCREATE_FUNCS(srate)
 671
 672 #define MIN_FREQ 55250000L
 673 #define MAX_FREQ 850000000L
 674
 675 /* Table definition of all controls which can be manipulated */
 676 static const struct pvr2_ctl_info control_defs[] = {
 677         {
 678                 .v4l_id = V4L2_CID_BRIGHTNESS,
 679                 .desc = "Brightness",
 680                 .name = "brightness",
 681                 .default_value = 128,
 682                 DEFREF(brightness),
 683                 DEFINT(0,255),
 684         },{
 685                 .v4l_id = V4L2_CID_CONTRAST,
 686                 .desc = "Contrast",
 687                 .name = "contrast",
 688                 .default_value = 68,
 689                 DEFREF(contrast),
 690                 DEFINT(0,127),
 691         },{
 692                 .v4l_id = V4L2_CID_SATURATION,
 693                 .desc = "Saturation",
 694                 .name = "saturation",
 695                 .default_value = 64,
 696                 DEFREF(saturation),
 697                 DEFINT(0,127),
 698         },{
 699                 .v4l_id = V4L2_CID_HUE,
 700                 .desc = "Hue",
 701                 .name = "hue",
 702                 .default_value = 0,
 703                 DEFREF(hue),
 704                 DEFINT(-128,127),
 705         },{
 706                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
 707                 .desc = "Volume",
 708                 .name = "volume",
 709                 .default_value = 65535,
 710                 DEFREF(volume),
 711                 DEFINT(0,65535),
 712         },{
 713                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
 714                 .desc = "Balance",
 715                 .name = "balance",
 716                 .default_value = 0,
 717                 DEFREF(balance),
 718                 DEFINT(-32768,32767),
 719         },{
 720                 .v4l_id = V4L2_CID_AUDIO_BASS,
 721                 .desc = "Bass",
 722                 .name = "bass",
 723                 .default_value = 0,
 724                 DEFREF(bass),
 725                 DEFINT(-32768,32767),
 726         },{
 727                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
 728                 .desc = "Treble",
 729                 .name = "treble",
 730                 .default_value = 0,
 731                 DEFREF(treble),
 732                 DEFINT(-32768,32767),
 733         },{
 734                 .v4l_id = V4L2_CID_AUDIO_MUTE,
 735                 .desc = "Mute",
 736                 .name = "mute",
 737                 .default_value = 0,
 738                 DEFREF(mute),
 739                 DEFBOOL,
 740         },{
 741                 .desc = "Video Source",
 742                 .name = "input",
 743                 .internal_id = PVR2_CID_INPUT,
 744                 .default_value = PVR2_CVAL_INPUT_TV,
 745                 DEFREF(input),
 746                 DEFENUM(control_values_input),
 747         },{
 748                 .desc = "Audio Mode",
 749                 .name = "audio_mode",
 750                 .internal_id = PVR2_CID_AUDIOMODE,
 751                 .default_value = V4L2_TUNER_MODE_STEREO,
 752                 DEFREF(audiomode),
 753                 DEFENUM(control_values_audiomode),
 754         },{
 755                 .desc = "Horizontal capture resolution",
 756                 .name = "resolution_hor",
 757                 .internal_id = PVR2_CID_HRES,
 758                 .default_value = 720,
 759                 DEFREF(res_hor),
 760                 DEFINT(19,720),
 761                 /* Hook in check for clamp on horizontal resolution in
 762                    order to avoid unsolved problem involving cx25840. */
 763                 .get_max_value = ctrl_hres_max_get,
 764                 .get_min_value = ctrl_hres_min_get,
 765         },{
 766                 .desc = "Vertical capture resolution",
 767                 .name = "resolution_ver",
 768                 .internal_id = PVR2_CID_VRES,
 769                 .default_value = 480,
 770                 DEFREF(res_ver),
 771                 DEFINT(17,576),
 772                 /* Hook in check for video standard and adjust maximum
 773                    depending on the standard. */
 774                 .get_max_value = ctrl_vres_max_get,
 775                 .get_min_value = ctrl_vres_min_get,
 776         },{
 777                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
 778                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
 779                 .desc = "Audio Sampling Frequency",
 780                 .name = "srate",
 781                 DEFREF(srate),
 782                 DEFENUM(control_values_srate),
 783         },{
 784                 .desc = "Tuner Frequency (Hz)",
 785                 .name = "frequency",
 786                 .internal_id = PVR2_CID_FREQUENCY,
 787                 .default_value = 175250000L,
 788                 .set_value = ctrl_freq_set,
 789                 .get_value = ctrl_freq_get,
 790                 .is_dirty = ctrl_freq_is_dirty,
 791                 .clear_dirty = ctrl_freq_clear_dirty,
 792                 DEFINT(MIN_FREQ,MAX_FREQ),
 793         },{
 794                 .desc = "Channel",
 795                 .name = "channel",
 796                 .set_value = ctrl_channel_set,
 797                 .get_value = ctrl_channel_get,
 798                 DEFINT(0,FREQTABLE_SIZE),
 799         },{
 800                 .desc = "Channel Program Frequency",
 801                 .name = "freq_table_value",
 802                 .set_value = ctrl_channelfreq_set,
 803                 .get_value = ctrl_channelfreq_get,
 804                 DEFINT(MIN_FREQ,MAX_FREQ),
 805         },{
 806                 .desc = "Channel Program ID",
 807                 .name = "freq_table_channel",
 808                 .set_value = ctrl_channelprog_set,
 809                 .get_value = ctrl_channelprog_get,
 810                 DEFINT(0,FREQTABLE_SIZE),
 811         },{
 812                 .desc = "Streaming Enabled",
 813                 .name = "streaming_enabled",
 814                 .get_value = ctrl_streamingenabled_get,
 815                 DEFBOOL,
 816         },{
 817                 .desc = "USB Speed",
 818                 .name = "usb_speed",
 819                 .get_value = ctrl_hsm_get,
 820                 DEFENUM(control_values_hsm),
 821         },{
 822                 .desc = "Signal Present",
 823                 .name = "signal_present",
 824                 .get_value = ctrl_signal_get,
 825                 DEFBOOL,
 826         },{
 827                 .desc = "Video Standards Available Mask",
 828                 .name = "video_standard_mask_available",
 829                 .internal_id = PVR2_CID_STDAVAIL,
 830                 .skip_init = !0,
 831                 .get_value = ctrl_stdavail_get,
 832                 .set_value = ctrl_stdavail_set,
 833                 .val_to_sym = ctrl_std_val_to_sym,
 834                 .sym_to_val = ctrl_std_sym_to_val,
 835                 .type = pvr2_ctl_bitmask,
 836         },{
 837                 .desc = "Video Standards In Use Mask",
 838                 .name = "video_standard_mask_active",
 839                 .internal_id = PVR2_CID_STDCUR,
 840                 .skip_init = !0,
 841                 .get_value = ctrl_stdcur_get,
 842                 .set_value = ctrl_stdcur_set,
 843                 .is_dirty = ctrl_stdcur_is_dirty,
 844                 .clear_dirty = ctrl_stdcur_clear_dirty,
 845                 .val_to_sym = ctrl_std_val_to_sym,
 846                 .sym_to_val = ctrl_std_sym_to_val,
 847                 .type = pvr2_ctl_bitmask,
 848         },{
 849                 .desc = "Subsystem enabled mask",
 850                 .name = "debug_subsys_mask",
 851                 .skip_init = !0,
 852                 .get_value = ctrl_subsys_get,
 853                 .set_value = ctrl_subsys_set,
 854                 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
 855         },{
 856                 .desc = "Subsystem stream mask",
 857                 .name = "debug_subsys_stream_mask",
 858                 .skip_init = !0,
 859                 .get_value = ctrl_subsys_stream_get,
 860                 .set_value = ctrl_subsys_stream_set,
 861                 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
 862         },{
 863                 .desc = "Video Standard Name",
 864                 .name = "video_standard",
 865                 .internal_id = PVR2_CID_STDENUM,
 866                 .skip_init = !0,
 867                 .get_value = ctrl_stdenumcur_get,
 868                 .set_value = ctrl_stdenumcur_set,
 869                 .is_dirty = ctrl_stdenumcur_is_dirty,
 870                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
 871                 .type = pvr2_ctl_enum,
 872         }
 873 };
 874
 875 #define CTRLDEF_COUNT (sizeof(control_defs)/sizeof(control_defs[0]))
 876
 877
 878 const char *pvr2_config_get_name(enum pvr2_config cfg)
 879 {
 880         switch (cfg) {
 881         case pvr2_config_empty: return "empty";
 882         case pvr2_config_mpeg: return "mpeg";
 883         case pvr2_config_vbi: return "vbi";
 884         case pvr2_config_radio: return "radio";
 885         }
 886         return "<unknown>";
 887 }
 888
 889
 890 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
 891 {
 892         return hdw->usb_dev;
 893 }
 894
 895
 896 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
 897 {
 898         return hdw->serial_number;
 899 }
 900
 901 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
 902 {
 903         return hdw->unit_number;
 904 }
 905
 906
 907 /* Attempt to locate one of the given set of files.  Messages are logged
 908    appropriate to what has been found.  The return value will be 0 or
 909    greater on success (it will be the index of the file name found) and
 910    fw_entry will be filled in.  Otherwise a negative error is returned on
 911    failure.  If the return value is -ENOENT then no viable firmware file
 912    could be located. */
 913 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
 914                                 const struct firmware **fw_entry,
 915                                 const char *fwtypename,
 916                                 unsigned int fwcount,
 917                                 const char *fwnames[])
 918 {
 919         unsigned int idx;
 920         int ret = -EINVAL;
 921         for (idx = 0; idx < fwcount; idx++) {
 922                 ret = request_firmware(fw_entry,
 923                                        fwnames[idx],
 924                                        &hdw->usb_dev->dev);
 925                 if (!ret) {
 926                         trace_firmware("Located %s firmware: %s;"
 927                                        " uploading...",
 928                                        fwtypename,
 929                                        fwnames[idx]);
 930                         return idx;
 931                 }
 932                 if (ret == -ENOENT) continue;
 933                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 934                            "request_firmware fatal error with code=%d",ret);
 935                 return ret;
 936         }
 937         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 938                    "***WARNING***"
 939                    " Device %s firmware"
 940                    " seems to be missing.",
 941                    fwtypename);
 942         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 943                    "Did you install the pvrusb2 firmware files"
 944                    " in their proper location?");
 945         if (fwcount == 1) {
 946                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 947                            "request_firmware unable to locate %s file %s",
 948                            fwtypename,fwnames[0]);
 949         } else {
 950                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 951                            "request_firmware unable to locate"
 952                            " one of the following %s files:",
 953                            fwtypename);
 954                 for (idx = 0; idx < fwcount; idx++) {
 955                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 956                                    "request_firmware: Failed to find %s",
 957                                    fwnames[idx]);
 958                 }
 959         }
 960         return ret;
 961 }
 962
 963
 964 /*
 965  * pvr2_upload_firmware1().
 966  *
 967  * Send the 8051 firmware to the device.  After the upload, arrange for
 968  * device to re-enumerate.
 969  *
 970  * NOTE : the pointer to the firmware data given by request_firmware()
 971  * is not suitable for an usb transaction.
 972  *
 973  */
 974 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
 975 {
 976         const struct firmware *fw_entry = NULL;
 977         void  *fw_ptr;
 978         unsigned int pipe;
 979         int ret;
 980         u16 address;
 981         static const char *fw_files_29xxx[] = {
 982                 "v4l-pvrusb2-29xxx-01.fw",
 983         };
 984         static const char *fw_files_24xxx[] = {
 985                 "v4l-pvrusb2-24xxx-01.fw",
 986         };
 987         static const struct pvr2_string_table fw_file_defs[] = {
 988                 [PVR2_HDW_TYPE_29XXX] = {
 989                         fw_files_29xxx,
 990                         sizeof(fw_files_29xxx)/sizeof(fw_files_29xxx[0]),
 991                 },
 992                 [PVR2_HDW_TYPE_24XXX] = {
 993                         fw_files_24xxx,
 994                         sizeof(fw_files_24xxx)/sizeof(fw_files_24xxx[0]),
 995                 },
 996         };
 997         hdw->fw1_state = FW1_STATE_FAILED; // default result
 998
 999         trace_firmware("pvr2_upload_firmware1");
1000
1001         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1002                                    fw_file_defs[hdw->hdw_type].cnt,
1003                                    fw_file_defs[hdw->hdw_type].lst);
1004         if (ret < 0) {
1005                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1006                 return ret;
1007         }
1008
1009         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1010         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1011
1012         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1013
1014         if (fw_entry->size != 0x2000){
1015                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1016                 release_firmware(fw_entry);
1017                 return -ENOMEM;
1018         }
1019
1020         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1021         if (fw_ptr == NULL){
1022                 release_firmware(fw_entry);
1023                 return -ENOMEM;
1024         }
1025
1026         /* We have to hold the CPU during firmware upload. */
1027         pvr2_hdw_cpureset_assert(hdw,1);
1028
1029         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1030            chunk. */
1031
1032         ret = 0;
1033         for(address = 0; address < fw_entry->size; address += 0x800) {
1034                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1035                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1036                                        0, fw_ptr, 0x800, HZ);
1037         }
1038
1039         trace_firmware("Upload done, releasing device's CPU");
1040
1041         /* Now release the CPU.  It will disconnect and reconnect later. */
1042         pvr2_hdw_cpureset_assert(hdw,0);
1043
1044         kfree(fw_ptr);
1045         release_firmware(fw_entry);
1046
1047         trace_firmware("Upload done (%d bytes sent)",ret);
1048
1049         /* We should have written 8192 bytes */
1050         if (ret == 8192) {
1051                 hdw->fw1_state = FW1_STATE_RELOAD;
1052                 return 0;
1053         }
1054
1055         return -EIO;
1056 }
1057
1058
1059 /*
1060  * pvr2_upload_firmware2()
1061  *
1062  * This uploads encoder firmware on endpoint 2.
1063  *
1064  */
1065
1066 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1067 {
1068         const struct firmware *fw_entry = NULL;
1069         void  *fw_ptr;
1070         unsigned int pipe, fw_len, fw_done;
1071         int actual_length;
1072         int ret = 0;
1073         int fwidx;
1074         static const char *fw_files[] = {
1075                 CX2341X_FIRM_ENC_FILENAME,
1076         };
1077
1078         trace_firmware("pvr2_upload_firmware2");
1079
1080         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1081                                    sizeof(fw_files)/sizeof(fw_files[0]),
1082                                    fw_files);
1083         if (ret < 0) return ret;
1084         fwidx = ret;
1085         ret = 0;
1086         /* Since we're about to completely reinitialize the encoder,
1087            invalidate our cached copy of its configuration state.  Next
1088            time we configure the encoder, then we'll fully configure it. */
1089         hdw->enc_cur_valid = 0;
1090
1091         /* First prepare firmware loading */
1092         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1093         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1094         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1095         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1096         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1097         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1098         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1099         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1100         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1101         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1102         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1103         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1104         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1105         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1106         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1107         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1108         ret |= pvr2_write_u8(hdw, 0x52, 0);
1109         ret |= pvr2_write_u16(hdw, 0x0600, 0);
1110
1111         if (ret) {
1112                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1113                            "firmware2 upload prep failed, ret=%d",ret);
1114                 release_firmware(fw_entry);
1115                 return ret;
1116         }
1117
1118         /* Now send firmware */
1119
1120         fw_len = fw_entry->size;
1121
1122         if (fw_len % FIRMWARE_CHUNK_SIZE) {
1123                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1124                            "size of %s firmware"
1125                            " must be a multiple of 8192B",
1126                            fw_files[fwidx]);
1127                 release_firmware(fw_entry);
1128                 return -1;
1129         }
1130
1131         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1132         if (fw_ptr == NULL){
1133                 release_firmware(fw_entry);
1134                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1135                            "failed to allocate memory for firmware2 upload");
1136                 return -ENOMEM;
1137         }
1138
1139         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1140
1141         for (fw_done = 0 ; (fw_done < fw_len) && !ret ;
1142              fw_done += FIRMWARE_CHUNK_SIZE ) {
1143                 int i;
1144                 memcpy(fw_ptr, fw_entry->data + fw_done, FIRMWARE_CHUNK_SIZE);
1145                 /* Usbsnoop log  shows that we must swap bytes... */
1146                 for (i = 0; i < FIRMWARE_CHUNK_SIZE/4 ; i++)
1147                         ((u32 *)fw_ptr)[i] = ___swab32(((u32 *)fw_ptr)[i]);
1148
1149                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,
1150                                     FIRMWARE_CHUNK_SIZE,
1151                                     &actual_length, HZ);
1152                 ret |= (actual_length != FIRMWARE_CHUNK_SIZE);
1153         }
1154
1155         trace_firmware("upload of %s : %i / %i ",
1156                        fw_files[fwidx],fw_done,fw_len);
1157
1158         kfree(fw_ptr);
1159         release_firmware(fw_entry);
1160
1161         if (ret) {
1162                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1163                            "firmware2 upload transfer failure");
1164                 return ret;
1165         }
1166
1167         /* Finish upload */
1168
1169         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1170         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1171         ret |= pvr2_write_u16(hdw, 0x0600, 0);
1172
1173         if (ret) {
1174                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1175                            "firmware2 upload post-proc failure");
1176         } else {
1177                 hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_FIRMWARE);
1178         }
1179         return ret;
1180 }
1181
1182
1183 #define FIRMWARE_RECOVERY_BITS \
1184         ((1<<PVR2_SUBSYS_B_ENC_CFG) | \
1185          (1<<PVR2_SUBSYS_B_ENC_RUN) | \
1186          (1<<PVR2_SUBSYS_B_ENC_FIRMWARE) | \
1187          (1<<PVR2_SUBSYS_B_USBSTREAM_RUN))
1188
1189 /*
1190
1191   This single function is key to pretty much everything.  The pvrusb2
1192   device can logically be viewed as a series of subsystems which can be
1193   stopped / started or unconfigured / configured.  To get things streaming,
1194   one must configure everything and start everything, but there may be
1195   various reasons over time to deconfigure something or stop something.
1196   This function handles all of this activity.  Everything EVERYWHERE that
1197   must affect a subsystem eventually comes here to do the work.
1198
1199   The current state of all subsystems is represented by a single bit mask,
1200   known as subsys_enabled_mask.  The bit positions are defined by the
1201   PVR2_SUBSYS_xxxx macros, with one subsystem per bit position.  At any
1202   time the set of configured or active subsystems can be queried just by
1203   looking at that mask.  To change bits in that mask, this function here
1204   must be called.  The "msk" argument indicates which bit positions to
1205   change, and the "val" argument defines the new values for the positions
1206   defined by "msk".
1207
1208   There is a priority ordering of starting / stopping things, and for
1209   multiple requested changes, this function implements that ordering.
1210   (Thus we will act on a request to load encoder firmware before we
1211   configure the encoder.)  In addition to priority ordering, there is a
1212   recovery strategy implemented here.  If a particular step fails and we
1213   detect that failure, this function will clear the affected subsystem bits
1214   and restart.  Thus we have a means for recovering from a dead encoder:
1215   Clear all bits that correspond to subsystems that we need to restart /
1216   reconfigure and start over.
1217
1218 */
1219 static void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
1220                                             unsigned long msk,
1221                                             unsigned long val)
1222 {
1223         unsigned long nmsk;
1224         unsigned long vmsk;
1225         int ret;
1226         unsigned int tryCount = 0;
1227
1228         if (!hdw->flag_ok) return;
1229
1230         msk &= PVR2_SUBSYS_ALL;
1231         nmsk = (hdw->subsys_enabled_mask & ~msk) | (val & msk);
1232         nmsk &= PVR2_SUBSYS_ALL;
1233
1234         for (;;) {
1235                 tryCount++;
1236                 if (!((nmsk ^ hdw->subsys_enabled_mask) &
1237                       PVR2_SUBSYS_ALL)) break;
1238                 if (tryCount > 4) {
1239                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1240                                    "Too many retries when configuring device;"
1241                                    " giving up");
1242                         pvr2_hdw_render_useless(hdw);
1243                         break;
1244                 }
1245                 if (tryCount > 1) {
1246                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1247                                    "Retrying device reconfiguration");
1248                 }
1249                 pvr2_trace(PVR2_TRACE_INIT,
1250                            "subsys mask changing 0x%lx:0x%lx"
1251                            " from 0x%lx to 0x%lx",
1252                            msk,val,hdw->subsys_enabled_mask,nmsk);
1253
1254                 vmsk = (nmsk ^ hdw->subsys_enabled_mask) &
1255                         hdw->subsys_enabled_mask;
1256                 if (vmsk) {
1257                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1258                                 pvr2_trace(PVR2_TRACE_CTL,
1259                                            "/*---TRACE_CTL----*/"
1260                                            " pvr2_encoder_stop");
1261                                 ret = pvr2_encoder_stop(hdw);
1262                                 if (ret) {
1263                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1264                                                    "Error recovery initiated");
1265                                         hdw->subsys_enabled_mask &=
1266                                                 ~FIRMWARE_RECOVERY_BITS;
1267                                         continue;
1268                                 }
1269                         }
1270                         if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1271                                 pvr2_trace(PVR2_TRACE_CTL,
1272                                            "/*---TRACE_CTL----*/"
1273                                            " pvr2_hdw_cmd_usbstream(0)");
1274                                 pvr2_hdw_cmd_usbstream(hdw,0);
1275                         }
1276                         if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1277                                 pvr2_trace(PVR2_TRACE_CTL,
1278                                            "/*---TRACE_CTL----*/"
1279                                            " decoder disable");
1280                                 if (hdw->decoder_ctrl) {
1281                                         hdw->decoder_ctrl->enable(
1282                                                 hdw->decoder_ctrl->ctxt,0);
1283                                 } else {
1284                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1285                                                    "WARNING:"
1286                                                    " No decoder present");
1287                                 }
1288                                 hdw->subsys_enabled_mask &=
1289                                         ~(1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1290                         }
1291                         if (vmsk & PVR2_SUBSYS_CFG_ALL) {
1292                                 hdw->subsys_enabled_mask &=
1293                                         ~(vmsk & PVR2_SUBSYS_CFG_ALL);
1294                         }
1295                 }
1296                 vmsk = (nmsk ^ hdw->subsys_enabled_mask) & nmsk;
1297                 if (vmsk) {
1298                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_FIRMWARE)) {
1299                                 pvr2_trace(PVR2_TRACE_CTL,
1300                                            "/*---TRACE_CTL----*/"
1301                                            " pvr2_upload_firmware2");
1302                                 ret = pvr2_upload_firmware2(hdw);
1303                                 if (ret) {
1304                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1305                                                    "Failure uploading encoder"
1306                                                    " firmware");
1307                                         pvr2_hdw_render_useless(hdw);
1308                                         break;
1309                                 }
1310                         }
1311                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_CFG)) {
1312                                 pvr2_trace(PVR2_TRACE_CTL,
1313                                            "/*---TRACE_CTL----*/"
1314                                            " pvr2_encoder_configure");
1315                                 ret = pvr2_encoder_configure(hdw);
1316                                 if (ret) {
1317                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1318                                                    "Error recovery initiated");
1319                                         hdw->subsys_enabled_mask &=
1320                                                 ~FIRMWARE_RECOVERY_BITS;
1321                                         continue;
1322                                 }
1323                         }
1324                         if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1325                                 pvr2_trace(PVR2_TRACE_CTL,
1326                                            "/*---TRACE_CTL----*/"
1327                                            " decoder enable");
1328                                 if (hdw->decoder_ctrl) {
1329                                         hdw->decoder_ctrl->enable(
1330                                                 hdw->decoder_ctrl->ctxt,!0);
1331                                 } else {
1332                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1333                                                    "WARNING:"
1334                                                    " No decoder present");
1335                                 }
1336                                 hdw->subsys_enabled_mask |=
1337                                         (1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1338                         }
1339                         if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1340                                 pvr2_trace(PVR2_TRACE_CTL,
1341                                            "/*---TRACE_CTL----*/"
1342                                            " pvr2_hdw_cmd_usbstream(1)");
1343                                 pvr2_hdw_cmd_usbstream(hdw,!0);
1344                         }
1345                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1346                                 pvr2_trace(PVR2_TRACE_CTL,
1347                                            "/*---TRACE_CTL----*/"
1348                                            " pvr2_encoder_start");
1349                                 ret = pvr2_encoder_start(hdw);
1350                                 if (ret) {
1351                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1352                                                    "Error recovery initiated");
1353                                         hdw->subsys_enabled_mask &=
1354                                                 ~FIRMWARE_RECOVERY_BITS;
1355                                         continue;
1356                                 }
1357                         }
1358                 }
1359         }
1360 }
1361
1362
1363 void pvr2_hdw_subsys_bit_chg(struct pvr2_hdw *hdw,
1364                              unsigned long msk,unsigned long val)
1365 {
1366         LOCK_TAKE(hdw->big_lock); do {
1367                 pvr2_hdw_subsys_bit_chg_no_lock(hdw,msk,val);
1368         } while (0); LOCK_GIVE(hdw->big_lock);
1369 }
1370
1371
1372 unsigned long pvr2_hdw_subsys_get(struct pvr2_hdw *hdw)
1373 {
1374         return hdw->subsys_enabled_mask;
1375 }
1376
1377
1378 unsigned long pvr2_hdw_subsys_stream_get(struct pvr2_hdw *hdw)
1379 {
1380         return hdw->subsys_stream_mask;
1381 }
1382
1383
1384 static void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
1385                                                    unsigned long msk,
1386                                                    unsigned long val)
1387 {
1388         unsigned long val2;
1389         msk &= PVR2_SUBSYS_ALL;
1390         val2 = ((hdw->subsys_stream_mask & ~msk) | (val & msk));
1391         pvr2_trace(PVR2_TRACE_INIT,
1392                    "stream mask changing 0x%lx:0x%lx from 0x%lx to 0x%lx",
1393                    msk,val,hdw->subsys_stream_mask,val2);
1394         hdw->subsys_stream_mask = val2;
1395 }
1396
1397
1398 void pvr2_hdw_subsys_stream_bit_chg(struct pvr2_hdw *hdw,
1399                                     unsigned long msk,
1400                                     unsigned long val)
1401 {
1402         LOCK_TAKE(hdw->big_lock); do {
1403                 pvr2_hdw_subsys_stream_bit_chg_no_lock(hdw,msk,val);
1404         } while (0); LOCK_GIVE(hdw->big_lock);
1405 }
1406
1407
1408 static int pvr2_hdw_set_streaming_no_lock(struct pvr2_hdw *hdw,int enableFl)
1409 {
1410         if ((!enableFl) == !(hdw->flag_streaming_enabled)) return 0;
1411         if (enableFl) {
1412                 pvr2_trace(PVR2_TRACE_START_STOP,
1413                            "/*--TRACE_STREAM--*/ enable");
1414                 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,~0);
1415         } else {
1416                 pvr2_trace(PVR2_TRACE_START_STOP,
1417                            "/*--TRACE_STREAM--*/ disable");
1418                 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1419         }
1420         if (!hdw->flag_ok) return -EIO;
1421         hdw->flag_streaming_enabled = enableFl != 0;
1422         return 0;
1423 }
1424
1425
1426 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1427 {
1428         return hdw->flag_streaming_enabled != 0;
1429 }
1430
1431
1432 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1433 {
1434         int ret;
1435         LOCK_TAKE(hdw->big_lock); do {
1436                 ret = pvr2_hdw_set_streaming_no_lock(hdw,enable_flag);
1437         } while (0); LOCK_GIVE(hdw->big_lock);
1438         return ret;
1439 }
1440
1441
1442 static int pvr2_hdw_set_stream_type_no_lock(struct pvr2_hdw *hdw,
1443                                             enum pvr2_config config)
1444 {
1445         unsigned long sm = hdw->subsys_enabled_mask;
1446         if (!hdw->flag_ok) return -EIO;
1447         pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1448         hdw->config = config;
1449         pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,sm);
1450         return 0;
1451 }
1452
1453
1454 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1455 {
1456         int ret;
1457         if (!hdw->flag_ok) return -EIO;
1458         LOCK_TAKE(hdw->big_lock);
1459         ret = pvr2_hdw_set_stream_type_no_lock(hdw,config);
1460         LOCK_GIVE(hdw->big_lock);
1461         return ret;
1462 }
1463
1464
1465 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1466 {
1467         int unit_number = hdw->unit_number;
1468         int tp = -1;
1469         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1470                 tp = tuner[unit_number];
1471         }
1472         if (tp < 0) return -EINVAL;
1473         hdw->tuner_type = tp;
1474         return 0;
1475 }
1476
1477
1478 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1479 {
1480         int unit_number = hdw->unit_number;
1481         int tp = 0;
1482         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1483                 tp = video_std[unit_number];
1484         }
1485         return tp;
1486 }
1487
1488
1489 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1490 {
1491         int unit_number = hdw->unit_number;
1492         int tp = 0;
1493         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1494                 tp = tolerance[unit_number];
1495         }
1496         return tp;
1497 }
1498
1499
1500 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1501 {
1502         /* Try a harmless request to fetch the eeprom's address over
1503            endpoint 1.  See what happens.  Only the full FX2 image can
1504            respond to this.  If this probe fails then likely the FX2
1505            firmware needs be loaded. */
1506         int result;
1507         LOCK_TAKE(hdw->ctl_lock); do {
1508                 hdw->cmd_buffer[0] = 0xeb;
1509                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1510                                            hdw->cmd_buffer,1,
1511                                            hdw->cmd_buffer,1);
1512                 if (result < 0) break;
1513         } while(0); LOCK_GIVE(hdw->ctl_lock);
1514         if (result) {
1515                 pvr2_trace(PVR2_TRACE_INIT,
1516                            "Probe of device endpoint 1 result status %d",
1517                            result);
1518         } else {
1519                 pvr2_trace(PVR2_TRACE_INIT,
1520                            "Probe of device endpoint 1 succeeded");
1521         }
1522         return result == 0;
1523 }
1524
1525 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1526 {
1527         char buf[40];
1528         unsigned int bcnt;
1529         v4l2_std_id std1,std2;
1530
1531         std1 = get_default_standard(hdw);
1532
1533         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1534         pvr2_trace(PVR2_TRACE_INIT,
1535                    "Supported video standard(s) reported by eeprom: %.*s",
1536                    bcnt,buf);
1537
1538         hdw->std_mask_avail = hdw->std_mask_eeprom;
1539
1540         std2 = std1 & ~hdw->std_mask_avail;
1541         if (std2) {
1542                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1543                 pvr2_trace(PVR2_TRACE_INIT,
1544                            "Expanding supported video standards"
1545                            " to include: %.*s",
1546                            bcnt,buf);
1547                 hdw->std_mask_avail |= std2;
1548         }
1549
1550         pvr2_hdw_internal_set_std_avail(hdw);
1551
1552         if (std1) {
1553                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1554                 pvr2_trace(PVR2_TRACE_INIT,
1555                            "Initial video standard forced to %.*s",
1556                            bcnt,buf);
1557                 hdw->std_mask_cur = std1;
1558                 hdw->std_dirty = !0;
1559                 pvr2_hdw_internal_find_stdenum(hdw);
1560                 return;
1561         }
1562
1563         if (hdw->std_enum_cnt > 1) {
1564                 // Autoselect the first listed standard
1565                 hdw->std_enum_cur = 1;
1566                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1567                 hdw->std_dirty = !0;
1568                 pvr2_trace(PVR2_TRACE_INIT,
1569                            "Initial video standard auto-selected to %s",
1570                            hdw->std_defs[hdw->std_enum_cur-1].name);
1571                 return;
1572         }
1573
1574         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1575                    "Unable to select a viable initial video standard");
1576 }
1577
1578
1579 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1580 {
1581         int ret;
1582         unsigned int idx;
1583         struct pvr2_ctrl *cptr;
1584         int reloadFl = 0;
1585         if (!reloadFl) {
1586                 reloadFl = (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1587                             == 0);
1588                 if (reloadFl) {
1589                         pvr2_trace(PVR2_TRACE_INIT,
1590                                    "USB endpoint config looks strange"
1591                                    "; possibly firmware needs to be loaded");
1592                 }
1593         }
1594         if (!reloadFl) {
1595                 reloadFl = !pvr2_hdw_check_firmware(hdw);
1596                 if (reloadFl) {
1597                         pvr2_trace(PVR2_TRACE_INIT,
1598                                    "Check for FX2 firmware failed"
1599                                    "; possibly firmware needs to be loaded");
1600                 }
1601         }
1602         if (reloadFl) {
1603                 if (pvr2_upload_firmware1(hdw) != 0) {
1604                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1605                                    "Failure uploading firmware1");
1606                 }
1607                 return;
1608         }
1609         hdw->fw1_state = FW1_STATE_OK;
1610
1611         if (initusbreset) {
1612                 pvr2_hdw_device_reset(hdw);
1613         }
1614         if (!pvr2_hdw_dev_ok(hdw)) return;
1615
1616         for (idx = 0; idx < pvr2_client_lists[hdw->hdw_type].cnt; idx++) {
1617                 request_module(pvr2_client_lists[hdw->hdw_type].lst[idx]);
1618         }
1619
1620         pvr2_hdw_cmd_powerup(hdw);
1621         if (!pvr2_hdw_dev_ok(hdw)) return;
1622
1623         if (pvr2_upload_firmware2(hdw)){
1624                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"device unstable!!");
1625                 pvr2_hdw_render_useless(hdw);
1626                 return;
1627         }
1628
1629         // This step MUST happen after the earlier powerup step.
1630         pvr2_i2c_core_init(hdw);
1631         if (!pvr2_hdw_dev_ok(hdw)) return;
1632
1633         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1634                 cptr = hdw->controls + idx;
1635                 if (cptr->info->skip_init) continue;
1636                 if (!cptr->info->set_value) continue;
1637                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1638         }
1639
1640         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
1641         // thread-safe against the normal pvr2_send_request() mechanism.
1642         // (We should make it thread safe).
1643
1644         ret = pvr2_hdw_get_eeprom_addr(hdw);
1645         if (!pvr2_hdw_dev_ok(hdw)) return;
1646         if (ret < 0) {
1647                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1648                            "Unable to determine location of eeprom, skipping");
1649         } else {
1650                 hdw->eeprom_addr = ret;
1651                 pvr2_eeprom_analyze(hdw);
1652                 if (!pvr2_hdw_dev_ok(hdw)) return;
1653         }
1654
1655         pvr2_hdw_setup_std(hdw);
1656
1657         if (!get_default_tuner_type(hdw)) {
1658                 pvr2_trace(PVR2_TRACE_INIT,
1659                            "pvr2_hdw_setup: Tuner type overridden to %d",
1660                            hdw->tuner_type);
1661         }
1662
1663         hdw->tuner_updated = !0;
1664         pvr2_i2c_core_check_stale(hdw);
1665         hdw->tuner_updated = 0;
1666
1667         if (!pvr2_hdw_dev_ok(hdw)) return;
1668
1669         pvr2_hdw_commit_ctl_internal(hdw);
1670         if (!pvr2_hdw_dev_ok(hdw)) return;
1671
1672         hdw->vid_stream = pvr2_stream_create();
1673         if (!pvr2_hdw_dev_ok(hdw)) return;
1674         pvr2_trace(PVR2_TRACE_INIT,
1675                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1676         if (hdw->vid_stream) {
1677                 idx = get_default_error_tolerance(hdw);
1678                 if (idx) {
1679                         pvr2_trace(PVR2_TRACE_INIT,
1680                                    "pvr2_hdw_setup: video stream %p"
1681                                    " setting tolerance %u",
1682                                    hdw->vid_stream,idx);
1683                 }
1684                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1685                                   PVR2_VID_ENDPOINT,idx);
1686         }
1687
1688         if (!pvr2_hdw_dev_ok(hdw)) return;
1689
1690         /* Make sure everything is up to date */
1691         pvr2_i2c_core_sync(hdw);
1692
1693         if (!pvr2_hdw_dev_ok(hdw)) return;
1694
1695         hdw->flag_init_ok = !0;
1696 }
1697
1698
1699 int pvr2_hdw_setup(struct pvr2_hdw *hdw)
1700 {
1701         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1702         LOCK_TAKE(hdw->big_lock); do {
1703                 pvr2_hdw_setup_low(hdw);
1704                 pvr2_trace(PVR2_TRACE_INIT,
1705                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1706                            hdw,hdw->flag_ok,hdw->flag_init_ok);
1707                 if (pvr2_hdw_dev_ok(hdw)) {
1708                         if (pvr2_hdw_init_ok(hdw)) {
1709                                 pvr2_trace(
1710                                         PVR2_TRACE_INFO,
1711                                         "Device initialization"
1712                                         " completed successfully.");
1713                                 break;
1714                         }
1715                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
1716                                 pvr2_trace(
1717                                         PVR2_TRACE_INFO,
1718                                         "Device microcontroller firmware"
1719                                         " (re)loaded; it should now reset"
1720                                         " and reconnect.");
1721                                 break;
1722                         }
1723                         pvr2_trace(
1724                                 PVR2_TRACE_ERROR_LEGS,
1725                                 "Device initialization was not successful.");
1726                         if (hdw->fw1_state == FW1_STATE_MISSING) {
1727                                 pvr2_trace(
1728                                         PVR2_TRACE_ERROR_LEGS,
1729                                         "Giving up since device"
1730                                         " microcontroller firmware"
1731                                         " appears to be missing.");
1732                                 break;
1733                         }
1734                 }
1735                 if (procreload) {
1736                         pvr2_trace(
1737                                 PVR2_TRACE_ERROR_LEGS,
1738                                 "Attempting pvrusb2 recovery by reloading"
1739                                 " primary firmware.");
1740                         pvr2_trace(
1741                                 PVR2_TRACE_ERROR_LEGS,
1742                                 "If this works, device should disconnect"
1743                                 " and reconnect in a sane state.");
1744                         hdw->fw1_state = FW1_STATE_UNKNOWN;
1745                         pvr2_upload_firmware1(hdw);
1746                 } else {
1747                         pvr2_trace(
1748                                 PVR2_TRACE_ERROR_LEGS,
1749                                 "***WARNING*** pvrusb2 device hardware"
1750                                 " appears to be jammed"
1751                                 " and I can't clear it.");
1752                         pvr2_trace(
1753                                 PVR2_TRACE_ERROR_LEGS,
1754                                 "You might need to power cycle"
1755                                 " the pvrusb2 device"
1756                                 " in order to recover.");
1757                 }
1758         } while (0); LOCK_GIVE(hdw->big_lock);
1759         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1760         return hdw->flag_init_ok;
1761 }
1762
1763
1764 /* Create and return a structure for interacting with the underlying
1765    hardware */
1766 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1767                                  const struct usb_device_id *devid)
1768 {
1769         unsigned int idx,cnt1,cnt2;
1770         struct pvr2_hdw *hdw;
1771         unsigned int hdw_type;
1772         int valid_std_mask;
1773         struct pvr2_ctrl *cptr;
1774         __u8 ifnum;
1775         struct v4l2_queryctrl qctrl;
1776         struct pvr2_ctl_info *ciptr;
1777
1778         hdw_type = devid - pvr2_device_table;
1779         if (hdw_type >=
1780             sizeof(pvr2_device_names)/sizeof(pvr2_device_names[0])) {
1781                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1782                            "Bogus device type of %u reported",hdw_type);
1783                 return NULL;
1784         }
1785
1786         hdw = kmalloc(sizeof(*hdw),GFP_KERNEL);
1787         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1788                    hdw,pvr2_device_names[hdw_type]);
1789         if (!hdw) goto fail;
1790         memset(hdw,0,sizeof(*hdw));
1791         cx2341x_fill_defaults(&hdw->enc_ctl_state);
1792
1793         hdw->control_cnt = CTRLDEF_COUNT;
1794         hdw->control_cnt += MPEGDEF_COUNT;
1795         hdw->controls = kmalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
1796                                 GFP_KERNEL);
1797         if (!hdw->controls) goto fail;
1798         memset(hdw->controls,0,sizeof(struct pvr2_ctrl) * hdw->control_cnt);
1799         hdw->hdw_type = hdw_type;
1800         for (idx = 0; idx < hdw->control_cnt; idx++) {
1801                 cptr = hdw->controls + idx;
1802                 cptr->hdw = hdw;
1803         }
1804         for (idx = 0; idx < 32; idx++) {
1805                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1806         }
1807         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1808                 cptr = hdw->controls + idx;
1809                 cptr->info = control_defs+idx;
1810         }
1811         /* Define and configure additional controls from cx2341x module. */
1812         hdw->mpeg_ctrl_info = kmalloc(
1813                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1814         if (!hdw->mpeg_ctrl_info) goto fail;
1815         memset(hdw->mpeg_ctrl_info,0,
1816                sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT);
1817         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1818                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1819                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1820                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1821                 ciptr->name = mpeg_ids[idx].strid;
1822                 ciptr->v4l_id = mpeg_ids[idx].id;
1823                 ciptr->skip_init = !0;
1824                 ciptr->get_value = ctrl_cx2341x_get;
1825                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1826                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1827                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1828                 qctrl.id = ciptr->v4l_id;
1829                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1830                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1831                         ciptr->set_value = ctrl_cx2341x_set;
1832                 }
1833                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
1834                         PVR2_CTLD_INFO_DESC_SIZE);
1835                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
1836                 ciptr->default_value = qctrl.default_value;
1837                 switch (qctrl.type) {
1838                 default:
1839                 case V4L2_CTRL_TYPE_INTEGER:
1840                         ciptr->type = pvr2_ctl_int;
1841                         ciptr->def.type_int.min_value = qctrl.minimum;
1842                         ciptr->def.type_int.max_value = qctrl.maximum;
1843                         break;
1844                 case V4L2_CTRL_TYPE_BOOLEAN:
1845                         ciptr->type = pvr2_ctl_bool;
1846                         break;
1847                 case V4L2_CTRL_TYPE_MENU:
1848                         ciptr->type = pvr2_ctl_enum;
1849                         ciptr->def.type_enum.value_names =
1850                                 cx2341x_ctrl_get_menu(ciptr->v4l_id);
1851                         for (cnt1 = 0;
1852                              ciptr->def.type_enum.value_names[cnt1] != NULL;
1853                              cnt1++) { }
1854                         ciptr->def.type_enum.count = cnt1;
1855                         break;
1856                 }
1857                 cptr->info = ciptr;
1858         }
1859
1860         // Initialize video standard enum dynamic control
1861         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1862         if (cptr) {
1863                 memcpy(&hdw->std_info_enum,cptr->info,
1864                        sizeof(hdw->std_info_enum));
1865                 cptr->info = &hdw->std_info_enum;
1866
1867         }
1868         // Initialize control data regarding video standard masks
1869         valid_std_mask = pvr2_std_get_usable();
1870         for (idx = 0; idx < 32; idx++) {
1871                 if (!(valid_std_mask & (1 << idx))) continue;
1872                 cnt1 = pvr2_std_id_to_str(
1873                         hdw->std_mask_names[idx],
1874                         sizeof(hdw->std_mask_names[idx])-1,
1875                         1 << idx);
1876                 hdw->std_mask_names[idx][cnt1] = 0;
1877         }
1878         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1879         if (cptr) {
1880                 memcpy(&hdw->std_info_avail,cptr->info,
1881                        sizeof(hdw->std_info_avail));
1882                 cptr->info = &hdw->std_info_avail;
1883                 hdw->std_info_avail.def.type_bitmask.bit_names =
1884                         hdw->std_mask_ptrs;
1885                 hdw->std_info_avail.def.type_bitmask.valid_bits =
1886                         valid_std_mask;
1887         }
1888         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1889         if (cptr) {
1890                 memcpy(&hdw->std_info_cur,cptr->info,
1891                        sizeof(hdw->std_info_cur));
1892                 cptr->info = &hdw->std_info_cur;
1893                 hdw->std_info_cur.def.type_bitmask.bit_names =
1894                         hdw->std_mask_ptrs;
1895                 hdw->std_info_avail.def.type_bitmask.valid_bits =
1896                         valid_std_mask;
1897         }
1898
1899         hdw->eeprom_addr = -1;
1900         hdw->unit_number = -1;
1901         hdw->v4l_minor_number = -1;
1902         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1903         if (!hdw->ctl_write_buffer) goto fail;
1904         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1905         if (!hdw->ctl_read_buffer) goto fail;
1906         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
1907         if (!hdw->ctl_write_urb) goto fail;
1908         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
1909         if (!hdw->ctl_read_urb) goto fail;
1910
1911         down(&pvr2_unit_sem); do {
1912                 for (idx = 0; idx < PVR_NUM; idx++) {
1913                         if (unit_pointers[idx]) continue;
1914                         hdw->unit_number = idx;
1915                         unit_pointers[idx] = hdw;
1916                         break;
1917                 }
1918         } while (0); up(&pvr2_unit_sem);
1919
1920         cnt1 = 0;
1921         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
1922         cnt1 += cnt2;
1923         if (hdw->unit_number >= 0) {
1924                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
1925                                  ('a' + hdw->unit_number));
1926                 cnt1 += cnt2;
1927         }
1928         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
1929         hdw->name[cnt1] = 0;
1930
1931         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
1932                    hdw->unit_number,hdw->name);
1933
1934         hdw->tuner_type = -1;
1935         hdw->flag_ok = !0;
1936         /* Initialize the mask of subsystems that we will shut down when we
1937            stop streaming. */
1938         hdw->subsys_stream_mask = PVR2_SUBSYS_RUN_ALL;
1939         hdw->subsys_stream_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
1940
1941         pvr2_trace(PVR2_TRACE_INIT,"subsys_stream_mask: 0x%lx",
1942                    hdw->subsys_stream_mask);
1943
1944         hdw->usb_intf = intf;
1945         hdw->usb_dev = interface_to_usbdev(intf);
1946
1947         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
1948         usb_set_interface(hdw->usb_dev,ifnum,0);
1949
1950         mutex_init(&hdw->ctl_lock_mutex);
1951         mutex_init(&hdw->big_lock_mutex);
1952
1953         return hdw;
1954  fail:
1955         if (hdw) {
1956                 usb_free_urb(hdw->ctl_read_urb);
1957                 usb_free_urb(hdw->ctl_write_urb);
1958                 if (hdw->ctl_read_buffer) kfree(hdw->ctl_read_buffer);
1959                 if (hdw->ctl_write_buffer) kfree(hdw->ctl_write_buffer);
1960                 if (hdw->controls) kfree(hdw->controls);
1961                 if (hdw->mpeg_ctrl_info) kfree(hdw->mpeg_ctrl_info);
1962                 kfree(hdw);
1963         }
1964         return NULL;
1965 }
1966
1967
1968 /* Remove _all_ associations between this driver and the underlying USB
1969    layer. */
1970 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
1971 {
1972         if (hdw->flag_disconnected) return;
1973         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
1974         if (hdw->ctl_read_urb) {
1975                 usb_kill_urb(hdw->ctl_read_urb);
1976                 usb_free_urb(hdw->ctl_read_urb);
1977                 hdw->ctl_read_urb = NULL;
1978         }
1979         if (hdw->ctl_write_urb) {
1980                 usb_kill_urb(hdw->ctl_write_urb);
1981                 usb_free_urb(hdw->ctl_write_urb);
1982                 hdw->ctl_write_urb = NULL;
1983         }
1984         if (hdw->ctl_read_buffer) {
1985                 kfree(hdw->ctl_read_buffer);
1986                 hdw->ctl_read_buffer = NULL;
1987         }
1988         if (hdw->ctl_write_buffer) {
1989                 kfree(hdw->ctl_write_buffer);
1990                 hdw->ctl_write_buffer = NULL;
1991         }
1992         pvr2_hdw_render_useless_unlocked(hdw);
1993         hdw->flag_disconnected = !0;
1994         hdw->usb_dev = NULL;
1995         hdw->usb_intf = NULL;
1996 }
1997
1998
1999 /* Destroy hardware interaction structure */
2000 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2001 {
2002         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2003         if (hdw->fw_buffer) {
2004                 kfree(hdw->fw_buffer);
2005                 hdw->fw_buffer = NULL;
2006         }
2007         if (hdw->vid_stream) {
2008                 pvr2_stream_destroy(hdw->vid_stream);
2009                 hdw->vid_stream = NULL;
2010         }
2011         if (hdw->audio_stat) {
2012                 hdw->audio_stat->detach(hdw->audio_stat->ctxt);
2013         }
2014         if (hdw->decoder_ctrl) {
2015                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2016         }
2017         pvr2_i2c_core_done(hdw);
2018         pvr2_hdw_remove_usb_stuff(hdw);
2019         down(&pvr2_unit_sem); do {
2020                 if ((hdw->unit_number >= 0) &&
2021                     (hdw->unit_number < PVR_NUM) &&
2022                     (unit_pointers[hdw->unit_number] == hdw)) {
2023                         unit_pointers[hdw->unit_number] = NULL;
2024                 }
2025         } while (0); up(&pvr2_unit_sem);
2026         if (hdw->controls) kfree(hdw->controls);
2027         if (hdw->mpeg_ctrl_info) kfree(hdw->mpeg_ctrl_info);
2028         if (hdw->std_defs) kfree(hdw->std_defs);
2029         if (hdw->std_enum_names) kfree(hdw->std_enum_names);
2030         kfree(hdw);
2031 }
2032
2033
2034 int pvr2_hdw_init_ok(struct pvr2_hdw *hdw)
2035 {
2036         return hdw->flag_init_ok;
2037 }
2038
2039
2040 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2041 {
2042         return (hdw && hdw->flag_ok);
2043 }
2044
2045
2046 /* Called when hardware has been unplugged */
2047 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2048 {
2049         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2050         LOCK_TAKE(hdw->big_lock);
2051         LOCK_TAKE(hdw->ctl_lock);
2052         pvr2_hdw_remove_usb_stuff(hdw);
2053         LOCK_GIVE(hdw->ctl_lock);
2054         LOCK_GIVE(hdw->big_lock);
2055 }
2056
2057
2058 // Attempt to autoselect an appropriate value for std_enum_cur given
2059 // whatever is currently in std_mask_cur
2060 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2061 {
2062         unsigned int idx;
2063         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2064                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2065                         hdw->std_enum_cur = idx;
2066                         return;
2067                 }
2068         }
2069         hdw->std_enum_cur = 0;
2070 }
2071
2072
2073 // Calculate correct set of enumerated standards based on currently known
2074 // set of available standards bits.
2075 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2076 {
2077         struct v4l2_standard *newstd;
2078         unsigned int std_cnt;
2079         unsigned int idx;
2080
2081         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2082
2083         if (hdw->std_defs) {
2084                 kfree(hdw->std_defs);
2085                 hdw->std_defs = NULL;
2086         }
2087         hdw->std_enum_cnt = 0;
2088         if (hdw->std_enum_names) {
2089                 kfree(hdw->std_enum_names);
2090                 hdw->std_enum_names = NULL;
2091         }
2092
2093         if (!std_cnt) {
2094                 pvr2_trace(
2095                         PVR2_TRACE_ERROR_LEGS,
2096                         "WARNING: Failed to identify any viable standards");
2097         }
2098         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2099         hdw->std_enum_names[0] = "none";
2100         for (idx = 0; idx < std_cnt; idx++) {
2101                 hdw->std_enum_names[idx+1] =
2102                         newstd[idx].name;
2103         }
2104         // Set up the dynamic control for this standard
2105         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2106         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2107         hdw->std_defs = newstd;
2108         hdw->std_enum_cnt = std_cnt+1;
2109         hdw->std_enum_cur = 0;
2110         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2111 }
2112
2113
2114 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2115                                struct v4l2_standard *std,
2116                                unsigned int idx)
2117 {
2118         int ret = -EINVAL;
2119         if (!idx) return ret;
2120         LOCK_TAKE(hdw->big_lock); do {
2121                 if (idx >= hdw->std_enum_cnt) break;
2122                 idx--;
2123                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2124                 ret = 0;
2125         } while (0); LOCK_GIVE(hdw->big_lock);
2126         return ret;
2127 }
2128
2129
2130 /* Get the number of defined controls */
2131 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2132 {
2133         return hdw->control_cnt;
2134 }
2135
2136
2137 /* Retrieve a control handle given its index (0..count-1) */
2138 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2139                                              unsigned int idx)
2140 {
2141         if (idx >= hdw->control_cnt) return NULL;
2142         return hdw->controls + idx;
2143 }
2144
2145
2146 /* Retrieve a control handle given its index (0..count-1) */
2147 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2148                                           unsigned int ctl_id)
2149 {
2150         struct pvr2_ctrl *cptr;
2151         unsigned int idx;
2152         int i;
2153
2154         /* This could be made a lot more efficient, but for now... */
2155         for (idx = 0; idx < hdw->control_cnt; idx++) {
2156                 cptr = hdw->controls + idx;
2157                 i = cptr->info->internal_id;
2158                 if (i && (i == ctl_id)) return cptr;
2159         }
2160         return NULL;
2161 }
2162
2163
2164 /* Given a V4L ID, retrieve the control structure associated with it. */
2165 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2166 {
2167         struct pvr2_ctrl *cptr;
2168         unsigned int idx;
2169         int i;
2170
2171         /* This could be made a lot more efficient, but for now... */
2172         for (idx = 0; idx < hdw->control_cnt; idx++) {
2173                 cptr = hdw->controls + idx;
2174                 i = cptr->info->v4l_id;
2175                 if (i && (i == ctl_id)) return cptr;
2176         }
2177         return NULL;
2178 }
2179
2180
2181 /* Given a V4L ID for its immediate predecessor, retrieve the control
2182    structure associated with it. */
2183 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2184                                             unsigned int ctl_id)
2185 {
2186         struct pvr2_ctrl *cptr,*cp2;
2187         unsigned int idx;
2188         int i;
2189
2190         /* This could be made a lot more efficient, but for now... */
2191         cp2 = NULL;
2192         for (idx = 0; idx < hdw->control_cnt; idx++) {
2193                 cptr = hdw->controls + idx;
2194                 i = cptr->info->v4l_id;
2195                 if (!i) continue;
2196                 if (i <= ctl_id) continue;
2197                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2198                 cp2 = cptr;
2199         }
2200         return cp2;
2201         return NULL;
2202 }
2203
2204
2205 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2206 {
2207         switch (tp) {
2208         case pvr2_ctl_int: return "integer";
2209         case pvr2_ctl_enum: return "enum";
2210         case pvr2_ctl_bool: return "boolean";
2211         case pvr2_ctl_bitmask: return "bitmask";
2212         }
2213         return "";
2214 }
2215
2216
2217 /* Commit all control changes made up to this point.  Subsystems can be
2218    indirectly affected by these changes.  For a given set of things being
2219    committed, we'll clear the affected subsystem bits and then once we're
2220    done committing everything we'll make a request to restore the subsystem
2221    state(s) back to their previous value before this function was called.
2222    Thus we can automatically reconfigure affected pieces of the driver as
2223    controls are changed. */
2224 static int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw)
2225 {
2226         unsigned long saved_subsys_mask = hdw->subsys_enabled_mask;
2227         unsigned long stale_subsys_mask = 0;
2228         unsigned int idx;
2229         struct pvr2_ctrl *cptr;
2230         int value;
2231         int commit_flag = 0;
2232         char buf[100];
2233         unsigned int bcnt,ccnt;
2234
2235         for (idx = 0; idx < hdw->control_cnt; idx++) {
2236                 cptr = hdw->controls + idx;
2237                 if (cptr->info->is_dirty == 0) continue;
2238                 if (!cptr->info->is_dirty(cptr)) continue;
2239                 if (!commit_flag) {
2240                         commit_flag = !0;
2241                 }
2242
2243                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2244                                  cptr->info->name);
2245                 value = 0;
2246                 cptr->info->get_value(cptr,&value);
2247                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2248                                                 buf+bcnt,
2249                                                 sizeof(buf)-bcnt,&ccnt);
2250                 bcnt += ccnt;
2251                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2252                                   get_ctrl_typename(cptr->info->type));
2253                 pvr2_trace(PVR2_TRACE_CTL,
2254                            "/*--TRACE_COMMIT--*/ %.*s",
2255                            bcnt,buf);
2256         }
2257
2258         if (!commit_flag) {
2259                 /* Nothing has changed */
2260                 return 0;
2261         }
2262
2263         /* When video standard changes, reset the hres and vres values -
2264            but if the user has pending changes there, then let the changes
2265            take priority. */
2266         if (hdw->std_dirty) {
2267                 /* Rewrite the vertical resolution to be appropriate to the
2268                    video standard that has been selected. */
2269                 int nvres;
2270                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2271                         nvres = 480;
2272                 } else {
2273                         nvres = 576;
2274                 }
2275                 if (nvres != hdw->res_ver_val) {
2276                         hdw->res_ver_val = nvres;
2277                         hdw->res_ver_dirty = !0;
2278                 }
2279         }
2280
2281         if (hdw->std_dirty ||
2282             hdw->enc_stale ||
2283             hdw->srate_dirty ||
2284             hdw->res_ver_dirty ||
2285             hdw->res_hor_dirty ||
2286             0) {
2287                 /* If any of this changes, then the encoder needs to be
2288                    reconfigured, and we need to reset the stream. */
2289                 stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
2290         }
2291
2292         if (hdw->srate_dirty) {
2293                 /* Write new sample rate into control structure since
2294                  * the master copy is stale.  We must track srate
2295                  * separate from the mpeg control structure because
2296                  * other logic also uses this value. */
2297                 struct v4l2_ext_controls cs;
2298                 struct v4l2_ext_control c1;
2299                 memset(&cs,0,sizeof(cs));
2300                 memset(&c1,0,sizeof(c1));
2301                 cs.controls = &c1;
2302                 cs.count = 1;
2303                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2304                 c1.value = hdw->srate_val;
2305                 cx2341x_ext_ctrls(&hdw->enc_ctl_state,&cs,VIDIOC_S_EXT_CTRLS);
2306         }
2307
2308         /* Scan i2c core at this point - before we clear all the dirty
2309            bits.  Various parts of the i2c core will notice dirty bits as
2310            appropriate and arrange to broadcast or directly send updates to
2311            the client drivers in order to keep everything in sync */
2312         pvr2_i2c_core_check_stale(hdw);
2313
2314         for (idx = 0; idx < hdw->control_cnt; idx++) {
2315                 cptr = hdw->controls + idx;
2316                 if (!cptr->info->clear_dirty) continue;
2317                 cptr->info->clear_dirty(cptr);
2318         }
2319
2320         /* Now execute i2c core update */
2321         pvr2_i2c_core_sync(hdw);
2322
2323         pvr2_hdw_subsys_bit_chg_no_lock(hdw,stale_subsys_mask,0);
2324         pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,saved_subsys_mask);
2325
2326         return 0;
2327 }
2328
2329
2330 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2331 {
2332         LOCK_TAKE(hdw->big_lock); do {
2333                 pvr2_hdw_commit_ctl_internal(hdw);
2334         } while (0); LOCK_GIVE(hdw->big_lock);
2335         return 0;
2336 }
2337
2338
2339 void pvr2_hdw_poll(struct pvr2_hdw *hdw)
2340 {
2341         LOCK_TAKE(hdw->big_lock); do {
2342                 pvr2_i2c_core_sync(hdw);
2343         } while (0); LOCK_GIVE(hdw->big_lock);
2344 }
2345
2346
2347 void pvr2_hdw_setup_poll_trigger(struct pvr2_hdw *hdw,
2348                                  void (*func)(void *),
2349                                  void *data)
2350 {
2351         LOCK_TAKE(hdw->big_lock); do {
2352                 hdw->poll_trigger_func = func;
2353                 hdw->poll_trigger_data = data;
2354         } while (0); LOCK_GIVE(hdw->big_lock);
2355 }
2356
2357
2358 void pvr2_hdw_poll_trigger_unlocked(struct pvr2_hdw *hdw)
2359 {
2360         if (hdw->poll_trigger_func) {
2361                 hdw->poll_trigger_func(hdw->poll_trigger_data);
2362         }
2363 }
2364
2365 /* Return name for this driver instance */
2366 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2367 {
2368         return hdw->name;
2369 }
2370
2371
2372 /* Return bit mask indicating signal status */
2373 static unsigned int pvr2_hdw_get_signal_status_internal(struct pvr2_hdw *hdw)
2374 {
2375         unsigned int msk = 0;
2376         switch (hdw->input_val) {
2377         case PVR2_CVAL_INPUT_TV:
2378         case PVR2_CVAL_INPUT_RADIO:
2379                 if (hdw->decoder_ctrl &&
2380                     hdw->decoder_ctrl->tuned(hdw->decoder_ctrl->ctxt)) {
2381                         msk |= PVR2_SIGNAL_OK;
2382                         if (hdw->audio_stat &&
2383                             hdw->audio_stat->status(hdw->audio_stat->ctxt)) {
2384                                 if (hdw->flag_stereo) {
2385                                         msk |= PVR2_SIGNAL_STEREO;
2386                                 }
2387                                 if (hdw->flag_bilingual) {
2388                                         msk |= PVR2_SIGNAL_SAP;
2389                                 }
2390                         }
2391                 }
2392                 break;
2393         default:
2394                 msk |= PVR2_SIGNAL_OK | PVR2_SIGNAL_STEREO;
2395         }
2396         return msk;
2397 }
2398
2399
2400 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2401 {
2402         int result;
2403         LOCK_TAKE(hdw->ctl_lock); do {
2404                 hdw->cmd_buffer[0] = 0x0b;
2405                 result = pvr2_send_request(hdw,
2406                                            hdw->cmd_buffer,1,
2407                                            hdw->cmd_buffer,1);
2408                 if (result < 0) break;
2409                 result = (hdw->cmd_buffer[0] != 0);
2410         } while(0); LOCK_GIVE(hdw->ctl_lock);
2411         return result;
2412 }
2413
2414
2415 /* Return bit mask indicating signal status */
2416 unsigned int pvr2_hdw_get_signal_status(struct pvr2_hdw *hdw)
2417 {
2418         unsigned int msk = 0;
2419         LOCK_TAKE(hdw->big_lock); do {
2420                 msk = pvr2_hdw_get_signal_status_internal(hdw);
2421         } while (0); LOCK_GIVE(hdw->big_lock);
2422         return msk;
2423 }
2424
2425
2426 /* Get handle to video output stream */
2427 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2428 {
2429         return hp->vid_stream;
2430 }
2431
2432
2433 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2434 {
2435         int nr = pvr2_hdw_get_unit_number(hdw);
2436         LOCK_TAKE(hdw->big_lock); do {
2437                 hdw->log_requested = !0;
2438                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
2439                 pvr2_i2c_core_check_stale(hdw);
2440                 hdw->log_requested = 0;
2441                 pvr2_i2c_core_sync(hdw);
2442                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
2443                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
2444                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
2445         } while (0); LOCK_GIVE(hdw->big_lock);
2446 }
2447
2448 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw, int enable_flag)
2449 {
2450         int ret;
2451         u16 address;
2452         unsigned int pipe;
2453         LOCK_TAKE(hdw->big_lock); do {
2454                 if ((hdw->fw_buffer == 0) == !enable_flag) break;
2455
2456                 if (!enable_flag) {
2457                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2458                                    "Cleaning up after CPU firmware fetch");
2459                         kfree(hdw->fw_buffer);
2460                         hdw->fw_buffer = NULL;
2461                         hdw->fw_size = 0;
2462                         /* Now release the CPU.  It will disconnect and
2463                            reconnect later. */
2464                         pvr2_hdw_cpureset_assert(hdw,0);
2465                         break;
2466                 }
2467
2468                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2469                            "Preparing to suck out CPU firmware");
2470                 hdw->fw_size = 0x2000;
2471                 hdw->fw_buffer = kmalloc(hdw->fw_size,GFP_KERNEL);
2472                 if (!hdw->fw_buffer) {
2473                         hdw->fw_size = 0;
2474                         break;
2475                 }
2476
2477                 memset(hdw->fw_buffer,0,hdw->fw_size);
2478
2479                 /* We have to hold the CPU during firmware upload. */
2480                 pvr2_hdw_cpureset_assert(hdw,1);
2481
2482                 /* download the firmware from address 0000-1fff in 2048
2483                    (=0x800) bytes chunk. */
2484
2485                 pvr2_trace(PVR2_TRACE_FIRMWARE,"Grabbing CPU firmware");
2486                 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2487                 for(address = 0; address < hdw->fw_size; address += 0x800) {
2488                         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0xc0,
2489                                               address,0,
2490                                               hdw->fw_buffer+address,0x800,HZ);
2491                         if (ret < 0) break;
2492                 }
2493
2494                 pvr2_trace(PVR2_TRACE_FIRMWARE,"Done grabbing CPU firmware");
2495
2496         } while (0); LOCK_GIVE(hdw->big_lock);
2497 }
2498
2499
2500 /* Return true if we're in a mode for retrieval CPU firmware */
2501 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2502 {
2503         return hdw->fw_buffer != 0;
2504 }
2505
2506
2507 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2508                        char *buf,unsigned int cnt)
2509 {
2510         int ret = -EINVAL;
2511         LOCK_TAKE(hdw->big_lock); do {
2512                 if (!buf) break;
2513                 if (!cnt) break;
2514
2515                 if (!hdw->fw_buffer) {
2516                         ret = -EIO;
2517                         break;
2518                 }
2519
2520                 if (offs >= hdw->fw_size) {
2521                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2522                                    "Read firmware data offs=%d EOF",
2523                                    offs);
2524                         ret = 0;
2525                         break;
2526                 }
2527
2528                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2529
2530                 memcpy(buf,hdw->fw_buffer+offs,cnt);
2531
2532                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2533                            "Read firmware data offs=%d cnt=%d",
2534                            offs,cnt);
2535                 ret = cnt;
2536         } while (0); LOCK_GIVE(hdw->big_lock);
2537
2538         return ret;
2539 }
2540
2541
2542 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw)
2543 {
2544         return hdw->v4l_minor_number;
2545 }
2546
2547
2548 /* Store the v4l minor device number */
2549 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,int v)
2550 {
2551         hdw->v4l_minor_number = v;
2552 }
2553
2554
2555 static void pvr2_ctl_write_complete(struct urb *urb)
2556 {
2557         struct pvr2_hdw *hdw = urb->context;
2558         hdw->ctl_write_pend_flag = 0;
2559         if (hdw->ctl_read_pend_flag) return;
2560         complete(&hdw->ctl_done);
2561 }
2562
2563
2564 static void pvr2_ctl_read_complete(struct urb *urb)
2565 {
2566         struct pvr2_hdw *hdw = urb->context;
2567         hdw->ctl_read_pend_flag = 0;
2568         if (hdw->ctl_write_pend_flag) return;
2569         complete(&hdw->ctl_done);
2570 }
2571
2572
2573 static void pvr2_ctl_timeout(unsigned long data)
2574 {
2575         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2576         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2577                 hdw->ctl_timeout_flag = !0;
2578                 if (hdw->ctl_write_pend_flag)
2579                         usb_unlink_urb(hdw->ctl_write_urb);
2580                 if (hdw->ctl_read_pend_flag)
2581                         usb_unlink_urb(hdw->ctl_read_urb);
2582         }
2583 }
2584
2585
2586 /* Issue a command and get a response from the device.  This extended
2587    version includes a probe flag (which if set means that device errors
2588    should not be logged or treated as fatal) and a timeout in jiffies.
2589    This can be used to non-lethally probe the health of endpoint 1. */
2590 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2591                                 unsigned int timeout,int probe_fl,
2592                                 void *write_data,unsigned int write_len,
2593                                 void *read_data,unsigned int read_len)
2594 {
2595         unsigned int idx;
2596         int status = 0;
2597         struct timer_list timer;
2598         if (!hdw->ctl_lock_held) {
2599                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2600                            "Attempted to execute control transfer"
2601                            " without lock!!");
2602                 return -EDEADLK;
2603         }
2604         if ((!hdw->flag_ok) && !probe_fl) {
2605                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2606                            "Attempted to execute control transfer"
2607                            " when device not ok");
2608                 return -EIO;
2609         }
2610         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2611                 if (!probe_fl) {
2612                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2613                                    "Attempted to execute control transfer"
2614                                    " when USB is disconnected");
2615                 }
2616                 return -ENOTTY;
2617         }
2618
2619         /* Ensure that we have sane parameters */
2620         if (!write_data) write_len = 0;
2621         if (!read_data) read_len = 0;
2622         if (write_len > PVR2_CTL_BUFFSIZE) {
2623                 pvr2_trace(
2624                         PVR2_TRACE_ERROR_LEGS,
2625                         "Attempted to execute %d byte"
2626                         " control-write transfer (limit=%d)",
2627                         write_len,PVR2_CTL_BUFFSIZE);
2628                 return -EINVAL;
2629         }
2630         if (read_len > PVR2_CTL_BUFFSIZE) {
2631                 pvr2_trace(
2632                         PVR2_TRACE_ERROR_LEGS,
2633                         "Attempted to execute %d byte"
2634                         " control-read transfer (limit=%d)",
2635                         write_len,PVR2_CTL_BUFFSIZE);
2636                 return -EINVAL;
2637         }
2638         if ((!write_len) && (!read_len)) {
2639                 pvr2_trace(
2640                         PVR2_TRACE_ERROR_LEGS,
2641                         "Attempted to execute null control transfer?");
2642                 return -EINVAL;
2643         }
2644
2645
2646         hdw->cmd_debug_state = 1;
2647         if (write_len) {
2648                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2649         } else {
2650                 hdw->cmd_debug_code = 0;
2651         }
2652         hdw->cmd_debug_write_len = write_len;
2653         hdw->cmd_debug_read_len = read_len;
2654
2655         /* Initialize common stuff */
2656         init_completion(&hdw->ctl_done);
2657         hdw->ctl_timeout_flag = 0;
2658         hdw->ctl_write_pend_flag = 0;
2659         hdw->ctl_read_pend_flag = 0;
2660         init_timer(&timer);
2661         timer.expires = jiffies + timeout;
2662         timer.data = (unsigned long)hdw;
2663         timer.function = pvr2_ctl_timeout;
2664
2665         if (write_len) {
2666                 hdw->cmd_debug_state = 2;
2667                 /* Transfer write data to internal buffer */
2668                 for (idx = 0; idx < write_len; idx++) {
2669                         hdw->ctl_write_buffer[idx] =
2670                                 ((unsigned char *)write_data)[idx];
2671                 }
2672                 /* Initiate a write request */
2673                 usb_fill_bulk_urb(hdw->ctl_write_urb,
2674                                   hdw->usb_dev,
2675                                   usb_sndbulkpipe(hdw->usb_dev,
2676                                                   PVR2_CTL_WRITE_ENDPOINT),
2677                                   hdw->ctl_write_buffer,
2678                                   write_len,
2679                                   pvr2_ctl_write_complete,
2680                                   hdw);
2681                 hdw->ctl_write_urb->actual_length = 0;
2682                 hdw->ctl_write_pend_flag = !0;
2683                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2684                 if (status < 0) {
2685                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2686                                    "Failed to submit write-control"
2687                                    " URB status=%d",status);
2688                         hdw->ctl_write_pend_flag = 0;
2689                         goto done;
2690                 }
2691         }
2692
2693         if (read_len) {
2694                 hdw->cmd_debug_state = 3;
2695                 memset(hdw->ctl_read_buffer,0x43,read_len);
2696                 /* Initiate a read request */
2697                 usb_fill_bulk_urb(hdw->ctl_read_urb,
2698                                   hdw->usb_dev,
2699                                   usb_rcvbulkpipe(hdw->usb_dev,
2700                                                   PVR2_CTL_READ_ENDPOINT),
2701                                   hdw->ctl_read_buffer,
2702                                   read_len,
2703                                   pvr2_ctl_read_complete,
2704                                   hdw);
2705                 hdw->ctl_read_urb->actual_length = 0;
2706                 hdw->ctl_read_pend_flag = !0;
2707                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2708                 if (status < 0) {
2709                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2710                                    "Failed to submit read-control"
2711                                    " URB status=%d",status);
2712                         hdw->ctl_read_pend_flag = 0;
2713                         goto done;
2714                 }
2715         }
2716
2717         /* Start timer */
2718         add_timer(&timer);
2719
2720         /* Now wait for all I/O to complete */
2721         hdw->cmd_debug_state = 4;
2722         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2723                 wait_for_completion(&hdw->ctl_done);
2724         }
2725         hdw->cmd_debug_state = 5;
2726
2727         /* Stop timer */
2728         del_timer_sync(&timer);
2729
2730         hdw->cmd_debug_state = 6;
2731         status = 0;
2732
2733         if (hdw->ctl_timeout_flag) {
2734                 status = -ETIMEDOUT;
2735                 if (!probe_fl) {
2736                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2737                                    "Timed out control-write");
2738                 }
2739                 goto done;
2740         }
2741
2742         if (write_len) {
2743                 /* Validate results of write request */
2744                 if ((hdw->ctl_write_urb->status != 0) &&
2745                     (hdw->ctl_write_urb->status != -ENOENT) &&
2746                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
2747                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
2748                         /* USB subsystem is reporting some kind of failure
2749                            on the write */
2750                         status = hdw->ctl_write_urb->status;
2751                         if (!probe_fl) {
2752                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2753                                            "control-write URB failure,"
2754                                            " status=%d",
2755                                            status);
2756                         }
2757                         goto done;
2758                 }
2759                 if (hdw->ctl_write_urb->actual_length < write_len) {
2760                         /* Failed to write enough data */
2761                         status = -EIO;
2762                         if (!probe_fl) {
2763                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2764                                            "control-write URB short,"
2765                                            " expected=%d got=%d",
2766                                            write_len,
2767                                            hdw->ctl_write_urb->actual_length);
2768                         }
2769                         goto done;
2770                 }
2771         }
2772         if (read_len) {
2773                 /* Validate results of read request */
2774                 if ((hdw->ctl_read_urb->status != 0) &&
2775                     (hdw->ctl_read_urb->status != -ENOENT) &&
2776                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
2777                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
2778                         /* USB subsystem is reporting some kind of failure
2779                            on the read */
2780                         status = hdw->ctl_read_urb->status;
2781                         if (!probe_fl) {
2782                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2783                                            "control-read URB failure,"
2784                                            " status=%d",
2785                                            status);
2786                         }
2787                         goto done;
2788                 }
2789                 if (hdw->ctl_read_urb->actual_length < read_len) {
2790                         /* Failed to read enough data */
2791                         status = -EIO;
2792                         if (!probe_fl) {
2793                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2794                                            "control-read URB short,"
2795                                            " expected=%d got=%d",
2796                                            read_len,
2797                                            hdw->ctl_read_urb->actual_length);
2798                         }
2799                         goto done;
2800                 }
2801                 /* Transfer retrieved data out from internal buffer */
2802                 for (idx = 0; idx < read_len; idx++) {
2803                         ((unsigned char *)read_data)[idx] =
2804                                 hdw->ctl_read_buffer[idx];
2805                 }
2806         }
2807
2808  done:
2809
2810         hdw->cmd_debug_state = 0;
2811         if ((status < 0) && (!probe_fl)) {
2812                 pvr2_hdw_render_useless_unlocked(hdw);
2813         }
2814         return status;
2815 }
2816
2817
2818 int pvr2_send_request(struct pvr2_hdw *hdw,
2819                       void *write_data,unsigned int write_len,
2820                       void *read_data,unsigned int read_len)
2821 {
2822         return pvr2_send_request_ex(hdw,HZ*4,0,
2823                                     write_data,write_len,
2824                                     read_data,read_len);
2825 }
2826
2827 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
2828 {
2829         int ret;
2830
2831         LOCK_TAKE(hdw->ctl_lock);
2832
2833         hdw->cmd_buffer[0] = 0x04;  /* write register prefix */
2834         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
2835         hdw->cmd_buffer[5] = 0;
2836         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2837         hdw->cmd_buffer[7] = reg & 0xff;
2838
2839
2840         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
2841
2842         LOCK_GIVE(hdw->ctl_lock);
2843
2844         return ret;
2845 }
2846
2847
2848 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
2849 {
2850         int ret = 0;
2851
2852         LOCK_TAKE(hdw->ctl_lock);
2853
2854         hdw->cmd_buffer[0] = 0x05;  /* read register prefix */
2855         hdw->cmd_buffer[1] = 0;
2856         hdw->cmd_buffer[2] = 0;
2857         hdw->cmd_buffer[3] = 0;
2858         hdw->cmd_buffer[4] = 0;
2859         hdw->cmd_buffer[5] = 0;
2860         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2861         hdw->cmd_buffer[7] = reg & 0xff;
2862
2863         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
2864         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
2865
2866         LOCK_GIVE(hdw->ctl_lock);
2867
2868         return ret;
2869 }
2870
2871
2872 static int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res)
2873 {
2874         int ret;
2875
2876         LOCK_TAKE(hdw->ctl_lock);
2877
2878         hdw->cmd_buffer[0] = (data >> 8) & 0xff;
2879         hdw->cmd_buffer[1] = data & 0xff;
2880
2881         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 2, hdw->cmd_buffer, res);
2882
2883         LOCK_GIVE(hdw->ctl_lock);
2884
2885         return ret;
2886 }
2887
2888
2889 static int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res)
2890 {
2891         int ret;
2892
2893         LOCK_TAKE(hdw->ctl_lock);
2894
2895         hdw->cmd_buffer[0] = data;
2896
2897         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 1, hdw->cmd_buffer, res);
2898
2899         LOCK_GIVE(hdw->ctl_lock);
2900
2901         return ret;
2902 }
2903
2904
2905 static void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw)
2906 {
2907         if (!hdw->flag_ok) return;
2908         pvr2_trace(PVR2_TRACE_INIT,"render_useless");
2909         hdw->flag_ok = 0;
2910         if (hdw->vid_stream) {
2911                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
2912         }
2913         hdw->flag_streaming_enabled = 0;
2914         hdw->subsys_enabled_mask = 0;
2915 }
2916
2917
2918 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
2919 {
2920         LOCK_TAKE(hdw->ctl_lock);
2921         pvr2_hdw_render_useless_unlocked(hdw);
2922         LOCK_GIVE(hdw->ctl_lock);
2923 }
2924
2925
2926 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
2927 {
2928         int ret;
2929         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
2930         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
2931         if (ret == 1) {
2932                 ret = usb_reset_device(hdw->usb_dev);
2933                 usb_unlock_device(hdw->usb_dev);
2934         } else {
2935                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2936                            "Failed to lock USB device ret=%d",ret);
2937         }
2938         if (init_pause_msec) {
2939                 pvr2_trace(PVR2_TRACE_INFO,
2940                            "Waiting %u msec for hardware to settle",
2941                            init_pause_msec);
2942                 msleep(init_pause_msec);
2943         }
2944
2945 }
2946
2947
2948 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
2949 {
2950         char da[1];
2951         unsigned int pipe;
2952         int ret;
2953
2954         if (!hdw->usb_dev) return;
2955
2956         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
2957
2958         da[0] = val ? 0x01 : 0x00;
2959
2960         /* Write the CPUCS register on the 8051.  The lsb of the register
2961            is the reset bit; a 1 asserts reset while a 0 clears it. */
2962         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
2963         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
2964         if (ret < 0) {
2965                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2966                            "cpureset_assert(%d) error=%d",val,ret);
2967                 pvr2_hdw_render_useless(hdw);
2968         }
2969 }
2970
2971
2972 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
2973 {
2974         int status;
2975         LOCK_TAKE(hdw->ctl_lock); do {
2976                 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
2977                 hdw->flag_ok = !0;
2978                 hdw->cmd_buffer[0] = 0xdd;
2979                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
2980         } while (0); LOCK_GIVE(hdw->ctl_lock);
2981         return status;
2982 }
2983
2984
2985 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
2986 {
2987         int status;
2988         LOCK_TAKE(hdw->ctl_lock); do {
2989                 pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup");
2990                 hdw->cmd_buffer[0] = 0xde;
2991                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
2992         } while (0); LOCK_GIVE(hdw->ctl_lock);
2993         return status;
2994 }
2995
2996
2997 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
2998 {
2999         if (!hdw->decoder_ctrl) {
3000                 pvr2_trace(PVR2_TRACE_INIT,
3001                            "Unable to reset decoder: nothing attached");
3002                 return -ENOTTY;
3003         }
3004
3005         if (!hdw->decoder_ctrl->force_reset) {
3006                 pvr2_trace(PVR2_TRACE_INIT,
3007                            "Unable to reset decoder: not implemented");
3008                 return -ENOTTY;
3009         }
3010
3011         pvr2_trace(PVR2_TRACE_INIT,
3012                    "Requesting decoder reset");
3013         hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3014         return 0;
3015 }
3016
3017
3018 /* Stop / start video stream transport */
3019 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
3020 {
3021         int status;
3022         LOCK_TAKE(hdw->ctl_lock); do {
3023                 hdw->cmd_buffer[0] = (runFl ? 0x36 : 0x37);
3024                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3025         } while (0); LOCK_GIVE(hdw->ctl_lock);
3026         if (!status) {
3027                 hdw->subsys_enabled_mask =
3028                         ((hdw->subsys_enabled_mask &
3029                           ~(1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) |
3030                          (runFl ? (1<<PVR2_SUBSYS_B_USBSTREAM_RUN) : 0));
3031         }
3032         return status;
3033 }
3034
3035
3036 void pvr2_hdw_get_debug_info(const struct pvr2_hdw *hdw,
3037                              struct pvr2_hdw_debug_info *ptr)
3038 {
3039         ptr->big_lock_held = hdw->big_lock_held;
3040         ptr->ctl_lock_held = hdw->ctl_lock_held;
3041         ptr->flag_ok = hdw->flag_ok;
3042         ptr->flag_disconnected = hdw->flag_disconnected;
3043         ptr->flag_init_ok = hdw->flag_init_ok;
3044         ptr->flag_streaming_enabled = hdw->flag_streaming_enabled;
3045         ptr->subsys_flags = hdw->subsys_enabled_mask;
3046         ptr->cmd_debug_state = hdw->cmd_debug_state;
3047         ptr->cmd_code = hdw->cmd_debug_code;
3048         ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
3049         ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
3050         ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
3051         ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
3052         ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
3053         ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
3054         ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
3055 }
3056
3057
3058 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
3059 {
3060         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
3061 }
3062
3063
3064 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
3065 {
3066         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
3067 }
3068
3069
3070 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
3071 {
3072         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
3073 }
3074
3075
3076 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
3077 {
3078         u32 cval,nval;
3079         int ret;
3080         if (~msk) {
3081                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
3082                 if (ret) return ret;
3083                 nval = (cval & ~msk) | (val & msk);
3084                 pvr2_trace(PVR2_TRACE_GPIO,
3085                            "GPIO direction changing 0x%x:0x%x"
3086                            " from 0x%x to 0x%x",
3087                            msk,val,cval,nval);
3088         } else {
3089                 nval = val;
3090                 pvr2_trace(PVR2_TRACE_GPIO,
3091                            "GPIO direction changing to 0x%x",nval);
3092         }
3093         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
3094 }
3095
3096
3097 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
3098 {
3099         u32 cval,nval;
3100         int ret;
3101         if (~msk) {
3102                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
3103                 if (ret) return ret;
3104                 nval = (cval & ~msk) | (val & msk);
3105                 pvr2_trace(PVR2_TRACE_GPIO,
3106                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
3107                            msk,val,cval,nval);
3108         } else {
3109                 nval = val;
3110                 pvr2_trace(PVR2_TRACE_GPIO,
3111                            "GPIO output changing to 0x%x",nval);
3112         }
3113         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
3114 }
3115
3116
3117 /* Find I2C address of eeprom */
3118 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
3119 {
3120         int result;
3121         LOCK_TAKE(hdw->ctl_lock); do {
3122                 hdw->cmd_buffer[0] = 0xeb;
3123                 result = pvr2_send_request(hdw,
3124                                            hdw->cmd_buffer,1,
3125                                            hdw->cmd_buffer,1);
3126                 if (result < 0) break;
3127                 result = hdw->cmd_buffer[0];
3128         } while(0); LOCK_GIVE(hdw->ctl_lock);
3129         return result;
3130 }
3131
3132
3133 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
3134                              u32 chip_id,unsigned long reg_id,
3135                              int setFl,u32 *val_ptr)
3136 {
3137 #ifdef CONFIG_VIDEO_ADV_DEBUG
3138         struct list_head *item;
3139         struct pvr2_i2c_client *cp;
3140         struct v4l2_register req;
3141         int stat = 0;
3142         int okFl = 0;
3143
3144         req.i2c_id = chip_id;
3145         req.reg = reg_id;
3146         if (setFl) req.val = *val_ptr;
3147         mutex_lock(&hdw->i2c_list_lock); do {
3148                 list_for_each(item,&hdw->i2c_clients) {
3149                         cp = list_entry(item,struct pvr2_i2c_client,list);
3150                         if (cp->client->driver->id != chip_id) continue;
3151                         stat = pvr2_i2c_client_cmd(
3152                                 cp,(setFl ? VIDIOC_INT_S_REGISTER :
3153                                     VIDIOC_INT_G_REGISTER),&req);
3154                         if (!setFl) *val_ptr = req.val;
3155                         okFl = !0;
3156                         break;
3157                 }
3158         } while (0); mutex_unlock(&hdw->i2c_list_lock);
3159         if (okFl) {
3160                 return stat;
3161         }
3162         return -EINVAL;
3163 #else
3164         return -ENOSYS;
3165 #endif
3166 }
3167
3168
3169 /*
3170   Stuff for Emacs to see, in order to encourage consistent editing style:
3171   *** Local Variables: ***
3172   *** mode: c ***
3173   *** fill-column: 75 ***
3174   *** tab-width: 8 ***
3175   *** c-basic-offset: 8 ***
3176   *** End: ***
3177   */