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   1 /*************************************************************************
   2  * myri10ge.c: Myricom Myri-10G Ethernet driver.
   3  *
   4  * Copyright (C) 2005 - 2007 Myricom, Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. Neither the name of Myricom, Inc. nor the names of its contributors
  16  *    may be used to endorse or promote products derived from this software
  17  *    without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  *
  32  * If the eeprom on your board is not recent enough, you will need to get a
  33  * newer firmware image at:
  34  *   http://www.myri.com/scs/download-Myri10GE.html
  35  *
  36  * Contact Information:
  37  *   <help@myri.com>
  38  *   Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
  39  *************************************************************************/
  40
  41 #include <linux/tcp.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/skbuff.h>
  44 #include <linux/string.h>
  45 #include <linux/module.h>
  46 #include <linux/pci.h>
  47 #include <linux/dma-mapping.h>
  48 #include <linux/etherdevice.h>
  49 #include <linux/if_ether.h>
  50 #include <linux/if_vlan.h>
  51 #include <linux/inet_lro.h>
  52 #include <linux/dca.h>
  53 #include <linux/ip.h>
  54 #include <linux/inet.h>
  55 #include <linux/in.h>
  56 #include <linux/ethtool.h>
  57 #include <linux/firmware.h>
  58 #include <linux/delay.h>
  59 #include <linux/version.h>
  60 #include <linux/timer.h>
  61 #include <linux/vmalloc.h>
  62 #include <linux/crc32.h>
  63 #include <linux/moduleparam.h>
  64 #include <linux/io.h>
  65 #include <linux/log2.h>
  66 #include <net/checksum.h>
  67 #include <net/ip.h>
  68 #include <net/tcp.h>
  69 #include <asm/byteorder.h>
  70 #include <asm/io.h>
  71 #include <asm/processor.h>
  72 #ifdef CONFIG_MTRR
  73 #include <asm/mtrr.h>
  74 #endif
  75
  76 #include "myri10ge_mcp.h"
  77 #include "myri10ge_mcp_gen_header.h"
  78
  79 #define MYRI10GE_VERSION_STR "1.3.99-1.347"
  80
  81 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
  82 MODULE_AUTHOR("Maintainer: help@myri.com");
  83 MODULE_VERSION(MYRI10GE_VERSION_STR);
  84 MODULE_LICENSE("Dual BSD/GPL");
  85
  86 #define MYRI10GE_MAX_ETHER_MTU 9014
  87
  88 #define MYRI10GE_ETH_STOPPED 0
  89 #define MYRI10GE_ETH_STOPPING 1
  90 #define MYRI10GE_ETH_STARTING 2
  91 #define MYRI10GE_ETH_RUNNING 3
  92 #define MYRI10GE_ETH_OPEN_FAILED 4
  93
  94 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
  95 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
  96 #define MYRI10GE_MAX_LRO_DESCRIPTORS 8
  97 #define MYRI10GE_LRO_MAX_PKTS 64
  98
  99 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
 100 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
 101
 102 #define MYRI10GE_ALLOC_ORDER 0
 103 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
 104 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
 105
 106 struct myri10ge_rx_buffer_state {
 107         struct page *page;
 108         int page_offset;
 109          DECLARE_PCI_UNMAP_ADDR(bus)
 110          DECLARE_PCI_UNMAP_LEN(len)
 111 };
 112
 113 struct myri10ge_tx_buffer_state {
 114         struct sk_buff *skb;
 115         int last;
 116          DECLARE_PCI_UNMAP_ADDR(bus)
 117          DECLARE_PCI_UNMAP_LEN(len)
 118 };
 119
 120 struct myri10ge_cmd {
 121         u32 data0;
 122         u32 data1;
 123         u32 data2;
 124 };
 125
 126 struct myri10ge_rx_buf {
 127         struct mcp_kreq_ether_recv __iomem *lanai;      /* lanai ptr for recv ring */
 128         u8 __iomem *wc_fifo;    /* w/c rx dma addr fifo address */
 129         struct mcp_kreq_ether_recv *shadow;     /* host shadow of recv ring */
 130         struct myri10ge_rx_buffer_state *info;
 131         struct page *page;
 132         dma_addr_t bus;
 133         int page_offset;
 134         int cnt;
 135         int fill_cnt;
 136         int alloc_fail;
 137         int mask;               /* number of rx slots -1 */
 138         int watchdog_needed;
 139 };
 140
 141 struct myri10ge_tx_buf {
 142         struct mcp_kreq_ether_send __iomem *lanai;      /* lanai ptr for sendq */
 143         u8 __iomem *wc_fifo;    /* w/c send fifo address */
 144         struct mcp_kreq_ether_send *req_list;   /* host shadow of sendq */
 145         char *req_bytes;
 146         struct myri10ge_tx_buffer_state *info;
 147         int mask;               /* number of transmit slots -1  */
 148         int req ____cacheline_aligned;  /* transmit slots submitted     */
 149         int pkt_start;          /* packets started */
 150         int stop_queue;
 151         int linearized;
 152         int done ____cacheline_aligned; /* transmit slots completed     */
 153         int pkt_done;           /* packets completed */
 154         int wake_queue;
 155 };
 156
 157 struct myri10ge_rx_done {
 158         struct mcp_slot *entry;
 159         dma_addr_t bus;
 160         int cnt;
 161         int idx;
 162         struct net_lro_mgr lro_mgr;
 163         struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
 164 };
 165
 166 struct myri10ge_slice_netstats {
 167         unsigned long rx_packets;
 168         unsigned long tx_packets;
 169         unsigned long rx_bytes;
 170         unsigned long tx_bytes;
 171         unsigned long rx_dropped;
 172         unsigned long tx_dropped;
 173 };
 174
 175 struct myri10ge_slice_state {
 176         struct myri10ge_tx_buf tx;      /* transmit ring        */
 177         struct myri10ge_rx_buf rx_small;
 178         struct myri10ge_rx_buf rx_big;
 179         struct myri10ge_rx_done rx_done;
 180         struct net_device *dev;
 181         struct napi_struct napi;
 182         struct myri10ge_priv *mgp;
 183         struct myri10ge_slice_netstats stats;
 184         __be32 __iomem *irq_claim;
 185         struct mcp_irq_data *fw_stats;
 186         dma_addr_t fw_stats_bus;
 187         int watchdog_tx_done;
 188         int watchdog_tx_req;
 189 #ifdef CONFIG_DCA
 190         int cached_dca_tag;
 191         int cpu;
 192         __be32 __iomem *dca_tag;
 193 #endif
 194         char irq_desc[32];
 195 };
 196
 197 struct myri10ge_priv {
 198         struct myri10ge_slice_state *ss;
 199         int tx_boundary;        /* boundary transmits cannot cross */
 200         int num_slices;
 201         int running;            /* running?             */
 202         int csum_flag;          /* rx_csums?            */
 203         int small_bytes;
 204         int big_bytes;
 205         int max_intr_slots;
 206         struct net_device *dev;
 207         struct net_device_stats stats;
 208         spinlock_t stats_lock;
 209         u8 __iomem *sram;
 210         int sram_size;
 211         unsigned long board_span;
 212         unsigned long iomem_base;
 213         __be32 __iomem *irq_deassert;
 214         char *mac_addr_string;
 215         struct mcp_cmd_response *cmd;
 216         dma_addr_t cmd_bus;
 217         struct pci_dev *pdev;
 218         int msi_enabled;
 219         int msix_enabled;
 220         struct msix_entry *msix_vectors;
 221 #ifdef CONFIG_DCA
 222         int dca_enabled;
 223 #endif
 224         u32 link_state;
 225         unsigned int rdma_tags_available;
 226         int intr_coal_delay;
 227         __be32 __iomem *intr_coal_delay_ptr;
 228         int mtrr;
 229         int wc_enabled;
 230         int down_cnt;
 231         wait_queue_head_t down_wq;
 232         struct work_struct watchdog_work;
 233         struct timer_list watchdog_timer;
 234         int watchdog_resets;
 235         int watchdog_pause;
 236         int pause;
 237         char *fw_name;
 238         char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
 239         char *product_code_string;
 240         char fw_version[128];
 241         int fw_ver_major;
 242         int fw_ver_minor;
 243         int fw_ver_tiny;
 244         int adopted_rx_filter_bug;
 245         u8 mac_addr[6];         /* eeprom mac address */
 246         unsigned long serial_number;
 247         int vendor_specific_offset;
 248         int fw_multicast_support;
 249         unsigned long features;
 250         u32 max_tso6;
 251         u32 read_dma;
 252         u32 write_dma;
 253         u32 read_write_dma;
 254         u32 link_changes;
 255         u32 msg_enable;
 256 };
 257
 258 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
 259 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
 260 static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
 261 static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
 262
 263 static char *myri10ge_fw_name = NULL;
 264 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
 265 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
 266
 267 static int myri10ge_ecrc_enable = 1;
 268 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
 269 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
 270
 271 static int myri10ge_small_bytes = -1;   /* -1 == auto */
 272 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
 273 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
 274
 275 static int myri10ge_msi = 1;    /* enable msi by default */
 276 module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
 277 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
 278
 279 static int myri10ge_intr_coal_delay = 75;
 280 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
 281 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
 282
 283 static int myri10ge_flow_control = 1;
 284 module_param(myri10ge_flow_control, int, S_IRUGO);
 285 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
 286
 287 static int myri10ge_deassert_wait = 1;
 288 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
 289 MODULE_PARM_DESC(myri10ge_deassert_wait,
 290                  "Wait when deasserting legacy interrupts");
 291
 292 static int myri10ge_force_firmware = 0;
 293 module_param(myri10ge_force_firmware, int, S_IRUGO);
 294 MODULE_PARM_DESC(myri10ge_force_firmware,
 295                  "Force firmware to assume aligned completions");
 296
 297 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
 298 module_param(myri10ge_initial_mtu, int, S_IRUGO);
 299 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
 300
 301 static int myri10ge_napi_weight = 64;
 302 module_param(myri10ge_napi_weight, int, S_IRUGO);
 303 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
 304
 305 static int myri10ge_watchdog_timeout = 1;
 306 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
 307 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
 308
 309 static int myri10ge_max_irq_loops = 1048576;
 310 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
 311 MODULE_PARM_DESC(myri10ge_max_irq_loops,
 312                  "Set stuck legacy IRQ detection threshold");
 313
 314 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
 315
 316 static int myri10ge_debug = -1; /* defaults above */
 317 module_param(myri10ge_debug, int, 0);
 318 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
 319
 320 static int myri10ge_lro = 1;
 321 module_param(myri10ge_lro, int, S_IRUGO);
 322 MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload");
 323
 324 static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
 325 module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
 326 MODULE_PARM_DESC(myri10ge_lro_max_pkts,
 327                  "Number of LRO packets to be aggregated");
 328
 329 static int myri10ge_fill_thresh = 256;
 330 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
 331 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
 332
 333 static int myri10ge_reset_recover = 1;
 334
 335 static int myri10ge_wcfifo = 0;
 336 module_param(myri10ge_wcfifo, int, S_IRUGO);
 337 MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled");
 338
 339 static int myri10ge_max_slices = 1;
 340 module_param(myri10ge_max_slices, int, S_IRUGO);
 341 MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
 342
 343 static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
 344 module_param(myri10ge_rss_hash, int, S_IRUGO);
 345 MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
 346
 347 static int myri10ge_dca = 1;
 348 module_param(myri10ge_dca, int, S_IRUGO);
 349 MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
 350
 351 #define MYRI10GE_FW_OFFSET 1024*1024
 352 #define MYRI10GE_HIGHPART_TO_U32(X) \
 353 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
 354 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
 355
 356 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
 357
 358 static void myri10ge_set_multicast_list(struct net_device *dev);
 359 static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev);
 360
 361 static inline void put_be32(__be32 val, __be32 __iomem * p)
 362 {
 363         __raw_writel((__force __u32) val, (__force void __iomem *)p);
 364 }
 365
 366 static int
 367 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
 368                   struct myri10ge_cmd *data, int atomic)
 369 {
 370         struct mcp_cmd *buf;
 371         char buf_bytes[sizeof(*buf) + 8];
 372         struct mcp_cmd_response *response = mgp->cmd;
 373         char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
 374         u32 dma_low, dma_high, result, value;
 375         int sleep_total = 0;
 376
 377         /* ensure buf is aligned to 8 bytes */
 378         buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
 379
 380         buf->data0 = htonl(data->data0);
 381         buf->data1 = htonl(data->data1);
 382         buf->data2 = htonl(data->data2);
 383         buf->cmd = htonl(cmd);
 384         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
 385         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
 386
 387         buf->response_addr.low = htonl(dma_low);
 388         buf->response_addr.high = htonl(dma_high);
 389         response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
 390         mb();
 391         myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
 392
 393         /* wait up to 15ms. Longest command is the DMA benchmark,
 394          * which is capped at 5ms, but runs from a timeout handler
 395          * that runs every 7.8ms. So a 15ms timeout leaves us with
 396          * a 2.2ms margin
 397          */
 398         if (atomic) {
 399                 /* if atomic is set, do not sleep,
 400                  * and try to get the completion quickly
 401                  * (1ms will be enough for those commands) */
 402                 for (sleep_total = 0;
 403                      sleep_total < 1000
 404                      && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
 405                      sleep_total += 10) {
 406                         udelay(10);
 407                         mb();
 408                 }
 409         } else {
 410                 /* use msleep for most command */
 411                 for (sleep_total = 0;
 412                      sleep_total < 15
 413                      && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
 414                      sleep_total++)
 415                         msleep(1);
 416         }
 417
 418         result = ntohl(response->result);
 419         value = ntohl(response->data);
 420         if (result != MYRI10GE_NO_RESPONSE_RESULT) {
 421                 if (result == 0) {
 422                         data->data0 = value;
 423                         return 0;
 424                 } else if (result == MXGEFW_CMD_UNKNOWN) {
 425                         return -ENOSYS;
 426                 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
 427                         return -E2BIG;
 428                 } else {
 429                         dev_err(&mgp->pdev->dev,
 430                                 "command %d failed, result = %d\n",
 431                                 cmd, result);
 432                         return -ENXIO;
 433                 }
 434         }
 435
 436         dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
 437                 cmd, result);
 438         return -EAGAIN;
 439 }
 440
 441 /*
 442  * The eeprom strings on the lanaiX have the format
 443  * SN=x\0
 444  * MAC=x:x:x:x:x:x\0
 445  * PT:ddd mmm xx xx:xx:xx xx\0
 446  * PV:ddd mmm xx xx:xx:xx xx\0
 447  */
 448 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
 449 {
 450         char *ptr, *limit;
 451         int i;
 452
 453         ptr = mgp->eeprom_strings;
 454         limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
 455
 456         while (*ptr != '\0' && ptr < limit) {
 457                 if (memcmp(ptr, "MAC=", 4) == 0) {
 458                         ptr += 4;
 459                         mgp->mac_addr_string = ptr;
 460                         for (i = 0; i < 6; i++) {
 461                                 if ((ptr + 2) > limit)
 462                                         goto abort;
 463                                 mgp->mac_addr[i] =
 464                                     simple_strtoul(ptr, &ptr, 16);
 465                                 ptr += 1;
 466                         }
 467                 }
 468                 if (memcmp(ptr, "PC=", 3) == 0) {
 469                         ptr += 3;
 470                         mgp->product_code_string = ptr;
 471                 }
 472                 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
 473                         ptr += 3;
 474                         mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
 475                 }
 476                 while (ptr < limit && *ptr++) ;
 477         }
 478
 479         return 0;
 480
 481 abort:
 482         dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
 483         return -ENXIO;
 484 }
 485
 486 /*
 487  * Enable or disable periodic RDMAs from the host to make certain
 488  * chipsets resend dropped PCIe messages
 489  */
 490
 491 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
 492 {
 493         char __iomem *submit;
 494         __be32 buf[16] __attribute__ ((__aligned__(8)));
 495         u32 dma_low, dma_high;
 496         int i;
 497
 498         /* clear confirmation addr */
 499         mgp->cmd->data = 0;
 500         mb();
 501
 502         /* send a rdma command to the PCIe engine, and wait for the
 503          * response in the confirmation address.  The firmware should
 504          * write a -1 there to indicate it is alive and well
 505          */
 506         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
 507         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
 508
 509         buf[0] = htonl(dma_high);       /* confirm addr MSW */
 510         buf[1] = htonl(dma_low);        /* confirm addr LSW */
 511         buf[2] = MYRI10GE_NO_CONFIRM_DATA;      /* confirm data */
 512         buf[3] = htonl(dma_high);       /* dummy addr MSW */
 513         buf[4] = htonl(dma_low);        /* dummy addr LSW */
 514         buf[5] = htonl(enable); /* enable? */
 515
 516         submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
 517
 518         myri10ge_pio_copy(submit, &buf, sizeof(buf));
 519         for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
 520                 msleep(1);
 521         if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
 522                 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
 523                         (enable ? "enable" : "disable"));
 524 }
 525
 526 static int
 527 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
 528                            struct mcp_gen_header *hdr)
 529 {
 530         struct device *dev = &mgp->pdev->dev;
 531
 532         /* check firmware type */
 533         if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
 534                 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
 535                 return -EINVAL;
 536         }
 537
 538         /* save firmware version for ethtool */
 539         strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
 540
 541         sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
 542                &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
 543
 544         if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
 545               && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
 546                 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
 547                 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
 548                         MXGEFW_VERSION_MINOR);
 549                 return -EINVAL;
 550         }
 551         return 0;
 552 }
 553
 554 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
 555 {
 556         unsigned crc, reread_crc;
 557         const struct firmware *fw;
 558         struct device *dev = &mgp->pdev->dev;
 559         unsigned char *fw_readback;
 560         struct mcp_gen_header *hdr;
 561         size_t hdr_offset;
 562         int status;
 563         unsigned i;
 564
 565         if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
 566                 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
 567                         mgp->fw_name);
 568                 status = -EINVAL;
 569                 goto abort_with_nothing;
 570         }
 571
 572         /* check size */
 573
 574         if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
 575             fw->size < MCP_HEADER_PTR_OFFSET + 4) {
 576                 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
 577                 status = -EINVAL;
 578                 goto abort_with_fw;
 579         }
 580
 581         /* check id */
 582         hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
 583         if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
 584                 dev_err(dev, "Bad firmware file\n");
 585                 status = -EINVAL;
 586                 goto abort_with_fw;
 587         }
 588         hdr = (void *)(fw->data + hdr_offset);
 589
 590         status = myri10ge_validate_firmware(mgp, hdr);
 591         if (status != 0)
 592                 goto abort_with_fw;
 593
 594         crc = crc32(~0, fw->data, fw->size);
 595         for (i = 0; i < fw->size; i += 256) {
 596                 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
 597                                   fw->data + i,
 598                                   min(256U, (unsigned)(fw->size - i)));
 599                 mb();
 600                 readb(mgp->sram);
 601         }
 602         fw_readback = vmalloc(fw->size);
 603         if (!fw_readback) {
 604                 status = -ENOMEM;
 605                 goto abort_with_fw;
 606         }
 607         /* corruption checking is good for parity recovery and buggy chipset */
 608         memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
 609         reread_crc = crc32(~0, fw_readback, fw->size);
 610         vfree(fw_readback);
 611         if (crc != reread_crc) {
 612                 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
 613                         (unsigned)fw->size, reread_crc, crc);
 614                 status = -EIO;
 615                 goto abort_with_fw;
 616         }
 617         *size = (u32) fw->size;
 618
 619 abort_with_fw:
 620         release_firmware(fw);
 621
 622 abort_with_nothing:
 623         return status;
 624 }
 625
 626 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
 627 {
 628         struct mcp_gen_header *hdr;
 629         struct device *dev = &mgp->pdev->dev;
 630         const size_t bytes = sizeof(struct mcp_gen_header);
 631         size_t hdr_offset;
 632         int status;
 633
 634         /* find running firmware header */
 635         hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
 636
 637         if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
 638                 dev_err(dev, "Running firmware has bad header offset (%d)\n",
 639                         (int)hdr_offset);
 640                 return -EIO;
 641         }
 642
 643         /* copy header of running firmware from SRAM to host memory to
 644          * validate firmware */
 645         hdr = kmalloc(bytes, GFP_KERNEL);
 646         if (hdr == NULL) {
 647                 dev_err(dev, "could not malloc firmware hdr\n");
 648                 return -ENOMEM;
 649         }
 650         memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
 651         status = myri10ge_validate_firmware(mgp, hdr);
 652         kfree(hdr);
 653
 654         /* check to see if adopted firmware has bug where adopting
 655          * it will cause broadcasts to be filtered unless the NIC
 656          * is kept in ALLMULTI mode */
 657         if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
 658             mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
 659                 mgp->adopted_rx_filter_bug = 1;
 660                 dev_warn(dev, "Adopting fw %d.%d.%d: "
 661                          "working around rx filter bug\n",
 662                          mgp->fw_ver_major, mgp->fw_ver_minor,
 663                          mgp->fw_ver_tiny);
 664         }
 665         return status;
 666 }
 667
 668 static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
 669 {
 670         struct myri10ge_cmd cmd;
 671         int status;
 672
 673         /* probe for IPv6 TSO support */
 674         mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
 675         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
 676                                    &cmd, 0);
 677         if (status == 0) {
 678                 mgp->max_tso6 = cmd.data0;
 679                 mgp->features |= NETIF_F_TSO6;
 680         }
 681
 682         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
 683         if (status != 0) {
 684                 dev_err(&mgp->pdev->dev,
 685                         "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
 686                 return -ENXIO;
 687         }
 688
 689         mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
 690
 691         return 0;
 692 }
 693
 694 static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
 695 {
 696         char __iomem *submit;
 697         __be32 buf[16] __attribute__ ((__aligned__(8)));
 698         u32 dma_low, dma_high, size;
 699         int status, i;
 700
 701         size = 0;
 702         status = myri10ge_load_hotplug_firmware(mgp, &size);
 703         if (status) {
 704                 if (!adopt)
 705                         return status;
 706                 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
 707
 708                 /* Do not attempt to adopt firmware if there
 709                  * was a bad crc */
 710                 if (status == -EIO)
 711                         return status;
 712
 713                 status = myri10ge_adopt_running_firmware(mgp);
 714                 if (status != 0) {
 715                         dev_err(&mgp->pdev->dev,
 716                                 "failed to adopt running firmware\n");
 717                         return status;
 718                 }
 719                 dev_info(&mgp->pdev->dev,
 720                          "Successfully adopted running firmware\n");
 721                 if (mgp->tx_boundary == 4096) {
 722                         dev_warn(&mgp->pdev->dev,
 723                                  "Using firmware currently running on NIC"
 724                                  ".  For optimal\n");
 725                         dev_warn(&mgp->pdev->dev,
 726                                  "performance consider loading optimized "
 727                                  "firmware\n");
 728                         dev_warn(&mgp->pdev->dev, "via hotplug\n");
 729                 }
 730
 731                 mgp->fw_name = "adopted";
 732                 mgp->tx_boundary = 2048;
 733                 myri10ge_dummy_rdma(mgp, 1);
 734                 status = myri10ge_get_firmware_capabilities(mgp);
 735                 return status;
 736         }
 737
 738         /* clear confirmation addr */
 739         mgp->cmd->data = 0;
 740         mb();
 741
 742         /* send a reload command to the bootstrap MCP, and wait for the
 743          *  response in the confirmation address.  The firmware should
 744          * write a -1 there to indicate it is alive and well
 745          */
 746         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
 747         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
 748
 749         buf[0] = htonl(dma_high);       /* confirm addr MSW */
 750         buf[1] = htonl(dma_low);        /* confirm addr LSW */
 751         buf[2] = MYRI10GE_NO_CONFIRM_DATA;      /* confirm data */
 752
 753         /* FIX: All newest firmware should un-protect the bottom of
 754          * the sram before handoff. However, the very first interfaces
 755          * do not. Therefore the handoff copy must skip the first 8 bytes
 756          */
 757         buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
 758         buf[4] = htonl(size - 8);       /* length of code */
 759         buf[5] = htonl(8);      /* where to copy to */
 760         buf[6] = htonl(0);      /* where to jump to */
 761
 762         submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
 763
 764         myri10ge_pio_copy(submit, &buf, sizeof(buf));
 765         mb();
 766         msleep(1);
 767         mb();
 768         i = 0;
 769         while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
 770                 msleep(1 << i);
 771                 i++;
 772         }
 773         if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
 774                 dev_err(&mgp->pdev->dev, "handoff failed\n");
 775                 return -ENXIO;
 776         }
 777         myri10ge_dummy_rdma(mgp, 1);
 778         status = myri10ge_get_firmware_capabilities(mgp);
 779
 780         return status;
 781 }
 782
 783 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
 784 {
 785         struct myri10ge_cmd cmd;
 786         int status;
 787
 788         cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
 789                      | (addr[2] << 8) | addr[3]);
 790
 791         cmd.data1 = ((addr[4] << 8) | (addr[5]));
 792
 793         status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
 794         return status;
 795 }
 796
 797 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
 798 {
 799         struct myri10ge_cmd cmd;
 800         int status, ctl;
 801
 802         ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
 803         status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
 804
 805         if (status) {
 806                 printk(KERN_ERR
 807                        "myri10ge: %s: Failed to set flow control mode\n",
 808                        mgp->dev->name);
 809                 return status;
 810         }
 811         mgp->pause = pause;
 812         return 0;
 813 }
 814
 815 static void
 816 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
 817 {
 818         struct myri10ge_cmd cmd;
 819         int status, ctl;
 820
 821         ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
 822         status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
 823         if (status)
 824                 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
 825                        mgp->dev->name);
 826 }
 827
 828 static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
 829 {
 830         struct myri10ge_cmd cmd;
 831         int status;
 832         u32 len;
 833         struct page *dmatest_page;
 834         dma_addr_t dmatest_bus;
 835         char *test = " ";
 836
 837         dmatest_page = alloc_page(GFP_KERNEL);
 838         if (!dmatest_page)
 839                 return -ENOMEM;
 840         dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
 841                                    DMA_BIDIRECTIONAL);
 842
 843         /* Run a small DMA test.
 844          * The magic multipliers to the length tell the firmware
 845          * to do DMA read, write, or read+write tests.  The
 846          * results are returned in cmd.data0.  The upper 16
 847          * bits or the return is the number of transfers completed.
 848          * The lower 16 bits is the time in 0.5us ticks that the
 849          * transfers took to complete.
 850          */
 851
 852         len = mgp->tx_boundary;
 853
 854         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
 855         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
 856         cmd.data2 = len * 0x10000;
 857         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
 858         if (status != 0) {
 859                 test = "read";
 860                 goto abort;
 861         }
 862         mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
 863         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
 864         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
 865         cmd.data2 = len * 0x1;
 866         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
 867         if (status != 0) {
 868                 test = "write";
 869                 goto abort;
 870         }
 871         mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
 872
 873         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
 874         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
 875         cmd.data2 = len * 0x10001;
 876         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
 877         if (status != 0) {
 878                 test = "read/write";
 879                 goto abort;
 880         }
 881         mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
 882             (cmd.data0 & 0xffff);
 883
 884 abort:
 885         pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
 886         put_page(dmatest_page);
 887
 888         if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
 889                 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
 890                          test, status);
 891
 892         return status;
 893 }
 894
 895 static int myri10ge_reset(struct myri10ge_priv *mgp)
 896 {
 897         struct myri10ge_cmd cmd;
 898         struct myri10ge_slice_state *ss;
 899         int i, status;
 900         size_t bytes;
 901 #ifdef CONFIG_DCA
 902         unsigned long dca_tag_off;
 903 #endif
 904
 905         /* try to send a reset command to the card to see if it
 906          * is alive */
 907         memset(&cmd, 0, sizeof(cmd));
 908         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
 909         if (status != 0) {
 910                 dev_err(&mgp->pdev->dev, "failed reset\n");
 911                 return -ENXIO;
 912         }
 913
 914         (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
 915         /*
 916          * Use non-ndis mcp_slot (eg, 4 bytes total,
 917          * no toeplitz hash value returned.  Older firmware will
 918          * not understand this command, but will use the correct
 919          * sized mcp_slot, so we ignore error returns
 920          */
 921         cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
 922         (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
 923
 924         /* Now exchange information about interrupts  */
 925
 926         bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
 927         cmd.data0 = (u32) bytes;
 928         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
 929
 930         /*
 931          * Even though we already know how many slices are supported
 932          * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
 933          * has magic side effects, and must be called after a reset.
 934          * It must be called prior to calling any RSS related cmds,
 935          * including assigning an interrupt queue for anything but
 936          * slice 0.  It must also be called *after*
 937          * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
 938          * the firmware to compute offsets.
 939          */
 940
 941         if (mgp->num_slices > 1) {
 942
 943                 /* ask the maximum number of slices it supports */
 944                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
 945                                            &cmd, 0);
 946                 if (status != 0) {
 947                         dev_err(&mgp->pdev->dev,
 948                                 "failed to get number of slices\n");
 949                 }
 950
 951                 /*
 952                  * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
 953                  * to setting up the interrupt queue DMA
 954                  */
 955
 956                 cmd.data0 = mgp->num_slices;
 957                 cmd.data1 = 1;  /* use MSI-X */
 958                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
 959                                            &cmd, 0);
 960                 if (status != 0) {
 961                         dev_err(&mgp->pdev->dev,
 962                                 "failed to set number of slices\n");
 963
 964                         return status;
 965                 }
 966         }
 967         for (i = 0; i < mgp->num_slices; i++) {
 968                 ss = &mgp->ss[i];
 969                 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
 970                 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
 971                 cmd.data2 = i;
 972                 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
 973                                             &cmd, 0);
 974         };
 975
 976         status |=
 977             myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
 978         for (i = 0; i < mgp->num_slices; i++) {
 979                 ss = &mgp->ss[i];
 980                 ss->irq_claim =
 981                     (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
 982         }
 983         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
 984                                     &cmd, 0);
 985         mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
 986
 987         status |= myri10ge_send_cmd
 988             (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
 989         mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
 990         if (status != 0) {
 991                 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
 992                 return status;
 993         }
 994         put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
 995
 996 #ifdef CONFIG_DCA
 997         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
 998         dca_tag_off = cmd.data0;
 999         for (i = 0; i < mgp->num_slices; i++) {
1000                 ss = &mgp->ss[i];
1001                 if (status == 0) {
1002                         ss->dca_tag = (__iomem __be32 *)
1003                             (mgp->sram + dca_tag_off + 4 * i);
1004                 } else {
1005                         ss->dca_tag = NULL;
1006                 }
1007         }
1008 #endif                          /* CONFIG_DCA */
1009
1010         /* reset mcp/driver shared state back to 0 */
1011
1012         mgp->link_changes = 0;
1013         for (i = 0; i < mgp->num_slices; i++) {
1014                 ss = &mgp->ss[i];
1015
1016                 memset(ss->rx_done.entry, 0, bytes);
1017                 ss->tx.req = 0;
1018                 ss->tx.done = 0;
1019                 ss->tx.pkt_start = 0;
1020                 ss->tx.pkt_done = 0;
1021                 ss->rx_big.cnt = 0;
1022                 ss->rx_small.cnt = 0;
1023                 ss->rx_done.idx = 0;
1024                 ss->rx_done.cnt = 0;
1025                 ss->tx.wake_queue = 0;
1026                 ss->tx.stop_queue = 0;
1027         }
1028
1029         status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
1030         myri10ge_change_pause(mgp, mgp->pause);
1031         myri10ge_set_multicast_list(mgp->dev);
1032         return status;
1033 }
1034
1035 #ifdef CONFIG_DCA
1036 static void
1037 myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1038 {
1039         ss->cpu = cpu;
1040         ss->cached_dca_tag = tag;
1041         put_be32(htonl(tag), ss->dca_tag);
1042 }
1043
1044 static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1045 {
1046         int cpu = get_cpu();
1047         int tag;
1048
1049         if (cpu != ss->cpu) {
1050                 tag = dca_get_tag(cpu);
1051                 if (ss->cached_dca_tag != tag)
1052                         myri10ge_write_dca(ss, cpu, tag);
1053         }
1054         put_cpu();
1055 }
1056
1057 static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1058 {
1059         int err, i;
1060         struct pci_dev *pdev = mgp->pdev;
1061
1062         if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1063                 return;
1064         if (!myri10ge_dca) {
1065                 dev_err(&pdev->dev, "dca disabled by administrator\n");
1066                 return;
1067         }
1068         err = dca_add_requester(&pdev->dev);
1069         if (err) {
1070                 dev_err(&pdev->dev,
1071                         "dca_add_requester() failed, err=%d\n", err);
1072                 return;
1073         }
1074         mgp->dca_enabled = 1;
1075         for (i = 0; i < mgp->num_slices; i++)
1076                 myri10ge_write_dca(&mgp->ss[i], -1, 0);
1077 }
1078
1079 static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1080 {
1081         struct pci_dev *pdev = mgp->pdev;
1082         int err;
1083
1084         if (!mgp->dca_enabled)
1085                 return;
1086         mgp->dca_enabled = 0;
1087         err = dca_remove_requester(&pdev->dev);
1088 }
1089
1090 static int myri10ge_notify_dca_device(struct device *dev, void *data)
1091 {
1092         struct myri10ge_priv *mgp;
1093         unsigned long event;
1094
1095         mgp = dev_get_drvdata(dev);
1096         event = *(unsigned long *)data;
1097
1098         if (event == DCA_PROVIDER_ADD)
1099                 myri10ge_setup_dca(mgp);
1100         else if (event == DCA_PROVIDER_REMOVE)
1101                 myri10ge_teardown_dca(mgp);
1102         return 0;
1103 }
1104 #endif                          /* CONFIG_DCA */
1105
1106 static inline void
1107 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1108                     struct mcp_kreq_ether_recv *src)
1109 {
1110         __be32 low;
1111
1112         low = src->addr_low;
1113         src->addr_low = htonl(DMA_32BIT_MASK);
1114         myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1115         mb();
1116         myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
1117         mb();
1118         src->addr_low = low;
1119         put_be32(low, &dst->addr_low);
1120         mb();
1121 }
1122
1123 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
1124 {
1125         struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1126
1127         if ((skb->protocol == htons(ETH_P_8021Q)) &&
1128             (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1129              vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1130                 skb->csum = hw_csum;
1131                 skb->ip_summed = CHECKSUM_COMPLETE;
1132         }
1133 }
1134
1135 static inline void
1136 myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
1137                       struct skb_frag_struct *rx_frags, int len, int hlen)
1138 {
1139         struct skb_frag_struct *skb_frags;
1140
1141         skb->len = skb->data_len = len;
1142         skb->truesize = len + sizeof(struct sk_buff);
1143         /* attach the page(s) */
1144
1145         skb_frags = skb_shinfo(skb)->frags;
1146         while (len > 0) {
1147                 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
1148                 len -= rx_frags->size;
1149                 skb_frags++;
1150                 rx_frags++;
1151                 skb_shinfo(skb)->nr_frags++;
1152         }
1153
1154         /* pskb_may_pull is not available in irq context, but
1155          * skb_pull() (for ether_pad and eth_type_trans()) requires
1156          * the beginning of the packet in skb_headlen(), move it
1157          * manually */
1158         skb_copy_to_linear_data(skb, va, hlen);
1159         skb_shinfo(skb)->frags[0].page_offset += hlen;
1160         skb_shinfo(skb)->frags[0].size -= hlen;
1161         skb->data_len -= hlen;
1162         skb->tail += hlen;
1163         skb_pull(skb, MXGEFW_PAD);
1164 }
1165
1166 static void
1167 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1168                         int bytes, int watchdog)
1169 {
1170         struct page *page;
1171         int idx;
1172
1173         if (unlikely(rx->watchdog_needed && !watchdog))
1174                 return;
1175
1176         /* try to refill entire ring */
1177         while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1178                 idx = rx->fill_cnt & rx->mask;
1179                 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
1180                         /* we can use part of previous page */
1181                         get_page(rx->page);
1182                 } else {
1183                         /* we need a new page */
1184                         page =
1185                             alloc_pages(GFP_ATOMIC | __GFP_COMP,
1186                                         MYRI10GE_ALLOC_ORDER);
1187                         if (unlikely(page == NULL)) {
1188                                 if (rx->fill_cnt - rx->cnt < 16)
1189                                         rx->watchdog_needed = 1;
1190                                 return;
1191                         }
1192                         rx->page = page;
1193                         rx->page_offset = 0;
1194                         rx->bus = pci_map_page(mgp->pdev, page, 0,
1195                                                MYRI10GE_ALLOC_SIZE,
1196                                                PCI_DMA_FROMDEVICE);
1197                 }
1198                 rx->info[idx].page = rx->page;
1199                 rx->info[idx].page_offset = rx->page_offset;
1200                 /* note that this is the address of the start of the
1201                  * page */
1202                 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1203                 rx->shadow[idx].addr_low =
1204                     htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1205                 rx->shadow[idx].addr_high =
1206                     htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1207
1208                 /* start next packet on a cacheline boundary */
1209                 rx->page_offset += SKB_DATA_ALIGN(bytes);
1210
1211 #if MYRI10GE_ALLOC_SIZE > 4096
1212                 /* don't cross a 4KB boundary */
1213                 if ((rx->page_offset >> 12) !=
1214                     ((rx->page_offset + bytes - 1) >> 12))
1215                         rx->page_offset = (rx->page_offset + 4096) & ~4095;
1216 #endif
1217                 rx->fill_cnt++;
1218
1219                 /* copy 8 descriptors to the firmware at a time */
1220                 if ((idx & 7) == 7) {
1221                         if (rx->wc_fifo == NULL)
1222                                 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1223                                                     &rx->shadow[idx - 7]);
1224                         else {
1225                                 mb();
1226                                 myri10ge_pio_copy(rx->wc_fifo,
1227                                                   &rx->shadow[idx - 7], 64);
1228                         }
1229                 }
1230         }
1231 }
1232
1233 static inline void
1234 myri10ge_unmap_rx_page(struct pci_dev *pdev,
1235                        struct myri10ge_rx_buffer_state *info, int bytes)
1236 {
1237         /* unmap the recvd page if we're the only or last user of it */
1238         if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1239             (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1240                 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1241                                       & ~(MYRI10GE_ALLOC_SIZE - 1)),
1242                                MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1243         }
1244 }
1245
1246 #define MYRI10GE_HLEN 64        /* The number of bytes to copy from a
1247                                  * page into an skb */
1248
1249 static inline int
1250 myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
1251                  int bytes, int len, __wsum csum)
1252 {
1253         struct myri10ge_priv *mgp = ss->mgp;
1254         struct sk_buff *skb;
1255         struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1256         int i, idx, hlen, remainder;
1257         struct pci_dev *pdev = mgp->pdev;
1258         struct net_device *dev = mgp->dev;
1259         u8 *va;
1260
1261         len += MXGEFW_PAD;
1262         idx = rx->cnt & rx->mask;
1263         va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1264         prefetch(va);
1265         /* Fill skb_frag_struct(s) with data from our receive */
1266         for (i = 0, remainder = len; remainder > 0; i++) {
1267                 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1268                 rx_frags[i].page = rx->info[idx].page;
1269                 rx_frags[i].page_offset = rx->info[idx].page_offset;
1270                 if (remainder < MYRI10GE_ALLOC_SIZE)
1271                         rx_frags[i].size = remainder;
1272                 else
1273                         rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1274                 rx->cnt++;
1275                 idx = rx->cnt & rx->mask;
1276                 remainder -= MYRI10GE_ALLOC_SIZE;
1277         }
1278
1279         if (mgp->csum_flag && myri10ge_lro) {
1280                 rx_frags[0].page_offset += MXGEFW_PAD;
1281                 rx_frags[0].size -= MXGEFW_PAD;
1282                 len -= MXGEFW_PAD;
1283                 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
1284                                   /* opaque, will come back in get_frag_header */
1285                                   len, len,
1286                                   (void *)(__force unsigned long)csum, csum);
1287
1288                 return 1;
1289         }
1290
1291         hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1292
1293         /* allocate an skb to attach the page(s) to. This is done
1294          * after trying LRO, so as to avoid skb allocation overheads */
1295
1296         skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1297         if (unlikely(skb == NULL)) {
1298                 mgp->stats.rx_dropped++;
1299                 do {
1300                         i--;
1301                         put_page(rx_frags[i].page);
1302                 } while (i != 0);
1303                 return 0;
1304         }
1305
1306         /* Attach the pages to the skb, and trim off any padding */
1307         myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1308         if (skb_shinfo(skb)->frags[0].size <= 0) {
1309                 put_page(skb_shinfo(skb)->frags[0].page);
1310                 skb_shinfo(skb)->nr_frags = 0;
1311         }
1312         skb->protocol = eth_type_trans(skb, dev);
1313
1314         if (mgp->csum_flag) {
1315                 if ((skb->protocol == htons(ETH_P_IP)) ||
1316                     (skb->protocol == htons(ETH_P_IPV6))) {
1317                         skb->csum = csum;
1318                         skb->ip_summed = CHECKSUM_COMPLETE;
1319                 } else
1320                         myri10ge_vlan_ip_csum(skb, csum);
1321         }
1322         netif_receive_skb(skb);
1323         dev->last_rx = jiffies;
1324         return 1;
1325 }
1326
1327 static inline void
1328 myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
1329 {
1330         struct pci_dev *pdev = ss->mgp->pdev;
1331         struct myri10ge_tx_buf *tx = &ss->tx;
1332         struct sk_buff *skb;
1333         int idx, len;
1334
1335         while (tx->pkt_done != mcp_index) {
1336                 idx = tx->done & tx->mask;
1337                 skb = tx->info[idx].skb;
1338
1339                 /* Mark as free */
1340                 tx->info[idx].skb = NULL;
1341                 if (tx->info[idx].last) {
1342                         tx->pkt_done++;
1343                         tx->info[idx].last = 0;
1344                 }
1345                 tx->done++;
1346                 len = pci_unmap_len(&tx->info[idx], len);
1347                 pci_unmap_len_set(&tx->info[idx], len, 0);
1348                 if (skb) {
1349                         ss->stats.tx_bytes += skb->len;
1350                         ss->stats.tx_packets++;
1351                         dev_kfree_skb_irq(skb);
1352                         if (len)
1353                                 pci_unmap_single(pdev,
1354                                                  pci_unmap_addr(&tx->info[idx],
1355                                                                 bus), len,
1356                                                  PCI_DMA_TODEVICE);
1357                 } else {
1358                         if (len)
1359                                 pci_unmap_page(pdev,
1360                                                pci_unmap_addr(&tx->info[idx],
1361                                                               bus), len,
1362                                                PCI_DMA_TODEVICE);
1363                 }
1364         }
1365         /* start the queue if we've stopped it */
1366         if (netif_queue_stopped(ss->dev)
1367             && tx->req - tx->done < (tx->mask >> 1)) {
1368                 tx->wake_queue++;
1369                 netif_wake_queue(ss->dev);
1370         }
1371 }
1372
1373 static inline int
1374 myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
1375 {
1376         struct myri10ge_rx_done *rx_done = &ss->rx_done;
1377         struct myri10ge_priv *mgp = ss->mgp;
1378         unsigned long rx_bytes = 0;
1379         unsigned long rx_packets = 0;
1380         unsigned long rx_ok;
1381
1382         int idx = rx_done->idx;
1383         int cnt = rx_done->cnt;
1384         int work_done = 0;
1385         u16 length;
1386         __wsum checksum;
1387
1388         while (rx_done->entry[idx].length != 0 && work_done < budget) {
1389                 length = ntohs(rx_done->entry[idx].length);
1390                 rx_done->entry[idx].length = 0;
1391                 checksum = csum_unfold(rx_done->entry[idx].checksum);
1392                 if (length <= mgp->small_bytes)
1393                         rx_ok = myri10ge_rx_done(ss, &ss->rx_small,
1394                                                  mgp->small_bytes,
1395                                                  length, checksum);
1396                 else
1397                         rx_ok = myri10ge_rx_done(ss, &ss->rx_big,
1398                                                  mgp->big_bytes,
1399                                                  length, checksum);
1400                 rx_packets += rx_ok;
1401                 rx_bytes += rx_ok * (unsigned long)length;
1402                 cnt++;
1403                 idx = cnt & (mgp->max_intr_slots - 1);
1404                 work_done++;
1405         }
1406         rx_done->idx = idx;
1407         rx_done->cnt = cnt;
1408         ss->stats.rx_packets += rx_packets;
1409         ss->stats.rx_bytes += rx_bytes;
1410
1411         if (myri10ge_lro)
1412                 lro_flush_all(&rx_done->lro_mgr);
1413
1414         /* restock receive rings if needed */
1415         if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1416                 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1417                                         mgp->small_bytes + MXGEFW_PAD, 0);
1418         if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1419                 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1420
1421         return work_done;
1422 }
1423
1424 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1425 {
1426         struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
1427
1428         if (unlikely(stats->stats_updated)) {
1429                 unsigned link_up = ntohl(stats->link_up);
1430                 if (mgp->link_state != link_up) {
1431                         mgp->link_state = link_up;
1432
1433                         if (mgp->link_state == MXGEFW_LINK_UP) {
1434                                 if (netif_msg_link(mgp))
1435                                         printk(KERN_INFO
1436                                                "myri10ge: %s: link up\n",
1437                                                mgp->dev->name);
1438                                 netif_carrier_on(mgp->dev);
1439                                 mgp->link_changes++;
1440                         } else {
1441                                 if (netif_msg_link(mgp))
1442                                         printk(KERN_INFO
1443                                                "myri10ge: %s: link %s\n",
1444                                                mgp->dev->name,
1445                                                (link_up == MXGEFW_LINK_MYRINET ?
1446                                                 "mismatch (Myrinet detected)" :
1447                                                 "down"));
1448                                 netif_carrier_off(mgp->dev);
1449                                 mgp->link_changes++;
1450                         }
1451                 }
1452                 if (mgp->rdma_tags_available !=
1453                     ntohl(stats->rdma_tags_available)) {
1454                         mgp->rdma_tags_available =
1455                             ntohl(stats->rdma_tags_available);
1456                         printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1457                                "%d tags left\n", mgp->dev->name,
1458                                mgp->rdma_tags_available);
1459                 }
1460                 mgp->down_cnt += stats->link_down;
1461                 if (stats->link_down)
1462                         wake_up(&mgp->down_wq);
1463         }
1464 }
1465
1466 static int myri10ge_poll(struct napi_struct *napi, int budget)
1467 {
1468         struct myri10ge_slice_state *ss =
1469             container_of(napi, struct myri10ge_slice_state, napi);
1470         struct net_device *netdev = ss->mgp->dev;
1471         int work_done;
1472
1473 #ifdef CONFIG_DCA
1474         if (ss->mgp->dca_enabled)
1475                 myri10ge_update_dca(ss);
1476 #endif
1477
1478         /* process as many rx events as NAPI will allow */
1479         work_done = myri10ge_clean_rx_done(ss, budget);
1480
1481         if (work_done < budget) {
1482                 netif_rx_complete(netdev, napi);
1483                 put_be32(htonl(3), ss->irq_claim);
1484         }
1485         return work_done;
1486 }
1487
1488 static irqreturn_t myri10ge_intr(int irq, void *arg)
1489 {
1490         struct myri10ge_slice_state *ss = arg;
1491         struct myri10ge_priv *mgp = ss->mgp;
1492         struct mcp_irq_data *stats = ss->fw_stats;
1493         struct myri10ge_tx_buf *tx = &ss->tx;
1494         u32 send_done_count;
1495         int i;
1496
1497         /* an interrupt on a non-zero slice is implicitly valid
1498          * since MSI-X irqs are not shared */
1499         if (ss != mgp->ss) {
1500                 netif_rx_schedule(ss->dev, &ss->napi);
1501                 return (IRQ_HANDLED);
1502         }
1503
1504         /* make sure it is our IRQ, and that the DMA has finished */
1505         if (unlikely(!stats->valid))
1506                 return (IRQ_NONE);
1507
1508         /* low bit indicates receives are present, so schedule
1509          * napi poll handler */
1510         if (stats->valid & 1)
1511                 netif_rx_schedule(ss->dev, &ss->napi);
1512
1513         if (!mgp->msi_enabled && !mgp->msix_enabled) {
1514                 put_be32(0, mgp->irq_deassert);
1515                 if (!myri10ge_deassert_wait)
1516                         stats->valid = 0;
1517                 mb();
1518         } else
1519                 stats->valid = 0;
1520
1521         /* Wait for IRQ line to go low, if using INTx */
1522         i = 0;
1523         while (1) {
1524                 i++;
1525                 /* check for transmit completes and receives */
1526                 send_done_count = ntohl(stats->send_done_count);
1527                 if (send_done_count != tx->pkt_done)
1528                         myri10ge_tx_done(ss, (int)send_done_count);
1529                 if (unlikely(i > myri10ge_max_irq_loops)) {
1530                         printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1531                                mgp->dev->name);
1532                         stats->valid = 0;
1533                         schedule_work(&mgp->watchdog_work);
1534                 }
1535                 if (likely(stats->valid == 0))
1536                         break;
1537                 cpu_relax();
1538                 barrier();
1539         }
1540
1541         myri10ge_check_statblock(mgp);
1542
1543         put_be32(htonl(3), ss->irq_claim + 1);
1544         return (IRQ_HANDLED);
1545 }
1546
1547 static int
1548 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1549 {
1550         struct myri10ge_priv *mgp = netdev_priv(netdev);
1551         char *ptr;
1552         int i;
1553
1554         cmd->autoneg = AUTONEG_DISABLE;
1555         cmd->speed = SPEED_10000;
1556         cmd->duplex = DUPLEX_FULL;
1557
1558         /*
1559          * parse the product code to deterimine the interface type
1560          * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1561          * after the 3rd dash in the driver's cached copy of the
1562          * EEPROM's product code string.
1563          */
1564         ptr = mgp->product_code_string;
1565         if (ptr == NULL) {
1566                 printk(KERN_ERR "myri10ge: %s: Missing product code\n",
1567                        netdev->name);
1568                 return 0;
1569         }
1570         for (i = 0; i < 3; i++, ptr++) {
1571                 ptr = strchr(ptr, '-');
1572                 if (ptr == NULL) {
1573                         printk(KERN_ERR "myri10ge: %s: Invalid product "
1574                                "code %s\n", netdev->name,
1575                                mgp->product_code_string);
1576                         return 0;
1577                 }
1578         }
1579         if (*ptr == 'R' || *ptr == 'Q') {
1580                 /* We've found either an XFP or quad ribbon fiber */
1581                 cmd->port = PORT_FIBRE;
1582         }
1583         return 0;
1584 }
1585
1586 static void
1587 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1588 {
1589         struct myri10ge_priv *mgp = netdev_priv(netdev);
1590
1591         strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1592         strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1593         strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1594         strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1595 }
1596
1597 static int
1598 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1599 {
1600         struct myri10ge_priv *mgp = netdev_priv(netdev);
1601
1602         coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1603         return 0;
1604 }
1605
1606 static int
1607 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1608 {
1609         struct myri10ge_priv *mgp = netdev_priv(netdev);
1610
1611         mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1612         put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1613         return 0;
1614 }
1615
1616 static void
1617 myri10ge_get_pauseparam(struct net_device *netdev,
1618                         struct ethtool_pauseparam *pause)
1619 {
1620         struct myri10ge_priv *mgp = netdev_priv(netdev);
1621
1622         pause->autoneg = 0;
1623         pause->rx_pause = mgp->pause;
1624         pause->tx_pause = mgp->pause;
1625 }
1626
1627 static int
1628 myri10ge_set_pauseparam(struct net_device *netdev,
1629                         struct ethtool_pauseparam *pause)
1630 {
1631         struct myri10ge_priv *mgp = netdev_priv(netdev);
1632
1633         if (pause->tx_pause != mgp->pause)
1634                 return myri10ge_change_pause(mgp, pause->tx_pause);
1635         if (pause->rx_pause != mgp->pause)
1636                 return myri10ge_change_pause(mgp, pause->tx_pause);
1637         if (pause->autoneg != 0)
1638                 return -EINVAL;
1639         return 0;
1640 }
1641
1642 static void
1643 myri10ge_get_ringparam(struct net_device *netdev,
1644                        struct ethtool_ringparam *ring)
1645 {
1646         struct myri10ge_priv *mgp = netdev_priv(netdev);
1647
1648         ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1649         ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
1650         ring->rx_jumbo_max_pending = 0;
1651         ring->tx_max_pending = mgp->ss[0].rx_small.mask + 1;
1652         ring->rx_mini_pending = ring->rx_mini_max_pending;
1653         ring->rx_pending = ring->rx_max_pending;
1654         ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1655         ring->tx_pending = ring->tx_max_pending;
1656 }
1657
1658 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1659 {
1660         struct myri10ge_priv *mgp = netdev_priv(netdev);
1661
1662         if (mgp->csum_flag)
1663                 return 1;
1664         else
1665                 return 0;
1666 }
1667
1668 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1669 {
1670         struct myri10ge_priv *mgp = netdev_priv(netdev);
1671
1672         if (csum_enabled)
1673                 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1674         else
1675                 mgp->csum_flag = 0;
1676         return 0;
1677 }
1678
1679 static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1680 {
1681         struct myri10ge_priv *mgp = netdev_priv(netdev);
1682         unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1683
1684         if (tso_enabled)
1685                 netdev->features |= flags;
1686         else
1687                 netdev->features &= ~flags;
1688         return 0;
1689 }
1690
1691 static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
1692         "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1693         "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1694         "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1695         "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1696         "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1697         "tx_heartbeat_errors", "tx_window_errors",
1698         /* device-specific stats */
1699         "tx_boundary", "WC", "irq", "MSI", "MSIX",
1700         "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1701         "serial_number", "watchdog_resets",
1702 #ifdef CONFIG_DCA
1703         "dca_capable", "dca_enabled",
1704 #endif
1705         "link_changes", "link_up", "dropped_link_overflow",
1706         "dropped_link_error_or_filtered",
1707         "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1708         "dropped_unicast_filtered", "dropped_multicast_filtered",
1709         "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1710         "dropped_no_big_buffer"
1711 };
1712
1713 static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1714         "----------- slice ---------",
1715         "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1716         "rx_small_cnt", "rx_big_cnt",
1717         "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1718             "LRO flushed",
1719         "LRO avg aggr", "LRO no_desc"
1720 };
1721
1722 #define MYRI10GE_NET_STATS_LEN      21
1723 #define MYRI10GE_MAIN_STATS_LEN  ARRAY_SIZE(myri10ge_gstrings_main_stats)
1724 #define MYRI10GE_SLICE_STATS_LEN  ARRAY_SIZE(myri10ge_gstrings_slice_stats)
1725
1726 static void
1727 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1728 {
1729         struct myri10ge_priv *mgp = netdev_priv(netdev);
1730         int i;
1731
1732         switch (stringset) {
1733         case ETH_SS_STATS:
1734                 memcpy(data, *myri10ge_gstrings_main_stats,
1735                        sizeof(myri10ge_gstrings_main_stats));
1736                 data += sizeof(myri10ge_gstrings_main_stats);
1737                 for (i = 0; i < mgp->num_slices; i++) {
1738                         memcpy(data, *myri10ge_gstrings_slice_stats,
1739                                sizeof(myri10ge_gstrings_slice_stats));
1740                         data += sizeof(myri10ge_gstrings_slice_stats);
1741                 }
1742                 break;
1743         }
1744 }
1745
1746 static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
1747 {
1748         struct myri10ge_priv *mgp = netdev_priv(netdev);
1749
1750         switch (sset) {
1751         case ETH_SS_STATS:
1752                 return MYRI10GE_MAIN_STATS_LEN +
1753                     mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
1754         default:
1755                 return -EOPNOTSUPP;
1756         }
1757 }
1758
1759 static void
1760 myri10ge_get_ethtool_stats(struct net_device *netdev,
1761                            struct ethtool_stats *stats, u64 * data)
1762 {
1763         struct myri10ge_priv *mgp = netdev_priv(netdev);
1764         struct myri10ge_slice_state *ss;
1765         int slice;
1766         int i;
1767
1768         for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1769                 data[i] = ((unsigned long *)&mgp->stats)[i];
1770
1771         data[i++] = (unsigned int)mgp->tx_boundary;
1772         data[i++] = (unsigned int)mgp->wc_enabled;
1773         data[i++] = (unsigned int)mgp->pdev->irq;
1774         data[i++] = (unsigned int)mgp->msi_enabled;
1775         data[i++] = (unsigned int)mgp->msix_enabled;
1776         data[i++] = (unsigned int)mgp->read_dma;
1777         data[i++] = (unsigned int)mgp->write_dma;
1778         data[i++] = (unsigned int)mgp->read_write_dma;
1779         data[i++] = (unsigned int)mgp->serial_number;
1780         data[i++] = (unsigned int)mgp->watchdog_resets;
1781 #ifdef CONFIG_DCA
1782         data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1783         data[i++] = (unsigned int)(mgp->dca_enabled);
1784 #endif
1785         data[i++] = (unsigned int)mgp->link_changes;
1786
1787         /* firmware stats are useful only in the first slice */
1788         ss = &mgp->ss[0];
1789         data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1790         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
1791         data[i++] =
1792             (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1793         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1794         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1795         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1796         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
1797         data[i++] =
1798             (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1799         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1800         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1801         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1802         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1803
1804         for (slice = 0; slice < mgp->num_slices; slice++) {
1805                 ss = &mgp->ss[slice];
1806                 data[i++] = slice;
1807                 data[i++] = (unsigned int)ss->tx.pkt_start;
1808                 data[i++] = (unsigned int)ss->tx.pkt_done;
1809                 data[i++] = (unsigned int)ss->tx.req;
1810                 data[i++] = (unsigned int)ss->tx.done;
1811                 data[i++] = (unsigned int)ss->rx_small.cnt;
1812                 data[i++] = (unsigned int)ss->rx_big.cnt;
1813                 data[i++] = (unsigned int)ss->tx.wake_queue;
1814                 data[i++] = (unsigned int)ss->tx.stop_queue;
1815                 data[i++] = (unsigned int)ss->tx.linearized;
1816                 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1817                 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1818                 if (ss->rx_done.lro_mgr.stats.flushed)
1819                         data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1820                             ss->rx_done.lro_mgr.stats.flushed;
1821                 else
1822                         data[i++] = 0;
1823                 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1824         }
1825 }
1826
1827 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1828 {
1829         struct myri10ge_priv *mgp = netdev_priv(netdev);
1830         mgp->msg_enable = value;
1831 }
1832
1833 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1834 {
1835         struct myri10ge_priv *mgp = netdev_priv(netdev);
1836         return mgp->msg_enable;
1837 }
1838
1839 static const struct ethtool_ops myri10ge_ethtool_ops = {
1840         .get_settings = myri10ge_get_settings,
1841         .get_drvinfo = myri10ge_get_drvinfo,
1842         .get_coalesce = myri10ge_get_coalesce,
1843         .set_coalesce = myri10ge_set_coalesce,
1844         .get_pauseparam = myri10ge_get_pauseparam,
1845         .set_pauseparam = myri10ge_set_pauseparam,
1846         .get_ringparam = myri10ge_get_ringparam,
1847         .get_rx_csum = myri10ge_get_rx_csum,
1848         .set_rx_csum = myri10ge_set_rx_csum,
1849         .set_tx_csum = ethtool_op_set_tx_hw_csum,
1850         .set_sg = ethtool_op_set_sg,
1851         .set_tso = myri10ge_set_tso,
1852         .get_link = ethtool_op_get_link,
1853         .get_strings = myri10ge_get_strings,
1854         .get_sset_count = myri10ge_get_sset_count,
1855         .get_ethtool_stats = myri10ge_get_ethtool_stats,
1856         .set_msglevel = myri10ge_set_msglevel,
1857         .get_msglevel = myri10ge_get_msglevel
1858 };
1859
1860 static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
1861 {
1862         struct myri10ge_priv *mgp = ss->mgp;
1863         struct myri10ge_cmd cmd;
1864         struct net_device *dev = mgp->dev;
1865         int tx_ring_size, rx_ring_size;
1866         int tx_ring_entries, rx_ring_entries;
1867         int i, slice, status;
1868         size_t bytes;
1869
1870         /* get ring sizes */
1871         slice = ss - mgp->ss;
1872         cmd.data0 = slice;
1873         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1874         tx_ring_size = cmd.data0;
1875         cmd.data0 = slice;
1876         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1877         if (status != 0)
1878                 return status;
1879         rx_ring_size = cmd.data0;
1880
1881         tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1882         rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1883         ss->tx.mask = tx_ring_entries - 1;
1884         ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
1885
1886         status = -ENOMEM;
1887
1888         /* allocate the host shadow rings */
1889
1890         bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1891             * sizeof(*ss->tx.req_list);
1892         ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1893         if (ss->tx.req_bytes == NULL)
1894                 goto abort_with_nothing;
1895
1896         /* ensure req_list entries are aligned to 8 bytes */
1897         ss->tx.req_list = (struct mcp_kreq_ether_send *)
1898             ALIGN((unsigned long)ss->tx.req_bytes, 8);
1899
1900         bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1901         ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1902         if (ss->rx_small.shadow == NULL)
1903                 goto abort_with_tx_req_bytes;
1904
1905         bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1906         ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1907         if (ss->rx_big.shadow == NULL)
1908                 goto abort_with_rx_small_shadow;
1909
1910         /* allocate the host info rings */
1911
1912         bytes = tx_ring_entries * sizeof(*ss->tx.info);
1913         ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1914         if (ss->tx.info == NULL)
1915                 goto abort_with_rx_big_shadow;
1916
1917         bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1918         ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1919         if (ss->rx_small.info == NULL)
1920                 goto abort_with_tx_info;
1921
1922         bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1923         ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1924         if (ss->rx_big.info == NULL)
1925                 goto abort_with_rx_small_info;
1926
1927         /* Fill the receive rings */
1928         ss->rx_big.cnt = 0;
1929         ss->rx_small.cnt = 0;
1930         ss->rx_big.fill_cnt = 0;
1931         ss->rx_small.fill_cnt = 0;
1932         ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1933         ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1934         ss->rx_small.watchdog_needed = 0;
1935         ss->rx_big.watchdog_needed = 0;
1936         myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1937                                 mgp->small_bytes + MXGEFW_PAD, 0);
1938
1939         if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
1940                 printk(KERN_ERR
1941                        "myri10ge: %s:slice-%d: alloced only %d small bufs\n",
1942                        dev->name, slice, ss->rx_small.fill_cnt);
1943                 goto abort_with_rx_small_ring;
1944         }
1945
1946         myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1947         if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
1948                 printk(KERN_ERR
1949                        "myri10ge: %s:slice-%d: alloced only %d big bufs\n",
1950                        dev->name, slice, ss->rx_big.fill_cnt);
1951                 goto abort_with_rx_big_ring;
1952         }
1953
1954         return 0;
1955
1956 abort_with_rx_big_ring:
1957         for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
1958                 int idx = i & ss->rx_big.mask;
1959                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
1960                                        mgp->big_bytes);
1961                 put_page(ss->rx_big.info[idx].page);
1962         }
1963
1964 abort_with_rx_small_ring:
1965         for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
1966                 int idx = i & ss->rx_small.mask;
1967                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
1968                                        mgp->small_bytes + MXGEFW_PAD);
1969                 put_page(ss->rx_small.info[idx].page);
1970         }
1971
1972         kfree(ss->rx_big.info);
1973
1974 abort_with_rx_small_info:
1975         kfree(ss->rx_small.info);
1976
1977 abort_with_tx_info:
1978         kfree(ss->tx.info);
1979
1980 abort_with_rx_big_shadow:
1981         kfree(ss->rx_big.shadow);
1982
1983 abort_with_rx_small_shadow:
1984         kfree(ss->rx_small.shadow);
1985
1986 abort_with_tx_req_bytes:
1987         kfree(ss->tx.req_bytes);
1988         ss->tx.req_bytes = NULL;
1989         ss->tx.req_list = NULL;
1990
1991 abort_with_nothing:
1992         return status;
1993 }
1994
1995 static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
1996 {
1997         struct myri10ge_priv *mgp = ss->mgp;
1998         struct sk_buff *skb;
1999         struct myri10ge_tx_buf *tx;
2000         int i, len, idx;
2001
2002         /* If not allocated, skip it */
2003         if (ss->tx.req_list == NULL)
2004                 return;
2005
2006         for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2007                 idx = i & ss->rx_big.mask;
2008                 if (i == ss->rx_big.fill_cnt - 1)
2009                         ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2010                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2011                                        mgp->big_bytes);
2012                 put_page(ss->rx_big.info[idx].page);
2013         }
2014
2015         for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2016                 idx = i & ss->rx_small.mask;
2017                 if (i == ss->rx_small.fill_cnt - 1)
2018                         ss->rx_small.info[idx].page_offset =
2019                             MYRI10GE_ALLOC_SIZE;
2020                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2021                                        mgp->small_bytes + MXGEFW_PAD);
2022                 put_page(ss->rx_small.info[idx].page);
2023         }
2024         tx = &ss->tx;
2025         while (tx->done != tx->req) {
2026                 idx = tx->done & tx->mask;
2027                 skb = tx->info[idx].skb;
2028
2029                 /* Mark as free */
2030                 tx->info[idx].skb = NULL;
2031                 tx->done++;
2032                 len = pci_unmap_len(&tx->info[idx], len);
2033                 pci_unmap_len_set(&tx->info[idx], len, 0);
2034                 if (skb) {
2035                         ss->stats.tx_dropped++;
2036                         dev_kfree_skb_any(skb);
2037                         if (len)
2038                                 pci_unmap_single(mgp->pdev,
2039                                                  pci_unmap_addr(&tx->info[idx],
2040                                                                 bus), len,
2041                                                  PCI_DMA_TODEVICE);
2042                 } else {
2043                         if (len)
2044                                 pci_unmap_page(mgp->pdev,
2045                                                pci_unmap_addr(&tx->info[idx],
2046                                                               bus), len,
2047                                                PCI_DMA_TODEVICE);
2048                 }
2049         }
2050         kfree(ss->rx_big.info);
2051
2052         kfree(ss->rx_small.info);
2053
2054         kfree(ss->tx.info);
2055
2056         kfree(ss->rx_big.shadow);
2057
2058         kfree(ss->rx_small.shadow);
2059
2060         kfree(ss->tx.req_bytes);
2061         ss->tx.req_bytes = NULL;
2062         ss->tx.req_list = NULL;
2063 }
2064
2065 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2066 {
2067         struct pci_dev *pdev = mgp->pdev;
2068         struct myri10ge_slice_state *ss;
2069         struct net_device *netdev = mgp->dev;
2070         int i;
2071         int status;
2072
2073         mgp->msi_enabled = 0;
2074         mgp->msix_enabled = 0;
2075         status = 0;
2076         if (myri10ge_msi) {
2077                 if (mgp->num_slices > 1) {
2078                         status =
2079                             pci_enable_msix(pdev, mgp->msix_vectors,
2080                                             mgp->num_slices);
2081                         if (status == 0) {
2082                                 mgp->msix_enabled = 1;
2083                         } else {
2084                                 dev_err(&pdev->dev,
2085                                         "Error %d setting up MSI-X\n", status);
2086                                 return status;
2087                         }
2088                 }
2089                 if (mgp->msix_enabled == 0) {
2090                         status = pci_enable_msi(pdev);
2091                         if (status != 0) {
2092                                 dev_err(&pdev->dev,
2093                                         "Error %d setting up MSI; falling back to xPIC\n",
2094                                         status);
2095                         } else {
2096                                 mgp->msi_enabled = 1;
2097                         }
2098                 }
2099         }
2100         if (mgp->msix_enabled) {
2101                 for (i = 0; i < mgp->num_slices; i++) {
2102                         ss = &mgp->ss[i];
2103                         snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2104                                  "%s:slice-%d", netdev->name, i);
2105                         status = request_irq(mgp->msix_vectors[i].vector,
2106                                              myri10ge_intr, 0, ss->irq_desc,
2107                                              ss);
2108                         if (status != 0) {
2109                                 dev_err(&pdev->dev,
2110                                         "slice %d failed to allocate IRQ\n", i);
2111                                 i--;
2112                                 while (i >= 0) {
2113                                         free_irq(mgp->msix_vectors[i].vector,
2114                                                  &mgp->ss[i]);
2115                                         i--;
2116                                 }
2117                                 pci_disable_msix(pdev);
2118                                 return status;
2119                         }
2120                 }
2121         } else {
2122                 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2123                                      mgp->dev->name, &mgp->ss[0]);
2124                 if (status != 0) {
2125                         dev_err(&pdev->dev, "failed to allocate IRQ\n");
2126                         if (mgp->msi_enabled)
2127                                 pci_disable_msi(pdev);
2128                 }
2129         }
2130         return status;
2131 }
2132
2133 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2134 {
2135         struct pci_dev *pdev = mgp->pdev;
2136         int i;
2137
2138         if (mgp->msix_enabled) {
2139                 for (i = 0; i < mgp->num_slices; i++)
2140                         free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2141         } else {
2142                 free_irq(pdev->irq, &mgp->ss[0]);
2143         }
2144         if (mgp->msi_enabled)
2145                 pci_disable_msi(pdev);
2146         if (mgp->msix_enabled)
2147                 pci_disable_msix(pdev);
2148 }
2149
2150 static int
2151 myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
2152                          void **ip_hdr, void **tcpudp_hdr,
2153                          u64 * hdr_flags, void *priv)
2154 {
2155         struct ethhdr *eh;
2156         struct vlan_ethhdr *veh;
2157         struct iphdr *iph;
2158         u8 *va = page_address(frag->page) + frag->page_offset;
2159         unsigned long ll_hlen;
2160         /* passed opaque through lro_receive_frags() */
2161         __wsum csum = (__force __wsum) (unsigned long)priv;
2162
2163         /* find the mac header, aborting if not IPv4 */
2164
2165         eh = (struct ethhdr *)va;
2166         *mac_hdr = eh;
2167         ll_hlen = ETH_HLEN;
2168         if (eh->h_proto != htons(ETH_P_IP)) {
2169                 if (eh->h_proto == htons(ETH_P_8021Q)) {
2170                         veh = (struct vlan_ethhdr *)va;
2171                         if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
2172                                 return -1;
2173
2174                         ll_hlen += VLAN_HLEN;
2175
2176                         /*
2177                          *  HW checksum starts ETH_HLEN bytes into
2178                          *  frame, so we must subtract off the VLAN
2179                          *  header's checksum before csum can be used
2180                          */
2181                         csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
2182                                                            VLAN_HLEN, 0));
2183                 } else {
2184                         return -1;
2185                 }
2186         }
2187         *hdr_flags = LRO_IPV4;
2188
2189         iph = (struct iphdr *)(va + ll_hlen);
2190         *ip_hdr = iph;
2191         if (iph->protocol != IPPROTO_TCP)
2192                 return -1;
2193         *hdr_flags |= LRO_TCP;
2194         *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
2195
2196         /* verify the IP checksum */
2197         if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
2198                 return -1;
2199
2200         /* verify the  checksum */
2201         if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
2202                                        ntohs(iph->tot_len) - (iph->ihl << 2),
2203                                        IPPROTO_TCP, csum)))
2204                 return -1;
2205
2206         return 0;
2207 }
2208
2209 static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2210 {
2211         struct myri10ge_cmd cmd;
2212         struct myri10ge_slice_state *ss;
2213         int status;
2214
2215         ss = &mgp->ss[slice];
2216         cmd.data0 = 0;          /* single slice for now */
2217         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
2218         ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2219             (mgp->sram + cmd.data0);
2220
2221         cmd.data0 = slice;
2222         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2223                                     &cmd, 0);
2224         ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2225             (mgp->sram + cmd.data0);
2226
2227         cmd.data0 = slice;
2228         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2229         ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2230             (mgp->sram + cmd.data0);
2231
2232         if (myri10ge_wcfifo && mgp->wc_enabled) {
2233                 ss->tx.wc_fifo = (u8 __iomem *)
2234                     mgp->sram + MXGEFW_ETH_SEND_4 + 64 * slice;
2235                 ss->rx_small.wc_fifo = (u8 __iomem *)
2236                     mgp->sram + MXGEFW_ETH_RECV_SMALL + 64 * slice;
2237                 ss->rx_big.wc_fifo = (u8 __iomem *)
2238                     mgp->sram + MXGEFW_ETH_RECV_BIG + 64 * slice;
2239         } else {
2240                 ss->tx.wc_fifo = NULL;
2241                 ss->rx_small.wc_fifo = NULL;
2242                 ss->rx_big.wc_fifo = NULL;
2243         }
2244         return status;
2245
2246 }
2247
2248 static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2249 {
2250         struct myri10ge_cmd cmd;
2251         struct myri10ge_slice_state *ss;
2252         int status;
2253
2254         ss = &mgp->ss[slice];
2255         cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2256         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
2257         cmd.data2 = sizeof(struct mcp_irq_data);
2258         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2259         if (status == -ENOSYS) {
2260                 dma_addr_t bus = ss->fw_stats_bus;
2261                 if (slice != 0)
2262                         return -EINVAL;
2263                 bus += offsetof(struct mcp_irq_data, send_done_count);
2264                 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2265                 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2266                 status = myri10ge_send_cmd(mgp,
2267                                            MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2268                                            &cmd, 0);
2269                 /* Firmware cannot support multicast without STATS_DMA_V2 */
2270                 mgp->fw_multicast_support = 0;
2271         } else {
2272                 mgp->fw_multicast_support = 1;
2273         }
2274         return 0;
2275 }
2276
2277 static int myri10ge_open(struct net_device *dev)
2278 {
2279         struct myri10ge_slice_state *ss;
2280         struct myri10ge_priv *mgp = netdev_priv(dev);
2281         struct myri10ge_cmd cmd;
2282         int i, status, big_pow2, slice;
2283         u8 *itable;
2284         struct net_lro_mgr *lro_mgr;
2285
2286         if (mgp->running != MYRI10GE_ETH_STOPPED)
2287                 return -EBUSY;
2288
2289         mgp->running = MYRI10GE_ETH_STARTING;
2290         status = myri10ge_reset(mgp);
2291         if (status != 0) {
2292                 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
2293                 goto abort_with_nothing;
2294         }
2295
2296         if (mgp->num_slices > 1) {
2297                 cmd.data0 = mgp->num_slices;
2298                 cmd.data1 = 1;  /* use MSI-X */
2299                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2300                                            &cmd, 0);
2301                 if (status != 0) {
2302                         printk(KERN_ERR
2303                                "myri10ge: %s: failed to set number of slices\n",
2304                                dev->name);
2305                         goto abort_with_nothing;
2306                 }
2307                 /* setup the indirection table */
2308                 cmd.data0 = mgp->num_slices;
2309                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2310                                            &cmd, 0);
2311
2312                 status |= myri10ge_send_cmd(mgp,
2313                                             MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2314                                             &cmd, 0);
2315                 if (status != 0) {
2316                         printk(KERN_ERR
2317                                "myri10ge: %s: failed to setup rss tables\n",
2318                                dev->name);
2319                 }
2320
2321                 /* just enable an identity mapping */
2322                 itable = mgp->sram + cmd.data0;
2323                 for (i = 0; i < mgp->num_slices; i++)
2324                         __raw_writeb(i, &itable[i]);
2325
2326                 cmd.data0 = 1;
2327                 cmd.data1 = myri10ge_rss_hash;
2328                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2329                                            &cmd, 0);
2330                 if (status != 0) {
2331                         printk(KERN_ERR
2332                                "myri10ge: %s: failed to enable slices\n",
2333                                dev->name);
2334                         goto abort_with_nothing;
2335                 }
2336         }
2337
2338         status = myri10ge_request_irq(mgp);
2339         if (status != 0)
2340                 goto abort_with_nothing;
2341
2342         /* decide what small buffer size to use.  For good TCP rx
2343          * performance, it is important to not receive 1514 byte
2344          * frames into jumbo buffers, as it confuses the socket buffer
2345          * accounting code, leading to drops and erratic performance.
2346          */
2347
2348         if (dev->mtu <= ETH_DATA_LEN)
2349                 /* enough for a TCP header */
2350                 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2351                     ? (128 - MXGEFW_PAD)
2352                     : (SMP_CACHE_BYTES - MXGEFW_PAD);
2353         else
2354                 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2355                 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
2356
2357         /* Override the small buffer size? */
2358         if (myri10ge_small_bytes > 0)
2359                 mgp->small_bytes = myri10ge_small_bytes;
2360
2361         /* Firmware needs the big buff size as a power of 2.  Lie and
2362          * tell him the buffer is larger, because we only use 1
2363          * buffer/pkt, and the mtu will prevent overruns.
2364          */
2365         big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2366         if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
2367                 while (!is_power_of_2(big_pow2))
2368                         big_pow2++;
2369                 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2370         } else {
2371                 big_pow2 = MYRI10GE_ALLOC_SIZE;
2372                 mgp->big_bytes = big_pow2;
2373         }
2374
2375         /* setup the per-slice data structures */
2376         for (slice = 0; slice < mgp->num_slices; slice++) {
2377                 ss = &mgp->ss[slice];
2378
2379                 status = myri10ge_get_txrx(mgp, slice);
2380                 if (status != 0) {
2381                         printk(KERN_ERR
2382                                "myri10ge: %s: failed to get ring sizes or locations\n",
2383                                dev->name);
2384                         goto abort_with_rings;
2385                 }
2386                 status = myri10ge_allocate_rings(ss);
2387                 if (status != 0)
2388                         goto abort_with_rings;
2389                 if (slice == 0)
2390                         status = myri10ge_set_stats(mgp, slice);
2391                 if (status) {
2392                         printk(KERN_ERR
2393                                "myri10ge: %s: Couldn't set stats DMA\n",
2394                                dev->name);
2395                         goto abort_with_rings;
2396                 }
2397
2398                 lro_mgr = &ss->rx_done.lro_mgr;
2399                 lro_mgr->dev = dev;
2400                 lro_mgr->features = LRO_F_NAPI;
2401                 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2402                 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2403                 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2404                 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2405                 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2406                 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
2407                 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2408                         lro_mgr->max_aggr = MAX_SKB_FRAGS;
2409
2410                 /* must happen prior to any irq */
2411                 napi_enable(&(ss)->napi);
2412         }
2413
2414         /* now give firmware buffers sizes, and MTU */
2415         cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2416         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2417         cmd.data0 = mgp->small_bytes;
2418         status |=
2419             myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2420         cmd.data0 = big_pow2;
2421         status |=
2422             myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2423         if (status) {
2424                 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
2425                        dev->name);
2426                 goto abort_with_rings;
2427         }
2428
2429         /*
2430          * Set Linux style TSO mode; this is needed only on newer
2431          *  firmware versions.  Older versions default to Linux
2432          *  style TSO
2433          */
2434         cmd.data0 = 0;
2435         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2436         if (status && status != -ENOSYS) {
2437                 printk(KERN_ERR "myri10ge: %s: Couldn't set TSO mode\n",
2438                        dev->name);
2439                 goto abort_with_rings;
2440         }
2441
2442         mgp->link_state = ~0U;
2443         mgp->rdma_tags_available = 15;
2444
2445         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2446         if (status) {
2447                 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
2448                        dev->name);
2449                 goto abort_with_rings;
2450         }
2451
2452         mgp->running = MYRI10GE_ETH_RUNNING;
2453         mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2454         add_timer(&mgp->watchdog_timer);
2455         netif_wake_queue(dev);
2456         return 0;
2457
2458 abort_with_rings:
2459         for (i = 0; i < mgp->num_slices; i++)
2460                 myri10ge_free_rings(&mgp->ss[i]);
2461
2462         myri10ge_free_irq(mgp);
2463
2464 abort_with_nothing:
2465         mgp->running = MYRI10GE_ETH_STOPPED;
2466         return -ENOMEM;
2467 }
2468
2469 static int myri10ge_close(struct net_device *dev)
2470 {
2471         struct myri10ge_priv *mgp = netdev_priv(dev);
2472         struct myri10ge_cmd cmd;
2473         int status, old_down_cnt;
2474         int i;
2475
2476         if (mgp->running != MYRI10GE_ETH_RUNNING)
2477                 return 0;
2478
2479         if (mgp->ss[0].tx.req_bytes == NULL)
2480                 return 0;
2481
2482         del_timer_sync(&mgp->watchdog_timer);
2483         mgp->running = MYRI10GE_ETH_STOPPING;
2484         for (i = 0; i < mgp->num_slices; i++) {
2485                 napi_disable(&mgp->ss[i].napi);
2486         }
2487         netif_carrier_off(dev);
2488         netif_stop_queue(dev);
2489         old_down_cnt = mgp->down_cnt;
2490         mb();
2491         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2492         if (status)
2493                 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2494                        dev->name);
2495
2496         wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2497         if (old_down_cnt == mgp->down_cnt)
2498                 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2499
2500         netif_tx_disable(dev);
2501         myri10ge_free_irq(mgp);
2502         for (i = 0; i < mgp->num_slices; i++)
2503                 myri10ge_free_rings(&mgp->ss[i]);
2504
2505         mgp->running = MYRI10GE_ETH_STOPPED;
2506         return 0;
2507 }
2508
2509 /* copy an array of struct mcp_kreq_ether_send's to the mcp.  Copy
2510  * backwards one at a time and handle ring wraps */
2511
2512 static inline void
2513 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2514                               struct mcp_kreq_ether_send *src, int cnt)
2515 {
2516         int idx, starting_slot;
2517         starting_slot = tx->req;
2518         while (cnt > 1) {
2519                 cnt--;
2520                 idx = (starting_slot + cnt) & tx->mask;
2521                 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2522                 mb();
2523         }
2524 }
2525
2526 /*
2527  * copy an array of struct mcp_kreq_ether_send's to the mcp.  Copy
2528  * at most 32 bytes at a time, so as to avoid involving the software
2529  * pio handler in the nic.   We re-write the first segment's flags
2530  * to mark them valid only after writing the entire chain.
2531  */
2532
2533 static inline void
2534 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2535                     int cnt)
2536 {
2537         int idx, i;
2538         struct mcp_kreq_ether_send __iomem *dstp, *dst;
2539         struct mcp_kreq_ether_send *srcp;
2540         u8 last_flags;
2541
2542         idx = tx->req & tx->mask;
2543
2544         last_flags = src->flags;
2545         src->flags = 0;
2546         mb();
2547         dst = dstp = &tx->lanai[idx];
2548         srcp = src;
2549
2550         if ((idx + cnt) < tx->mask) {
2551                 for (i = 0; i < (cnt - 1); i += 2) {
2552                         myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2553                         mb();   /* force write every 32 bytes */
2554                         srcp += 2;
2555                         dstp += 2;
2556                 }
2557         } else {
2558                 /* submit all but the first request, and ensure
2559                  * that it is submitted below */
2560                 myri10ge_submit_req_backwards(tx, src, cnt);
2561                 i = 0;
2562         }
2563         if (i < cnt) {
2564                 /* submit the first request */
2565                 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2566                 mb();           /* barrier before setting valid flag */
2567         }
2568
2569         /* re-write the last 32-bits with the valid flags */
2570         src->flags = last_flags;
2571         put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
2572         tx->req += cnt;
2573         mb();
2574 }
2575
2576 static inline void
2577 myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
2578                        struct mcp_kreq_ether_send *src, int cnt)
2579 {
2580         tx->req += cnt;
2581         mb();
2582         while (cnt >= 4) {
2583                 myri10ge_pio_copy(tx->wc_fifo, src, 64);
2584                 mb();
2585                 src += 4;
2586                 cnt -= 4;
2587         }
2588         if (cnt > 0) {
2589                 /* pad it to 64 bytes.  The src is 64 bytes bigger than it
2590                  * needs to be so that we don't overrun it */
2591                 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
2592                                   src, 64);
2593                 mb();
2594         }
2595 }
2596
2597 /*
2598  * Transmit a packet.  We need to split the packet so that a single
2599  * segment does not cross myri10ge->tx_boundary, so this makes segment
2600  * counting tricky.  So rather than try to count segments up front, we
2601  * just give up if there are too few segments to hold a reasonably
2602  * fragmented packet currently available.  If we run
2603  * out of segments while preparing a packet for DMA, we just linearize
2604  * it and try again.
2605  */
2606
2607 static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2608 {
2609         struct myri10ge_priv *mgp = netdev_priv(dev);
2610         struct myri10ge_slice_state *ss;
2611         struct mcp_kreq_ether_send *req;
2612         struct myri10ge_tx_buf *tx;
2613         struct skb_frag_struct *frag;
2614         dma_addr_t bus;
2615         u32 low;
2616         __be32 high_swapped;
2617         unsigned int len;
2618         int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2619         u16 pseudo_hdr_offset, cksum_offset;
2620         int cum_len, seglen, boundary, rdma_count;
2621         u8 flags, odd_flag;
2622
2623         /* always transmit through slot 0 */
2624         ss = mgp->ss;
2625         tx = &ss->tx;
2626 again:
2627         req = tx->req_list;
2628         avail = tx->mask - 1 - (tx->req - tx->done);
2629
2630         mss = 0;
2631         max_segments = MXGEFW_MAX_SEND_DESC;
2632
2633         if (skb_is_gso(skb)) {
2634                 mss = skb_shinfo(skb)->gso_size;
2635                 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
2636         }
2637
2638         if ((unlikely(avail < max_segments))) {
2639                 /* we are out of transmit resources */
2640                 tx->stop_queue++;
2641                 netif_stop_queue(dev);
2642                 return 1;
2643         }
2644
2645         /* Setup checksum offloading, if needed */
2646         cksum_offset = 0;
2647         pseudo_hdr_offset = 0;
2648         odd_flag = 0;
2649         flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
2650         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2651                 cksum_offset = skb_transport_offset(skb);
2652                 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
2653                 /* If the headers are excessively large, then we must
2654                  * fall back to a software checksum */
2655                 if (unlikely(!mss && (cksum_offset > 255 ||
2656                                       pseudo_hdr_offset > 127))) {
2657                         if (skb_checksum_help(skb))
2658                                 goto drop;
2659                         cksum_offset = 0;
2660                         pseudo_hdr_offset = 0;
2661                 } else {
2662                         odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2663                         flags |= MXGEFW_FLAGS_CKSUM;
2664                 }
2665         }
2666
2667         cum_len = 0;
2668
2669         if (mss) {              /* TSO */
2670                 /* this removes any CKSUM flag from before */
2671                 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2672
2673                 /* negative cum_len signifies to the
2674                  * send loop that we are still in the
2675                  * header portion of the TSO packet.
2676                  * TSO header can be at most 1KB long */
2677                 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
2678
2679                 /* for IPv6 TSO, the checksum offset stores the
2680                  * TCP header length, to save the firmware from
2681                  * the need to parse the headers */
2682                 if (skb_is_gso_v6(skb)) {
2683                         cksum_offset = tcp_hdrlen(skb);
2684                         /* Can only handle headers <= max_tso6 long */
2685                         if (unlikely(-cum_len > mgp->max_tso6))
2686                                 return myri10ge_sw_tso(skb, dev);
2687                 }
2688                 /* for TSO, pseudo_hdr_offset holds mss.
2689                  * The firmware figures out where to put
2690                  * the checksum by parsing the header. */
2691                 pseudo_hdr_offset = mss;
2692         } else
2693                 /* Mark small packets, and pad out tiny packets */
2694         if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2695                 flags |= MXGEFW_FLAGS_SMALL;
2696
2697                 /* pad frames to at least ETH_ZLEN bytes */
2698                 if (unlikely(skb->len < ETH_ZLEN)) {
2699                         if (skb_padto(skb, ETH_ZLEN)) {
2700                                 /* The packet is gone, so we must
2701                                  * return 0 */
2702                                 ss->stats.tx_dropped += 1;
2703                                 return 0;
2704                         }
2705                         /* adjust the len to account for the zero pad
2706                          * so that the nic can know how long it is */
2707                         skb->len = ETH_ZLEN;
2708                 }
2709         }
2710
2711         /* map the skb for DMA */
2712         len = skb->len - skb->data_len;
2713         idx = tx->req & tx->mask;
2714         tx->info[idx].skb = skb;
2715         bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2716         pci_unmap_addr_set(&tx->info[idx], bus, bus);
2717         pci_unmap_len_set(&tx->info[idx], len, len);
2718
2719         frag_cnt = skb_shinfo(skb)->nr_frags;
2720         frag_idx = 0;
2721         count = 0;
2722         rdma_count = 0;
2723
2724         /* "rdma_count" is the number of RDMAs belonging to the
2725          * current packet BEFORE the current send request. For
2726          * non-TSO packets, this is equal to "count".
2727          * For TSO packets, rdma_count needs to be reset
2728          * to 0 after a segment cut.
2729          *
2730          * The rdma_count field of the send request is
2731          * the number of RDMAs of the packet starting at
2732          * that request. For TSO send requests with one ore more cuts
2733          * in the middle, this is the number of RDMAs starting
2734          * after the last cut in the request. All previous
2735          * segments before the last cut implicitly have 1 RDMA.
2736          *
2737          * Since the number of RDMAs is not known beforehand,
2738          * it must be filled-in retroactively - after each
2739          * segmentation cut or at the end of the entire packet.
2740          */
2741
2742         while (1) {
2743                 /* Break the SKB or Fragment up into pieces which
2744                  * do not cross mgp->tx_boundary */
2745                 low = MYRI10GE_LOWPART_TO_U32(bus);
2746                 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2747                 while (len) {
2748                         u8 flags_next;
2749                         int cum_len_next;
2750
2751                         if (unlikely(count == max_segments))
2752                                 goto abort_linearize;
2753
2754                         boundary =
2755                             (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
2756                         seglen = boundary - low;
2757                         if (seglen > len)
2758                                 seglen = len;
2759                         flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2760                         cum_len_next = cum_len + seglen;
2761                         if (mss) {      /* TSO */
2762                                 (req - rdma_count)->rdma_count = rdma_count + 1;
2763
2764                                 if (likely(cum_len >= 0)) {     /* payload */
2765                                         int next_is_first, chop;
2766
2767                                         chop = (cum_len_next > mss);
2768                                         cum_len_next = cum_len_next % mss;
2769                                         next_is_first = (cum_len_next == 0);
2770                                         flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2771                                         flags_next |= next_is_first *
2772                                             MXGEFW_FLAGS_FIRST;
2773                                         rdma_count |= -(chop | next_is_first);
2774                                         rdma_count += chop & !next_is_first;
2775                                 } else if (likely(cum_len_next >= 0)) { /* header ends */
2776                                         int small;
2777
2778                                         rdma_count = -1;
2779                                         cum_len_next = 0;
2780                                         seglen = -cum_len;
2781                                         small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2782                                         flags_next = MXGEFW_FLAGS_TSO_PLD |
2783                                             MXGEFW_FLAGS_FIRST |
2784                                             (small * MXGEFW_FLAGS_SMALL);
2785                                 }
2786                         }
2787                         req->addr_high = high_swapped;
2788                         req->addr_low = htonl(low);
2789                         req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2790                         req->pad = 0;   /* complete solid 16-byte block; does this matter? */
2791                         req->rdma_count = 1;
2792                         req->length = htons(seglen);
2793                         req->cksum_offset = cksum_offset;
2794                         req->flags = flags | ((cum_len & 1) * odd_flag);
2795
2796                         low += seglen;
2797                         len -= seglen;
2798                         cum_len = cum_len_next;
2799                         flags = flags_next;
2800                         req++;
2801                         count++;
2802                         rdma_count++;
2803                         if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2804                                 if (unlikely(cksum_offset > seglen))
2805                                         cksum_offset -= seglen;
2806                                 else
2807                                         cksum_offset = 0;
2808                         }
2809                 }
2810                 if (frag_idx == frag_cnt)
2811                         break;
2812
2813                 /* map next fragment for DMA */
2814                 idx = (count + tx->req) & tx->mask;
2815                 frag = &skb_shinfo(skb)->frags[frag_idx];
2816                 frag_idx++;
2817                 len = frag->size;
2818                 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2819                                    len, PCI_DMA_TODEVICE);
2820                 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2821                 pci_unmap_len_set(&tx->info[idx], len, len);
2822         }
2823
2824         (req - rdma_count)->rdma_count = rdma_count;
2825         if (mss)
2826                 do {
2827                         req--;
2828                         req->flags |= MXGEFW_FLAGS_TSO_LAST;
2829                 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2830                                          MXGEFW_FLAGS_FIRST)));
2831         idx = ((count - 1) + tx->req) & tx->mask;
2832         tx->info[idx].last = 1;
2833         if (tx->wc_fifo == NULL)
2834                 myri10ge_submit_req(tx, tx->req_list, count);
2835         else
2836                 myri10ge_submit_req_wc(tx, tx->req_list, count);
2837         tx->pkt_start++;
2838         if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2839                 tx->stop_queue++;
2840                 netif_stop_queue(dev);
2841         }
2842         dev->trans_start = jiffies;
2843         return 0;
2844
2845 abort_linearize:
2846         /* Free any DMA resources we've alloced and clear out the skb
2847          * slot so as to not trip up assertions, and to avoid a
2848          * double-free if linearizing fails */
2849
2850         last_idx = (idx + 1) & tx->mask;
2851         idx = tx->req & tx->mask;
2852         tx->info[idx].skb = NULL;
2853         do {
2854                 len = pci_unmap_len(&tx->info[idx], len);
2855                 if (len) {
2856                         if (tx->info[idx].skb != NULL)
2857                                 pci_unmap_single(mgp->pdev,
2858                                                  pci_unmap_addr(&tx->info[idx],
2859                                                                 bus), len,
2860                                                  PCI_DMA_TODEVICE);
2861                         else
2862                                 pci_unmap_page(mgp->pdev,
2863                                                pci_unmap_addr(&tx->info[idx],
2864                                                               bus), len,
2865                                                PCI_DMA_TODEVICE);
2866                         pci_unmap_len_set(&tx->info[idx], len, 0);
2867                         tx->info[idx].skb = NULL;
2868                 }
2869                 idx = (idx + 1) & tx->mask;
2870         } while (idx != last_idx);
2871         if (skb_is_gso(skb)) {
2872                 printk(KERN_ERR
2873                        "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2874                        mgp->dev->name);
2875                 goto drop;
2876         }
2877
2878         if (skb_linearize(skb))
2879                 goto drop;
2880
2881         tx->linearized++;
2882         goto again;
2883
2884 drop:
2885         dev_kfree_skb_any(skb);
2886         ss->stats.tx_dropped += 1;
2887         return 0;
2888
2889 }
2890
2891 static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev)
2892 {
2893         struct sk_buff *segs, *curr;
2894         struct myri10ge_priv *mgp = netdev_priv(dev);
2895         int status;
2896
2897         segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
2898         if (IS_ERR(segs))
2899                 goto drop;
2900
2901         while (segs) {
2902                 curr = segs;
2903                 segs = segs->next;
2904                 curr->next = NULL;
2905                 status = myri10ge_xmit(curr, dev);
2906                 if (status != 0) {
2907                         dev_kfree_skb_any(curr);
2908                         if (segs != NULL) {
2909                                 curr = segs;
2910                                 segs = segs->next;
2911                                 curr->next = NULL;
2912                                 dev_kfree_skb_any(segs);
2913                         }
2914                         goto drop;
2915                 }
2916         }
2917         dev_kfree_skb_any(skb);
2918         return 0;
2919
2920 drop:
2921         dev_kfree_skb_any(skb);
2922         mgp->stats.tx_dropped += 1;
2923         return 0;
2924 }
2925
2926 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2927 {
2928         struct myri10ge_priv *mgp = netdev_priv(dev);
2929         struct myri10ge_slice_netstats *slice_stats;
2930         struct net_device_stats *stats = &mgp->stats;
2931         int i;
2932
2933         memset(stats, 0, sizeof(*stats));
2934         for (i = 0; i < mgp->num_slices; i++) {
2935                 slice_stats = &mgp->ss[i].stats;
2936                 stats->rx_packets += slice_stats->rx_packets;
2937                 stats->tx_packets += slice_stats->tx_packets;
2938                 stats->rx_bytes += slice_stats->rx_bytes;
2939                 stats->tx_bytes += slice_stats->tx_bytes;
2940                 stats->rx_dropped += slice_stats->rx_dropped;
2941                 stats->tx_dropped += slice_stats->tx_dropped;
2942         }
2943         return stats;
2944 }
2945
2946 static void myri10ge_set_multicast_list(struct net_device *dev)
2947 {
2948         struct myri10ge_priv *mgp = netdev_priv(dev);
2949         struct myri10ge_cmd cmd;
2950         struct dev_mc_list *mc_list;
2951         __be32 data[2] = { 0, 0 };
2952         int err;
2953         DECLARE_MAC_BUF(mac);
2954
2955         /* can be called from atomic contexts,
2956          * pass 1 to force atomicity in myri10ge_send_cmd() */
2957         myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2958
2959         /* This firmware is known to not support multicast */
2960         if (!mgp->fw_multicast_support)
2961                 return;
2962
2963         /* Disable multicast filtering */
2964
2965         err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2966         if (err != 0) {
2967                 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2968                        " error status: %d\n", dev->name, err);
2969                 goto abort;
2970         }
2971
2972         if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
2973                 /* request to disable multicast filtering, so quit here */
2974                 return;
2975         }
2976
2977         /* Flush the filters */
2978
2979         err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2980                                 &cmd, 1);
2981         if (err != 0) {
2982                 printk(KERN_ERR
2983                        "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2984                        ", error status: %d\n", dev->name, err);
2985                 goto abort;
2986         }
2987
2988         /* Walk the multicast list, and add each address */
2989         for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
2990                 memcpy(data, &mc_list->dmi_addr, 6);
2991                 cmd.data0 = ntohl(data[0]);
2992                 cmd.data1 = ntohl(data[1]);
2993                 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2994                                         &cmd, 1);
2995
2996                 if (err != 0) {
2997                         printk(KERN_ERR "myri10ge: %s: Failed "
2998                                "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2999                                "%d\t", dev->name, err);
3000                         printk(KERN_ERR "MAC %s\n",
3001                                print_mac(mac, mc_list->dmi_addr));
3002                         goto abort;
3003                 }
3004         }
3005         /* Enable multicast filtering */
3006         err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3007         if (err != 0) {
3008                 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
3009                        "error status: %d\n", dev->name, err);
3010                 goto abort;
3011         }
3012
3013         return;
3014
3015 abort:
3016         return;
3017 }
3018
3019 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3020 {
3021         struct sockaddr *sa = addr;
3022         struct myri10ge_priv *mgp = netdev_priv(dev);
3023         int status;
3024
3025         if (!is_valid_ether_addr(sa->sa_data))
3026                 return -EADDRNOTAVAIL;
3027
3028         status = myri10ge_update_mac_address(mgp, sa->sa_data);
3029         if (status != 0) {
3030                 printk(KERN_ERR
3031                        "myri10ge: %s: changing mac address failed with %d\n",
3032                        dev->name, status);
3033                 return status;
3034         }
3035
3036         /* change the dev structure */
3037         memcpy(dev->dev_addr, sa->sa_data, 6);
3038         return 0;
3039 }
3040
3041 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3042 {
3043         struct myri10ge_priv *mgp = netdev_priv(dev);
3044         int error = 0;
3045
3046         if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
3047                 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
3048                        dev->name, new_mtu);
3049                 return -EINVAL;
3050         }
3051         printk(KERN_INFO "%s: changing mtu from %d to %d\n",
3052                dev->name, dev->mtu, new_mtu);
3053         if (mgp->running) {
3054                 /* if we change the mtu on an active device, we must
3055                  * reset the device so the firmware sees the change */
3056                 myri10ge_close(dev);
3057                 dev->mtu = new_mtu;
3058                 myri10ge_open(dev);
3059         } else
3060                 dev->mtu = new_mtu;
3061
3062         return error;
3063 }
3064
3065 /*
3066  * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3067  * Only do it if the bridge is a root port since we don't want to disturb
3068  * any other device, except if forced with myri10ge_ecrc_enable > 1.
3069  */
3070
3071 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3072 {
3073         struct pci_dev *bridge = mgp->pdev->bus->self;
3074         struct device *dev = &mgp->pdev->dev;
3075         unsigned cap;
3076         unsigned err_cap;
3077         u16 val;
3078         u8 ext_type;
3079         int ret;
3080
3081         if (!myri10ge_ecrc_enable || !bridge)
3082                 return;
3083
3084         /* check that the bridge is a root port */
3085         cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
3086         pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
3087         ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3088         if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
3089                 if (myri10ge_ecrc_enable > 1) {
3090                         struct pci_dev *prev_bridge, *old_bridge = bridge;
3091
3092                         /* Walk the hierarchy up to the root port
3093                          * where ECRC has to be enabled */
3094                         do {
3095                                 prev_bridge = bridge;
3096                                 bridge = bridge->bus->self;
3097                                 if (!bridge || prev_bridge == bridge) {
3098                                         dev_err(dev,
3099                                                 "Failed to find root port"
3100                                                 " to force ECRC\n");
3101                                         return;
3102                                 }
3103                                 cap =
3104                                     pci_find_capability(bridge, PCI_CAP_ID_EXP);
3105                                 pci_read_config_word(bridge,
3106                                                      cap + PCI_CAP_FLAGS, &val);
3107                                 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3108                         } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
3109
3110                         dev_info(dev,
3111                                  "Forcing ECRC on non-root port %s"
3112                                  " (enabling on root port %s)\n",
3113                                  pci_name(old_bridge), pci_name(bridge));
3114                 } else {
3115                         dev_err(dev,
3116                                 "Not enabling ECRC on non-root port %s\n",
3117                                 pci_name(bridge));
3118                         return;
3119                 }
3120         }
3121
3122         cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
3123         if (!cap)
3124                 return;
3125
3126         ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3127         if (ret) {
3128                 dev_err(dev, "failed reading ext-conf-space of %s\n",
3129                         pci_name(bridge));
3130                 dev_err(dev, "\t pci=nommconf in use? "
3131                         "or buggy/incomplete/absent ACPI MCFG attr?\n");
3132                 return;
3133         }
3134         if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3135                 return;
3136
3137         err_cap |= PCI_ERR_CAP_ECRC_GENE;
3138         pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3139         dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
3140 }
3141
3142 /*
3143  * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3144  * when the PCI-E Completion packets are aligned on an 8-byte
3145  * boundary.  Some PCI-E chip sets always align Completion packets; on
3146  * the ones that do not, the alignment can be enforced by enabling
3147  * ECRC generation (if supported).
3148  *
3149  * When PCI-E Completion packets are not aligned, it is actually more
3150  * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3151  *
3152  * If the driver can neither enable ECRC nor verify that it has
3153  * already been enabled, then it must use a firmware image which works
3154  * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
3155  * should also ensure that it never gives the device a Read-DMA which is
3156  * larger than 2KB by setting the tx_boundary to 2KB.  If ECRC is
3157  * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
3158  * firmware image, and set tx_boundary to 4KB.
3159  */
3160
3161 static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
3162 {
3163         struct pci_dev *pdev = mgp->pdev;
3164         struct device *dev = &pdev->dev;
3165         int status;
3166
3167         mgp->tx_boundary = 4096;
3168         /*
3169          * Verify the max read request size was set to 4KB
3170          * before trying the test with 4KB.
3171          */
3172         status = pcie_get_readrq(pdev);
3173         if (status < 0) {
3174                 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3175                 goto abort;
3176         }
3177         if (status != 4096) {
3178                 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
3179                 mgp->tx_boundary = 2048;
3180         }
3181         /*
3182          * load the optimized firmware (which assumes aligned PCIe
3183          * completions) in order to see if it works on this host.
3184          */
3185         mgp->fw_name = myri10ge_fw_aligned;
3186         status = myri10ge_load_firmware(mgp, 1);
3187         if (status != 0) {
3188                 goto abort;
3189         }
3190
3191         /*
3192          * Enable ECRC if possible
3193          */
3194         myri10ge_enable_ecrc(mgp);
3195
3196         /*
3197          * Run a DMA test which watches for unaligned completions and
3198          * aborts on the first one seen.
3199          */
3200
3201         status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3202         if (status == 0)
3203                 return;         /* keep the aligned firmware */
3204
3205         if (status != -E2BIG)
3206                 dev_warn(dev, "DMA test failed: %d\n", status);
3207         if (status == -ENOSYS)
3208                 dev_warn(dev, "Falling back to ethp! "
3209                          "Please install up to date fw\n");
3210 abort:
3211         /* fall back to using the unaligned firmware */
3212         mgp->tx_boundary = 2048;
3213         mgp->fw_name = myri10ge_fw_unaligned;
3214
3215 }
3216
3217 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3218 {
3219         if (myri10ge_force_firmware == 0) {
3220                 int link_width, exp_cap;
3221                 u16 lnk;
3222
3223                 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
3224                 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
3225                 link_width = (lnk >> 4) & 0x3f;
3226
3227                 /* Check to see if Link is less than 8 or if the
3228                  * upstream bridge is known to provide aligned
3229                  * completions */
3230                 if (link_width < 8) {
3231                         dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3232                                  link_width);
3233                         mgp->tx_boundary = 4096;
3234                         mgp->fw_name = myri10ge_fw_aligned;
3235                 } else {
3236                         myri10ge_firmware_probe(mgp);
3237                 }
3238         } else {
3239                 if (myri10ge_force_firmware == 1) {
3240                         dev_info(&mgp->pdev->dev,
3241                                  "Assuming aligned completions (forced)\n");
3242                         mgp->tx_boundary = 4096;
3243                         mgp->fw_name = myri10ge_fw_aligned;
3244                 } else {
3245                         dev_info(&mgp->pdev->dev,
3246                                  "Assuming unaligned completions (forced)\n");
3247                         mgp->tx_boundary = 2048;
3248                         mgp->fw_name = myri10ge_fw_unaligned;
3249                 }
3250         }
3251         if (myri10ge_fw_name != NULL) {
3252                 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3253                          myri10ge_fw_name);
3254                 mgp->fw_name = myri10ge_fw_name;
3255         }
3256 }
3257
3258 #ifdef CONFIG_PM
3259 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3260 {
3261         struct myri10ge_priv *mgp;
3262         struct net_device *netdev;
3263
3264         mgp = pci_get_drvdata(pdev);
3265         if (mgp == NULL)
3266                 return -EINVAL;
3267         netdev = mgp->dev;
3268
3269         netif_device_detach(netdev);
3270         if (netif_running(netdev)) {
3271                 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
3272                 rtnl_lock();
3273                 myri10ge_close(netdev);
3274                 rtnl_unlock();
3275         }
3276         myri10ge_dummy_rdma(mgp, 0);
3277         pci_save_state(pdev);
3278         pci_disable_device(pdev);
3279
3280         return pci_set_power_state(pdev, pci_choose_state(pdev, state));
3281 }
3282
3283 static int myri10ge_resume(struct pci_dev *pdev)
3284 {
3285         struct myri10ge_priv *mgp;
3286         struct net_device *netdev;
3287         int status;
3288         u16 vendor;
3289
3290         mgp = pci_get_drvdata(pdev);
3291         if (mgp == NULL)
3292                 return -EINVAL;
3293         netdev = mgp->dev;
3294         pci_set_power_state(pdev, 0);   /* zeros conf space as a side effect */
3295         msleep(5);              /* give card time to respond */
3296         pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3297         if (vendor == 0xffff) {
3298                 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
3299                        mgp->dev->name);
3300                 return -EIO;
3301         }
3302
3303         status = pci_restore_state(pdev);
3304         if (status)
3305                 return status;
3306
3307         status = pci_enable_device(pdev);
3308         if (status) {
3309                 dev_err(&pdev->dev, "failed to enable device\n");
3310                 return status;
3311         }
3312
3313         pci_set_master(pdev);
3314
3315         myri10ge_reset(mgp);
3316         myri10ge_dummy_rdma(mgp, 1);
3317
3318         /* Save configuration space to be restored if the
3319          * nic resets due to a parity error */
3320         pci_save_state(pdev);
3321
3322         if (netif_running(netdev)) {
3323                 rtnl_lock();
3324                 status = myri10ge_open(netdev);
3325                 rtnl_unlock();
3326                 if (status != 0)
3327                         goto abort_with_enabled;
3328
3329         }
3330         netif_device_attach(netdev);
3331
3332         return 0;
3333
3334 abort_with_enabled:
3335         pci_disable_device(pdev);
3336         return -EIO;
3337
3338 }
3339 #endif                          /* CONFIG_PM */
3340
3341 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3342 {
3343         struct pci_dev *pdev = mgp->pdev;
3344         int vs = mgp->vendor_specific_offset;
3345         u32 reboot;
3346
3347         /*enter read32 mode */
3348         pci_write_config_byte(pdev, vs + 0x10, 0x3);
3349
3350         /*read REBOOT_STATUS (0xfffffff0) */
3351         pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3352         pci_read_config_dword(pdev, vs + 0x14, &reboot);
3353         return reboot;
3354 }
3355
3356 /*
3357  * This watchdog is used to check whether the board has suffered
3358  * from a parity error and needs to be recovered.
3359  */
3360 static void myri10ge_watchdog(struct work_struct *work)
3361 {
3362         struct myri10ge_priv *mgp =
3363             container_of(work, struct myri10ge_priv, watchdog_work);
3364         struct myri10ge_tx_buf *tx;
3365         u32 reboot;
3366         int status;
3367         int i;
3368         u16 cmd, vendor;
3369
3370         mgp->watchdog_resets++;
3371         pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3372         if ((cmd & PCI_COMMAND_MASTER) == 0) {
3373                 /* Bus master DMA disabled?  Check to see
3374                  * if the card rebooted due to a parity error
3375                  * For now, just report it */
3376                 reboot = myri10ge_read_reboot(mgp);
3377                 printk(KERN_ERR
3378                        "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
3379                        mgp->dev->name, reboot,
3380                        myri10ge_reset_recover ? " " : " not");
3381                 if (myri10ge_reset_recover == 0)
3382                         return;
3383
3384                 myri10ge_reset_recover--;
3385
3386                 /*
3387                  * A rebooted nic will come back with config space as
3388                  * it was after power was applied to PCIe bus.
3389                  * Attempt to restore config space which was saved
3390                  * when the driver was loaded, or the last time the
3391                  * nic was resumed from power saving mode.
3392                  */
3393                 pci_restore_state(mgp->pdev);
3394
3395                 /* save state again for accounting reasons */
3396                 pci_save_state(mgp->pdev);
3397
3398         } else {
3399                 /* if we get back -1's from our slot, perhaps somebody
3400                  * powered off our card.  Don't try to reset it in
3401                  * this case */
3402                 if (cmd == 0xffff) {
3403                         pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3404                         if (vendor == 0xffff) {
3405                                 printk(KERN_ERR
3406                                        "myri10ge: %s: device disappeared!\n",
3407                                        mgp->dev->name);
3408                                 return;
3409                         }
3410                 }
3411                 /* Perhaps it is a software error.  Try to reset */
3412
3413                 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
3414                        mgp->dev->name);
3415                 for (i = 0; i < mgp->num_slices; i++) {
3416                         tx = &mgp->ss[i].tx;
3417                         printk(KERN_INFO
3418                                "myri10ge: %s: (%d): %d %d %d %d %d\n",
3419                                mgp->dev->name, i, tx->req, tx->done,
3420                                tx->pkt_start, tx->pkt_done,
3421                                (int)ntohl(mgp->ss[i].fw_stats->
3422                                           send_done_count));
3423                         msleep(2000);
3424                         printk(KERN_INFO
3425                                "myri10ge: %s: (%d): %d %d %d %d %d\n",
3426                                mgp->dev->name, i, tx->req, tx->done,
3427                                tx->pkt_start, tx->pkt_done,
3428                                (int)ntohl(mgp->ss[i].fw_stats->
3429                                           send_done_count));
3430                 }
3431         }
3432         rtnl_lock();
3433         myri10ge_close(mgp->dev);
3434         status = myri10ge_load_firmware(mgp, 1);
3435         if (status != 0)
3436                 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
3437                        mgp->dev->name);
3438         else
3439                 myri10ge_open(mgp->dev);
3440         rtnl_unlock();
3441 }
3442
3443 /*
3444  * We use our own timer routine rather than relying upon
3445  * netdev->tx_timeout because we have a very large hardware transmit
3446  * queue.  Due to the large queue, the netdev->tx_timeout function
3447  * cannot detect a NIC with a parity error in a timely fashion if the
3448  * NIC is lightly loaded.
3449  */
3450 static void myri10ge_watchdog_timer(unsigned long arg)
3451 {
3452         struct myri10ge_priv *mgp;
3453         struct myri10ge_slice_state *ss;
3454         int i, reset_needed;
3455         u32 rx_pause_cnt;
3456
3457         mgp = (struct myri10ge_priv *)arg;
3458
3459         rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3460         for (i = 0, reset_needed = 0;
3461              i < mgp->num_slices && reset_needed == 0; ++i) {
3462
3463                 ss = &mgp->ss[i];
3464                 if (ss->rx_small.watchdog_needed) {
3465                         myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3466                                                 mgp->small_bytes + MXGEFW_PAD,
3467                                                 1);
3468                         if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3469                             myri10ge_fill_thresh)
3470                                 ss->rx_small.watchdog_needed = 0;
3471                 }
3472                 if (ss->rx_big.watchdog_needed) {
3473                         myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3474                                                 mgp->big_bytes, 1);
3475                         if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3476                             myri10ge_fill_thresh)
3477                                 ss->rx_big.watchdog_needed = 0;
3478                 }
3479
3480                 if (ss->tx.req != ss->tx.done &&
3481                     ss->tx.done == ss->watchdog_tx_done &&
3482                     ss->watchdog_tx_req != ss->watchdog_tx_done) {
3483                         /* nic seems like it might be stuck.. */
3484                         if (rx_pause_cnt != mgp->watchdog_pause) {
3485                                 if (net_ratelimit())
3486                                         printk(KERN_WARNING "myri10ge %s:"
3487                                                "TX paused, check link partner\n",
3488                                                mgp->dev->name);
3489                         } else {
3490                                 reset_needed = 1;
3491                         }
3492                 }
3493                 ss->watchdog_tx_done = ss->tx.done;
3494                 ss->watchdog_tx_req = ss->tx.req;
3495         }
3496         mgp->watchdog_pause = rx_pause_cnt;
3497
3498         if (reset_needed) {
3499                 schedule_work(&mgp->watchdog_work);
3500         } else {
3501                 /* rearm timer */
3502                 mod_timer(&mgp->watchdog_timer,
3503                           jiffies + myri10ge_watchdog_timeout * HZ);
3504         }
3505 }
3506
3507 static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3508 {
3509         struct myri10ge_slice_state *ss;
3510         struct pci_dev *pdev = mgp->pdev;
3511         size_t bytes;
3512         int i;
3513
3514         if (mgp->ss == NULL)
3515                 return;
3516
3517         for (i = 0; i < mgp->num_slices; i++) {
3518                 ss = &mgp->ss[i];
3519                 if (ss->rx_done.entry != NULL) {
3520                         bytes = mgp->max_intr_slots *
3521                             sizeof(*ss->rx_done.entry);
3522                         dma_free_coherent(&pdev->dev, bytes,
3523                                           ss->rx_done.entry, ss->rx_done.bus);
3524                         ss->rx_done.entry = NULL;
3525                 }
3526                 if (ss->fw_stats != NULL) {
3527                         bytes = sizeof(*ss->fw_stats);
3528                         dma_free_coherent(&pdev->dev, bytes,
3529                                           ss->fw_stats, ss->fw_stats_bus);
3530                         ss->fw_stats = NULL;
3531                 }
3532         }
3533         kfree(mgp->ss);
3534         mgp->ss = NULL;
3535 }
3536
3537 static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3538 {
3539         struct myri10ge_slice_state *ss;
3540         struct pci_dev *pdev = mgp->pdev;
3541         size_t bytes;
3542         int i;
3543
3544         bytes = sizeof(*mgp->ss) * mgp->num_slices;
3545         mgp->ss = kzalloc(bytes, GFP_KERNEL);
3546         if (mgp->ss == NULL) {
3547                 return -ENOMEM;
3548         }
3549
3550         for (i = 0; i < mgp->num_slices; i++) {
3551                 ss = &mgp->ss[i];
3552                 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3553                 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3554                                                        &ss->rx_done.bus,
3555                                                        GFP_KERNEL);
3556                 if (ss->rx_done.entry == NULL)
3557                         goto abort;
3558                 memset(ss->rx_done.entry, 0, bytes);
3559                 bytes = sizeof(*ss->fw_stats);
3560                 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3561                                                   &ss->fw_stats_bus,
3562                                                   GFP_KERNEL);
3563                 if (ss->fw_stats == NULL)
3564                         goto abort;
3565                 ss->mgp = mgp;
3566                 ss->dev = mgp->dev;
3567                 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3568                                myri10ge_napi_weight);
3569         }
3570         return 0;
3571 abort:
3572         myri10ge_free_slices(mgp);
3573         return -ENOMEM;
3574 }
3575
3576 /*
3577  * This function determines the number of slices supported.
3578  * The number slices is the minumum of the number of CPUS,
3579  * the number of MSI-X irqs supported, the number of slices
3580  * supported by the firmware
3581  */
3582 static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3583 {
3584         struct myri10ge_cmd cmd;
3585         struct pci_dev *pdev = mgp->pdev;
3586         char *old_fw;
3587         int i, status, ncpus, msix_cap;
3588
3589         mgp->num_slices = 1;
3590         msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3591         ncpus = num_online_cpus();
3592
3593         if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3594             (myri10ge_max_slices == -1 && ncpus < 2))
3595                 return;
3596
3597         /* try to load the slice aware rss firmware */
3598         old_fw = mgp->fw_name;
3599         if (old_fw == myri10ge_fw_aligned)
3600                 mgp->fw_name = myri10ge_fw_rss_aligned;
3601         else
3602                 mgp->fw_name = myri10ge_fw_rss_unaligned;
3603         status = myri10ge_load_firmware(mgp, 0);
3604         if (status != 0) {
3605                 dev_info(&pdev->dev, "Rss firmware not found\n");
3606                 return;
3607         }
3608
3609         /* hit the board with a reset to ensure it is alive */
3610         memset(&cmd, 0, sizeof(cmd));
3611         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3612         if (status != 0) {
3613                 dev_err(&mgp->pdev->dev, "failed reset\n");
3614                 goto abort_with_fw;
3615                 return;
3616         }
3617
3618         mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3619
3620         /* tell it the size of the interrupt queues */
3621         cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3622         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3623         if (status != 0) {
3624                 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3625                 goto abort_with_fw;
3626         }
3627
3628         /* ask the maximum number of slices it supports */
3629         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3630         if (status != 0)
3631                 goto abort_with_fw;
3632         else
3633                 mgp->num_slices = cmd.data0;
3634
3635         /* Only allow multiple slices if MSI-X is usable */
3636         if (!myri10ge_msi) {
3637                 goto abort_with_fw;
3638         }
3639
3640         /* if the admin did not specify a limit to how many
3641          * slices we should use, cap it automatically to the
3642          * number of CPUs currently online */
3643         if (myri10ge_max_slices == -1)
3644                 myri10ge_max_slices = ncpus;
3645
3646         if (mgp->num_slices > myri10ge_max_slices)
3647                 mgp->num_slices = myri10ge_max_slices;
3648
3649         /* Now try to allocate as many MSI-X vectors as we have
3650          * slices. We give up on MSI-X if we can only get a single
3651          * vector. */
3652
3653         mgp->msix_vectors = kzalloc(mgp->num_slices *
3654                                     sizeof(*mgp->msix_vectors), GFP_KERNEL);
3655         if (mgp->msix_vectors == NULL)
3656                 goto disable_msix;
3657         for (i = 0; i < mgp->num_slices; i++) {
3658                 mgp->msix_vectors[i].entry = i;
3659         }
3660
3661         while (mgp->num_slices > 1) {
3662                 /* make sure it is a power of two */
3663                 while (!is_power_of_2(mgp->num_slices))
3664                         mgp->num_slices--;
3665                 if (mgp->num_slices == 1)
3666                         goto disable_msix;
3667                 status = pci_enable_msix(pdev, mgp->msix_vectors,
3668                                          mgp->num_slices);
3669                 if (status == 0) {
3670                         pci_disable_msix(pdev);
3671                         return;
3672                 }
3673                 if (status > 0)
3674                         mgp->num_slices = status;
3675                 else
3676                         goto disable_msix;
3677         }
3678
3679 disable_msix:
3680         if (mgp->msix_vectors != NULL) {
3681                 kfree(mgp->msix_vectors);
3682                 mgp->msix_vectors = NULL;
3683         }
3684
3685 abort_with_fw:
3686         mgp->num_slices = 1;
3687         mgp->fw_name = old_fw;
3688         myri10ge_load_firmware(mgp, 0);
3689 }
3690
3691 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3692 {
3693         struct net_device *netdev;
3694         struct myri10ge_priv *mgp;
3695         struct device *dev = &pdev->dev;
3696         int i;
3697         int status = -ENXIO;
3698         int dac_enabled;
3699
3700         netdev = alloc_etherdev(sizeof(*mgp));
3701         if (netdev == NULL) {
3702                 dev_err(dev, "Could not allocate ethernet device\n");
3703                 return -ENOMEM;
3704         }
3705
3706         SET_NETDEV_DEV(netdev, &pdev->dev);
3707
3708         mgp = netdev_priv(netdev);
3709         mgp->dev = netdev;
3710         mgp->pdev = pdev;
3711         mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3712         mgp->pause = myri10ge_flow_control;
3713         mgp->intr_coal_delay = myri10ge_intr_coal_delay;
3714         mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
3715         init_waitqueue_head(&mgp->down_wq);
3716
3717         if (pci_enable_device(pdev)) {
3718                 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3719                 status = -ENODEV;
3720                 goto abort_with_netdev;
3721         }
3722
3723         /* Find the vendor-specific cap so we can check
3724          * the reboot register later on */
3725         mgp->vendor_specific_offset
3726             = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3727
3728         /* Set our max read request to 4KB */
3729         status = pcie_set_readrq(pdev, 4096);
3730         if (status != 0) {
3731                 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3732                         status);
3733                 goto abort_with_netdev;
3734         }
3735
3736         pci_set_master(pdev);
3737         dac_enabled = 1;
3738         status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
3739         if (status != 0) {
3740                 dac_enabled = 0;
3741                 dev_err(&pdev->dev,
3742                         "64-bit pci address mask was refused, "
3743                         "trying 32-bit\n");
3744                 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3745         }
3746         if (status != 0) {
3747                 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3748                 goto abort_with_netdev;
3749         }
3750         mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3751                                       &mgp->cmd_bus, GFP_KERNEL);
3752         if (mgp->cmd == NULL)
3753                 goto abort_with_netdev;
3754
3755         mgp->board_span = pci_resource_len(pdev, 0);
3756         mgp->iomem_base = pci_resource_start(pdev, 0);
3757         mgp->mtrr = -1;
3758         mgp->wc_enabled = 0;
3759 #ifdef CONFIG_MTRR
3760         mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3761                              MTRR_TYPE_WRCOMB, 1);
3762         if (mgp->mtrr >= 0)
3763                 mgp->wc_enabled = 1;
3764 #endif
3765         /* Hack.  need to get rid of these magic numbers */
3766         mgp->sram_size =
3767             2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
3768         if (mgp->sram_size > mgp->board_span) {
3769                 dev_err(&pdev->dev, "board span %ld bytes too small\n",
3770                         mgp->board_span);
3771                 goto abort_with_wc;
3772         }
3773         mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
3774         if (mgp->sram == NULL) {
3775                 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3776                         mgp->board_span, mgp->iomem_base);
3777                 status = -ENXIO;
3778                 goto abort_with_wc;
3779         }
3780         memcpy_fromio(mgp->eeprom_strings,
3781                       mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
3782                       MYRI10GE_EEPROM_STRINGS_SIZE);
3783         memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3784         status = myri10ge_read_mac_addr(mgp);
3785         if (status)
3786                 goto abort_with_ioremap;
3787
3788         for (i = 0; i < ETH_ALEN; i++)
3789                 netdev->dev_addr[i] = mgp->mac_addr[i];
3790
3791         myri10ge_select_firmware(mgp);
3792
3793         status = myri10ge_load_firmware(mgp, 1);
3794         if (status != 0) {
3795                 dev_err(&pdev->dev, "failed to load firmware\n");
3796                 goto abort_with_ioremap;
3797         }
3798         myri10ge_probe_slices(mgp);
3799         status = myri10ge_alloc_slices(mgp);
3800         if (status != 0) {
3801                 dev_err(&pdev->dev, "failed to alloc slice state\n");
3802                 goto abort_with_firmware;
3803         }
3804
3805         status = myri10ge_reset(mgp);
3806         if (status != 0) {
3807                 dev_err(&pdev->dev, "failed reset\n");
3808                 goto abort_with_slices;
3809         }
3810 #ifdef CONFIG_DCA
3811         myri10ge_setup_dca(mgp);
3812 #endif
3813         pci_set_drvdata(pdev, mgp);
3814         if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3815                 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3816         if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3817                 myri10ge_initial_mtu = 68;
3818         netdev->mtu = myri10ge_initial_mtu;
3819         netdev->open = myri10ge_open;
3820         netdev->stop = myri10ge_close;
3821         netdev->hard_start_xmit = myri10ge_xmit;
3822         netdev->get_stats = myri10ge_get_stats;
3823         netdev->base_addr = mgp->iomem_base;
3824         netdev->change_mtu = myri10ge_change_mtu;
3825         netdev->set_multicast_list = myri10ge_set_multicast_list;
3826         netdev->set_mac_address = myri10ge_set_mac_address;
3827         netdev->features = mgp->features;
3828         if (dac_enabled)
3829                 netdev->features |= NETIF_F_HIGHDMA;
3830
3831         /* make sure we can get an irq, and that MSI can be
3832          * setup (if available).  Also ensure netdev->irq
3833          * is set to correct value if MSI is enabled */
3834         status = myri10ge_request_irq(mgp);
3835         if (status != 0)
3836                 goto abort_with_firmware;
3837         netdev->irq = pdev->irq;
3838         myri10ge_free_irq(mgp);
3839
3840         /* Save configuration space to be restored if the
3841          * nic resets due to a parity error */
3842         pci_save_state(pdev);
3843
3844         /* Setup the watchdog timer */
3845         setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3846                     (unsigned long)mgp);
3847
3848         SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
3849         INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
3850         status = register_netdev(netdev);
3851         if (status != 0) {
3852                 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
3853                 goto abort_with_state;
3854         }
3855         if (mgp->msix_enabled)
3856                 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3857                          mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3858                          (mgp->wc_enabled ? "Enabled" : "Disabled"));
3859         else
3860                 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3861                          mgp->msi_enabled ? "MSI" : "xPIC",
3862                          netdev->irq, mgp->tx_boundary, mgp->fw_name,
3863                          (mgp->wc_enabled ? "Enabled" : "Disabled"));
3864
3865         return 0;
3866
3867 abort_with_state:
3868         pci_restore_state(pdev);
3869
3870 abort_with_slices:
3871         myri10ge_free_slices(mgp);
3872
3873 abort_with_firmware:
3874         myri10ge_dummy_rdma(mgp, 0);
3875
3876 abort_with_ioremap:
3877         iounmap(mgp->sram);
3878
3879 abort_with_wc:
3880 #ifdef CONFIG_MTRR
3881         if (mgp->mtrr >= 0)
3882                 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3883 #endif
3884         dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3885                           mgp->cmd, mgp->cmd_bus);
3886
3887 abort_with_netdev:
3888
3889         free_netdev(netdev);
3890         return status;
3891 }
3892
3893 /*
3894  * myri10ge_remove
3895  *
3896  * Does what is necessary to shutdown one Myrinet device. Called
3897  *   once for each Myrinet card by the kernel when a module is
3898  *   unloaded.
3899  */
3900 static void myri10ge_remove(struct pci_dev *pdev)
3901 {
3902         struct myri10ge_priv *mgp;
3903         struct net_device *netdev;
3904
3905         mgp = pci_get_drvdata(pdev);
3906         if (mgp == NULL)
3907                 return;
3908
3909         flush_scheduled_work();
3910         netdev = mgp->dev;
3911         unregister_netdev(netdev);
3912
3913 #ifdef CONFIG_DCA
3914         myri10ge_teardown_dca(mgp);
3915 #endif
3916         myri10ge_dummy_rdma(mgp, 0);
3917
3918         /* avoid a memory leak */
3919         pci_restore_state(pdev);
3920
3921         iounmap(mgp->sram);
3922
3923 #ifdef CONFIG_MTRR
3924         if (mgp->mtrr >= 0)
3925                 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3926 #endif
3927         myri10ge_free_slices(mgp);
3928         if (mgp->msix_vectors != NULL)
3929                 kfree(mgp->msix_vectors);
3930         dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3931                           mgp->cmd, mgp->cmd_bus);
3932
3933         free_netdev(netdev);
3934         pci_set_drvdata(pdev, NULL);
3935 }
3936
3937 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E      0x0008
3938 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9    0x0009
3939
3940 static struct pci_device_id myri10ge_pci_tbl[] = {
3941         {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
3942         {PCI_DEVICE
3943          (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
3944         {0},
3945 };
3946
3947 static struct pci_driver myri10ge_driver = {
3948         .name = "myri10ge",
3949         .probe = myri10ge_probe,
3950         .remove = myri10ge_remove,
3951         .id_table = myri10ge_pci_tbl,
3952 #ifdef CONFIG_PM
3953         .suspend = myri10ge_suspend,
3954         .resume = myri10ge_resume,
3955 #endif
3956 };
3957
3958 #ifdef CONFIG_DCA
3959 static int
3960 myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
3961 {
3962         int err = driver_for_each_device(&myri10ge_driver.driver,
3963                                          NULL, &event,
3964                                          myri10ge_notify_dca_device);
3965
3966         if (err)
3967                 return NOTIFY_BAD;
3968         return NOTIFY_DONE;
3969 }
3970
3971 static struct notifier_block myri10ge_dca_notifier = {
3972         .notifier_call = myri10ge_notify_dca,
3973         .next = NULL,
3974         .priority = 0,
3975 };
3976 #endif                          /* CONFIG_DCA */
3977
3978 static __init int myri10ge_init_module(void)
3979 {
3980         printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3981                MYRI10GE_VERSION_STR);
3982
3983         if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_SRC_PORT ||
3984             myri10ge_rss_hash < MXGEFW_RSS_HASH_TYPE_IPV4) {
3985                 printk(KERN_ERR
3986                        "%s: Illegal rssh hash type %d, defaulting to source port\n",
3987                        myri10ge_driver.name, myri10ge_rss_hash);
3988                 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
3989         }
3990 #ifdef CONFIG_DCA
3991         dca_register_notify(&myri10ge_dca_notifier);
3992 #endif
3993
3994         return pci_register_driver(&myri10ge_driver);
3995 }
3996
3997 module_init(myri10ge_init_module);
3998
3999 static __exit void myri10ge_cleanup_module(void)
4000 {
4001 #ifdef CONFIG_DCA
4002         dca_unregister_notify(&myri10ge_dca_notifier);
4003 #endif
4004         pci_unregister_driver(&myri10ge_driver);
4005 }
4006
4007 module_exit(myri10ge_cleanup_module);