git.oblomov.eu Git - linux-2.6/blob - drivers/crypto/talitos.c

   1 /*
   2  * talitos - Freescale Integrated Security Engine (SEC) device driver
   3  *
   4  * Copyright (c) 2008 Freescale Semiconductor, Inc.
   5  *
   6  * Scatterlist Crypto API glue code copied from files with the following:
   7  * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
   8  *
   9  * Crypto algorithm registration code copied from hifn driver:
  10  * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
  11  * All rights reserved.
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  26  */
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/device.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/crypto.h>
  34 #include <linux/hw_random.h>
  35 #include <linux/of_platform.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/io.h>
  38 #include <linux/spinlock.h>
  39 #include <linux/rtnetlink.h>
  40
  41 #include <crypto/algapi.h>
  42 #include <crypto/aes.h>
  43 #include <crypto/des.h>
  44 #include <crypto/sha.h>
  45 #include <crypto/aead.h>
  46 #include <crypto/authenc.h>
  47
  48 #include "talitos.h"
  49
  50 #define TALITOS_TIMEOUT 100000
  51 #define TALITOS_MAX_DATA_LEN 65535
  52
  53 #define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
  54 #define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
  55 #define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
  56
  57 /* descriptor pointer entry */
  58 struct talitos_ptr {
  59         __be16 len;     /* length */
  60         u8 j_extent;    /* jump to sg link table and/or extent */
  61         u8 eptr;        /* extended address */
  62         __be32 ptr;     /* address */
  63 };
  64
  65 /* descriptor */
  66 struct talitos_desc {
  67         __be32 hdr;                     /* header high bits */
  68         __be32 hdr_lo;                  /* header low bits */
  69         struct talitos_ptr ptr[7];      /* ptr/len pair array */
  70 };
  71
  72 /**
  73  * talitos_request - descriptor submission request
  74  * @desc: descriptor pointer (kernel virtual)
  75  * @dma_desc: descriptor's physical bus address
  76  * @callback: whom to call when descriptor processing is done
  77  * @context: caller context (optional)
  78  */
  79 struct talitos_request {
  80         struct talitos_desc *desc;
  81         dma_addr_t dma_desc;
  82         void (*callback) (struct device *dev, struct talitos_desc *desc,
  83                           void *context, int error);
  84         void *context;
  85 };
  86
  87 struct talitos_private {
  88         struct device *dev;
  89         struct of_device *ofdev;
  90         void __iomem *reg;
  91         int irq;
  92
  93         /* SEC version geometry (from device tree node) */
  94         unsigned int num_channels;
  95         unsigned int chfifo_len;
  96         unsigned int exec_units;
  97         unsigned int desc_types;
  98
  99         /* SEC Compatibility info */
 100         unsigned long features;
 101
 102         /* next channel to be assigned next incoming descriptor */
 103         atomic_t last_chan;
 104
 105         /* per-channel number of requests pending in channel h/w fifo */
 106         atomic_t *submit_count;
 107
 108         /* per-channel request fifo */
 109         struct talitos_request **fifo;
 110
 111         /*
 112          * length of the request fifo
 113          * fifo_len is chfifo_len rounded up to next power of 2
 114          * so we can use bitwise ops to wrap
 115          */
 116         unsigned int fifo_len;
 117
 118         /* per-channel index to next free descriptor request */
 119         int *head;
 120
 121         /* per-channel index to next in-progress/done descriptor request */
 122         int *tail;
 123
 124         /* per-channel request submission (head) and release (tail) locks */
 125         spinlock_t *head_lock;
 126         spinlock_t *tail_lock;
 127
 128         /* request callback tasklet */
 129         struct tasklet_struct done_task;
 130
 131         /* list of registered algorithms */
 132         struct list_head alg_list;
 133
 134         /* hwrng device */
 135         struct hwrng rng;
 136 };
 137
 138 /* .features flag */
 139 #define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
 140
 141 /*
 142  * map virtual single (contiguous) pointer to h/w descriptor pointer
 143  */
 144 static void map_single_talitos_ptr(struct device *dev,
 145                                    struct talitos_ptr *talitos_ptr,
 146                                    unsigned short len, void *data,
 147                                    unsigned char extent,
 148                                    enum dma_data_direction dir)
 149 {
 150         talitos_ptr->len = cpu_to_be16(len);
 151         talitos_ptr->ptr = cpu_to_be32(dma_map_single(dev, data, len, dir));
 152         talitos_ptr->j_extent = extent;
 153 }
 154
 155 /*
 156  * unmap bus single (contiguous) h/w descriptor pointer
 157  */
 158 static void unmap_single_talitos_ptr(struct device *dev,
 159                                      struct talitos_ptr *talitos_ptr,
 160                                      enum dma_data_direction dir)
 161 {
 162         dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
 163                          be16_to_cpu(talitos_ptr->len), dir);
 164 }
 165
 166 static int reset_channel(struct device *dev, int ch)
 167 {
 168         struct talitos_private *priv = dev_get_drvdata(dev);
 169         unsigned int timeout = TALITOS_TIMEOUT;
 170
 171         setbits32(priv->reg + TALITOS_CCCR(ch), TALITOS_CCCR_RESET);
 172
 173         while ((in_be32(priv->reg + TALITOS_CCCR(ch)) & TALITOS_CCCR_RESET)
 174                && --timeout)
 175                 cpu_relax();
 176
 177         if (timeout == 0) {
 178                 dev_err(dev, "failed to reset channel %d\n", ch);
 179                 return -EIO;
 180         }
 181
 182         /* set done writeback and IRQ */
 183         setbits32(priv->reg + TALITOS_CCCR_LO(ch), TALITOS_CCCR_LO_CDWE |
 184                   TALITOS_CCCR_LO_CDIE);
 185
 186         return 0;
 187 }
 188
 189 static int reset_device(struct device *dev)
 190 {
 191         struct talitos_private *priv = dev_get_drvdata(dev);
 192         unsigned int timeout = TALITOS_TIMEOUT;
 193
 194         setbits32(priv->reg + TALITOS_MCR, TALITOS_MCR_SWR);
 195
 196         while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
 197                && --timeout)
 198                 cpu_relax();
 199
 200         if (timeout == 0) {
 201                 dev_err(dev, "failed to reset device\n");
 202                 return -EIO;
 203         }
 204
 205         return 0;
 206 }
 207
 208 /*
 209  * Reset and initialize the device
 210  */
 211 static int init_device(struct device *dev)
 212 {
 213         struct talitos_private *priv = dev_get_drvdata(dev);
 214         int ch, err;
 215
 216         /*
 217          * Master reset
 218          * errata documentation: warning: certain SEC interrupts
 219          * are not fully cleared by writing the MCR:SWR bit,
 220          * set bit twice to completely reset
 221          */
 222         err = reset_device(dev);
 223         if (err)
 224                 return err;
 225
 226         err = reset_device(dev);
 227         if (err)
 228                 return err;
 229
 230         /* reset channels */
 231         for (ch = 0; ch < priv->num_channels; ch++) {
 232                 err = reset_channel(dev, ch);
 233                 if (err)
 234                         return err;
 235         }
 236
 237         /* enable channel done and error interrupts */
 238         setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
 239         setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
 240
 241         return 0;
 242 }
 243
 244 /**
 245  * talitos_submit - submits a descriptor to the device for processing
 246  * @dev:        the SEC device to be used
 247  * @desc:       the descriptor to be processed by the device
 248  * @callback:   whom to call when processing is complete
 249  * @context:    a handle for use by caller (optional)
 250  *
 251  * desc must contain valid dma-mapped (bus physical) address pointers.
 252  * callback must check err and feedback in descriptor header
 253  * for device processing status.
 254  */
 255 static int talitos_submit(struct device *dev, struct talitos_desc *desc,
 256                           void (*callback)(struct device *dev,
 257                                            struct talitos_desc *desc,
 258                                            void *context, int error),
 259                           void *context)
 260 {
 261         struct talitos_private *priv = dev_get_drvdata(dev);
 262         struct talitos_request *request;
 263         unsigned long flags, ch;
 264         int head;
 265
 266         /* select done notification */
 267         desc->hdr |= DESC_HDR_DONE_NOTIFY;
 268
 269         /* emulate SEC's round-robin channel fifo polling scheme */
 270         ch = atomic_inc_return(&priv->last_chan) & (priv->num_channels - 1);
 271
 272         spin_lock_irqsave(&priv->head_lock[ch], flags);
 273
 274         if (!atomic_inc_not_zero(&priv->submit_count[ch])) {
 275                 /* h/w fifo is full */
 276                 spin_unlock_irqrestore(&priv->head_lock[ch], flags);
 277                 return -EAGAIN;
 278         }
 279
 280         head = priv->head[ch];
 281         request = &priv->fifo[ch][head];
 282
 283         /* map descriptor and save caller data */
 284         request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
 285                                            DMA_BIDIRECTIONAL);
 286         request->callback = callback;
 287         request->context = context;
 288
 289         /* increment fifo head */
 290         priv->head[ch] = (priv->head[ch] + 1) & (priv->fifo_len - 1);
 291
 292         smp_wmb();
 293         request->desc = desc;
 294
 295         /* GO! */
 296         wmb();
 297         out_be32(priv->reg + TALITOS_FF_LO(ch), request->dma_desc);
 298
 299         spin_unlock_irqrestore(&priv->head_lock[ch], flags);
 300
 301         return -EINPROGRESS;
 302 }
 303
 304 /*
 305  * process what was done, notify callback of error if not
 306  */
 307 static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
 308 {
 309         struct talitos_private *priv = dev_get_drvdata(dev);
 310         struct talitos_request *request, saved_req;
 311         unsigned long flags;
 312         int tail, status;
 313
 314         spin_lock_irqsave(&priv->tail_lock[ch], flags);
 315
 316         tail = priv->tail[ch];
 317         while (priv->fifo[ch][tail].desc) {
 318                 request = &priv->fifo[ch][tail];
 319
 320                 /* descriptors with their done bits set don't get the error */
 321                 rmb();
 322                 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE) {
 323                         status = 0;
 324                         /* Ack each pkt completed on channel */
 325                         out_be32(priv->reg + TALITOS_ICR, (1 << (ch * 2)));
 326                 } else
 327                         if (!error)
 328                                 break;
 329                         else
 330                                 status = error;
 331
 332                 dma_unmap_single(dev, request->dma_desc,
 333                         sizeof(struct talitos_desc), DMA_BIDIRECTIONAL);
 334
 335                 /* copy entries so we can call callback outside lock */
 336                 saved_req.desc = request->desc;
 337                 saved_req.callback = request->callback;
 338                 saved_req.context = request->context;
 339
 340                 /* release request entry in fifo */
 341                 smp_wmb();
 342                 request->desc = NULL;
 343
 344                 /* increment fifo tail */
 345                 priv->tail[ch] = (tail + 1) & (priv->fifo_len - 1);
 346
 347                 spin_unlock_irqrestore(&priv->tail_lock[ch], flags);
 348
 349                 atomic_dec(&priv->submit_count[ch]);
 350
 351                 saved_req.callback(dev, saved_req.desc, saved_req.context,
 352                                    status);
 353                 /* channel may resume processing in single desc error case */
 354                 if (error && !reset_ch && status == error)
 355                         return;
 356                 spin_lock_irqsave(&priv->tail_lock[ch], flags);
 357                 tail = priv->tail[ch];
 358         }
 359
 360         spin_unlock_irqrestore(&priv->tail_lock[ch], flags);
 361 }
 362
 363 /*
 364  * process completed requests for channels that have done status
 365  */
 366 static void talitos_done(unsigned long data)
 367 {
 368         struct device *dev = (struct device *)data;
 369         struct talitos_private *priv = dev_get_drvdata(dev);
 370         int ch;
 371
 372         for (ch = 0; ch < priv->num_channels; ch++)
 373                 flush_channel(dev, ch, 0, 0);
 374
 375         /* At this point, all completed channels have been processed.
 376          * Unmask done interrupts for channels completed later on.
 377          */
 378         setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_DONE);
 379 }
 380
 381 /*
 382  * locate current (offending) descriptor
 383  */
 384 static struct talitos_desc *current_desc(struct device *dev, int ch)
 385 {
 386         struct talitos_private *priv = dev_get_drvdata(dev);
 387         int tail = priv->tail[ch];
 388         dma_addr_t cur_desc;
 389
 390         cur_desc = in_be32(priv->reg + TALITOS_CDPR_LO(ch));
 391
 392         while (priv->fifo[ch][tail].dma_desc != cur_desc) {
 393                 tail = (tail + 1) & (priv->fifo_len - 1);
 394                 if (tail == priv->tail[ch]) {
 395                         dev_err(dev, "couldn't locate current descriptor\n");
 396                         return NULL;
 397                 }
 398         }
 399
 400         return priv->fifo[ch][tail].desc;
 401 }
 402
 403 /*
 404  * user diagnostics; report root cause of error based on execution unit status
 405  */
 406 static void report_eu_error(struct device *dev, int ch, struct talitos_desc *desc)
 407 {
 408         struct talitos_private *priv = dev_get_drvdata(dev);
 409         int i;
 410
 411         switch (desc->hdr & DESC_HDR_SEL0_MASK) {
 412         case DESC_HDR_SEL0_AFEU:
 413                 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
 414                         in_be32(priv->reg + TALITOS_AFEUISR),
 415                         in_be32(priv->reg + TALITOS_AFEUISR_LO));
 416                 break;
 417         case DESC_HDR_SEL0_DEU:
 418                 dev_err(dev, "DEUISR 0x%08x_%08x\n",
 419                         in_be32(priv->reg + TALITOS_DEUISR),
 420                         in_be32(priv->reg + TALITOS_DEUISR_LO));
 421                 break;
 422         case DESC_HDR_SEL0_MDEUA:
 423         case DESC_HDR_SEL0_MDEUB:
 424                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
 425                         in_be32(priv->reg + TALITOS_MDEUISR),
 426                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
 427                 break;
 428         case DESC_HDR_SEL0_RNG:
 429                 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
 430                         in_be32(priv->reg + TALITOS_RNGUISR),
 431                         in_be32(priv->reg + TALITOS_RNGUISR_LO));
 432                 break;
 433         case DESC_HDR_SEL0_PKEU:
 434                 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
 435                         in_be32(priv->reg + TALITOS_PKEUISR),
 436                         in_be32(priv->reg + TALITOS_PKEUISR_LO));
 437                 break;
 438         case DESC_HDR_SEL0_AESU:
 439                 dev_err(dev, "AESUISR 0x%08x_%08x\n",
 440                         in_be32(priv->reg + TALITOS_AESUISR),
 441                         in_be32(priv->reg + TALITOS_AESUISR_LO));
 442                 break;
 443         case DESC_HDR_SEL0_CRCU:
 444                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
 445                         in_be32(priv->reg + TALITOS_CRCUISR),
 446                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
 447                 break;
 448         case DESC_HDR_SEL0_KEU:
 449                 dev_err(dev, "KEUISR 0x%08x_%08x\n",
 450                         in_be32(priv->reg + TALITOS_KEUISR),
 451                         in_be32(priv->reg + TALITOS_KEUISR_LO));
 452                 break;
 453         }
 454
 455         switch (desc->hdr & DESC_HDR_SEL1_MASK) {
 456         case DESC_HDR_SEL1_MDEUA:
 457         case DESC_HDR_SEL1_MDEUB:
 458                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
 459                         in_be32(priv->reg + TALITOS_MDEUISR),
 460                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
 461                 break;
 462         case DESC_HDR_SEL1_CRCU:
 463                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
 464                         in_be32(priv->reg + TALITOS_CRCUISR),
 465                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
 466                 break;
 467         }
 468
 469         for (i = 0; i < 8; i++)
 470                 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
 471                         in_be32(priv->reg + TALITOS_DESCBUF(ch) + 8*i),
 472                         in_be32(priv->reg + TALITOS_DESCBUF_LO(ch) + 8*i));
 473 }
 474
 475 /*
 476  * recover from error interrupts
 477  */
 478 static void talitos_error(unsigned long data, u32 isr, u32 isr_lo)
 479 {
 480         struct device *dev = (struct device *)data;
 481         struct talitos_private *priv = dev_get_drvdata(dev);
 482         unsigned int timeout = TALITOS_TIMEOUT;
 483         int ch, error, reset_dev = 0, reset_ch = 0;
 484         u32 v, v_lo;
 485
 486         for (ch = 0; ch < priv->num_channels; ch++) {
 487                 /* skip channels without errors */
 488                 if (!(isr & (1 << (ch * 2 + 1))))
 489                         continue;
 490
 491                 error = -EINVAL;
 492
 493                 v = in_be32(priv->reg + TALITOS_CCPSR(ch));
 494                 v_lo = in_be32(priv->reg + TALITOS_CCPSR_LO(ch));
 495
 496                 if (v_lo & TALITOS_CCPSR_LO_DOF) {
 497                         dev_err(dev, "double fetch fifo overflow error\n");
 498                         error = -EAGAIN;
 499                         reset_ch = 1;
 500                 }
 501                 if (v_lo & TALITOS_CCPSR_LO_SOF) {
 502                         /* h/w dropped descriptor */
 503                         dev_err(dev, "single fetch fifo overflow error\n");
 504                         error = -EAGAIN;
 505                 }
 506                 if (v_lo & TALITOS_CCPSR_LO_MDTE)
 507                         dev_err(dev, "master data transfer error\n");
 508                 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
 509                         dev_err(dev, "s/g data length zero error\n");
 510                 if (v_lo & TALITOS_CCPSR_LO_FPZ)
 511                         dev_err(dev, "fetch pointer zero error\n");
 512                 if (v_lo & TALITOS_CCPSR_LO_IDH)
 513                         dev_err(dev, "illegal descriptor header error\n");
 514                 if (v_lo & TALITOS_CCPSR_LO_IEU)
 515                         dev_err(dev, "invalid execution unit error\n");
 516                 if (v_lo & TALITOS_CCPSR_LO_EU)
 517                         report_eu_error(dev, ch, current_desc(dev, ch));
 518                 if (v_lo & TALITOS_CCPSR_LO_GB)
 519                         dev_err(dev, "gather boundary error\n");
 520                 if (v_lo & TALITOS_CCPSR_LO_GRL)
 521                         dev_err(dev, "gather return/length error\n");
 522                 if (v_lo & TALITOS_CCPSR_LO_SB)
 523                         dev_err(dev, "scatter boundary error\n");
 524                 if (v_lo & TALITOS_CCPSR_LO_SRL)
 525                         dev_err(dev, "scatter return/length error\n");
 526
 527                 flush_channel(dev, ch, error, reset_ch);
 528
 529                 if (reset_ch) {
 530                         reset_channel(dev, ch);
 531                 } else {
 532                         setbits32(priv->reg + TALITOS_CCCR(ch),
 533                                   TALITOS_CCCR_CONT);
 534                         setbits32(priv->reg + TALITOS_CCCR_LO(ch), 0);
 535                         while ((in_be32(priv->reg + TALITOS_CCCR(ch)) &
 536                                TALITOS_CCCR_CONT) && --timeout)
 537                                 cpu_relax();
 538                         if (timeout == 0) {
 539                                 dev_err(dev, "failed to restart channel %d\n",
 540                                         ch);
 541                                 reset_dev = 1;
 542                         }
 543                 }
 544         }
 545         if (reset_dev || isr & ~TALITOS_ISR_CHERR || isr_lo) {
 546                 dev_err(dev, "done overflow, internal time out, or rngu error: "
 547                         "ISR 0x%08x_%08x\n", isr, isr_lo);
 548
 549                 /* purge request queues */
 550                 for (ch = 0; ch < priv->num_channels; ch++)
 551                         flush_channel(dev, ch, -EIO, 1);
 552
 553                 /* reset and reinitialize the device */
 554                 init_device(dev);
 555         }
 556 }
 557
 558 static irqreturn_t talitos_interrupt(int irq, void *data)
 559 {
 560         struct device *dev = data;
 561         struct talitos_private *priv = dev_get_drvdata(dev);
 562         u32 isr, isr_lo;
 563
 564         isr = in_be32(priv->reg + TALITOS_ISR);
 565         isr_lo = in_be32(priv->reg + TALITOS_ISR_LO);
 566
 567         if (unlikely((isr & ~TALITOS_ISR_CHDONE) || isr_lo)) {
 568                 /*
 569                  * Acknowledge error interrupts here.
 570                  * Done interrupts are ack'ed as part of done_task.
 571                  */
 572                 out_be32(priv->reg + TALITOS_ICR, isr);
 573                 out_be32(priv->reg + TALITOS_ICR_LO, isr_lo);
 574
 575                 talitos_error((unsigned long)data, isr, isr_lo);
 576         } else
 577                 if (likely(isr & TALITOS_ISR_CHDONE)) {
 578                         /* mask further done interrupts. */
 579                         clrbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_DONE);
 580                         /* done_task will unmask done interrupts at exit */
 581                         tasklet_schedule(&priv->done_task);
 582                 }
 583
 584         return (isr || isr_lo) ? IRQ_HANDLED : IRQ_NONE;
 585 }
 586
 587 /*
 588  * hwrng
 589  */
 590 static int talitos_rng_data_present(struct hwrng *rng, int wait)
 591 {
 592         struct device *dev = (struct device *)rng->priv;
 593         struct talitos_private *priv = dev_get_drvdata(dev);
 594         u32 ofl;
 595         int i;
 596
 597         for (i = 0; i < 20; i++) {
 598                 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
 599                       TALITOS_RNGUSR_LO_OFL;
 600                 if (ofl || !wait)
 601                         break;
 602                 udelay(10);
 603         }
 604
 605         return !!ofl;
 606 }
 607
 608 static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
 609 {
 610         struct device *dev = (struct device *)rng->priv;
 611         struct talitos_private *priv = dev_get_drvdata(dev);
 612
 613         /* rng fifo requires 64-bit accesses */
 614         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
 615         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
 616
 617         return sizeof(u32);
 618 }
 619
 620 static int talitos_rng_init(struct hwrng *rng)
 621 {
 622         struct device *dev = (struct device *)rng->priv;
 623         struct talitos_private *priv = dev_get_drvdata(dev);
 624         unsigned int timeout = TALITOS_TIMEOUT;
 625
 626         setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
 627         while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
 628                && --timeout)
 629                 cpu_relax();
 630         if (timeout == 0) {
 631                 dev_err(dev, "failed to reset rng hw\n");
 632                 return -ENODEV;
 633         }
 634
 635         /* start generating */
 636         setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
 637
 638         return 0;
 639 }
 640
 641 static int talitos_register_rng(struct device *dev)
 642 {
 643         struct talitos_private *priv = dev_get_drvdata(dev);
 644
 645         priv->rng.name          = dev_driver_string(dev),
 646         priv->rng.init          = talitos_rng_init,
 647         priv->rng.data_present  = talitos_rng_data_present,
 648         priv->rng.data_read     = talitos_rng_data_read,
 649         priv->rng.priv          = (unsigned long)dev;
 650
 651         return hwrng_register(&priv->rng);
 652 }
 653
 654 static void talitos_unregister_rng(struct device *dev)
 655 {
 656         struct talitos_private *priv = dev_get_drvdata(dev);
 657
 658         hwrng_unregister(&priv->rng);
 659 }
 660
 661 /*
 662  * crypto alg
 663  */
 664 #define TALITOS_CRA_PRIORITY            3000
 665 #define TALITOS_MAX_KEY_SIZE            64
 666 #define TALITOS_MAX_IV_LENGTH           16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
 667
 668 #define MD5_DIGEST_SIZE   16
 669
 670 struct talitos_ctx {
 671         struct device *dev;
 672         __be32 desc_hdr_template;
 673         u8 key[TALITOS_MAX_KEY_SIZE];
 674         u8 iv[TALITOS_MAX_IV_LENGTH];
 675         unsigned int keylen;
 676         unsigned int enckeylen;
 677         unsigned int authkeylen;
 678         unsigned int authsize;
 679 };
 680
 681 static int aead_authenc_setauthsize(struct crypto_aead *authenc,
 682                                                  unsigned int authsize)
 683 {
 684         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 685
 686         ctx->authsize = authsize;
 687
 688         return 0;
 689 }
 690
 691 static int aead_authenc_setkey(struct crypto_aead *authenc,
 692                                             const u8 *key, unsigned int keylen)
 693 {
 694         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 695         struct rtattr *rta = (void *)key;
 696         struct crypto_authenc_key_param *param;
 697         unsigned int authkeylen;
 698         unsigned int enckeylen;
 699
 700         if (!RTA_OK(rta, keylen))
 701                 goto badkey;
 702
 703         if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
 704                 goto badkey;
 705
 706         if (RTA_PAYLOAD(rta) < sizeof(*param))
 707                 goto badkey;
 708
 709         param = RTA_DATA(rta);
 710         enckeylen = be32_to_cpu(param->enckeylen);
 711
 712         key += RTA_ALIGN(rta->rta_len);
 713         keylen -= RTA_ALIGN(rta->rta_len);
 714
 715         if (keylen < enckeylen)
 716                 goto badkey;
 717
 718         authkeylen = keylen - enckeylen;
 719
 720         if (keylen > TALITOS_MAX_KEY_SIZE)
 721                 goto badkey;
 722
 723         memcpy(&ctx->key, key, keylen);
 724
 725         ctx->keylen = keylen;
 726         ctx->enckeylen = enckeylen;
 727         ctx->authkeylen = authkeylen;
 728
 729         return 0;
 730
 731 badkey:
 732         crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
 733         return -EINVAL;
 734 }
 735
 736 /*
 737  * ipsec_esp_edesc - s/w-extended ipsec_esp descriptor
 738  * @src_nents: number of segments in input scatterlist
 739  * @dst_nents: number of segments in output scatterlist
 740  * @dma_len: length of dma mapped link_tbl space
 741  * @dma_link_tbl: bus physical address of link_tbl
 742  * @desc: h/w descriptor
 743  * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
 744  *
 745  * if decrypting (with authcheck), or either one of src_nents or dst_nents
 746  * is greater than 1, an integrity check value is concatenated to the end
 747  * of link_tbl data
 748  */
 749 struct ipsec_esp_edesc {
 750         int src_nents;
 751         int dst_nents;
 752         int dma_len;
 753         dma_addr_t dma_link_tbl;
 754         struct talitos_desc desc;
 755         struct talitos_ptr link_tbl[0];
 756 };
 757
 758 static void ipsec_esp_unmap(struct device *dev,
 759                             struct ipsec_esp_edesc *edesc,
 760                             struct aead_request *areq)
 761 {
 762         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
 763         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
 764         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
 765         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
 766
 767         dma_unmap_sg(dev, areq->assoc, 1, DMA_TO_DEVICE);
 768
 769         if (areq->src != areq->dst) {
 770                 dma_unmap_sg(dev, areq->src, edesc->src_nents ? : 1,
 771                              DMA_TO_DEVICE);
 772                 dma_unmap_sg(dev, areq->dst, edesc->dst_nents ? : 1,
 773                              DMA_FROM_DEVICE);
 774         } else {
 775                 dma_unmap_sg(dev, areq->src, edesc->src_nents ? : 1,
 776                              DMA_BIDIRECTIONAL);
 777         }
 778
 779         if (edesc->dma_len)
 780                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
 781                                  DMA_BIDIRECTIONAL);
 782 }
 783
 784 /*
 785  * ipsec_esp descriptor callbacks
 786  */
 787 static void ipsec_esp_encrypt_done(struct device *dev,
 788                                    struct talitos_desc *desc, void *context,
 789                                    int err)
 790 {
 791         struct aead_request *areq = context;
 792         struct ipsec_esp_edesc *edesc =
 793                  container_of(desc, struct ipsec_esp_edesc, desc);
 794         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
 795         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 796         struct scatterlist *sg;
 797         void *icvdata;
 798
 799         ipsec_esp_unmap(dev, edesc, areq);
 800
 801         /* copy the generated ICV to dst */
 802         if (edesc->dma_len) {
 803                 icvdata = &edesc->link_tbl[edesc->src_nents +
 804                                            edesc->dst_nents + 2];
 805                 sg = sg_last(areq->dst, edesc->dst_nents);
 806                 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
 807                        icvdata, ctx->authsize);
 808         }
 809
 810         kfree(edesc);
 811
 812         aead_request_complete(areq, err);
 813 }
 814
 815 static void ipsec_esp_decrypt_done(struct device *dev,
 816                                    struct talitos_desc *desc, void *context,
 817                                    int err)
 818 {
 819         struct aead_request *req = context;
 820         struct ipsec_esp_edesc *edesc =
 821                  container_of(desc, struct ipsec_esp_edesc, desc);
 822         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
 823         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 824         struct scatterlist *sg;
 825         void *icvdata;
 826
 827         ipsec_esp_unmap(dev, edesc, req);
 828
 829         if (!err) {
 830                 /* auth check */
 831                 if (edesc->dma_len)
 832                         icvdata = &edesc->link_tbl[edesc->src_nents +
 833                                                    edesc->dst_nents + 2];
 834                 else
 835                         icvdata = &edesc->link_tbl[0];
 836
 837                 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
 838                 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
 839                              ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
 840         }
 841
 842         kfree(edesc);
 843
 844         aead_request_complete(req, err);
 845 }
 846
 847 /*
 848  * convert scatterlist to SEC h/w link table format
 849  * stop at cryptlen bytes
 850  */
 851 static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
 852                            int cryptlen, struct talitos_ptr *link_tbl_ptr)
 853 {
 854         int n_sg = sg_count;
 855
 856         while (n_sg--) {
 857                 link_tbl_ptr->ptr = cpu_to_be32(sg_dma_address(sg));
 858                 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
 859                 link_tbl_ptr->j_extent = 0;
 860                 link_tbl_ptr++;
 861                 cryptlen -= sg_dma_len(sg);
 862                 sg = sg_next(sg);
 863         }
 864
 865         /* adjust (decrease) last one (or two) entry's len to cryptlen */
 866         link_tbl_ptr--;
 867         while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
 868                 /* Empty this entry, and move to previous one */
 869                 cryptlen += be16_to_cpu(link_tbl_ptr->len);
 870                 link_tbl_ptr->len = 0;
 871                 sg_count--;
 872                 link_tbl_ptr--;
 873         }
 874         link_tbl_ptr->len = cpu_to_be16(be16_to_cpu(link_tbl_ptr->len)
 875                                         + cryptlen);
 876
 877         /* tag end of link table */
 878         link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
 879
 880         return sg_count;
 881 }
 882
 883 /*
 884  * fill in and submit ipsec_esp descriptor
 885  */
 886 static int ipsec_esp(struct ipsec_esp_edesc *edesc, struct aead_request *areq,
 887                      u8 *giv, u64 seq,
 888                      void (*callback) (struct device *dev,
 889                                        struct talitos_desc *desc,
 890                                        void *context, int error))
 891 {
 892         struct crypto_aead *aead = crypto_aead_reqtfm(areq);
 893         struct talitos_ctx *ctx = crypto_aead_ctx(aead);
 894         struct device *dev = ctx->dev;
 895         struct talitos_desc *desc = &edesc->desc;
 896         unsigned int cryptlen = areq->cryptlen;
 897         unsigned int authsize = ctx->authsize;
 898         unsigned int ivsize;
 899         int sg_count, ret;
 900
 901         /* hmac key */
 902         map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
 903                                0, DMA_TO_DEVICE);
 904         /* hmac data */
 905         map_single_talitos_ptr(dev, &desc->ptr[1], sg_virt(areq->src) -
 906                                sg_virt(areq->assoc), sg_virt(areq->assoc), 0,
 907                                DMA_TO_DEVICE);
 908         /* cipher iv */
 909         ivsize = crypto_aead_ivsize(aead);
 910         map_single_talitos_ptr(dev, &desc->ptr[2], ivsize, giv ?: areq->iv, 0,
 911                                DMA_TO_DEVICE);
 912
 913         /* cipher key */
 914         map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
 915                                (char *)&ctx->key + ctx->authkeylen, 0,
 916                                DMA_TO_DEVICE);
 917
 918         /*
 919          * cipher in
 920          * map and adjust cipher len to aead request cryptlen.
 921          * extent is bytes of HMAC postpended to ciphertext,
 922          * typically 12 for ipsec
 923          */
 924         desc->ptr[4].len = cpu_to_be16(cryptlen);
 925         desc->ptr[4].j_extent = authsize;
 926
 927         if (areq->src == areq->dst)
 928                 sg_count = dma_map_sg(dev, areq->src, edesc->src_nents ? : 1,
 929                                       DMA_BIDIRECTIONAL);
 930         else
 931                 sg_count = dma_map_sg(dev, areq->src, edesc->src_nents ? : 1,
 932                                       DMA_TO_DEVICE);
 933
 934         if (sg_count == 1) {
 935                 desc->ptr[4].ptr = cpu_to_be32(sg_dma_address(areq->src));
 936         } else {
 937                 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
 938                                           &edesc->link_tbl[0]);
 939                 if (sg_count > 1) {
 940                         struct talitos_ptr *link_tbl_ptr =
 941                                 &edesc->link_tbl[sg_count-1];
 942                         struct scatterlist *sg;
 943                         struct talitos_private *priv = dev_get_drvdata(dev);
 944
 945                         desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
 946                         desc->ptr[4].ptr = cpu_to_be32(edesc->dma_link_tbl);
 947                         dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
 948                                                    edesc->dma_len, DMA_BIDIRECTIONAL);
 949                         /* If necessary for this SEC revision,
 950                          * add a link table entry for ICV.
 951                          */
 952                         if ((priv->features &
 953                              TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT) &&
 954                             (edesc->desc.hdr & DESC_HDR_MODE0_ENCRYPT) == 0) {
 955                                 link_tbl_ptr->j_extent = 0;
 956                                 link_tbl_ptr++;
 957                                 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
 958                                 link_tbl_ptr->len = cpu_to_be16(authsize);
 959                                 sg = sg_last(areq->src, edesc->src_nents ? : 1);
 960                                 link_tbl_ptr->ptr = cpu_to_be32(
 961                                                 (char *)sg_dma_address(sg)
 962                                                 + sg->length - authsize);
 963                         }
 964                 } else {
 965                         /* Only one segment now, so no link tbl needed */
 966                         desc->ptr[4].ptr = cpu_to_be32(sg_dma_address(areq->src));
 967                 }
 968         }
 969
 970         /* cipher out */
 971         desc->ptr[5].len = cpu_to_be16(cryptlen);
 972         desc->ptr[5].j_extent = authsize;
 973
 974         if (areq->src != areq->dst) {
 975                 sg_count = dma_map_sg(dev, areq->dst, edesc->dst_nents ? : 1,
 976                                       DMA_FROM_DEVICE);
 977         }
 978
 979         if (sg_count == 1) {
 980                 desc->ptr[5].ptr = cpu_to_be32(sg_dma_address(areq->dst));
 981         } else {
 982                 struct talitos_ptr *link_tbl_ptr =
 983                         &edesc->link_tbl[edesc->src_nents + 1];
 984
 985                 desc->ptr[5].ptr = cpu_to_be32((struct talitos_ptr *)
 986                                                edesc->dma_link_tbl +
 987                                                edesc->src_nents + 1);
 988                 if (areq->src == areq->dst) {
 989                         memcpy(link_tbl_ptr, &edesc->link_tbl[0],
 990                                edesc->src_nents * sizeof(struct talitos_ptr));
 991                 } else {
 992                         sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
 993                                                   link_tbl_ptr);
 994                 }
 995                 /* Add an entry to the link table for ICV data */
 996                 link_tbl_ptr += sg_count - 1;
 997                 link_tbl_ptr->j_extent = 0;
 998                 sg_count++;
 999                 link_tbl_ptr++;
1000                 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1001                 link_tbl_ptr->len = cpu_to_be16(authsize);
1002
1003                 /* icv data follows link tables */
1004                 link_tbl_ptr->ptr = cpu_to_be32((struct talitos_ptr *)
1005                                                 edesc->dma_link_tbl +
1006                                                 edesc->src_nents +
1007                                                 edesc->dst_nents + 2);
1008
1009                 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
1010                 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1011                                            edesc->dma_len, DMA_BIDIRECTIONAL);
1012         }
1013
1014         /* iv out */
1015         map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
1016                                DMA_FROM_DEVICE);
1017
1018         ret = talitos_submit(dev, desc, callback, areq);
1019         if (ret != -EINPROGRESS) {
1020                 ipsec_esp_unmap(dev, edesc, areq);
1021                 kfree(edesc);
1022         }
1023         return ret;
1024 }
1025
1026
1027 /*
1028  * derive number of elements in scatterlist
1029  */
1030 static int sg_count(struct scatterlist *sg_list, int nbytes)
1031 {
1032         struct scatterlist *sg = sg_list;
1033         int sg_nents = 0;
1034
1035         while (nbytes) {
1036                 sg_nents++;
1037                 nbytes -= sg->length;
1038                 sg = sg_next(sg);
1039         }
1040
1041         return sg_nents;
1042 }
1043
1044 /*
1045  * allocate and map the ipsec_esp extended descriptor
1046  */
1047 static struct ipsec_esp_edesc *ipsec_esp_edesc_alloc(struct aead_request *areq,
1048                                                      int icv_stashing)
1049 {
1050         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1051         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1052         struct ipsec_esp_edesc *edesc;
1053         int src_nents, dst_nents, alloc_len, dma_len;
1054         gfp_t flags = areq->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
1055                       GFP_ATOMIC;
1056
1057         if (areq->cryptlen + ctx->authsize > TALITOS_MAX_DATA_LEN) {
1058                 dev_err(ctx->dev, "cryptlen exceeds h/w max limit\n");
1059                 return ERR_PTR(-EINVAL);
1060         }
1061
1062         src_nents = sg_count(areq->src, areq->cryptlen + ctx->authsize);
1063         src_nents = (src_nents == 1) ? 0 : src_nents;
1064
1065         if (areq->dst == areq->src) {
1066                 dst_nents = src_nents;
1067         } else {
1068                 dst_nents = sg_count(areq->dst, areq->cryptlen + ctx->authsize);
1069                 dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1070         }
1071
1072         /*
1073          * allocate space for base edesc plus the link tables,
1074          * allowing for two separate entries for ICV and generated ICV (+ 2),
1075          * and the ICV data itself
1076          */
1077         alloc_len = sizeof(struct ipsec_esp_edesc);
1078         if (src_nents || dst_nents) {
1079                 dma_len = (src_nents + dst_nents + 2) *
1080                                  sizeof(struct talitos_ptr) + ctx->authsize;
1081                 alloc_len += dma_len;
1082         } else {
1083                 dma_len = 0;
1084                 alloc_len += icv_stashing ? ctx->authsize : 0;
1085         }
1086
1087         edesc = kmalloc(alloc_len, GFP_DMA | flags);
1088         if (!edesc) {
1089                 dev_err(ctx->dev, "could not allocate edescriptor\n");
1090                 return ERR_PTR(-ENOMEM);
1091         }
1092
1093         edesc->src_nents = src_nents;
1094         edesc->dst_nents = dst_nents;
1095         edesc->dma_len = dma_len;
1096         edesc->dma_link_tbl = dma_map_single(ctx->dev, &edesc->link_tbl[0],
1097                                              edesc->dma_len, DMA_BIDIRECTIONAL);
1098
1099         return edesc;
1100 }
1101
1102 static int aead_authenc_encrypt(struct aead_request *req)
1103 {
1104         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1105         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1106         struct ipsec_esp_edesc *edesc;
1107
1108         /* allocate extended descriptor */
1109         edesc = ipsec_esp_edesc_alloc(req, 0);
1110         if (IS_ERR(edesc))
1111                 return PTR_ERR(edesc);
1112
1113         /* set encrypt */
1114         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1115
1116         return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_encrypt_done);
1117 }
1118
1119 static int aead_authenc_decrypt(struct aead_request *req)
1120 {
1121         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1122         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1123         unsigned int authsize = ctx->authsize;
1124         struct ipsec_esp_edesc *edesc;
1125         struct scatterlist *sg;
1126         void *icvdata;
1127
1128         req->cryptlen -= authsize;
1129
1130         /* allocate extended descriptor */
1131         edesc = ipsec_esp_edesc_alloc(req, 1);
1132         if (IS_ERR(edesc))
1133                 return PTR_ERR(edesc);
1134
1135         /* stash incoming ICV for later cmp with ICV generated by the h/w */
1136         if (edesc->dma_len)
1137                 icvdata = &edesc->link_tbl[edesc->src_nents +
1138                                            edesc->dst_nents + 2];
1139         else
1140                 icvdata = &edesc->link_tbl[0];
1141
1142         sg = sg_last(req->src, edesc->src_nents ? : 1);
1143
1144         memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1145                ctx->authsize);
1146
1147         /* decrypt */
1148         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1149
1150         return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_decrypt_done);
1151 }
1152
1153 static int aead_authenc_givencrypt(
1154         struct aead_givcrypt_request *req)
1155 {
1156         struct aead_request *areq = &req->areq;
1157         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1158         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1159         struct ipsec_esp_edesc *edesc;
1160
1161         /* allocate extended descriptor */
1162         edesc = ipsec_esp_edesc_alloc(areq, 0);
1163         if (IS_ERR(edesc))
1164                 return PTR_ERR(edesc);
1165
1166         /* set encrypt */
1167         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1168
1169         memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
1170         /* avoid consecutive packets going out with same IV */
1171         *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
1172
1173         return ipsec_esp(edesc, areq, req->giv, req->seq,
1174                          ipsec_esp_encrypt_done);
1175 }
1176
1177 struct talitos_alg_template {
1178         char name[CRYPTO_MAX_ALG_NAME];
1179         char driver_name[CRYPTO_MAX_ALG_NAME];
1180         unsigned int blocksize;
1181         struct aead_alg aead;
1182         struct device *dev;
1183         __be32 desc_hdr_template;
1184 };
1185
1186 static struct talitos_alg_template driver_algs[] = {
1187         /* single-pass ipsec_esp descriptor */
1188         {
1189                 .name = "authenc(hmac(sha1),cbc(aes))",
1190                 .driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1191                 .blocksize = AES_BLOCK_SIZE,
1192                 .aead = {
1193                         .setkey = aead_authenc_setkey,
1194                         .setauthsize = aead_authenc_setauthsize,
1195                         .encrypt = aead_authenc_encrypt,
1196                         .decrypt = aead_authenc_decrypt,
1197                         .givencrypt = aead_authenc_givencrypt,
1198                         .geniv = "<built-in>",
1199                         .ivsize = AES_BLOCK_SIZE,
1200                         .maxauthsize = SHA1_DIGEST_SIZE,
1201                         },
1202                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1203                                      DESC_HDR_SEL0_AESU |
1204                                      DESC_HDR_MODE0_AESU_CBC |
1205                                      DESC_HDR_SEL1_MDEUA |
1206                                      DESC_HDR_MODE1_MDEU_INIT |
1207                                      DESC_HDR_MODE1_MDEU_PAD |
1208                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1209         },
1210         {
1211                 .name = "authenc(hmac(sha1),cbc(des3_ede))",
1212                 .driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
1213                 .blocksize = DES3_EDE_BLOCK_SIZE,
1214                 .aead = {
1215                         .setkey = aead_authenc_setkey,
1216                         .setauthsize = aead_authenc_setauthsize,
1217                         .encrypt = aead_authenc_encrypt,
1218                         .decrypt = aead_authenc_decrypt,
1219                         .givencrypt = aead_authenc_givencrypt,
1220                         .geniv = "<built-in>",
1221                         .ivsize = DES3_EDE_BLOCK_SIZE,
1222                         .maxauthsize = SHA1_DIGEST_SIZE,
1223                         },
1224                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1225                                      DESC_HDR_SEL0_DEU |
1226                                      DESC_HDR_MODE0_DEU_CBC |
1227                                      DESC_HDR_MODE0_DEU_3DES |
1228                                      DESC_HDR_SEL1_MDEUA |
1229                                      DESC_HDR_MODE1_MDEU_INIT |
1230                                      DESC_HDR_MODE1_MDEU_PAD |
1231                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1232         },
1233         {
1234                 .name = "authenc(hmac(sha256),cbc(aes))",
1235                 .driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
1236                 .blocksize = AES_BLOCK_SIZE,
1237                 .aead = {
1238                         .setkey = aead_authenc_setkey,
1239                         .setauthsize = aead_authenc_setauthsize,
1240                         .encrypt = aead_authenc_encrypt,
1241                         .decrypt = aead_authenc_decrypt,
1242                         .givencrypt = aead_authenc_givencrypt,
1243                         .geniv = "<built-in>",
1244                         .ivsize = AES_BLOCK_SIZE,
1245                         .maxauthsize = SHA256_DIGEST_SIZE,
1246                         },
1247                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1248                                      DESC_HDR_SEL0_AESU |
1249                                      DESC_HDR_MODE0_AESU_CBC |
1250                                      DESC_HDR_SEL1_MDEUA |
1251                                      DESC_HDR_MODE1_MDEU_INIT |
1252                                      DESC_HDR_MODE1_MDEU_PAD |
1253                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
1254         },
1255         {
1256                 .name = "authenc(hmac(sha256),cbc(des3_ede))",
1257                 .driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
1258                 .blocksize = DES3_EDE_BLOCK_SIZE,
1259                 .aead = {
1260                         .setkey = aead_authenc_setkey,
1261                         .setauthsize = aead_authenc_setauthsize,
1262                         .encrypt = aead_authenc_encrypt,
1263                         .decrypt = aead_authenc_decrypt,
1264                         .givencrypt = aead_authenc_givencrypt,
1265                         .geniv = "<built-in>",
1266                         .ivsize = DES3_EDE_BLOCK_SIZE,
1267                         .maxauthsize = SHA256_DIGEST_SIZE,
1268                         },
1269                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1270                                      DESC_HDR_SEL0_DEU |
1271                                      DESC_HDR_MODE0_DEU_CBC |
1272                                      DESC_HDR_MODE0_DEU_3DES |
1273                                      DESC_HDR_SEL1_MDEUA |
1274                                      DESC_HDR_MODE1_MDEU_INIT |
1275                                      DESC_HDR_MODE1_MDEU_PAD |
1276                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
1277         },
1278         {
1279                 .name = "authenc(hmac(md5),cbc(aes))",
1280                 .driver_name = "authenc-hmac-md5-cbc-aes-talitos",
1281                 .blocksize = AES_BLOCK_SIZE,
1282                 .aead = {
1283                         .setkey = aead_authenc_setkey,
1284                         .setauthsize = aead_authenc_setauthsize,
1285                         .encrypt = aead_authenc_encrypt,
1286                         .decrypt = aead_authenc_decrypt,
1287                         .givencrypt = aead_authenc_givencrypt,
1288                         .geniv = "<built-in>",
1289                         .ivsize = AES_BLOCK_SIZE,
1290                         .maxauthsize = MD5_DIGEST_SIZE,
1291                         },
1292                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1293                                      DESC_HDR_SEL0_AESU |
1294                                      DESC_HDR_MODE0_AESU_CBC |
1295                                      DESC_HDR_SEL1_MDEUA |
1296                                      DESC_HDR_MODE1_MDEU_INIT |
1297                                      DESC_HDR_MODE1_MDEU_PAD |
1298                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
1299         },
1300         {
1301                 .name = "authenc(hmac(md5),cbc(des3_ede))",
1302                 .driver_name = "authenc-hmac-md5-cbc-3des-talitos",
1303                 .blocksize = DES3_EDE_BLOCK_SIZE,
1304                 .aead = {
1305                         .setkey = aead_authenc_setkey,
1306                         .setauthsize = aead_authenc_setauthsize,
1307                         .encrypt = aead_authenc_encrypt,
1308                         .decrypt = aead_authenc_decrypt,
1309                         .givencrypt = aead_authenc_givencrypt,
1310                         .geniv = "<built-in>",
1311                         .ivsize = DES3_EDE_BLOCK_SIZE,
1312                         .maxauthsize = MD5_DIGEST_SIZE,
1313                         },
1314                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1315                                      DESC_HDR_SEL0_DEU |
1316                                      DESC_HDR_MODE0_DEU_CBC |
1317                                      DESC_HDR_MODE0_DEU_3DES |
1318                                      DESC_HDR_SEL1_MDEUA |
1319                                      DESC_HDR_MODE1_MDEU_INIT |
1320                                      DESC_HDR_MODE1_MDEU_PAD |
1321                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
1322         }
1323 };
1324
1325 struct talitos_crypto_alg {
1326         struct list_head entry;
1327         struct device *dev;
1328         __be32 desc_hdr_template;
1329         struct crypto_alg crypto_alg;
1330 };
1331
1332 static int talitos_cra_init(struct crypto_tfm *tfm)
1333 {
1334         struct crypto_alg *alg = tfm->__crt_alg;
1335         struct talitos_crypto_alg *talitos_alg =
1336                  container_of(alg, struct talitos_crypto_alg, crypto_alg);
1337         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
1338
1339         /* update context with ptr to dev */
1340         ctx->dev = talitos_alg->dev;
1341         /* copy descriptor header template value */
1342         ctx->desc_hdr_template = talitos_alg->desc_hdr_template;
1343
1344         /* random first IV */
1345         get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
1346
1347         return 0;
1348 }
1349
1350 /*
1351  * given the alg's descriptor header template, determine whether descriptor
1352  * type and primary/secondary execution units required match the hw
1353  * capabilities description provided in the device tree node.
1354  */
1355 static int hw_supports(struct device *dev, __be32 desc_hdr_template)
1356 {
1357         struct talitos_private *priv = dev_get_drvdata(dev);
1358         int ret;
1359
1360         ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
1361               (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
1362
1363         if (SECONDARY_EU(desc_hdr_template))
1364                 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
1365                               & priv->exec_units);
1366
1367         return ret;
1368 }
1369
1370 static int talitos_remove(struct of_device *ofdev)
1371 {
1372         struct device *dev = &ofdev->dev;
1373         struct talitos_private *priv = dev_get_drvdata(dev);
1374         struct talitos_crypto_alg *t_alg, *n;
1375         int i;
1376
1377         list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
1378                 crypto_unregister_alg(&t_alg->crypto_alg);
1379                 list_del(&t_alg->entry);
1380                 kfree(t_alg);
1381         }
1382
1383         if (hw_supports(dev, DESC_HDR_SEL0_RNG))
1384                 talitos_unregister_rng(dev);
1385
1386         kfree(priv->submit_count);
1387         kfree(priv->tail);
1388         kfree(priv->head);
1389
1390         if (priv->fifo)
1391                 for (i = 0; i < priv->num_channels; i++)
1392                         kfree(priv->fifo[i]);
1393
1394         kfree(priv->fifo);
1395         kfree(priv->head_lock);
1396         kfree(priv->tail_lock);
1397
1398         if (priv->irq != NO_IRQ) {
1399                 free_irq(priv->irq, dev);
1400                 irq_dispose_mapping(priv->irq);
1401         }
1402
1403         tasklet_kill(&priv->done_task);
1404
1405         iounmap(priv->reg);
1406
1407         dev_set_drvdata(dev, NULL);
1408
1409         kfree(priv);
1410
1411         return 0;
1412 }
1413
1414 static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
1415                                                     struct talitos_alg_template
1416                                                            *template)
1417 {
1418         struct talitos_crypto_alg *t_alg;
1419         struct crypto_alg *alg;
1420
1421         t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
1422         if (!t_alg)
1423                 return ERR_PTR(-ENOMEM);
1424
1425         alg = &t_alg->crypto_alg;
1426
1427         snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", template->name);
1428         snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
1429                  template->driver_name);
1430         alg->cra_module = THIS_MODULE;
1431         alg->cra_init = talitos_cra_init;
1432         alg->cra_priority = TALITOS_CRA_PRIORITY;
1433         alg->cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC;
1434         alg->cra_blocksize = template->blocksize;
1435         alg->cra_alignmask = 0;
1436         alg->cra_type = &crypto_aead_type;
1437         alg->cra_ctxsize = sizeof(struct talitos_ctx);
1438         alg->cra_u.aead = template->aead;
1439
1440         t_alg->desc_hdr_template = template->desc_hdr_template;
1441         t_alg->dev = dev;
1442
1443         return t_alg;
1444 }
1445
1446 static int talitos_probe(struct of_device *ofdev,
1447                          const struct of_device_id *match)
1448 {
1449         struct device *dev = &ofdev->dev;
1450         struct device_node *np = ofdev->node;
1451         struct talitos_private *priv;
1452         const unsigned int *prop;
1453         int i, err;
1454
1455         priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
1456         if (!priv)
1457                 return -ENOMEM;
1458
1459         dev_set_drvdata(dev, priv);
1460
1461         priv->ofdev = ofdev;
1462
1463         INIT_LIST_HEAD(&priv->alg_list);
1464
1465         tasklet_init(&priv->done_task, talitos_done, (unsigned long)dev);
1466
1467         priv->irq = irq_of_parse_and_map(np, 0);
1468
1469         if (priv->irq == NO_IRQ) {
1470                 dev_err(dev, "failed to map irq\n");
1471                 err = -EINVAL;
1472                 goto err_out;
1473         }
1474
1475         /* get the irq line */
1476         err = request_irq(priv->irq, talitos_interrupt, 0,
1477                           dev_driver_string(dev), dev);
1478         if (err) {
1479                 dev_err(dev, "failed to request irq %d\n", priv->irq);
1480                 irq_dispose_mapping(priv->irq);
1481                 priv->irq = NO_IRQ;
1482                 goto err_out;
1483         }
1484
1485         priv->reg = of_iomap(np, 0);
1486         if (!priv->reg) {
1487                 dev_err(dev, "failed to of_iomap\n");
1488                 err = -ENOMEM;
1489                 goto err_out;
1490         }
1491
1492         /* get SEC version capabilities from device tree */
1493         prop = of_get_property(np, "fsl,num-channels", NULL);
1494         if (prop)
1495                 priv->num_channels = *prop;
1496
1497         prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
1498         if (prop)
1499                 priv->chfifo_len = *prop;
1500
1501         prop = of_get_property(np, "fsl,exec-units-mask", NULL);
1502         if (prop)
1503                 priv->exec_units = *prop;
1504
1505         prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
1506         if (prop)
1507                 priv->desc_types = *prop;
1508
1509         if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
1510             !priv->exec_units || !priv->desc_types) {
1511                 dev_err(dev, "invalid property data in device tree node\n");
1512                 err = -EINVAL;
1513                 goto err_out;
1514         }
1515
1516         if (of_device_is_compatible(np, "fsl,sec3.0"))
1517                 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
1518
1519         priv->head_lock = kmalloc(sizeof(spinlock_t) * priv->num_channels,
1520                                   GFP_KERNEL);
1521         priv->tail_lock = kmalloc(sizeof(spinlock_t) * priv->num_channels,
1522                                   GFP_KERNEL);
1523         if (!priv->head_lock || !priv->tail_lock) {
1524                 dev_err(dev, "failed to allocate fifo locks\n");
1525                 err = -ENOMEM;
1526                 goto err_out;
1527         }
1528
1529         for (i = 0; i < priv->num_channels; i++) {
1530                 spin_lock_init(&priv->head_lock[i]);
1531                 spin_lock_init(&priv->tail_lock[i]);
1532         }
1533
1534         priv->fifo = kmalloc(sizeof(struct talitos_request *) *
1535                              priv->num_channels, GFP_KERNEL);
1536         if (!priv->fifo) {
1537                 dev_err(dev, "failed to allocate request fifo\n");
1538                 err = -ENOMEM;
1539                 goto err_out;
1540         }
1541
1542         priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
1543
1544         for (i = 0; i < priv->num_channels; i++) {
1545                 priv->fifo[i] = kzalloc(sizeof(struct talitos_request) *
1546                                         priv->fifo_len, GFP_KERNEL);
1547                 if (!priv->fifo[i]) {
1548                         dev_err(dev, "failed to allocate request fifo %d\n", i);
1549                         err = -ENOMEM;
1550                         goto err_out;
1551                 }
1552         }
1553
1554         priv->submit_count = kmalloc(sizeof(atomic_t) * priv->num_channels,
1555                                      GFP_KERNEL);
1556         if (!priv->submit_count) {
1557                 dev_err(dev, "failed to allocate fifo submit count space\n");
1558                 err = -ENOMEM;
1559                 goto err_out;
1560         }
1561         for (i = 0; i < priv->num_channels; i++)
1562                 atomic_set(&priv->submit_count[i], -priv->chfifo_len);
1563
1564         priv->head = kzalloc(sizeof(int) * priv->num_channels, GFP_KERNEL);
1565         priv->tail = kzalloc(sizeof(int) * priv->num_channels, GFP_KERNEL);
1566         if (!priv->head || !priv->tail) {
1567                 dev_err(dev, "failed to allocate request index space\n");
1568                 err = -ENOMEM;
1569                 goto err_out;
1570         }
1571
1572         /* reset and initialize the h/w */
1573         err = init_device(dev);
1574         if (err) {
1575                 dev_err(dev, "failed to initialize device\n");
1576                 goto err_out;
1577         }
1578
1579         /* register the RNG, if available */
1580         if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
1581                 err = talitos_register_rng(dev);
1582                 if (err) {
1583                         dev_err(dev, "failed to register hwrng: %d\n", err);
1584                         goto err_out;
1585                 } else
1586                         dev_info(dev, "hwrng\n");
1587         }
1588
1589         /* register crypto algorithms the device supports */
1590         for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
1591                 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
1592                         struct talitos_crypto_alg *t_alg;
1593
1594                         t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
1595                         if (IS_ERR(t_alg)) {
1596                                 err = PTR_ERR(t_alg);
1597                                 goto err_out;
1598                         }
1599
1600                         err = crypto_register_alg(&t_alg->crypto_alg);
1601                         if (err) {
1602                                 dev_err(dev, "%s alg registration failed\n",
1603                                         t_alg->crypto_alg.cra_driver_name);
1604                                 kfree(t_alg);
1605                         } else {
1606                                 list_add_tail(&t_alg->entry, &priv->alg_list);
1607                                 dev_info(dev, "%s\n",
1608                                          t_alg->crypto_alg.cra_driver_name);
1609                         }
1610                 }
1611         }
1612
1613         return 0;
1614
1615 err_out:
1616         talitos_remove(ofdev);
1617
1618         return err;
1619 }
1620
1621 static struct of_device_id talitos_match[] = {
1622         {
1623                 .compatible = "fsl,sec2.0",
1624         },
1625         {},
1626 };
1627 MODULE_DEVICE_TABLE(of, talitos_match);
1628
1629 static struct of_platform_driver talitos_driver = {
1630         .name = "talitos",
1631         .match_table = talitos_match,
1632         .probe = talitos_probe,
1633         .remove = talitos_remove,
1634 };
1635
1636 static int __init talitos_init(void)
1637 {
1638         return of_register_platform_driver(&talitos_driver);
1639 }
1640 module_init(talitos_init);
1641
1642 static void __exit talitos_exit(void)
1643 {
1644         of_unregister_platform_driver(&talitos_driver);
1645 }
1646 module_exit(talitos_exit);
1647
1648 MODULE_LICENSE("GPL");
1649 MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
1650 MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");