2 * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
4 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
6 * Contributors (thanks, all!)
9 * Overhaul for Linux 2.6
12 * Major contributions; Motorola PowerStack (PPC and PCI) support,
13 * GD54xx, 1280x1024 mode support, change MCLK based on VCLK.
16 * Excellent code review.
19 * Amiga updates and testing.
21 * Original cirrusfb author: Frank Neumann
23 * Based on retz3fb.c and cirrusfb.c:
24 * Copyright (C) 1997 Jes Sorensen
25 * Copyright (C) 1996 Frank Neumann
27 ***************************************************************
29 * Format this code with GNU indent '-kr -i8 -pcs' options.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive
37 #define CIRRUSFB_VERSION "2.0-pre2"
39 #include <linux/module.h>
40 #include <linux/kernel.h>
41 #include <linux/errno.h>
42 #include <linux/string.h>
44 #include <linux/slab.h>
45 #include <linux/delay.h>
47 #include <linux/init.h>
48 #include <asm/pgtable.h>
51 #include <linux/zorro.h>
54 #include <linux/pci.h>
57 #include <asm/amigahw.h>
59 #ifdef CONFIG_PPC_PREP
60 #include <asm/machdep.h>
61 #define isPReP machine_is(prep)
66 #include <video/vga.h>
67 #include <video/cirrus.h>
69 /*****************************************************************
71 * debugging and utility macros
75 /* enable debug output? */
76 /* #define CIRRUSFB_DEBUG 1 */
78 /* disable runtime assertions? */
79 /* #define CIRRUSFB_NDEBUG */
83 #define DPRINTK(fmt, args...) \
84 printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)
86 #define DPRINTK(fmt, args...)
89 /* debugging assertions */
90 #ifndef CIRRUSFB_NDEBUG
91 #define assert(expr) \
93 printk("Assertion failed! %s,%s,%s,line=%d\n", \
94 #expr, __FILE__, __func__, __LINE__); \
100 #define MB_ (1024 * 1024)
102 /*****************************************************************
104 * chipset information
115 BT_PICASSO4, /* GD5446 */
116 BT_ALPINE, /* GD543x/4x */
118 BT_LAGUNA, /* GD546x */
122 * per-board-type information, used for enumerating and abstracting
123 * chip-specific information
124 * NOTE: MUST be in the same order as enum cirrus_board in order to
125 * use direct indexing on this array
126 * NOTE: '__initdata' cannot be used as some of this info
127 * is required at runtime. Maybe separate into an init-only and
130 static const struct cirrusfb_board_info_rec {
131 char *name; /* ASCII name of chipset */
132 long maxclock[5]; /* maximum video clock */
133 /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
134 bool init_sr07 : 1; /* init SR07 during init_vgachip() */
135 bool init_sr1f : 1; /* write SR1F during init_vgachip() */
136 /* construct bit 19 of screen start address */
137 bool scrn_start_bit19 : 1;
139 /* initial SR07 value, then for each mode */
141 unsigned char sr07_1bpp;
142 unsigned char sr07_1bpp_mux;
143 unsigned char sr07_8bpp;
144 unsigned char sr07_8bpp_mux;
146 unsigned char sr1f; /* SR1F VGA initial register value */
147 } cirrusfb_board_info[] = {
152 /* the SD64/P4 have a higher max. videoclock */
153 140000, 140000, 140000, 140000, 140000,
157 .scrn_start_bit19 = true,
164 .name = "CL Piccolo",
167 90000, 90000, 90000, 90000, 90000
171 .scrn_start_bit19 = false,
178 .name = "CL Picasso",
181 90000, 90000, 90000, 90000, 90000
185 .scrn_start_bit19 = false,
192 .name = "CL Spectrum",
195 90000, 90000, 90000, 90000, 90000
199 .scrn_start_bit19 = false,
206 .name = "CL Picasso4",
208 135100, 135100, 85500, 85500, 0
212 .scrn_start_bit19 = true,
221 /* for the GD5430. GD5446 can do more... */
222 85500, 85500, 50000, 28500, 0
226 .scrn_start_bit19 = true,
229 .sr07_1bpp_mux = 0xA7,
231 .sr07_8bpp_mux = 0xA7,
237 135100, 200000, 200000, 135100, 135100
241 .scrn_start_bit19 = true,
251 135100, 135100, 135100, 135100, 135100,
255 .scrn_start_bit19 = true,
260 #define CHIP(id, btype) \
261 { PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
263 static struct pci_device_id cirrusfb_pci_table[] = {
264 CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),
265 CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_ALPINE),
266 CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_ALPINE),
267 CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
268 CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
269 CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
270 CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso likely */
271 CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */
272 CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
273 CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */
274 CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNA), /* CL Laguna 3DA*/
277 MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
279 #endif /* CONFIG_PCI */
282 static const struct zorro_device_id cirrusfb_zorro_table[] = {
284 .id = ZORRO_PROD_HELFRICH_SD64_RAM,
285 .driver_data = BT_SD64,
287 .id = ZORRO_PROD_HELFRICH_PICCOLO_RAM,
288 .driver_data = BT_PICCOLO,
290 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
291 .driver_data = BT_PICASSO,
293 .id = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
294 .driver_data = BT_SPECTRUM,
296 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3,
297 .driver_data = BT_PICASSO4,
302 static const struct {
305 } cirrusfb_zorro_table2[] = {
307 .id2 = ZORRO_PROD_HELFRICH_SD64_REG,
311 .id2 = ZORRO_PROD_HELFRICH_PICCOLO_REG,
315 .id2 = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG,
319 .id2 = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG,
327 #endif /* CONFIG_ZORRO */
329 struct cirrusfb_regs {
338 long HorizRes; /* The x resolution in pixel */
341 long HorizBlankStart;
346 long VertRes; /* the physical y resolution in scanlines */
355 #ifdef CIRRUSFB_DEBUG
356 enum cirrusfb_dbg_reg_class {
360 #endif /* CIRRUSFB_DEBUG */
362 /* info about board */
363 struct cirrusfb_info {
365 enum cirrus_board btype;
366 unsigned char SFR; /* Shadow of special function register */
368 struct cirrusfb_regs currentmode;
371 u32 pseudo_palette[16];
374 struct zorro_dev *zdev;
377 struct pci_dev *pdev;
379 void (*unmap)(struct fb_info *info);
382 static unsigned cirrusfb_def_mode = 1;
386 * Predefined Video Modes
389 static const struct {
391 struct fb_var_screeninfo var;
392 } cirrusfb_predefined[] = {
394 /* autodetect mode */
395 .name = "Autodetect",
397 /* 640x480, 31.25 kHz, 60 Hz, 25 MHz PixClock */
405 .red = { .length = 8 },
406 .green = { .length = 8 },
407 .blue = { .length = 8 },
417 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
418 .vmode = FB_VMODE_NONINTERLACED
421 /* 800x600, 48 kHz, 76 Hz, 50 MHz PixClock */
429 .red = { .length = 8 },
430 .green = { .length = 8 },
431 .blue = { .length = 8 },
441 .vmode = FB_VMODE_NONINTERLACED
445 * Modeline from XF86Config:
446 * Mode "1024x768" 80 1024 1136 1340 1432 768 770 774 805
448 /* 1024x768, 55.8 kHz, 70 Hz, 80 MHz PixClock */
453 .xres_virtual = 1024,
456 .red = { .length = 8 },
457 .green = { .length = 8 },
458 .blue = { .length = 8 },
468 .vmode = FB_VMODE_NONINTERLACED
473 #define NUM_TOTAL_MODES ARRAY_SIZE(cirrusfb_predefined)
475 /****************************************************************************/
476 /**** BEGIN PROTOTYPES ******************************************************/
478 /*--- Interface used by the world ------------------------------------------*/
479 static int cirrusfb_init(void);
481 static int cirrusfb_setup(char *options);
484 static int cirrusfb_open(struct fb_info *info, int user);
485 static int cirrusfb_release(struct fb_info *info, int user);
486 static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
487 unsigned blue, unsigned transp,
488 struct fb_info *info);
489 static int cirrusfb_check_var(struct fb_var_screeninfo *var,
490 struct fb_info *info);
491 static int cirrusfb_set_par(struct fb_info *info);
492 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
493 struct fb_info *info);
494 static int cirrusfb_blank(int blank_mode, struct fb_info *info);
495 static void cirrusfb_fillrect(struct fb_info *info,
496 const struct fb_fillrect *region);
497 static void cirrusfb_copyarea(struct fb_info *info,
498 const struct fb_copyarea *area);
499 static void cirrusfb_imageblit(struct fb_info *info,
500 const struct fb_image *image);
502 /* function table of the above functions */
503 static struct fb_ops cirrusfb_ops = {
504 .owner = THIS_MODULE,
505 .fb_open = cirrusfb_open,
506 .fb_release = cirrusfb_release,
507 .fb_setcolreg = cirrusfb_setcolreg,
508 .fb_check_var = cirrusfb_check_var,
509 .fb_set_par = cirrusfb_set_par,
510 .fb_pan_display = cirrusfb_pan_display,
511 .fb_blank = cirrusfb_blank,
512 .fb_fillrect = cirrusfb_fillrect,
513 .fb_copyarea = cirrusfb_copyarea,
514 .fb_imageblit = cirrusfb_imageblit,
517 /*--- Hardware Specific Routines -------------------------------------------*/
518 static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
519 struct cirrusfb_regs *regs,
520 struct fb_info *info);
521 /*--- Internal routines ----------------------------------------------------*/
522 static void init_vgachip(struct fb_info *info);
523 static void switch_monitor(struct cirrusfb_info *cinfo, int on);
524 static void WGen(const struct cirrusfb_info *cinfo,
525 int regnum, unsigned char val);
526 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
527 static void AttrOn(const struct cirrusfb_info *cinfo);
528 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
529 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
530 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
531 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
532 unsigned char red, unsigned char green, unsigned char blue);
534 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
535 unsigned char *red, unsigned char *green,
536 unsigned char *blue);
538 static void cirrusfb_WaitBLT(u8 __iomem *regbase);
539 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
540 u_short curx, u_short cury,
541 u_short destx, u_short desty,
542 u_short width, u_short height,
543 u_short line_length);
544 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
545 u_short x, u_short y,
546 u_short width, u_short height,
547 u_char color, u_short line_length);
549 static void bestclock(long freq, long *best,
550 long *nom, long *den,
551 long *div, long maxfreq);
553 #ifdef CIRRUSFB_DEBUG
554 static void cirrusfb_dump(void);
555 static void cirrusfb_dbg_reg_dump(caddr_t regbase);
556 static void cirrusfb_dbg_print_regs(caddr_t regbase,
557 enum cirrusfb_dbg_reg_class reg_class, ...);
558 static void cirrusfb_dbg_print_byte(const char *name, unsigned char val);
559 #endif /* CIRRUSFB_DEBUG */
561 /*** END PROTOTYPES ********************************************************/
562 /*****************************************************************************/
563 /*** BEGIN Interface Used by the World ***************************************/
565 static int opencount;
567 /*--- Open /dev/fbx ---------------------------------------------------------*/
568 static int cirrusfb_open(struct fb_info *info, int user)
570 if (opencount++ == 0)
571 switch_monitor(info->par, 1);
575 /*--- Close /dev/fbx --------------------------------------------------------*/
576 static int cirrusfb_release(struct fb_info *info, int user)
578 if (--opencount == 0)
579 switch_monitor(info->par, 0);
583 /**** END Interface used by the World *************************************/
584 /****************************************************************************/
585 /**** BEGIN Hardware specific Routines **************************************/
587 /* Get a good MCLK value */
588 static long cirrusfb_get_mclk(long freq, int bpp, long *div)
594 /* Calculate MCLK, in case VCLK is high enough to require > 50MHz.
595 * Assume a 64-bit data path for now. The formula is:
596 * ((B * PCLK * 2)/W) * 1.2
597 * B = bytes per pixel, PCLK = pixclock, W = data width in bytes */
598 mclk = ((bpp / 8) * freq * 2) / 4;
599 mclk = (mclk * 12) / 10;
602 DPRINTK("Use MCLK of %ld kHz\n", mclk);
604 /* Calculate value for SR1F. Multiply by 2 so we can round up. */
605 mclk = ((mclk * 16) / 14318);
606 mclk = (mclk + 1) / 2;
607 DPRINTK("Set SR1F[5:0] to 0x%lx\n", mclk);
609 /* Determine if we should use MCLK instead of VCLK, and if so, what we
610 * should divide it by to get VCLK */
612 case 24751 ... 25249:
614 DPRINTK("Using VCLK = MCLK/2\n");
616 case 49501 ... 50499:
618 DPRINTK("Using VCLK = MCLK\n");
628 static int cirrusfb_check_var(struct fb_var_screeninfo *var,
629 struct fb_info *info)
632 /* memory size in pixels */
633 unsigned pixels = info->screen_size * 8 / var->bits_per_pixel;
635 switch (var->bits_per_pixel) {
638 break; /* 8 pixel per byte, only 1/4th of mem usable */
642 break; /* 1 pixel == 1 byte */
644 printk(KERN_ERR "cirrusfb: mode %dx%dx%d rejected..."
645 "color depth not supported.\n",
646 var->xres, var->yres, var->bits_per_pixel);
647 DPRINTK("EXIT - EINVAL error\n");
651 if (var->xres_virtual < var->xres)
652 var->xres_virtual = var->xres;
653 /* use highest possible virtual resolution */
654 if (var->yres_virtual == -1) {
655 var->yres_virtual = pixels / var->xres_virtual;
657 printk(KERN_INFO "cirrusfb: virtual resolution set to "
658 "maximum of %dx%d\n", var->xres_virtual,
661 if (var->yres_virtual < var->yres)
662 var->yres_virtual = var->yres;
664 if (var->xres_virtual * var->yres_virtual > pixels) {
665 printk(KERN_ERR "cirrusfb: mode %dx%dx%d rejected... "
666 "virtual resolution too high to fit into video memory!\n",
667 var->xres_virtual, var->yres_virtual,
668 var->bits_per_pixel);
669 DPRINTK("EXIT - EINVAL error\n");
674 if (var->xoffset < 0)
676 if (var->yoffset < 0)
679 /* truncate xoffset and yoffset to maximum if too high */
680 if (var->xoffset > var->xres_virtual - var->xres)
681 var->xoffset = var->xres_virtual - var->xres - 1;
682 if (var->yoffset > var->yres_virtual - var->yres)
683 var->yoffset = var->yres_virtual - var->yres - 1;
685 switch (var->bits_per_pixel) {
689 var->green = var->red;
690 var->blue = var->red;
696 var->green = var->red;
697 var->blue = var->red;
703 var->green.offset = -3;
704 var->blue.offset = 8;
706 var->red.offset = 10;
707 var->green.offset = 5;
708 var->blue.offset = 0;
711 var->green.length = 5;
712 var->blue.length = 5;
718 var->green.offset = 16;
719 var->blue.offset = 24;
721 var->red.offset = 16;
722 var->green.offset = 8;
723 var->blue.offset = 0;
726 var->green.length = 8;
727 var->blue.length = 8;
731 DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel);
733 /* should never occur */
738 var->green.msb_right =
739 var->blue.msb_right =
742 var->transp.msb_right = 0;
745 if (var->vmode & FB_VMODE_DOUBLE)
747 else if (var->vmode & FB_VMODE_INTERLACED)
748 yres = (yres + 1) / 2;
751 printk(KERN_ERR "cirrusfb: ERROR: VerticalTotal >= 1280; "
752 "special treatment required! (TODO)\n");
753 DPRINTK("EXIT - EINVAL error\n");
760 static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
761 struct cirrusfb_regs *regs,
762 struct fb_info *info)
766 int maxclockidx = var->bits_per_pixel >> 3;
767 struct cirrusfb_info *cinfo = info->par;
768 int xres, hfront, hsync, hback;
769 int yres, vfront, vsync, vback;
771 switch (var->bits_per_pixel) {
773 info->fix.line_length = var->xres_virtual / 8;
774 info->fix.visual = FB_VISUAL_MONO10;
778 info->fix.line_length = var->xres_virtual;
779 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
784 info->fix.line_length = var->xres_virtual * maxclockidx;
785 info->fix.visual = FB_VISUAL_DIRECTCOLOR;
789 DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel);
791 /* should never occur */
795 info->fix.type = FB_TYPE_PACKED_PIXELS;
797 /* convert from ps to kHz */
798 freq = PICOS2KHZ(var->pixclock);
800 DPRINTK("desired pixclock: %ld kHz\n", freq);
802 maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
803 regs->multiplexing = 0;
805 /* If the frequency is greater than we can support, we might be able
806 * to use multiplexing for the video mode */
807 if (freq > maxclock) {
808 switch (cinfo->btype) {
811 regs->multiplexing = 1;
815 printk(KERN_ERR "cirrusfb: Frequency greater "
816 "than maxclock (%ld kHz)\n", maxclock);
817 DPRINTK("EXIT - return -EINVAL\n");
822 /* TODO: If we have a 1MB 5434, we need to put ourselves in a mode where
823 * the VCLK is double the pixel clock. */
824 switch (var->bits_per_pixel) {
827 if (regs->HorizRes <= 800)
828 /* Xbh has this type of clock for 32-bit */
834 bestclock(freq, ®s->freq, ®s->nom, ®s->den, ®s->div,
836 regs->mclk = cirrusfb_get_mclk(freq, var->bits_per_pixel,
840 hfront = var->right_margin;
841 hsync = var->hsync_len;
842 hback = var->left_margin;
845 vfront = var->lower_margin;
846 vsync = var->vsync_len;
847 vback = var->upper_margin;
849 if (var->vmode & FB_VMODE_DOUBLE) {
854 } else if (var->vmode & FB_VMODE_INTERLACED) {
855 yres = (yres + 1) / 2;
856 vfront = (vfront + 1) / 2;
857 vsync = (vsync + 1) / 2;
858 vback = (vback + 1) / 2;
860 regs->HorizRes = xres;
861 regs->HorizTotal = (xres + hfront + hsync + hback) / 8 - 5;
862 regs->HorizDispEnd = xres / 8 - 1;
863 regs->HorizBlankStart = xres / 8;
864 /* does not count with "-5" */
865 regs->HorizBlankEnd = regs->HorizTotal + 5;
866 regs->HorizSyncStart = (xres + hfront) / 8 + 1;
867 regs->HorizSyncEnd = (xres + hfront + hsync) / 8 + 1;
869 regs->VertRes = yres;
870 regs->VertTotal = yres + vfront + vsync + vback - 2;
871 regs->VertDispEnd = yres - 1;
872 regs->VertBlankStart = yres;
873 regs->VertBlankEnd = regs->VertTotal;
874 regs->VertSyncStart = yres + vfront - 1;
875 regs->VertSyncEnd = yres + vfront + vsync - 1;
877 if (regs->VertRes >= 1024) {
878 regs->VertTotal /= 2;
879 regs->VertSyncStart /= 2;
880 regs->VertSyncEnd /= 2;
881 regs->VertDispEnd /= 2;
883 if (regs->multiplexing) {
884 regs->HorizTotal /= 2;
885 regs->HorizSyncStart /= 2;
886 regs->HorizSyncEnd /= 2;
887 regs->HorizDispEnd /= 2;
893 static void cirrusfb_set_mclk(const struct cirrusfb_info *cinfo, int val,
896 assert(cinfo != NULL);
900 unsigned char old = vga_rseq(cinfo->regbase, CL_SEQR1E);
901 vga_wseq(cinfo->regbase, CL_SEQR1E, old | 0x1);
902 vga_wseq(cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
903 } else if (div == 1) {
905 unsigned char old = vga_rseq(cinfo->regbase, CL_SEQR1E);
906 vga_wseq(cinfo->regbase, CL_SEQR1E, old & ~0x1);
907 vga_wseq(cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
909 vga_wseq(cinfo->regbase, CL_SEQR1F, val & 0x3f);
913 /*************************************************************************
914 cirrusfb_set_par_foo()
916 actually writes the values for a new video mode into the hardware,
917 **************************************************************************/
918 static int cirrusfb_set_par_foo(struct fb_info *info)
920 struct cirrusfb_info *cinfo = info->par;
921 struct fb_var_screeninfo *var = &info->var;
922 struct cirrusfb_regs regs;
923 u8 __iomem *regbase = cinfo->regbase;
926 const struct cirrusfb_board_info_rec *bi;
929 DPRINTK("Requested mode: %dx%dx%d\n",
930 var->xres, var->yres, var->bits_per_pixel);
931 DPRINTK("pixclock: %d\n", var->pixclock);
935 err = cirrusfb_decode_var(var, ®s, info);
937 /* should never happen */
938 DPRINTK("mode change aborted. invalid var.\n");
942 bi = &cirrusfb_board_info[cinfo->btype];
944 /* unlock register VGA_CRTC_H_TOTAL..CRT7 */
945 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */
947 /* if debugging is enabled, all parameters get output before writing */
948 DPRINTK("CRT0: %ld\n", regs.HorizTotal);
949 vga_wcrt(regbase, VGA_CRTC_H_TOTAL, regs.HorizTotal);
951 DPRINTK("CRT1: %ld\n", regs.HorizDispEnd);
952 vga_wcrt(regbase, VGA_CRTC_H_DISP, regs.HorizDispEnd);
954 DPRINTK("CRT2: %ld\n", regs.HorizBlankStart);
955 vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, regs.HorizBlankStart);
957 /* + 128: Compatible read */
958 DPRINTK("CRT3: 128+%ld\n", regs.HorizBlankEnd % 32);
959 vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,
960 128 + (regs.HorizBlankEnd % 32));
962 DPRINTK("CRT4: %ld\n", regs.HorizSyncStart);
963 vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, regs.HorizSyncStart);
965 tmp = regs.HorizSyncEnd % 32;
966 if (regs.HorizBlankEnd & 32)
968 DPRINTK("CRT5: %d\n", tmp);
969 vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);
971 DPRINTK("CRT6: %ld\n", regs.VertTotal & 0xff);
972 vga_wcrt(regbase, VGA_CRTC_V_TOTAL, (regs.VertTotal & 0xff));
974 tmp = 16; /* LineCompare bit #9 */
975 if (regs.VertTotal & 256)
977 if (regs.VertDispEnd & 256)
979 if (regs.VertSyncStart & 256)
981 if (regs.VertBlankStart & 256)
983 if (regs.VertTotal & 512)
985 if (regs.VertDispEnd & 512)
987 if (regs.VertSyncStart & 512)
989 DPRINTK("CRT7: %d\n", tmp);
990 vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);
992 tmp = 0x40; /* LineCompare bit #8 */
993 if (regs.VertBlankStart & 512)
995 if (var->vmode & FB_VMODE_DOUBLE)
997 DPRINTK("CRT9: %d\n", tmp);
998 vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);
1000 DPRINTK("CRT10: %ld\n", regs.VertSyncStart & 0xff);
1001 vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, regs.VertSyncStart & 0xff);
1003 DPRINTK("CRT11: 64+32+%ld\n", regs.VertSyncEnd % 16);
1004 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, regs.VertSyncEnd % 16 + 64 + 32);
1006 DPRINTK("CRT12: %ld\n", regs.VertDispEnd & 0xff);
1007 vga_wcrt(regbase, VGA_CRTC_V_DISP_END, regs.VertDispEnd & 0xff);
1009 DPRINTK("CRT15: %ld\n", regs.VertBlankStart & 0xff);
1010 vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, regs.VertBlankStart & 0xff);
1012 DPRINTK("CRT16: %ld\n", regs.VertBlankEnd & 0xff);
1013 vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, regs.VertBlankEnd & 0xff);
1015 DPRINTK("CRT18: 0xff\n");
1016 vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);
1019 if (var->vmode & FB_VMODE_INTERLACED)
1021 if (regs.HorizBlankEnd & 64)
1023 if (regs.HorizBlankEnd & 128)
1025 if (regs.VertBlankEnd & 256)
1027 if (regs.VertBlankEnd & 512)
1030 DPRINTK("CRT1a: %d\n", tmp);
1031 vga_wcrt(regbase, CL_CRT1A, tmp);
1034 /* hardware RefClock: 14.31818 MHz */
1035 /* formula: VClk = (OSC * N) / (D * (1+P)) */
1036 /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
1038 vga_wseq(regbase, CL_SEQRB, regs.nom);
1039 tmp = regs.den << 1;
1043 /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
1044 if ((cinfo->btype == BT_SD64) ||
1045 (cinfo->btype == BT_ALPINE) ||
1046 (cinfo->btype == BT_GD5480))
1049 DPRINTK("CL_SEQR1B: %ld\n", (long) tmp);
1050 vga_wseq(regbase, CL_SEQR1B, tmp);
1052 if (regs.VertRes >= 1024)
1054 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);
1056 /* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit
1057 * address wrap, no compat. */
1058 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);
1060 /* HAEH? vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20);
1061 * previously: 0x00 unlock VGA_CRTC_H_TOTAL..CRT7 */
1063 /* don't know if it would hurt to also program this if no interlaced */
1064 /* mode is used, but I feel better this way.. :-) */
1065 if (var->vmode & FB_VMODE_INTERLACED)
1066 vga_wcrt(regbase, VGA_CRTC_REGS, regs.HorizTotal / 2);
1068 vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
1070 vga_wseq(regbase, VGA_SEQ_CHARACTER_MAP, 0);
1072 /* adjust horizontal/vertical sync type (low/high) */
1073 /* enable display memory & CRTC I/O address for color mode */
1075 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
1077 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
1079 WGen(cinfo, VGA_MIS_W, tmp);
1081 /* Screen A Preset Row-Scan register */
1082 vga_wcrt(regbase, VGA_CRTC_PRESET_ROW, 0);
1083 /* text cursor on and start line */
1084 vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
1085 /* text cursor end line */
1086 vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31);
1088 /******************************************************
1094 /* programming for different color depths */
1095 if (var->bits_per_pixel == 1) {
1096 DPRINTK("cirrusfb: preparing for 1 bit deep display\n");
1097 vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register */
1100 switch (cinfo->btype) {
1108 DPRINTK(" (for GD54xx)\n");
1109 vga_wseq(regbase, CL_SEQR7,
1111 bi->sr07_1bpp_mux : bi->sr07_1bpp);
1115 DPRINTK(" (for GD546x)\n");
1116 vga_wseq(regbase, CL_SEQR7,
1117 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1121 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1125 /* Extended Sequencer Mode */
1126 switch (cinfo->btype) {
1128 /* setting the SEQRF on SD64 is not necessary
1129 * (only during init)
1131 DPRINTK("(for SD64)\n");
1133 vga_wseq(regbase, CL_SEQR1F, 0x1a);
1138 DPRINTK("(for Piccolo/Spectrum)\n");
1139 /* ### ueberall 0x22? */
1140 /* ##vorher 1c MCLK select */
1141 vga_wseq(regbase, CL_SEQR1F, 0x22);
1142 /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
1143 vga_wseq(regbase, CL_SEQRF, 0xb0);
1147 DPRINTK("(for Picasso)\n");
1148 /* ##vorher 22 MCLK select */
1149 vga_wseq(regbase, CL_SEQR1F, 0x22);
1150 /* ## vorher d0 avoid FIFO underruns..? */
1151 vga_wseq(regbase, CL_SEQRF, 0xd0);
1158 DPRINTK(" (for GD54xx)\n");
1163 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1167 /* pixel mask: pass-through for first plane */
1168 WGen(cinfo, VGA_PEL_MSK, 0x01);
1169 if (regs.multiplexing)
1170 /* hidden dac reg: 1280x1024 */
1173 /* hidden dac: nothing */
1175 /* memory mode: odd/even, ext. memory */
1176 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06);
1177 /* plane mask: only write to first plane */
1178 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01);
1179 offset = var->xres_virtual / 16;
1182 /******************************************************
1188 else if (var->bits_per_pixel == 8) {
1189 DPRINTK("cirrusfb: preparing for 8 bit deep display\n");
1190 switch (cinfo->btype) {
1198 DPRINTK(" (for GD54xx)\n");
1199 vga_wseq(regbase, CL_SEQR7,
1201 bi->sr07_8bpp_mux : bi->sr07_8bpp);
1205 DPRINTK(" (for GD546x)\n");
1206 vga_wseq(regbase, CL_SEQR7,
1207 vga_rseq(regbase, CL_SEQR7) | 0x01);
1211 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1215 switch (cinfo->btype) {
1218 vga_wseq(regbase, CL_SEQR1F, 0x1d);
1224 /* ### vorher 1c MCLK select */
1225 vga_wseq(regbase, CL_SEQR1F, 0x22);
1226 /* Fast Page-Mode writes */
1227 vga_wseq(regbase, CL_SEQRF, 0xb0);
1232 /* ### INCOMPLETE!! */
1233 vga_wseq(regbase, CL_SEQRF, 0xb8);
1235 /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1239 DPRINTK(" (for GD543x)\n");
1240 cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
1241 /* We already set SRF and SR1F */
1246 DPRINTK(" (for GD54xx)\n");
1251 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1255 /* mode register: 256 color mode */
1256 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1257 /* pixel mask: pass-through all planes */
1258 WGen(cinfo, VGA_PEL_MSK, 0xff);
1259 if (regs.multiplexing)
1260 /* hidden dac reg: 1280x1024 */
1263 /* hidden dac: nothing */
1265 /* memory mode: chain4, ext. memory */
1266 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1267 /* plane mask: enable writing to all 4 planes */
1268 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1269 offset = var->xres_virtual / 8;
1272 /******************************************************
1278 else if (var->bits_per_pixel == 16) {
1279 DPRINTK("cirrusfb: preparing for 16 bit deep display\n");
1280 switch (cinfo->btype) {
1282 /* Extended Sequencer Mode: 256c col. mode */
1283 vga_wseq(regbase, CL_SEQR7, 0xf7);
1285 vga_wseq(regbase, CL_SEQR1F, 0x1e);
1290 vga_wseq(regbase, CL_SEQR7, 0x87);
1291 /* Fast Page-Mode writes */
1292 vga_wseq(regbase, CL_SEQRF, 0xb0);
1294 vga_wseq(regbase, CL_SEQR1F, 0x22);
1298 vga_wseq(regbase, CL_SEQR7, 0x27);
1299 /* Fast Page-Mode writes */
1300 vga_wseq(regbase, CL_SEQRF, 0xb0);
1302 vga_wseq(regbase, CL_SEQR1F, 0x22);
1306 vga_wseq(regbase, CL_SEQR7, 0x27);
1307 /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1311 DPRINTK(" (for GD543x)\n");
1312 if (regs.HorizRes >= 1024)
1313 vga_wseq(regbase, CL_SEQR7, 0xa7);
1315 vga_wseq(regbase, CL_SEQR7, 0xa3);
1316 cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
1320 DPRINTK(" (for GD5480)\n");
1321 vga_wseq(regbase, CL_SEQR7, 0x17);
1322 /* We already set SRF and SR1F */
1326 DPRINTK(" (for GD546x)\n");
1327 vga_wseq(regbase, CL_SEQR7,
1328 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1332 printk(KERN_WARNING "CIRRUSFB: unknown Board\n");
1336 /* mode register: 256 color mode */
1337 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1338 /* pixel mask: pass-through all planes */
1339 WGen(cinfo, VGA_PEL_MSK, 0xff);
1341 WHDR(cinfo, 0xc0); /* Copy Xbh */
1342 #elif defined(CONFIG_ZORRO)
1343 /* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
1344 WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */
1346 /* memory mode: chain4, ext. memory */
1347 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1348 /* plane mask: enable writing to all 4 planes */
1349 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1350 offset = var->xres_virtual / 4;
1353 /******************************************************
1359 else if (var->bits_per_pixel == 32) {
1360 DPRINTK("cirrusfb: preparing for 32 bit deep display\n");
1361 switch (cinfo->btype) {
1363 /* Extended Sequencer Mode: 256c col. mode */
1364 vga_wseq(regbase, CL_SEQR7, 0xf9);
1366 vga_wseq(regbase, CL_SEQR1F, 0x1e);
1371 vga_wseq(regbase, CL_SEQR7, 0x85);
1372 /* Fast Page-Mode writes */
1373 vga_wseq(regbase, CL_SEQRF, 0xb0);
1375 vga_wseq(regbase, CL_SEQR1F, 0x22);
1379 vga_wseq(regbase, CL_SEQR7, 0x25);
1380 /* Fast Page-Mode writes */
1381 vga_wseq(regbase, CL_SEQRF, 0xb0);
1383 vga_wseq(regbase, CL_SEQR1F, 0x22);
1387 vga_wseq(regbase, CL_SEQR7, 0x25);
1388 /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1392 DPRINTK(" (for GD543x)\n");
1393 vga_wseq(regbase, CL_SEQR7, 0xa9);
1394 cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
1398 DPRINTK(" (for GD5480)\n");
1399 vga_wseq(regbase, CL_SEQR7, 0x19);
1400 /* We already set SRF and SR1F */
1404 DPRINTK(" (for GD546x)\n");
1405 vga_wseq(regbase, CL_SEQR7,
1406 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1410 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1414 /* mode register: 256 color mode */
1415 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1416 /* pixel mask: pass-through all planes */
1417 WGen(cinfo, VGA_PEL_MSK, 0xff);
1418 /* hidden dac reg: 8-8-8 mode (24 or 32) */
1420 /* memory mode: chain4, ext. memory */
1421 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1422 /* plane mask: enable writing to all 4 planes */
1423 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1424 offset = var->xres_virtual / 4;
1427 /******************************************************
1429 * unknown/unsupported bpp
1434 printk(KERN_ERR "cirrusfb: What's this?? "
1435 " requested color depth == %d.\n",
1436 var->bits_per_pixel);
1438 vga_wcrt(regbase, VGA_CRTC_OFFSET, offset & 0xff);
1441 tmp |= 0x10; /* offset overflow bit */
1443 /* screen start addr #16-18, fastpagemode cycles */
1444 vga_wcrt(regbase, CL_CRT1B, tmp);
1446 if (cinfo->btype == BT_SD64 ||
1447 cinfo->btype == BT_PICASSO4 ||
1448 cinfo->btype == BT_ALPINE ||
1449 cinfo->btype == BT_GD5480)
1450 /* screen start address bit 19 */
1451 vga_wcrt(regbase, CL_CRT1D, 0x00);
1453 /* text cursor location high */
1454 vga_wcrt(regbase, VGA_CRTC_CURSOR_HI, 0);
1455 /* text cursor location low */
1456 vga_wcrt(regbase, VGA_CRTC_CURSOR_LO, 0);
1457 /* underline row scanline = at very bottom */
1458 vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0);
1460 /* controller mode */
1461 vga_wattr(regbase, VGA_ATC_MODE, 1);
1462 /* overscan (border) color */
1463 vga_wattr(regbase, VGA_ATC_OVERSCAN, 0);
1464 /* color plane enable */
1465 vga_wattr(regbase, VGA_ATC_PLANE_ENABLE, 15);
1467 vga_wattr(regbase, CL_AR33, 0);
1469 vga_wattr(regbase, VGA_ATC_COLOR_PAGE, 0);
1471 /* [ EGS: SetOffset(); ] */
1472 /* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
1475 /* set/reset register */
1476 vga_wgfx(regbase, VGA_GFX_SR_VALUE, 0);
1477 /* set/reset enable */
1478 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, 0);
1480 vga_wgfx(regbase, VGA_GFX_COMPARE_VALUE, 0);
1482 vga_wgfx(regbase, VGA_GFX_DATA_ROTATE, 0);
1483 /* read map select */
1484 vga_wgfx(regbase, VGA_GFX_PLANE_READ, 0);
1485 /* miscellaneous register */
1486 vga_wgfx(regbase, VGA_GFX_MISC, 1);
1487 /* color don't care */
1488 vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 15);
1490 vga_wgfx(regbase, VGA_GFX_BIT_MASK, 255);
1492 /* graphics cursor attributes: nothing special */
1493 vga_wseq(regbase, CL_SEQR12, 0x0);
1495 /* finally, turn on everything - turn off "FullBandwidth" bit */
1496 /* also, set "DotClock%2" bit where requested */
1499 /*** FB_VMODE_CLOCK_HALVE in linux/fb.h not defined anymore ?
1500 if (var->vmode & FB_VMODE_CLOCK_HALVE)
1504 vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);
1505 DPRINTK("CL_SEQR1: %d\n", tmp);
1507 cinfo->currentmode = regs;
1509 /* pan to requested offset */
1510 cirrusfb_pan_display(var, info);
1512 #ifdef CIRRUSFB_DEBUG
1520 /* for some reason incomprehensible to me, cirrusfb requires that you write
1521 * the registers twice for the settings to take..grr. -dte */
1522 static int cirrusfb_set_par(struct fb_info *info)
1524 cirrusfb_set_par_foo(info);
1525 return cirrusfb_set_par_foo(info);
1528 static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1529 unsigned blue, unsigned transp,
1530 struct fb_info *info)
1532 struct cirrusfb_info *cinfo = info->par;
1537 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
1539 red >>= (16 - info->var.red.length);
1540 green >>= (16 - info->var.green.length);
1541 blue >>= (16 - info->var.blue.length);
1545 v = (red << info->var.red.offset) |
1546 (green << info->var.green.offset) |
1547 (blue << info->var.blue.offset);
1549 cinfo->pseudo_palette[regno] = v;
1553 if (info->var.bits_per_pixel == 8)
1554 WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10);
1560 /*************************************************************************
1561 cirrusfb_pan_display()
1563 performs display panning - provided hardware permits this
1564 **************************************************************************/
1565 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
1566 struct fb_info *info)
1571 unsigned char tmp = 0, tmp2 = 0, xpix;
1572 struct cirrusfb_info *cinfo = info->par;
1575 DPRINTK("virtual offset: (%d,%d)\n", var->xoffset, var->yoffset);
1577 /* no range checks for xoffset and yoffset, */
1578 /* as fb_pan_display has already done this */
1579 if (var->vmode & FB_VMODE_YWRAP)
1582 info->var.xoffset = var->xoffset;
1583 info->var.yoffset = var->yoffset;
1585 xoffset = var->xoffset * info->var.bits_per_pixel / 8;
1586 yoffset = var->yoffset;
1588 base = yoffset * info->fix.line_length + xoffset;
1590 if (info->var.bits_per_pixel == 1) {
1591 /* base is already correct */
1592 xpix = (unsigned char) (var->xoffset % 8);
1595 xpix = (unsigned char) ((xoffset % 4) * 2);
1598 cirrusfb_WaitBLT(cinfo->regbase); /* make sure all the BLT's are done */
1600 /* lower 8 + 8 bits of screen start address */
1601 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO,
1602 (unsigned char) (base & 0xff));
1603 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI,
1604 (unsigned char) (base >> 8));
1606 /* construct bits 16, 17 and 18 of screen start address */
1614 /* 0xf2 is %11110010, exclude tmp bits */
1615 tmp2 = (vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2) | tmp;
1616 vga_wcrt(cinfo->regbase, CL_CRT1B, tmp2);
1618 /* construct bit 19 of screen start address */
1619 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
1620 vga_wcrt(cinfo->regbase, CL_CRT1D, (base >> 12) & 0x80);
1622 /* write pixel panning value to AR33; this does not quite work in 8bpp
1624 * ### Piccolo..? Will this work?
1626 if (info->var.bits_per_pixel == 1)
1627 vga_wattr(cinfo->regbase, CL_AR33, xpix);
1629 cirrusfb_WaitBLT(cinfo->regbase);
1635 static int cirrusfb_blank(int blank_mode, struct fb_info *info)
1638 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
1639 * then the caller blanks by setting the CLUT (Color Look Up Table)
1640 * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking
1641 * failed due to e.g. a video mode which doesn't support it.
1642 * Implements VESA suspend and powerdown modes on hardware that
1643 * supports disabling hsync/vsync:
1644 * blank_mode == 2: suspend vsync
1645 * blank_mode == 3: suspend hsync
1646 * blank_mode == 4: powerdown
1649 struct cirrusfb_info *cinfo = info->par;
1650 int current_mode = cinfo->blank_mode;
1652 DPRINTK("ENTER, blank mode = %d\n", blank_mode);
1654 if (info->state != FBINFO_STATE_RUNNING ||
1655 current_mode == blank_mode) {
1656 DPRINTK("EXIT, returning 0\n");
1661 if (current_mode == FB_BLANK_NORMAL ||
1662 current_mode == FB_BLANK_UNBLANK) {
1663 /* unblank the screen */
1664 val = vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE);
1665 /* clear "FullBandwidth" bit */
1666 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val & 0xdf);
1667 /* and undo VESA suspend trickery */
1668 vga_wgfx(cinfo->regbase, CL_GRE, 0x00);
1672 if (blank_mode > FB_BLANK_NORMAL) {
1673 /* blank the screen */
1674 val = vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE);
1675 /* set "FullBandwidth" bit */
1676 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val | 0x20);
1679 switch (blank_mode) {
1680 case FB_BLANK_UNBLANK:
1681 case FB_BLANK_NORMAL:
1683 case FB_BLANK_VSYNC_SUSPEND:
1684 vga_wgfx(cinfo->regbase, CL_GRE, 0x04);
1686 case FB_BLANK_HSYNC_SUSPEND:
1687 vga_wgfx(cinfo->regbase, CL_GRE, 0x02);
1689 case FB_BLANK_POWERDOWN:
1690 vga_wgfx(cinfo->regbase, CL_GRE, 0x06);
1693 DPRINTK("EXIT, returning 1\n");
1697 cinfo->blank_mode = blank_mode;
1698 DPRINTK("EXIT, returning 0\n");
1700 /* Let fbcon do a soft blank for us */
1701 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1703 /**** END Hardware specific Routines **************************************/
1704 /****************************************************************************/
1705 /**** BEGIN Internal Routines ***********************************************/
1707 static void init_vgachip(struct fb_info *info)
1709 struct cirrusfb_info *cinfo = info->par;
1710 const struct cirrusfb_board_info_rec *bi;
1714 assert(cinfo != NULL);
1716 bi = &cirrusfb_board_info[cinfo->btype];
1718 /* reset board globally */
1719 switch (cinfo->btype) {
1738 /* disable flickerfixer */
1739 vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
1741 /* from Klaus' NetBSD driver: */
1742 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1743 /* put blitter into 542x compat */
1744 vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
1746 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1750 /* from Klaus' NetBSD driver: */
1751 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1755 /* Nothing to do to reset the board. */
1759 printk(KERN_ERR "cirrusfb: Warning: Unknown board type\n");
1763 /* make sure RAM size set by this point */
1764 assert(info->screen_size > 0);
1766 /* the P4 is not fully initialized here; I rely on it having been */
1767 /* inited under AmigaOS already, which seems to work just fine */
1768 /* (Klaus advised to do it this way) */
1770 if (cinfo->btype != BT_PICASSO4) {
1771 WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
1772 WGen(cinfo, CL_POS102, 0x01);
1773 WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
1775 if (cinfo->btype != BT_SD64)
1776 WGen(cinfo, CL_VSSM2, 0x01);
1778 /* reset sequencer logic */
1779 vga_wseq(cinfo->regbase, CL_SEQR0, 0x03);
1781 /* FullBandwidth (video off) and 8/9 dot clock */
1782 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
1783 /* polarity (-/-), disable access to display memory,
1784 * VGA_CRTC_START_HI base address: color
1786 WGen(cinfo, VGA_MIS_W, 0xc1);
1788 /* "magic cookie" - doesn't make any sense to me.. */
1789 /* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */
1790 /* unlock all extension registers */
1791 vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
1794 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
1796 switch (cinfo->btype) {
1798 vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
1803 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
1806 vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
1807 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);
1811 /* plane mask: nothing */
1812 vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1813 /* character map select: doesn't even matter in gx mode */
1814 vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
1815 /* memory mode: chain-4, no odd/even, ext. memory */
1816 vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0e);
1818 /* controller-internal base address of video memory */
1820 vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);
1822 /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
1823 /* EEPROM control: shouldn't be necessary to write to this at all.. */
1825 /* graphics cursor X position (incomplete; position gives rem. 3 bits */
1826 vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
1827 /* graphics cursor Y position (..."... ) */
1828 vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
1829 /* graphics cursor attributes */
1830 vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
1831 /* graphics cursor pattern address */
1832 vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);
1834 /* writing these on a P4 might give problems.. */
1835 if (cinfo->btype != BT_PICASSO4) {
1836 /* configuration readback and ext. color */
1837 vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
1838 /* signature generator */
1839 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
1842 /* MCLK select etc. */
1844 vga_wseq(cinfo->regbase, CL_SEQR1F, bi->sr1f);
1846 /* Screen A preset row scan: none */
1847 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
1848 /* Text cursor start: disable text cursor */
1849 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
1850 /* Text cursor end: - */
1851 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
1852 /* Screen start address high: 0 */
1853 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, 0x00);
1854 /* Screen start address low: 0 */
1855 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, 0x00);
1856 /* text cursor location high: 0 */
1857 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
1858 /* text cursor location low: 0 */
1859 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);
1861 /* Underline Row scanline: - */
1862 vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
1863 /* mode control: timing enable, byte mode, no compat modes */
1864 vga_wcrt(cinfo->regbase, VGA_CRTC_MODE, 0xc3);
1865 /* Line Compare: not needed */
1866 vga_wcrt(cinfo->regbase, VGA_CRTC_LINE_COMPARE, 0x00);
1867 /* ### add 0x40 for text modes with > 30 MHz pixclock */
1868 /* ext. display controls: ext.adr. wrap */
1869 vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
1871 /* Set/Reset registes: - */
1872 vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);
1873 /* Set/Reset enable: - */
1874 vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);
1875 /* Color Compare: - */
1876 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
1877 /* Data Rotate: - */
1878 vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
1879 /* Read Map Select: - */
1880 vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);
1881 /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
1882 vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);
1883 /* Miscellaneous: memory map base address, graphics mode */
1884 vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);
1885 /* Color Don't care: involve all planes */
1886 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
1887 /* Bit Mask: no mask at all */
1888 vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
1889 if (cinfo->btype == BT_ALPINE)
1890 /* (5434 can't have bit 3 set for bitblt) */
1891 vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
1893 /* Graphics controller mode extensions: finer granularity,
1894 * 8byte data latches
1896 vga_wgfx(cinfo->regbase, CL_GRB, 0x28);
1898 vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
1899 vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
1900 vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
1901 /* Background color byte 1: - */
1902 /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */
1903 /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
1905 /* Attribute Controller palette registers: "identity mapping" */
1906 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);
1907 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
1908 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
1909 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
1910 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
1911 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
1912 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
1913 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
1914 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
1915 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
1916 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
1917 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
1918 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
1919 vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
1920 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
1921 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
1923 /* Attribute Controller mode: graphics mode */
1924 vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);
1925 /* Overscan color reg.: reg. 0 */
1926 vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
1927 /* Color Plane enable: Enable all 4 planes */
1928 vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
1929 /* ### vga_wattr(cinfo->regbase, CL_AR33, 0x00); * Pixel Panning: - */
1930 /* Color Select: - */
1931 vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
1933 WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
1935 if (cinfo->btype != BT_ALPINE && cinfo->btype != BT_GD5480)
1936 /* polarity (-/-), enable display mem,
1937 * VGA_CRTC_START_HI i/o base = color
1939 WGen(cinfo, VGA_MIS_W, 0xc3);
1941 /* BLT Start/status: Blitter reset */
1942 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
1943 /* - " - : "end-of-reset" */
1944 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1947 WHDR(cinfo, 0); /* Hidden DAC register: - */
1953 static void switch_monitor(struct cirrusfb_info *cinfo, int on)
1955 #ifdef CONFIG_ZORRO /* only works on Zorro boards */
1956 static int IsOn = 0; /* XXX not ok for multiple boards */
1960 if (cinfo->btype == BT_PICASSO4)
1961 return; /* nothing to switch */
1962 if (cinfo->btype == BT_ALPINE)
1963 return; /* nothing to switch */
1964 if (cinfo->btype == BT_GD5480)
1965 return; /* nothing to switch */
1966 if (cinfo->btype == BT_PICASSO) {
1967 if ((on && !IsOn) || (!on && IsOn))
1974 switch (cinfo->btype) {
1976 WSFR(cinfo, cinfo->SFR | 0x21);
1979 WSFR(cinfo, cinfo->SFR | 0x28);
1984 default: /* do nothing */ break;
1987 switch (cinfo->btype) {
1989 WSFR(cinfo, cinfo->SFR & 0xde);
1992 WSFR(cinfo, cinfo->SFR & 0xd7);
1997 default: /* do nothing */ break;
2002 #endif /* CONFIG_ZORRO */
2005 /******************************************/
2006 /* Linux 2.6-style accelerated functions */
2007 /******************************************/
2009 static void cirrusfb_fillrect(struct fb_info *info,
2010 const struct fb_fillrect *region)
2012 struct fb_fillrect modded;
2014 struct cirrusfb_info *cinfo = info->par;
2015 int m = info->var.bits_per_pixel;
2016 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
2017 cinfo->pseudo_palette[region->color] : region->color;
2019 if (info->state != FBINFO_STATE_RUNNING)
2021 if (info->flags & FBINFO_HWACCEL_DISABLED) {
2022 cfb_fillrect(info, region);
2026 vxres = info->var.xres_virtual;
2027 vyres = info->var.yres_virtual;
2029 memcpy(&modded, region, sizeof(struct fb_fillrect));
2031 if (!modded.width || !modded.height ||
2032 modded.dx >= vxres || modded.dy >= vyres)
2035 if (modded.dx + modded.width > vxres)
2036 modded.width = vxres - modded.dx;
2037 if (modded.dy + modded.height > vyres)
2038 modded.height = vyres - modded.dy;
2040 cirrusfb_RectFill(cinfo->regbase,
2041 info->var.bits_per_pixel,
2042 (region->dx * m) / 8, region->dy,
2043 (region->width * m) / 8, region->height,
2045 info->fix.line_length);
2048 static void cirrusfb_copyarea(struct fb_info *info,
2049 const struct fb_copyarea *area)
2051 struct fb_copyarea modded;
2053 struct cirrusfb_info *cinfo = info->par;
2054 int m = info->var.bits_per_pixel;
2056 if (info->state != FBINFO_STATE_RUNNING)
2058 if (info->flags & FBINFO_HWACCEL_DISABLED) {
2059 cfb_copyarea(info, area);
2063 vxres = info->var.xres_virtual;
2064 vyres = info->var.yres_virtual;
2065 memcpy(&modded, area, sizeof(struct fb_copyarea));
2067 if (!modded.width || !modded.height ||
2068 modded.sx >= vxres || modded.sy >= vyres ||
2069 modded.dx >= vxres || modded.dy >= vyres)
2072 if (modded.sx + modded.width > vxres)
2073 modded.width = vxres - modded.sx;
2074 if (modded.dx + modded.width > vxres)
2075 modded.width = vxres - modded.dx;
2076 if (modded.sy + modded.height > vyres)
2077 modded.height = vyres - modded.sy;
2078 if (modded.dy + modded.height > vyres)
2079 modded.height = vyres - modded.dy;
2081 cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel,
2082 (area->sx * m) / 8, area->sy,
2083 (area->dx * m) / 8, area->dy,
2084 (area->width * m) / 8, area->height,
2085 info->fix.line_length);
2089 static void cirrusfb_imageblit(struct fb_info *info,
2090 const struct fb_image *image)
2092 struct cirrusfb_info *cinfo = info->par;
2094 cirrusfb_WaitBLT(cinfo->regbase);
2095 cfb_imageblit(info, image);
2098 #ifdef CONFIG_PPC_PREP
2099 #define PREP_VIDEO_BASE ((volatile unsigned long) 0xC0000000)
2100 #define PREP_IO_BASE ((volatile unsigned char *) 0x80000000)
2101 static void get_prep_addrs(unsigned long *display, unsigned long *registers)
2105 *display = PREP_VIDEO_BASE;
2106 *registers = (unsigned long) PREP_IO_BASE;
2111 #endif /* CONFIG_PPC_PREP */
2114 static int release_io_ports;
2116 /* Pulled the logic from XFree86 Cirrus driver to get the memory size,
2117 * based on the DRAM bandwidth bit and DRAM bank switching bit. This
2118 * works with 1MB, 2MB and 4MB configurations (which the Motorola boards
2120 static unsigned int cirrusfb_get_memsize(u8 __iomem *regbase)
2127 SRF = vga_rseq(regbase, CL_SEQRF);
2128 switch ((SRF & 0x18)) {
2135 /* 64-bit DRAM data bus width; assume 2MB. Also indicates 2MB memory
2142 printk(KERN_WARNING "CLgenfb: Unknown memory size!\n");
2146 /* If DRAM bank switching is enabled, there must be twice as much
2147 * memory installed. (4MB on the 5434)
2151 /* TODO: Handling of GD5446/5480 (see XF86 sources ...) */
2157 static void get_pci_addrs(const struct pci_dev *pdev,
2158 unsigned long *display, unsigned long *registers)
2160 assert(pdev != NULL);
2161 assert(display != NULL);
2162 assert(registers != NULL);
2169 /* This is a best-guess for now */
2171 if (pci_resource_flags(pdev, 0) & IORESOURCE_IO) {
2172 *display = pci_resource_start(pdev, 1);
2173 *registers = pci_resource_start(pdev, 0);
2175 *display = pci_resource_start(pdev, 0);
2176 *registers = pci_resource_start(pdev, 1);
2179 assert(*display != 0);
2184 static void cirrusfb_pci_unmap(struct fb_info *info)
2186 struct cirrusfb_info *cinfo = info->par;
2187 struct pci_dev *pdev = cinfo->pdev;
2189 iounmap(info->screen_base);
2190 #if 0 /* if system didn't claim this region, we would... */
2191 release_mem_region(0xA0000, 65535);
2193 if (release_io_ports)
2194 release_region(0x3C0, 32);
2195 pci_release_regions(pdev);
2197 #endif /* CONFIG_PCI */
2200 static void __devexit cirrusfb_zorro_unmap(struct fb_info *info)
2202 struct cirrusfb_info *cinfo = info->par;
2203 zorro_release_device(cinfo->zdev);
2205 if (cinfo->btype == BT_PICASSO4) {
2206 cinfo->regbase -= 0x600000;
2207 iounmap((void *)cinfo->regbase);
2208 iounmap(info->screen_base);
2210 if (zorro_resource_start(cinfo->zdev) > 0x01000000)
2211 iounmap(info->screen_base);
2214 #endif /* CONFIG_ZORRO */
2216 static int cirrusfb_set_fbinfo(struct fb_info *info)
2218 struct cirrusfb_info *cinfo = info->par;
2219 struct fb_var_screeninfo *var = &info->var;
2221 info->pseudo_palette = cinfo->pseudo_palette;
2222 info->flags = FBINFO_DEFAULT
2223 | FBINFO_HWACCEL_XPAN
2224 | FBINFO_HWACCEL_YPAN
2225 | FBINFO_HWACCEL_FILLRECT
2226 | FBINFO_HWACCEL_COPYAREA;
2228 info->flags |= FBINFO_HWACCEL_DISABLED;
2229 info->fbops = &cirrusfb_ops;
2230 if (cinfo->btype == BT_GD5480) {
2231 if (var->bits_per_pixel == 16)
2232 info->screen_base += 1 * MB_;
2233 if (var->bits_per_pixel == 32)
2234 info->screen_base += 2 * MB_;
2237 /* Fill fix common fields */
2238 strlcpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name,
2239 sizeof(info->fix.id));
2241 /* monochrome: only 1 memory plane */
2242 /* 8 bit and above: Use whole memory area */
2243 info->fix.smem_len = info->screen_size;
2244 if (var->bits_per_pixel == 1)
2245 info->fix.smem_len /= 4;
2246 info->fix.type_aux = 0;
2247 info->fix.xpanstep = 1;
2248 info->fix.ypanstep = 1;
2249 info->fix.ywrapstep = 0;
2251 /* FIXME: map region at 0xB8000 if available, fill in here */
2252 info->fix.mmio_len = 0;
2253 info->fix.accel = FB_ACCEL_NONE;
2255 fb_alloc_cmap(&info->cmap, 256, 0);
2260 static int cirrusfb_register(struct fb_info *info)
2262 struct cirrusfb_info *cinfo = info->par;
2264 enum cirrus_board btype;
2268 printk(KERN_INFO "cirrusfb: Driver for Cirrus Logic based "
2269 "graphic boards, v" CIRRUSFB_VERSION "\n");
2271 btype = cinfo->btype;
2274 assert(btype != BT_NONE);
2276 DPRINTK("cirrusfb: (RAM start set to: 0x%p)\n", info->screen_base);
2278 /* Make pretend we've set the var so our structures are in a "good" */
2279 /* state, even though we haven't written the mode to the hw yet... */
2280 info->var = cirrusfb_predefined[cirrusfb_def_mode].var;
2281 info->var.activate = FB_ACTIVATE_NOW;
2283 err = cirrusfb_decode_var(&info->var, &cinfo->currentmode, info);
2285 /* should never happen */
2286 DPRINTK("choking on default var... umm, no good.\n");
2287 goto err_unmap_cirrusfb;
2290 /* set all the vital stuff */
2291 cirrusfb_set_fbinfo(info);
2293 err = register_framebuffer(info);
2295 printk(KERN_ERR "cirrusfb: could not register "
2296 "fb device; err = %d!\n", err);
2297 goto err_dealloc_cmap;
2300 DPRINTK("EXIT, returning 0\n");
2304 fb_dealloc_cmap(&info->cmap);
2307 framebuffer_release(info);
2311 static void __devexit cirrusfb_cleanup(struct fb_info *info)
2313 struct cirrusfb_info *cinfo = info->par;
2316 switch_monitor(cinfo, 0);
2318 unregister_framebuffer(info);
2319 fb_dealloc_cmap(&info->cmap);
2320 printk("Framebuffer unregistered\n");
2322 framebuffer_release(info);
2328 static int cirrusfb_pci_register(struct pci_dev *pdev,
2329 const struct pci_device_id *ent)
2331 struct cirrusfb_info *cinfo;
2332 struct fb_info *info;
2333 enum cirrus_board btype;
2334 unsigned long board_addr, board_size;
2337 ret = pci_enable_device(pdev);
2339 printk(KERN_ERR "cirrusfb: Cannot enable PCI device\n");
2343 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &pdev->dev);
2345 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2352 cinfo->btype = btype = (enum cirrus_board) ent->driver_data;
2354 DPRINTK(" Found PCI device, base address 0 is 0x%x, btype set to %d\n",
2355 pdev->resource[0].start, btype);
2356 DPRINTK(" base address 1 is 0x%x\n", pdev->resource[1].start);
2359 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, 0x00000000);
2360 #ifdef CONFIG_PPC_PREP
2361 get_prep_addrs(&board_addr, &info->fix.mmio_start);
2363 /* PReP dies if we ioremap the IO registers, but it works w/out... */
2364 cinfo->regbase = (char __iomem *) info->fix.mmio_start;
2366 DPRINTK("Attempt to get PCI info for Cirrus Graphics Card\n");
2367 get_pci_addrs(pdev, &board_addr, &info->fix.mmio_start);
2368 /* FIXME: this forces VGA. alternatives? */
2369 cinfo->regbase = NULL;
2372 DPRINTK("Board address: 0x%lx, register address: 0x%lx\n",
2373 board_addr, info->fix.mmio_start);
2375 board_size = (btype == BT_GD5480) ?
2376 32 * MB_ : cirrusfb_get_memsize(cinfo->regbase);
2378 ret = pci_request_regions(pdev, "cirrusfb");
2380 printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, "
2383 goto err_release_fb;
2385 #if 0 /* if the system didn't claim this region, we would... */
2386 if (!request_mem_region(0xA0000, 65535, "cirrusfb")) {
2387 printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, abort\n"
2391 goto err_release_regions;
2394 if (request_region(0x3C0, 32, "cirrusfb"))
2395 release_io_ports = 1;
2397 info->screen_base = ioremap(board_addr, board_size);
2398 if (!info->screen_base) {
2400 goto err_release_legacy;
2403 info->fix.smem_start = board_addr;
2404 info->screen_size = board_size;
2405 cinfo->unmap = cirrusfb_pci_unmap;
2407 printk(KERN_INFO "RAM (%lu kB) at 0x%lx, Cirrus "
2408 "Logic chipset on PCI bus\n",
2409 info->screen_size >> 10, board_addr);
2410 pci_set_drvdata(pdev, info);
2412 ret = cirrusfb_register(info);
2414 iounmap(info->screen_base);
2418 if (release_io_ports)
2419 release_region(0x3C0, 32);
2421 release_mem_region(0xA0000, 65535);
2422 err_release_regions:
2424 pci_release_regions(pdev);
2426 framebuffer_release(info);
2432 static void __devexit cirrusfb_pci_unregister(struct pci_dev *pdev)
2434 struct fb_info *info = pci_get_drvdata(pdev);
2437 cirrusfb_cleanup(info);
2442 static struct pci_driver cirrusfb_pci_driver = {
2444 .id_table = cirrusfb_pci_table,
2445 .probe = cirrusfb_pci_register,
2446 .remove = __devexit_p(cirrusfb_pci_unregister),
2449 .suspend = cirrusfb_pci_suspend,
2450 .resume = cirrusfb_pci_resume,
2454 #endif /* CONFIG_PCI */
2457 static int cirrusfb_zorro_register(struct zorro_dev *z,
2458 const struct zorro_device_id *ent)
2460 struct cirrusfb_info *cinfo;
2461 struct fb_info *info;
2462 enum cirrus_board btype;
2463 struct zorro_dev *z2 = NULL;
2464 unsigned long board_addr, board_size, size;
2467 btype = ent->driver_data;
2468 if (cirrusfb_zorro_table2[btype].id2)
2469 z2 = zorro_find_device(cirrusfb_zorro_table2[btype].id2, NULL);
2470 size = cirrusfb_zorro_table2[btype].size;
2471 printk(KERN_INFO "cirrusfb: %s board detected; ",
2472 cirrusfb_board_info[btype].name);
2474 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev);
2476 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2482 cinfo->btype = btype;
2485 assert(btype != BT_NONE);
2488 board_addr = zorro_resource_start(z);
2489 board_size = zorro_resource_len(z);
2490 info->screen_size = size;
2492 if (!zorro_request_device(z, "cirrusfb")) {
2493 printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, "
2497 goto err_release_fb;
2500 printk(" RAM (%lu MB) at $%lx, ", board_size / MB_, board_addr);
2504 if (btype == BT_PICASSO4) {
2505 printk(KERN_INFO " REG at $%lx\n", board_addr + 0x600000);
2507 /* To be precise, for the P4 this is not the */
2508 /* begin of the board, but the begin of RAM. */
2509 /* for P4, map in its address space in 2 chunks (### TEST! ) */
2510 /* (note the ugly hardcoded 16M number) */
2511 cinfo->regbase = ioremap(board_addr, 16777216);
2512 if (!cinfo->regbase)
2513 goto err_release_region;
2515 DPRINTK("cirrusfb: Virtual address for board set to: $%p\n",
2517 cinfo->regbase += 0x600000;
2518 info->fix.mmio_start = board_addr + 0x600000;
2520 info->fix.smem_start = board_addr + 16777216;
2521 info->screen_base = ioremap(info->fix.smem_start, 16777216);
2522 if (!info->screen_base)
2523 goto err_unmap_regbase;
2525 printk(KERN_INFO " REG at $%lx\n",
2526 (unsigned long) z2->resource.start);
2528 info->fix.smem_start = board_addr;
2529 if (board_addr > 0x01000000)
2530 info->screen_base = ioremap(board_addr, board_size);
2532 info->screen_base = (caddr_t) ZTWO_VADDR(board_addr);
2533 if (!info->screen_base)
2534 goto err_release_region;
2536 /* set address for REG area of board */
2537 cinfo->regbase = (caddr_t) ZTWO_VADDR(z2->resource.start);
2538 info->fix.mmio_start = z2->resource.start;
2540 DPRINTK("cirrusfb: Virtual address for board set to: $%p\n",
2543 cinfo->unmap = cirrusfb_zorro_unmap;
2545 printk(KERN_INFO "Cirrus Logic chipset on Zorro bus\n");
2546 zorro_set_drvdata(z, info);
2548 ret = cirrusfb_register(info);
2550 if (btype == BT_PICASSO4) {
2551 iounmap(info->screen_base);
2552 iounmap(cinfo->regbase - 0x600000);
2553 } else if (board_addr > 0x01000000)
2554 iounmap(info->screen_base);
2559 /* Parental advisory: explicit hack */
2560 iounmap(cinfo->regbase - 0x600000);
2562 release_region(board_addr, board_size);
2564 framebuffer_release(info);
2569 void __devexit cirrusfb_zorro_unregister(struct zorro_dev *z)
2571 struct fb_info *info = zorro_get_drvdata(z);
2574 cirrusfb_cleanup(info);
2579 static struct zorro_driver cirrusfb_zorro_driver = {
2581 .id_table = cirrusfb_zorro_table,
2582 .probe = cirrusfb_zorro_register,
2583 .remove = __devexit_p(cirrusfb_zorro_unregister),
2585 #endif /* CONFIG_ZORRO */
2587 static int __init cirrusfb_init(void)
2592 char *option = NULL;
2594 if (fb_get_options("cirrusfb", &option))
2596 cirrusfb_setup(option);
2600 error |= zorro_register_driver(&cirrusfb_zorro_driver);
2603 error |= pci_register_driver(&cirrusfb_pci_driver);
2609 static int __init cirrusfb_setup(char *options) {
2610 char *this_opt, s[32];
2615 if (!options || !*options)
2618 while ((this_opt = strsep(&options, ",")) != NULL) {
2619 if (!*this_opt) continue;
2621 DPRINTK("cirrusfb_setup: option '%s'\n", this_opt);
2623 for (i = 0; i < NUM_TOTAL_MODES; i++) {
2624 sprintf(s, "mode:%s", cirrusfb_predefined[i].name);
2625 if (strcmp(this_opt, s) == 0)
2626 cirrusfb_def_mode = i;
2628 if (!strcmp(this_opt, "noaccel"))
2639 MODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <jgarzik@pobox.com>");
2640 MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips");
2641 MODULE_LICENSE("GPL");
2643 static void __exit cirrusfb_exit(void)
2646 pci_unregister_driver(&cirrusfb_pci_driver);
2649 zorro_unregister_driver(&cirrusfb_zorro_driver);
2653 module_init(cirrusfb_init);
2656 module_exit(cirrusfb_exit);
2659 /**********************************************************************/
2660 /* about the following functions - I have used the same names for the */
2661 /* functions as Markus Wild did in his Retina driver for NetBSD as */
2662 /* they just made sense for this purpose. Apart from that, I wrote */
2663 /* these functions myself. */
2664 /**********************************************************************/
2666 /*** WGen() - write into one of the external/general registers ***/
2667 static void WGen(const struct cirrusfb_info *cinfo,
2668 int regnum, unsigned char val)
2670 unsigned long regofs = 0;
2672 if (cinfo->btype == BT_PICASSO) {
2673 /* Picasso II specific hack */
2674 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2675 regnum == CL_VSSM2) */
2676 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2680 vga_w(cinfo->regbase, regofs + regnum, val);
2683 /*** RGen() - read out one of the external/general registers ***/
2684 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum)
2686 unsigned long regofs = 0;
2688 if (cinfo->btype == BT_PICASSO) {
2689 /* Picasso II specific hack */
2690 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2691 regnum == CL_VSSM2) */
2692 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2696 return vga_r(cinfo->regbase, regofs + regnum);
2699 /*** AttrOn() - turn on VideoEnable for Attribute controller ***/
2700 static void AttrOn(const struct cirrusfb_info *cinfo)
2702 assert(cinfo != NULL);
2706 if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {
2707 /* if we're just in "write value" mode, write back the */
2708 /* same value as before to not modify anything */
2709 vga_w(cinfo->regbase, VGA_ATT_IW,
2710 vga_r(cinfo->regbase, VGA_ATT_R));
2712 /* turn on video bit */
2713 /* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */
2714 vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);
2716 /* dummy write on Reg0 to be on "write index" mode next time */
2717 vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);
2722 /*** WHDR() - write into the Hidden DAC register ***/
2723 /* as the HDR is the only extension register that requires special treatment
2724 * (the other extension registers are accessible just like the "ordinary"
2725 * registers of their functional group) here is a specialized routine for
2728 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
2730 unsigned char dummy;
2732 if (cinfo->btype == BT_PICASSO) {
2733 /* Klaus' hint for correct access to HDR on some boards */
2734 /* first write 0 to pixel mask (3c6) */
2735 WGen(cinfo, VGA_PEL_MSK, 0x00);
2737 /* next read dummy from pixel address (3c8) */
2738 dummy = RGen(cinfo, VGA_PEL_IW);
2741 /* now do the usual stuff to access the HDR */
2743 dummy = RGen(cinfo, VGA_PEL_MSK);
2745 dummy = RGen(cinfo, VGA_PEL_MSK);
2747 dummy = RGen(cinfo, VGA_PEL_MSK);
2749 dummy = RGen(cinfo, VGA_PEL_MSK);
2752 WGen(cinfo, VGA_PEL_MSK, val);
2755 if (cinfo->btype == BT_PICASSO) {
2756 /* now first reset HDR access counter */
2757 dummy = RGen(cinfo, VGA_PEL_IW);
2760 /* and at the end, restore the mask value */
2761 /* ## is this mask always 0xff? */
2762 WGen(cinfo, VGA_PEL_MSK, 0xff);
2767 /*** WSFR() - write to the "special function register" (SFR) ***/
2768 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val)
2771 assert(cinfo->regbase != NULL);
2773 z_writeb(val, cinfo->regbase + 0x8000);
2777 /* The Picasso has a second register for switching the monitor bit */
2778 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val)
2781 /* writing an arbitrary value to this one causes the monitor switcher */
2782 /* to flip to Amiga display */
2783 assert(cinfo->regbase != NULL);
2785 z_writeb(val, cinfo->regbase + 0x9000);
2789 /*** WClut - set CLUT entry (range: 0..63) ***/
2790 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
2791 unsigned char green, unsigned char blue)
2793 unsigned int data = VGA_PEL_D;
2795 /* address write mode register is not translated.. */
2796 vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
2798 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2799 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2800 /* but DAC data register IS, at least for Picasso II */
2801 if (cinfo->btype == BT_PICASSO)
2803 vga_w(cinfo->regbase, data, red);
2804 vga_w(cinfo->regbase, data, green);
2805 vga_w(cinfo->regbase, data, blue);
2807 vga_w(cinfo->regbase, data, blue);
2808 vga_w(cinfo->regbase, data, green);
2809 vga_w(cinfo->regbase, data, red);
2814 /*** RClut - read CLUT entry (range 0..63) ***/
2815 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
2816 unsigned char *green, unsigned char *blue)
2818 unsigned int data = VGA_PEL_D;
2820 vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
2822 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2823 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2824 if (cinfo->btype == BT_PICASSO)
2826 *red = vga_r(cinfo->regbase, data);
2827 *green = vga_r(cinfo->regbase, data);
2828 *blue = vga_r(cinfo->regbase, data);
2830 *blue = vga_r(cinfo->regbase, data);
2831 *green = vga_r(cinfo->regbase, data);
2832 *red = vga_r(cinfo->regbase, data);
2837 /*******************************************************************
2840 Wait for the BitBLT engine to complete a possible earlier job
2841 *********************************************************************/
2843 /* FIXME: use interrupts instead */
2844 static void cirrusfb_WaitBLT(u8 __iomem *regbase)
2846 /* now busy-wait until we're done */
2847 while (vga_rgfx(regbase, CL_GR31) & 0x08)
2851 /*******************************************************************
2854 perform accelerated "scrolling"
2855 ********************************************************************/
2857 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
2858 u_short curx, u_short cury,
2859 u_short destx, u_short desty,
2860 u_short width, u_short height,
2861 u_short line_length)
2863 u_short nwidth, nheight;
2870 nheight = height - 1;
2873 /* if source adr < dest addr, do the Blt backwards */
2874 if (cury <= desty) {
2875 if (cury == desty) {
2876 /* if src and dest are on the same line, check x */
2883 /* standard case: forward blitting */
2884 nsrc = (cury * line_length) + curx;
2885 ndest = (desty * line_length) + destx;
2887 /* this means start addresses are at the end,
2888 * counting backwards
2890 nsrc = cury * line_length + curx +
2891 nheight * line_length + nwidth;
2892 ndest = desty * line_length + destx +
2893 nheight * line_length + nwidth;
2897 run-down of registers to be programmed:
2905 VGA_GFX_SR_VALUE / VGA_GFX_SR_ENABLE: "fill color"
2909 cirrusfb_WaitBLT(regbase);
2911 /* pitch: set to line_length */
2912 /* dest pitch low */
2913 vga_wgfx(regbase, CL_GR24, line_length & 0xff);
2915 vga_wgfx(regbase, CL_GR25, line_length >> 8);
2916 /* source pitch low */
2917 vga_wgfx(regbase, CL_GR26, line_length & 0xff);
2918 /* source pitch hi */
2919 vga_wgfx(regbase, CL_GR27, line_length >> 8);
2921 /* BLT width: actual number of pixels - 1 */
2923 vga_wgfx(regbase, CL_GR20, nwidth & 0xff);
2925 vga_wgfx(regbase, CL_GR21, nwidth >> 8);
2927 /* BLT height: actual number of lines -1 */
2928 /* BLT height low */
2929 vga_wgfx(regbase, CL_GR22, nheight & 0xff);
2931 vga_wgfx(regbase, CL_GR23, nheight >> 8);
2933 /* BLT destination */
2935 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
2937 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
2939 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
2943 vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff));
2945 vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8));
2947 vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16));
2950 vga_wgfx(regbase, CL_GR30, bltmode); /* BLT mode */
2952 /* BLT ROP: SrcCopy */
2953 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
2955 /* and finally: GO! */
2956 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
2961 /*******************************************************************
2964 perform accelerated rectangle fill
2965 ********************************************************************/
2967 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
2968 u_short x, u_short y, u_short width, u_short height,
2969 u_char color, u_short line_length)
2971 u_short nwidth, nheight;
2978 nheight = height - 1;
2980 ndest = (y * line_length) + x;
2982 cirrusfb_WaitBLT(regbase);
2984 /* pitch: set to line_length */
2985 vga_wgfx(regbase, CL_GR24, line_length & 0xff); /* dest pitch low */
2986 vga_wgfx(regbase, CL_GR25, line_length >> 8); /* dest pitch hi */
2987 vga_wgfx(regbase, CL_GR26, line_length & 0xff); /* source pitch low */
2988 vga_wgfx(regbase, CL_GR27, line_length >> 8); /* source pitch hi */
2990 /* BLT width: actual number of pixels - 1 */
2991 vga_wgfx(regbase, CL_GR20, nwidth & 0xff); /* BLT width low */
2992 vga_wgfx(regbase, CL_GR21, nwidth >> 8); /* BLT width hi */
2994 /* BLT height: actual number of lines -1 */
2995 vga_wgfx(regbase, CL_GR22, nheight & 0xff); /* BLT height low */
2996 vga_wgfx(regbase, CL_GR23, nheight >> 8); /* BLT width hi */
2998 /* BLT destination */
3000 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
3002 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
3004 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
3006 /* BLT source: set to 0 (is a dummy here anyway) */
3007 vga_wgfx(regbase, CL_GR2C, 0x00); /* BLT src low */
3008 vga_wgfx(regbase, CL_GR2D, 0x00); /* BLT src mid */
3009 vga_wgfx(regbase, CL_GR2E, 0x00); /* BLT src hi */
3011 /* This is a ColorExpand Blt, using the */
3012 /* same color for foreground and background */
3013 vga_wgfx(regbase, VGA_GFX_SR_VALUE, color); /* foreground color */
3014 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, color); /* background color */
3017 if (bits_per_pixel == 16) {
3018 vga_wgfx(regbase, CL_GR10, color); /* foreground color */
3019 vga_wgfx(regbase, CL_GR11, color); /* background color */
3022 } else if (bits_per_pixel == 32) {
3023 vga_wgfx(regbase, CL_GR10, color); /* foreground color */
3024 vga_wgfx(regbase, CL_GR11, color); /* background color */
3025 vga_wgfx(regbase, CL_GR12, color); /* foreground color */
3026 vga_wgfx(regbase, CL_GR13, color); /* background color */
3027 vga_wgfx(regbase, CL_GR14, 0); /* foreground color */
3028 vga_wgfx(regbase, CL_GR15, 0); /* background color */
3032 /* BLT mode: color expand, Enable 8x8 copy (faster?) */
3033 vga_wgfx(regbase, CL_GR30, op); /* BLT mode */
3035 /* BLT ROP: SrcCopy */
3036 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
3038 /* and finally: GO! */
3039 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
3044 /**************************************************************************
3045 * bestclock() - determine closest possible clock lower(?) than the
3046 * desired pixel clock
3047 **************************************************************************/
3048 static void bestclock(long freq, long *best, long *nom,
3049 long *den, long *div, long maxfreq)
3053 assert(best != NULL);
3054 assert(nom != NULL);
3055 assert(den != NULL);
3056 assert(div != NULL);
3057 assert(maxfreq > 0);
3074 for (n = 32; n < 128; n++) {
3077 d = (143181 * n) / f;
3078 if ((d >= 7) && (d <= 63)) {
3085 h = ((14318 * n) / temp) >> s;
3086 if (abs(h - freq) < abs(*best - freq)) {
3094 if ((d >= 7) && (d <= 63)) {
3099 h = ((14318 * n) / d) >> s;
3100 if (abs(h - freq) < abs(*best - freq)) {
3109 DPRINTK("Best possible values for given frequency:\n");
3110 DPRINTK(" best: %ld kHz nom: %ld den: %ld div: %ld\n",
3111 freq, *nom, *den, *div);
3116 /* -------------------------------------------------------------------------
3118 * debugging functions
3120 * -------------------------------------------------------------------------
3123 #ifdef CIRRUSFB_DEBUG
3126 * cirrusfb_dbg_print_byte
3127 * @name: name associated with byte value to be displayed
3128 * @val: byte value to be displayed
3131 * Display an indented string, along with a hexidecimal byte value, and
3132 * its decoded bits. Bits 7 through 0 are listed in left-to-right
3137 void cirrusfb_dbg_print_byte(const char *name, unsigned char val)
3139 DPRINTK("%8s = 0x%02X (bits 7-0: %c%c%c%c%c%c%c%c)\n",
3141 val & 0x80 ? '1' : '0',
3142 val & 0x40 ? '1' : '0',
3143 val & 0x20 ? '1' : '0',
3144 val & 0x10 ? '1' : '0',
3145 val & 0x08 ? '1' : '0',
3146 val & 0x04 ? '1' : '0',
3147 val & 0x02 ? '1' : '0',
3148 val & 0x01 ? '1' : '0');
3152 * cirrusfb_dbg_print_regs
3153 * @base: If using newmmio, the newmmio base address, otherwise %NULL
3154 * @reg_class: type of registers to read: %CRT, or %SEQ
3157 * Dumps the given list of VGA CRTC registers. If @base is %NULL,
3158 * old-style I/O ports are queried for information, otherwise MMIO is
3159 * used at the given @base address to query the information.
3163 void cirrusfb_dbg_print_regs(caddr_t regbase,
3164 enum cirrusfb_dbg_reg_class reg_class, ...)
3167 unsigned char val = 0;
3171 va_start(list, reg_class);
3173 name = va_arg(list, char *);
3174 while (name != NULL) {
3175 reg = va_arg(list, int);
3177 switch (reg_class) {
3179 val = vga_rcrt(regbase, (unsigned char) reg);
3182 val = vga_rseq(regbase, (unsigned char) reg);
3185 /* should never occur */
3190 cirrusfb_dbg_print_byte(name, val);
3192 name = va_arg(list, char *);
3205 static void cirrusfb_dump(void)
3207 cirrusfb_dbg_reg_dump(NULL);
3211 * cirrusfb_dbg_reg_dump
3212 * @base: If using newmmio, the newmmio base address, otherwise %NULL
3215 * Dumps a list of interesting VGA and CIRRUSFB registers. If @base is %NULL,
3216 * old-style I/O ports are queried for information, otherwise MMIO is
3217 * used at the given @base address to query the information.
3221 void cirrusfb_dbg_reg_dump(caddr_t regbase)
3223 DPRINTK("CIRRUSFB VGA CRTC register dump:\n");
3225 cirrusfb_dbg_print_regs(regbase, CRT,
3277 DPRINTK("CIRRUSFB VGA SEQ register dump:\n");
3279 cirrusfb_dbg_print_regs(regbase, SEQ,
3311 #endif /* CIRRUSFB_DEBUG */