[ACPI] Merge acpi-2.6.12 branch into 2.6.13-rc3
[linux-2.6] / drivers / serial / jsm / jsm_neo.c
1 /************************************************************************
2  * Copyright 2003 Digi International (www.digi.com)
3  *
4  * Copyright (C) 2004 IBM Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2, or (at your option)
9  * any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
13  * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
14  * PURPOSE.  See the GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 * Temple Place - Suite 330, Boston,
19  * MA  02111-1307, USA.
20  *
21  * Contact Information:
22  * Scott H Kilau <Scott_Kilau@digi.com>
23  * Wendy Xiong   <wendyx@us.ltcfwd.linux.ibm.com>
24  *
25  ***********************************************************************/
26 #include <linux/delay.h>        /* For udelay */
27 #include <linux/serial_reg.h>   /* For the various UART offsets */
28 #include <linux/tty.h>
29 #include <linux/pci.h>
30 #include <asm/io.h>
31
32 #include "jsm.h"                /* Driver main header file */
33
34 static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
35
36 /*
37  * This function allows calls to ensure that all outstanding
38  * PCI writes have been completed, by doing a PCI read against
39  * a non-destructive, read-only location on the Neo card.
40  *
41  * In this case, we are reading the DVID (Read-only Device Identification)
42  * value of the Neo card.
43  */
44 static inline void neo_pci_posting_flush(struct jsm_board *bd)
45 {
46       readb(bd->re_map_membase + 0x8D);
47 }
48
49 static void neo_set_cts_flow_control(struct jsm_channel *ch)
50 {
51         u8 ier, efr;
52         ier = readb(&ch->ch_neo_uart->ier);
53         efr = readb(&ch->ch_neo_uart->efr);
54
55         jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n");
56
57         /* Turn on auto CTS flow control */
58         ier |= (UART_17158_IER_CTSDSR);
59         efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
60
61         /* Turn off auto Xon flow control */
62         efr &= ~(UART_17158_EFR_IXON);
63
64         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
65         writeb(0, &ch->ch_neo_uart->efr);
66
67         /* Turn on UART enhanced bits */
68         writeb(efr, &ch->ch_neo_uart->efr);
69
70         /* Turn on table D, with 8 char hi/low watermarks */
71         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
72
73         /* Feed the UART our trigger levels */
74         writeb(8, &ch->ch_neo_uart->tfifo);
75         ch->ch_t_tlevel = 8;
76
77         writeb(ier, &ch->ch_neo_uart->ier);
78 }
79
80 static void neo_set_rts_flow_control(struct jsm_channel *ch)
81 {
82         u8 ier, efr;
83         ier = readb(&ch->ch_neo_uart->ier);
84         efr = readb(&ch->ch_neo_uart->efr);
85
86         jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n");
87
88         /* Turn on auto RTS flow control */
89         ier |= (UART_17158_IER_RTSDTR);
90         efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
91
92         /* Turn off auto Xoff flow control */
93         ier &= ~(UART_17158_IER_XOFF);
94         efr &= ~(UART_17158_EFR_IXOFF);
95
96         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
97         writeb(0, &ch->ch_neo_uart->efr);
98
99         /* Turn on UART enhanced bits */
100         writeb(efr, &ch->ch_neo_uart->efr);
101
102         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
103         ch->ch_r_watermark = 4;
104
105         writeb(56, &ch->ch_neo_uart->rfifo);
106         ch->ch_r_tlevel = 56;
107
108         writeb(ier, &ch->ch_neo_uart->ier);
109
110         /*
111          * From the Neo UART spec sheet:
112          * The auto RTS/DTR function must be started by asserting
113          * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
114          * it is enabled.
115          */
116         ch->ch_mostat |= (UART_MCR_RTS);
117 }
118
119
120 static void neo_set_ixon_flow_control(struct jsm_channel *ch)
121 {
122         u8 ier, efr;
123         ier = readb(&ch->ch_neo_uart->ier);
124         efr = readb(&ch->ch_neo_uart->efr);
125
126         jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n");
127
128         /* Turn off auto CTS flow control */
129         ier &= ~(UART_17158_IER_CTSDSR);
130         efr &= ~(UART_17158_EFR_CTSDSR);
131
132         /* Turn on auto Xon flow control */
133         efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
134
135         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
136         writeb(0, &ch->ch_neo_uart->efr);
137
138         /* Turn on UART enhanced bits */
139         writeb(efr, &ch->ch_neo_uart->efr);
140
141         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
142         ch->ch_r_watermark = 4;
143
144         writeb(32, &ch->ch_neo_uart->rfifo);
145         ch->ch_r_tlevel = 32;
146
147         /* Tell UART what start/stop chars it should be looking for */
148         writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
149         writeb(0, &ch->ch_neo_uart->xonchar2);
150
151         writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
152         writeb(0, &ch->ch_neo_uart->xoffchar2);
153
154         writeb(ier, &ch->ch_neo_uart->ier);
155 }
156
157 static void neo_set_ixoff_flow_control(struct jsm_channel *ch)
158 {
159         u8 ier, efr;
160         ier = readb(&ch->ch_neo_uart->ier);
161         efr = readb(&ch->ch_neo_uart->efr);
162
163         jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n");
164
165         /* Turn off auto RTS flow control */
166         ier &= ~(UART_17158_IER_RTSDTR);
167         efr &= ~(UART_17158_EFR_RTSDTR);
168
169         /* Turn on auto Xoff flow control */
170         ier |= (UART_17158_IER_XOFF);
171         efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
172
173         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
174         writeb(0, &ch->ch_neo_uart->efr);
175
176         /* Turn on UART enhanced bits */
177         writeb(efr, &ch->ch_neo_uart->efr);
178
179         /* Turn on table D, with 8 char hi/low watermarks */
180         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
181
182         writeb(8, &ch->ch_neo_uart->tfifo);
183         ch->ch_t_tlevel = 8;
184
185         /* Tell UART what start/stop chars it should be looking for */
186         writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
187         writeb(0, &ch->ch_neo_uart->xonchar2);
188
189         writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
190         writeb(0, &ch->ch_neo_uart->xoffchar2);
191
192         writeb(ier, &ch->ch_neo_uart->ier);
193 }
194
195 static void neo_set_no_input_flow_control(struct jsm_channel *ch)
196 {
197         u8 ier, efr;
198         ier = readb(&ch->ch_neo_uart->ier);
199         efr = readb(&ch->ch_neo_uart->efr);
200
201         jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n");
202
203         /* Turn off auto RTS flow control */
204         ier &= ~(UART_17158_IER_RTSDTR);
205         efr &= ~(UART_17158_EFR_RTSDTR);
206
207         /* Turn off auto Xoff flow control */
208         ier &= ~(UART_17158_IER_XOFF);
209         if (ch->ch_c_iflag & IXON)
210                 efr &= ~(UART_17158_EFR_IXOFF);
211         else
212                 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
213
214         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
215         writeb(0, &ch->ch_neo_uart->efr);
216
217         /* Turn on UART enhanced bits */
218         writeb(efr, &ch->ch_neo_uart->efr);
219
220         /* Turn on table D, with 8 char hi/low watermarks */
221         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
222
223         ch->ch_r_watermark = 0;
224
225         writeb(16, &ch->ch_neo_uart->tfifo);
226         ch->ch_t_tlevel = 16;
227
228         writeb(16, &ch->ch_neo_uart->rfifo);
229         ch->ch_r_tlevel = 16;
230
231         writeb(ier, &ch->ch_neo_uart->ier);
232 }
233
234 static void neo_set_no_output_flow_control(struct jsm_channel *ch)
235 {
236         u8 ier, efr;
237         ier = readb(&ch->ch_neo_uart->ier);
238         efr = readb(&ch->ch_neo_uart->efr);
239
240         jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n");
241
242         /* Turn off auto CTS flow control */
243         ier &= ~(UART_17158_IER_CTSDSR);
244         efr &= ~(UART_17158_EFR_CTSDSR);
245
246         /* Turn off auto Xon flow control */
247         if (ch->ch_c_iflag & IXOFF)
248                 efr &= ~(UART_17158_EFR_IXON);
249         else
250                 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
251
252         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
253         writeb(0, &ch->ch_neo_uart->efr);
254
255         /* Turn on UART enhanced bits */
256         writeb(efr, &ch->ch_neo_uart->efr);
257
258         /* Turn on table D, with 8 char hi/low watermarks */
259         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
260
261         ch->ch_r_watermark = 0;
262
263         writeb(16, &ch->ch_neo_uart->tfifo);
264         ch->ch_t_tlevel = 16;
265
266         writeb(16, &ch->ch_neo_uart->rfifo);
267         ch->ch_r_tlevel = 16;
268
269         writeb(ier, &ch->ch_neo_uart->ier);
270 }
271
272 static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch)
273 {
274
275         /* if hardware flow control is set, then skip this whole thing */
276         if (ch->ch_c_cflag & CRTSCTS)
277                 return;
278
279         jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "start\n");
280
281         /* Tell UART what start/stop chars it should be looking for */
282         writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
283         writeb(0, &ch->ch_neo_uart->xonchar2);
284
285         writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
286         writeb(0, &ch->ch_neo_uart->xoffchar2);
287 }
288
289 static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch)
290 {
291         int qleft = 0;
292         u8 linestatus = 0;
293         u8 error_mask = 0;
294         int n = 0;
295         int total = 0;
296         u16 head;
297         u16 tail;
298
299         if (!ch)
300                 return;
301
302         /* cache head and tail of queue */
303         head = ch->ch_r_head & RQUEUEMASK;
304         tail = ch->ch_r_tail & RQUEUEMASK;
305
306         /* Get our cached LSR */
307         linestatus = ch->ch_cached_lsr;
308         ch->ch_cached_lsr = 0;
309
310         /* Store how much space we have left in the queue */
311         if ((qleft = tail - head - 1) < 0)
312                 qleft += RQUEUEMASK + 1;
313
314         /*
315          * If the UART is not in FIFO mode, force the FIFO copy to
316          * NOT be run, by setting total to 0.
317          *
318          * On the other hand, if the UART IS in FIFO mode, then ask
319          * the UART to give us an approximation of data it has RX'ed.
320          */
321         if (!(ch->ch_flags & CH_FIFO_ENABLED))
322                 total = 0;
323         else {
324                 total = readb(&ch->ch_neo_uart->rfifo);
325
326                 /*
327                  * EXAR chip bug - RX FIFO COUNT - Fudge factor.
328                  *
329                  * This resolves a problem/bug with the Exar chip that sometimes
330                  * returns a bogus value in the rfifo register.
331                  * The count can be any where from 0-3 bytes "off".
332                  * Bizarre, but true.
333                  */
334                 total -= 3;
335         }
336
337         /*
338          * Finally, bound the copy to make sure we don't overflow
339          * our own queue...
340          * The byte by byte copy loop below this loop this will
341          * deal with the queue overflow possibility.
342          */
343         total = min(total, qleft);
344
345         while (total > 0) {
346                 /*
347                  * Grab the linestatus register, we need to check
348                  * to see if there are any errors in the FIFO.
349                  */
350                 linestatus = readb(&ch->ch_neo_uart->lsr);
351
352                 /*
353                  * Break out if there is a FIFO error somewhere.
354                  * This will allow us to go byte by byte down below,
355                  * finding the exact location of the error.
356                  */
357                 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
358                         break;
359
360                 /* Make sure we don't go over the end of our queue */
361                 n = min(((u32) total), (RQUEUESIZE - (u32) head));
362
363                 /*
364                  * Cut down n even further if needed, this is to fix
365                  * a problem with memcpy_fromio() with the Neo on the
366                  * IBM pSeries platform.
367                  * 15 bytes max appears to be the magic number.
368                  */
369                 n = min((u32) n, (u32) 12);
370
371                 /*
372                  * Since we are grabbing the linestatus register, which
373                  * will reset some bits after our read, we need to ensure
374                  * we don't miss our TX FIFO emptys.
375                  */
376                 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
377                         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
378
379                 linestatus = 0;
380
381                 /* Copy data from uart to the queue */
382                 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
383                 /*
384                  * Since RX_FIFO_DATA_ERROR was 0, we are guarenteed
385                  * that all the data currently in the FIFO is free of
386                  * breaks and parity/frame/orun errors.
387                  */
388                 memset(ch->ch_equeue + head, 0, n);
389
390                 /* Add to and flip head if needed */
391                 head = (head + n) & RQUEUEMASK;
392                 total -= n;
393                 qleft -= n;
394                 ch->ch_rxcount += n;
395         }
396
397         /*
398          * Create a mask to determine whether we should
399          * insert the character (if any) into our queue.
400          */
401         if (ch->ch_c_iflag & IGNBRK)
402                 error_mask |= UART_LSR_BI;
403
404         /*
405          * Now cleanup any leftover bytes still in the UART.
406          * Also deal with any possible queue overflow here as well.
407          */
408         while (1) {
409
410                 /*
411                  * Its possible we have a linestatus from the loop above
412                  * this, so we "OR" on any extra bits.
413                  */
414                 linestatus |= readb(&ch->ch_neo_uart->lsr);
415
416                 /*
417                  * If the chip tells us there is no more data pending to
418                  * be read, we can then leave.
419                  * But before we do, cache the linestatus, just in case.
420                  */
421                 if (!(linestatus & UART_LSR_DR)) {
422                         ch->ch_cached_lsr = linestatus;
423                         break;
424                 }
425
426                 /* No need to store this bit */
427                 linestatus &= ~UART_LSR_DR;
428
429                 /*
430                  * Since we are grabbing the linestatus register, which
431                  * will reset some bits after our read, we need to ensure
432                  * we don't miss our TX FIFO emptys.
433                  */
434                 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
435                         linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
436                         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
437                 }
438
439                 /*
440                  * Discard character if we are ignoring the error mask.
441                  */
442                 if (linestatus & error_mask) {
443                         u8 discard;
444                         linestatus = 0;
445                         memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
446                         continue;
447                 }
448
449                 /*
450                  * If our queue is full, we have no choice but to drop some data.
451                  * The assumption is that HWFLOW or SWFLOW should have stopped
452                  * things way way before we got to this point.
453                  *
454                  * I decided that I wanted to ditch the oldest data first,
455                  * I hope thats okay with everyone? Yes? Good.
456                  */
457                 while (qleft < 1) {
458                         jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
459                                 "Queue full, dropping DATA:%x LSR:%x\n",
460                                 ch->ch_rqueue[tail], ch->ch_equeue[tail]);
461
462                         ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
463                         ch->ch_err_overrun++;
464                         qleft++;
465                 }
466
467                 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
468                 ch->ch_equeue[head] = (u8) linestatus;
469
470                 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
471                                 "DATA/LSR pair: %x %x\n", ch->ch_rqueue[head], ch->ch_equeue[head]);
472
473                 /* Ditch any remaining linestatus value. */
474                 linestatus = 0;
475
476                 /* Add to and flip head if needed */
477                 head = (head + 1) & RQUEUEMASK;
478
479                 qleft--;
480                 ch->ch_rxcount++;
481         }
482
483         /*
484          * Write new final heads to channel structure.
485          */
486         ch->ch_r_head = head & RQUEUEMASK;
487         ch->ch_e_head = head & EQUEUEMASK;
488         jsm_input(ch);
489 }
490
491 static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch)
492 {
493         u16 head;
494         u16 tail;
495         int n;
496         int s;
497         int qlen;
498         u32 len_written = 0;
499
500         if (!ch)
501                 return;
502
503         /* No data to write to the UART */
504         if (ch->ch_w_tail == ch->ch_w_head)
505                 return;
506
507         /* If port is "stopped", don't send any data to the UART */
508         if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))
509                 return;
510         /*
511          * If FIFOs are disabled. Send data directly to txrx register
512          */
513         if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
514                 u8 lsrbits = readb(&ch->ch_neo_uart->lsr);
515
516                 ch->ch_cached_lsr |= lsrbits;
517                 if (ch->ch_cached_lsr & UART_LSR_THRE) {
518                         ch->ch_cached_lsr &= ~(UART_LSR_THRE);
519
520                         writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_neo_uart->txrx);
521                         jsm_printk(WRITE, INFO, &ch->ch_bd->pci_dev,
522                                         "Tx data: %x\n", ch->ch_wqueue[ch->ch_w_head]);
523                         ch->ch_w_tail++;
524                         ch->ch_w_tail &= WQUEUEMASK;
525                         ch->ch_txcount++;
526                 }
527                 return;
528         }
529
530         /*
531          * We have to do it this way, because of the EXAR TXFIFO count bug.
532          */
533         if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
534                 return;
535
536         len_written = 0;
537         n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
538
539         /* cache head and tail of queue */
540         head = ch->ch_w_head & WQUEUEMASK;
541         tail = ch->ch_w_tail & WQUEUEMASK;
542         qlen = (head - tail) & WQUEUEMASK;
543
544         /* Find minimum of the FIFO space, versus queue length */
545         n = min(n, qlen);
546
547         while (n > 0) {
548
549                 s = ((head >= tail) ? head : WQUEUESIZE) - tail;
550                 s = min(s, n);
551
552                 if (s <= 0)
553                         break;
554
555                 memcpy_toio(&ch->ch_neo_uart->txrxburst, ch->ch_wqueue + tail, s);
556                 /* Add and flip queue if needed */
557                 tail = (tail + s) & WQUEUEMASK;
558                 n -= s;
559                 ch->ch_txcount += s;
560                 len_written += s;
561         }
562
563         /* Update the final tail */
564         ch->ch_w_tail = tail & WQUEUEMASK;
565
566         if (len_written >= ch->ch_t_tlevel)
567                 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
568
569         if (!jsm_tty_write(&ch->uart_port))
570                 uart_write_wakeup(&ch->uart_port);
571 }
572
573 static void neo_parse_modem(struct jsm_channel *ch, u8 signals)
574 {
575         u8 msignals = signals;
576
577         jsm_printk(MSIGS, INFO, &ch->ch_bd->pci_dev,
578                         "neo_parse_modem: port: %d msignals: %x\n", ch->ch_portnum, msignals);
579
580         if (!ch)
581                 return;
582
583         /* Scrub off lower bits. They signify delta's, which I don't care about */
584         msignals &= 0xf0;
585
586         if (msignals & UART_MSR_DCD)
587                 ch->ch_mistat |= UART_MSR_DCD;
588         else
589                 ch->ch_mistat &= ~UART_MSR_DCD;
590
591         if (msignals & UART_MSR_DSR)
592                 ch->ch_mistat |= UART_MSR_DSR;
593         else
594                 ch->ch_mistat &= ~UART_MSR_DSR;
595
596         if (msignals & UART_MSR_RI)
597                 ch->ch_mistat |= UART_MSR_RI;
598         else
599                 ch->ch_mistat &= ~UART_MSR_RI;
600
601         if (msignals & UART_MSR_CTS)
602                 ch->ch_mistat |= UART_MSR_CTS;
603         else
604                 ch->ch_mistat &= ~UART_MSR_CTS;
605
606         jsm_printk(MSIGS, INFO, &ch->ch_bd->pci_dev,
607                         "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
608                 ch->ch_portnum,
609                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
610                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
611                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
612                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
613                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
614                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));
615 }
616
617 /* Make the UART raise any of the output signals we want up */
618 static void neo_assert_modem_signals(struct jsm_channel *ch)
619 {
620         u8 out;
621
622         if (!ch)
623                 return;
624
625         out = ch->ch_mostat;
626
627         writeb(out, &ch->ch_neo_uart->mcr);
628
629         /* flush write operation */
630         neo_pci_posting_flush(ch->ch_bd);
631 }
632
633 /*
634  * Flush the WRITE FIFO on the Neo.
635  *
636  * NOTE: Channel lock MUST be held before calling this function!
637  */
638 static void neo_flush_uart_write(struct jsm_channel *ch)
639 {
640         u8 tmp = 0;
641         int i = 0;
642
643         if (!ch)
644                 return;
645
646         writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
647
648         for (i = 0; i < 10; i++) {
649
650                 /* Check to see if the UART feels it completely flushed the FIFO. */
651                 tmp = readb(&ch->ch_neo_uart->isr_fcr);
652                 if (tmp & 4) {
653                         jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev,
654                                         "Still flushing TX UART... i: %d\n", i);
655                         udelay(10);
656                 }
657                 else
658                         break;
659         }
660
661         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
662 }
663
664
665 /*
666  * Flush the READ FIFO on the Neo.
667  *
668  * NOTE: Channel lock MUST be held before calling this function!
669  */
670 static void neo_flush_uart_read(struct jsm_channel *ch)
671 {
672         u8 tmp = 0;
673         int i = 0;
674
675         if (!ch)
676                 return;
677
678         writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
679
680         for (i = 0; i < 10; i++) {
681
682                 /* Check to see if the UART feels it completely flushed the FIFO. */
683                 tmp = readb(&ch->ch_neo_uart->isr_fcr);
684                 if (tmp & 2) {
685                         jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev,
686                                         "Still flushing RX UART... i: %d\n", i);
687                         udelay(10);
688                 }
689                 else
690                         break;
691         }
692 }
693
694 /*
695  * No locks are assumed to be held when calling this function.
696  */
697 static void neo_clear_break(struct jsm_channel *ch, int force)
698 {
699         unsigned long lock_flags;
700
701         spin_lock_irqsave(&ch->ch_lock, lock_flags);
702
703         /* Turn break off, and unset some variables */
704         if (ch->ch_flags & CH_BREAK_SENDING) {
705                 u8 temp = readb(&ch->ch_neo_uart->lcr);
706                 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
707
708                 ch->ch_flags &= ~(CH_BREAK_SENDING);
709                 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev,
710                                 "clear break Finishing UART_LCR_SBC! finished: %lx\n", jiffies);
711
712                 /* flush write operation */
713                 neo_pci_posting_flush(ch->ch_bd);
714         }
715         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
716 }
717
718 /*
719  * Parse the ISR register.
720  */
721 static inline void neo_parse_isr(struct jsm_board *brd, u32 port)
722 {
723         struct jsm_channel *ch;
724         u8 isr;
725         u8 cause;
726         unsigned long lock_flags;
727
728         if (!brd)
729                 return;
730
731         if (port > brd->maxports)
732                 return;
733
734         ch = brd->channels[port];
735         if (!ch)
736                 return;
737
738         /* Here we try to figure out what caused the interrupt to happen */
739         while (1) {
740
741                 isr = readb(&ch->ch_neo_uart->isr_fcr);
742
743                 /* Bail if no pending interrupt */
744                 if (isr & UART_IIR_NO_INT)
745                         break;
746
747                 /*
748                  * Yank off the upper 2 bits, which just show that the FIFO's are enabled.
749                  */
750                 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
751
752                 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
753                                 "%s:%d isr: %x\n", __FILE__, __LINE__, isr);
754
755                 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
756                         /* Read data from uart -> queue */
757                         neo_copy_data_from_uart_to_queue(ch);
758
759                         /* Call our tty layer to enforce queue flow control if needed. */
760                         spin_lock_irqsave(&ch->ch_lock, lock_flags);
761                         jsm_check_queue_flow_control(ch);
762                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
763                 }
764
765                 if (isr & UART_IIR_THRI) {
766                         /* Transfer data (if any) from Write Queue -> UART. */
767                         spin_lock_irqsave(&ch->ch_lock, lock_flags);
768                         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
769                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
770                         neo_copy_data_from_queue_to_uart(ch);
771                 }
772
773                 if (isr & UART_17158_IIR_XONXOFF) {
774                         cause = readb(&ch->ch_neo_uart->xoffchar1);
775
776                         jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
777                                         "Port %d. Got ISR_XONXOFF: cause:%x\n", port, cause);
778
779                         /*
780                          * Since the UART detected either an XON or
781                          * XOFF match, we need to figure out which
782                          * one it was, so we can suspend or resume data flow.
783                          */
784                         spin_lock_irqsave(&ch->ch_lock, lock_flags);
785                         if (cause == UART_17158_XON_DETECT) {
786                                 /* Is output stopped right now, if so, resume it */
787                                 if (brd->channels[port]->ch_flags & CH_STOP) {
788                                         ch->ch_flags &= ~(CH_STOP);
789                                 }
790                                 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
791                                                 "Port %d. XON detected in incoming data\n", port);
792                         }
793                         else if (cause == UART_17158_XOFF_DETECT) {
794                                 if (!(brd->channels[port]->ch_flags & CH_STOP)) {
795                                         ch->ch_flags |= CH_STOP;
796                                         jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
797                                                         "Setting CH_STOP\n");
798                                 }
799                                 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
800                                                 "Port: %d. XOFF detected in incoming data\n", port);
801                         }
802                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
803                 }
804
805                 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
806                         /*
807                          * If we get here, this means the hardware is doing auto flow control.
808                          * Check to see whether RTS/DTR or CTS/DSR caused this interrupt.
809                          */
810                         cause = readb(&ch->ch_neo_uart->mcr);
811
812                         /* Which pin is doing auto flow? RTS or DTR? */
813                         spin_lock_irqsave(&ch->ch_lock, lock_flags);
814                         if ((cause & 0x4) == 0) {
815                                 if (cause & UART_MCR_RTS)
816                                         ch->ch_mostat |= UART_MCR_RTS;
817                                 else
818                                         ch->ch_mostat &= ~(UART_MCR_RTS);
819                         } else {
820                                 if (cause & UART_MCR_DTR)
821                                         ch->ch_mostat |= UART_MCR_DTR;
822                                 else
823                                         ch->ch_mostat &= ~(UART_MCR_DTR);
824                         }
825                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
826                 }
827
828                 /* Parse any modem signal changes */
829                 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
830                                 "MOD_STAT: sending to parse_modem_sigs\n");
831                 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
832         }
833 }
834
835 static inline void neo_parse_lsr(struct jsm_board *brd, u32 port)
836 {
837         struct jsm_channel *ch;
838         int linestatus;
839         unsigned long lock_flags;
840
841         if (!brd)
842                 return;
843
844         if (port > brd->maxports)
845                 return;
846
847         ch = brd->channels[port];
848         if (!ch)
849                 return;
850
851         linestatus = readb(&ch->ch_neo_uart->lsr);
852
853         jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
854                         "%s:%d port: %d linestatus: %x\n", __FILE__, __LINE__, port, linestatus);
855
856         ch->ch_cached_lsr |= linestatus;
857
858         if (ch->ch_cached_lsr & UART_LSR_DR) {
859                 /* Read data from uart -> queue */
860                 neo_copy_data_from_uart_to_queue(ch);
861                 spin_lock_irqsave(&ch->ch_lock, lock_flags);
862                 jsm_check_queue_flow_control(ch);
863                 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
864         }
865
866         /*
867          * This is a special flag. It indicates that at least 1
868          * RX error (parity, framing, or break) has happened.
869          * Mark this in our struct, which will tell me that I have
870          *to do the special RX+LSR read for this FIFO load.
871          */
872         if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
873                 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
874                         "%s:%d Port: %d Got an RX error, need to parse LSR\n",
875                         __FILE__, __LINE__, port);
876
877         /*
878          * The next 3 tests should *NOT* happen, as the above test
879          * should encapsulate all 3... At least, thats what Exar says.
880          */
881
882         if (linestatus & UART_LSR_PE) {
883                 ch->ch_err_parity++;
884                 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
885                         "%s:%d Port: %d. PAR ERR!\n", __FILE__, __LINE__, port);
886         }
887
888         if (linestatus & UART_LSR_FE) {
889                 ch->ch_err_frame++;
890                 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
891                         "%s:%d Port: %d. FRM ERR!\n", __FILE__, __LINE__, port);
892         }
893
894         if (linestatus & UART_LSR_BI) {
895                 ch->ch_err_break++;
896                 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
897                         "%s:%d Port: %d. BRK INTR!\n", __FILE__, __LINE__, port);
898         }
899
900         if (linestatus & UART_LSR_OE) {
901                 /*
902                  * Rx Oruns. Exar says that an orun will NOT corrupt
903                  * the FIFO. It will just replace the holding register
904                  * with this new data byte. So basically just ignore this.
905                  * Probably we should eventually have an orun stat in our driver...
906                  */
907                 ch->ch_err_overrun++;
908                 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
909                         "%s:%d Port: %d. Rx Overrun!\n", __FILE__, __LINE__, port);
910         }
911
912         if (linestatus & UART_LSR_THRE) {
913                 spin_lock_irqsave(&ch->ch_lock, lock_flags);
914                 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
915                 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
916
917                 /* Transfer data (if any) from Write Queue -> UART. */
918                 neo_copy_data_from_queue_to_uart(ch);
919         }
920         else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
921                 spin_lock_irqsave(&ch->ch_lock, lock_flags);
922                 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
923                 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
924
925                 /* Transfer data (if any) from Write Queue -> UART. */
926                 neo_copy_data_from_queue_to_uart(ch);
927         }
928 }
929
930 /*
931  * neo_param()
932  * Send any/all changes to the line to the UART.
933  */
934 static void neo_param(struct jsm_channel *ch)
935 {
936         u8 lcr = 0;
937         u8 uart_lcr = 0;
938         u8 ier = 0;
939         u32 baud = 9600;
940         int quot = 0;
941         struct jsm_board *bd;
942
943         bd = ch->ch_bd;
944         if (!bd)
945                 return;
946
947         /*
948          * If baud rate is zero, flush queues, and set mval to drop DTR.
949          */
950         if ((ch->ch_c_cflag & (CBAUD)) == 0) {
951                 ch->ch_r_head = ch->ch_r_tail = 0;
952                 ch->ch_e_head = ch->ch_e_tail = 0;
953                 ch->ch_w_head = ch->ch_w_tail = 0;
954
955                 neo_flush_uart_write(ch);
956                 neo_flush_uart_read(ch);
957
958                 ch->ch_flags |= (CH_BAUD0);
959                 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
960                 neo_assert_modem_signals(ch);
961                 ch->ch_old_baud = 0;
962                 return;
963
964         } else if (ch->ch_custom_speed) {
965                         baud = ch->ch_custom_speed;
966                         if (ch->ch_flags & CH_BAUD0)
967                                 ch->ch_flags &= ~(CH_BAUD0);
968                 } else {
969                         int iindex = 0;
970                         int jindex = 0;
971
972                         const u64 bauds[4][16] = {
973                                 {
974                                         0,      50,     75,     110,
975                                         134,    150,    200,    300,
976                                         600,    1200,   1800,   2400,
977                                         4800,   9600,   19200,  38400 },
978                                 {
979                                         0,      57600,  115200, 230400,
980                                         460800, 150,    200,    921600,
981                                         600,    1200,   1800,   2400,
982                                         4800,   9600,   19200,  38400 },
983                                 {
984                                         0,      57600,  76800, 115200,
985                                         131657, 153600, 230400, 460800,
986                                         921600, 1200,   1800,   2400,
987                                         4800,   9600,   19200,  38400 },
988                                 {
989                                         0,      57600,  115200, 230400,
990                                         460800, 150,    200,    921600,
991                                         600,    1200,   1800,   2400,
992                                         4800,   9600,   19200,  38400 }
993                         };
994
995                         baud = C_BAUD(ch->uart_port.info->tty) & 0xff;
996
997                         if (ch->ch_c_cflag & CBAUDEX)
998                                 iindex = 1;
999
1000                         jindex = baud;
1001
1002                         if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) && (jindex < 16))
1003                                 baud = bauds[iindex][jindex];
1004                         else {
1005                                 jsm_printk(IOCTL, DEBUG, &ch->ch_bd->pci_dev,
1006                                         "baud indices were out of range (%d)(%d)",
1007                                 iindex, jindex);
1008                                 baud = 0;
1009                         }
1010
1011                         if (baud == 0)
1012                                 baud = 9600;
1013
1014                         if (ch->ch_flags & CH_BAUD0)
1015                                 ch->ch_flags &= ~(CH_BAUD0);
1016                 }
1017
1018         if (ch->ch_c_cflag & PARENB)
1019                 lcr |= UART_LCR_PARITY;
1020
1021         if (!(ch->ch_c_cflag & PARODD))
1022                 lcr |= UART_LCR_EPAR;
1023
1024         /*
1025          * Not all platforms support mark/space parity,
1026          * so this will hide behind an ifdef.
1027          */
1028 #ifdef CMSPAR
1029         if (ch->ch_c_cflag & CMSPAR)
1030                 lcr |= UART_LCR_SPAR;
1031 #endif
1032
1033         if (ch->ch_c_cflag & CSTOPB)
1034                 lcr |= UART_LCR_STOP;
1035
1036         switch (ch->ch_c_cflag & CSIZE) {
1037                 case CS5:
1038                         lcr |= UART_LCR_WLEN5;
1039                         break;
1040                 case CS6:
1041                         lcr |= UART_LCR_WLEN6;
1042                         break;
1043                 case CS7:
1044                         lcr |= UART_LCR_WLEN7;
1045                         break;
1046                 case CS8:
1047                 default:
1048                         lcr |= UART_LCR_WLEN8;
1049                 break;
1050         }
1051
1052         ier = readb(&ch->ch_neo_uart->ier);
1053         uart_lcr = readb(&ch->ch_neo_uart->lcr);
1054
1055         if (baud == 0)
1056                 baud = 9600;
1057
1058         quot = ch->ch_bd->bd_dividend / baud;
1059
1060         if (quot != 0) {
1061                 ch->ch_old_baud = baud;
1062                 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
1063                 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
1064                 writeb((quot >> 8), &ch->ch_neo_uart->ier);
1065                 writeb(lcr, &ch->ch_neo_uart->lcr);
1066         }
1067
1068         if (uart_lcr != lcr)
1069                 writeb(lcr, &ch->ch_neo_uart->lcr);
1070
1071         if (ch->ch_c_cflag & CREAD)
1072                 ier |= (UART_IER_RDI | UART_IER_RLSI);
1073
1074         ier |= (UART_IER_THRI | UART_IER_MSI);
1075
1076         writeb(ier, &ch->ch_neo_uart->ier);
1077
1078         /* Set new start/stop chars */
1079         neo_set_new_start_stop_chars(ch);
1080
1081         if (ch->ch_c_cflag & CRTSCTS)
1082                 neo_set_cts_flow_control(ch);
1083         else if (ch->ch_c_iflag & IXON) {
1084                 /* If start/stop is set to disable, then we should disable flow control */
1085                 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1086                         neo_set_no_output_flow_control(ch);
1087                 else
1088                         neo_set_ixon_flow_control(ch);
1089         }
1090         else
1091                 neo_set_no_output_flow_control(ch);
1092
1093         if (ch->ch_c_cflag & CRTSCTS)
1094                 neo_set_rts_flow_control(ch);
1095         else if (ch->ch_c_iflag & IXOFF) {
1096                 /* If start/stop is set to disable, then we should disable flow control */
1097                 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1098                         neo_set_no_input_flow_control(ch);
1099                 else
1100                         neo_set_ixoff_flow_control(ch);
1101         }
1102         else
1103                 neo_set_no_input_flow_control(ch);
1104         /*
1105          * Adjust the RX FIFO Trigger level if baud is less than 9600.
1106          * Not exactly elegant, but this is needed because of the Exar chip's
1107          * delay on firing off the RX FIFO interrupt on slower baud rates.
1108          */
1109         if (baud < 9600) {
1110                 writeb(1, &ch->ch_neo_uart->rfifo);
1111                 ch->ch_r_tlevel = 1;
1112         }
1113
1114         neo_assert_modem_signals(ch);
1115
1116         /* Get current status of the modem signals now */
1117         neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
1118         return;
1119 }
1120
1121 /*
1122  * jsm_neo_intr()
1123  *
1124  * Neo specific interrupt handler.
1125  */
1126 static irqreturn_t neo_intr(int irq, void *voidbrd, struct pt_regs *regs)
1127 {
1128         struct jsm_board *brd = (struct jsm_board *) voidbrd;
1129         struct jsm_channel *ch;
1130         int port = 0;
1131         int type = 0;
1132         int current_port;
1133         u32 tmp;
1134         u32 uart_poll;
1135         unsigned long lock_flags;
1136         unsigned long lock_flags2;
1137         int outofloop_count = 0;
1138
1139         brd->intr_count++;
1140
1141         /* Lock out the slow poller from running on this board. */
1142         spin_lock_irqsave(&brd->bd_intr_lock, lock_flags);
1143
1144         /*
1145          * Read in "extended" IRQ information from the 32bit Neo register.
1146          * Bits 0-7: What port triggered the interrupt.
1147          * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
1148          */
1149         uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
1150
1151         jsm_printk(INTR, INFO, &brd->pci_dev,
1152                 "%s:%d uart_poll: %x\n", __FILE__, __LINE__, uart_poll);
1153
1154         if (!uart_poll) {
1155                 jsm_printk(INTR, INFO, &brd->pci_dev,
1156                         "Kernel interrupted to me, but no pending interrupts...\n");
1157                 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1158                 return IRQ_NONE;
1159         }
1160
1161         /* At this point, we have at least SOMETHING to service, dig further... */
1162
1163         current_port = 0;
1164
1165         /* Loop on each port */
1166         while (((uart_poll & 0xff) != 0) && (outofloop_count < 0xff)){
1167
1168                 tmp = uart_poll;
1169                 outofloop_count++;
1170
1171                 /* Check current port to see if it has interrupt pending */
1172                 if ((tmp & jsm_offset_table[current_port]) != 0) {
1173                         port = current_port;
1174                         type = tmp >> (8 + (port * 3));
1175                         type &= 0x7;
1176                 } else {
1177                         current_port++;
1178                         continue;
1179                 }
1180
1181                 jsm_printk(INTR, INFO, &brd->pci_dev,
1182                 "%s:%d port: %x type: %x\n", __FILE__, __LINE__, port, type);
1183
1184                 /* Remove this port + type from uart_poll */
1185                 uart_poll &= ~(jsm_offset_table[port]);
1186
1187                 if (!type) {
1188                         /* If no type, just ignore it, and move onto next port */
1189                         jsm_printk(INTR, ERR, &brd->pci_dev,
1190                                 "Interrupt with no type! port: %d\n", port);
1191                         continue;
1192                 }
1193
1194                 /* Switch on type of interrupt we have */
1195                 switch (type) {
1196
1197                 case UART_17158_RXRDY_TIMEOUT:
1198                         /*
1199                          * RXRDY Time-out is cleared by reading data in the
1200                         * RX FIFO until it falls below the trigger level.
1201                          */
1202
1203                         /* Verify the port is in range. */
1204                         if (port > brd->nasync)
1205                                 continue;
1206
1207                         ch = brd->channels[port];
1208                         neo_copy_data_from_uart_to_queue(ch);
1209
1210                         /* Call our tty layer to enforce queue flow control if needed. */
1211                         spin_lock_irqsave(&ch->ch_lock, lock_flags2);
1212                         jsm_check_queue_flow_control(ch);
1213                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags2);
1214
1215                         continue;
1216
1217                 case UART_17158_RX_LINE_STATUS:
1218                         /*
1219                          * RXRDY and RX LINE Status (logic OR of LSR[4:1])
1220                          */
1221                         neo_parse_lsr(brd, port);
1222                         continue;
1223
1224                 case UART_17158_TXRDY:
1225                         /*
1226                          * TXRDY interrupt clears after reading ISR register for the UART channel.
1227                          */
1228
1229                         /*
1230                          * Yes, this is odd...
1231                          * Why would I check EVERY possibility of type of
1232                          * interrupt, when we know its TXRDY???
1233                          * Becuz for some reason, even tho we got triggered for TXRDY,
1234                          * it seems to be occassionally wrong. Instead of TX, which
1235                          * it should be, I was getting things like RXDY too. Weird.
1236                          */
1237                         neo_parse_isr(brd, port);
1238                         continue;
1239
1240                 case UART_17158_MSR:
1241                         /*
1242                          * MSR or flow control was seen.
1243                          */
1244                         neo_parse_isr(brd, port);
1245                         continue;
1246
1247                 default:
1248                         /*
1249                          * The UART triggered us with a bogus interrupt type.
1250                          * It appears the Exar chip, when REALLY bogged down, will throw
1251                          * these once and awhile.
1252                          * Its harmless, just ignore it and move on.
1253                          */
1254                         jsm_printk(INTR, ERR, &brd->pci_dev,
1255                                 "%s:%d Unknown Interrupt type: %x\n", __FILE__, __LINE__, type);
1256                         continue;
1257                 }
1258         }
1259
1260         spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1261
1262         jsm_printk(INTR, INFO, &brd->pci_dev, "finish.\n");
1263         return IRQ_HANDLED;
1264 }
1265
1266 /*
1267  * Neo specific way of turning off the receiver.
1268  * Used as a way to enforce queue flow control when in
1269  * hardware flow control mode.
1270  */
1271 static void neo_disable_receiver(struct jsm_channel *ch)
1272 {
1273         u8 tmp = readb(&ch->ch_neo_uart->ier);
1274         tmp &= ~(UART_IER_RDI);
1275         writeb(tmp, &ch->ch_neo_uart->ier);
1276
1277         /* flush write operation */
1278         neo_pci_posting_flush(ch->ch_bd);
1279 }
1280
1281
1282 /*
1283  * Neo specific way of turning on the receiver.
1284  * Used as a way to un-enforce queue flow control when in
1285  * hardware flow control mode.
1286  */
1287 static void neo_enable_receiver(struct jsm_channel *ch)
1288 {
1289         u8 tmp = readb(&ch->ch_neo_uart->ier);
1290         tmp |= (UART_IER_RDI);
1291         writeb(tmp, &ch->ch_neo_uart->ier);
1292
1293         /* flush write operation */
1294         neo_pci_posting_flush(ch->ch_bd);
1295 }
1296
1297 static void neo_send_start_character(struct jsm_channel *ch)
1298 {
1299         if (!ch)
1300                 return;
1301
1302         if (ch->ch_startc != __DISABLED_CHAR) {
1303                 ch->ch_xon_sends++;
1304                 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1305
1306                 /* flush write operation */
1307                 neo_pci_posting_flush(ch->ch_bd);
1308         }
1309 }
1310
1311 static void neo_send_stop_character(struct jsm_channel *ch)
1312 {
1313         if (!ch)
1314                 return;
1315
1316         if (ch->ch_stopc != __DISABLED_CHAR) {
1317                 ch->ch_xoff_sends++;
1318                 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1319
1320                 /* flush write operation */
1321                 neo_pci_posting_flush(ch->ch_bd);
1322         }
1323 }
1324
1325 /*
1326  * neo_uart_init
1327  */
1328 static void neo_uart_init(struct jsm_channel *ch)
1329 {
1330         writeb(0, &ch->ch_neo_uart->ier);
1331         writeb(0, &ch->ch_neo_uart->efr);
1332         writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1333
1334         /* Clear out UART and FIFO */
1335         readb(&ch->ch_neo_uart->txrx);
1336         writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1337         readb(&ch->ch_neo_uart->lsr);
1338         readb(&ch->ch_neo_uart->msr);
1339
1340         ch->ch_flags |= CH_FIFO_ENABLED;
1341
1342         /* Assert any signals we want up */
1343         writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1344 }
1345
1346 /*
1347  * Make the UART completely turn off.
1348  */
1349 static void neo_uart_off(struct jsm_channel *ch)
1350 {
1351         /* Turn off UART enhanced bits */
1352         writeb(0, &ch->ch_neo_uart->efr);
1353
1354         /* Stop all interrupts from occurring. */
1355         writeb(0, &ch->ch_neo_uart->ier);
1356 }
1357
1358 static u32 neo_get_uart_bytes_left(struct jsm_channel *ch)
1359 {
1360         u8 left = 0;
1361         u8 lsr = readb(&ch->ch_neo_uart->lsr);
1362
1363         /* We must cache the LSR as some of the bits get reset once read... */
1364         ch->ch_cached_lsr |= lsr;
1365
1366         /* Determine whether the Transmitter is empty or not */
1367         if (!(lsr & UART_LSR_TEMT))
1368                 left = 1;
1369         else {
1370                 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1371                 left = 0;
1372         }
1373
1374         return left;
1375 }
1376
1377 /* Channel lock MUST be held by the calling function! */
1378 static void neo_send_break(struct jsm_channel *ch)
1379 {
1380         /*
1381          * Set the time we should stop sending the break.
1382          * If we are already sending a break, toss away the existing
1383          * time to stop, and use this new value instead.
1384          */
1385
1386         /* Tell the UART to start sending the break */
1387         if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1388                 u8 temp = readb(&ch->ch_neo_uart->lcr);
1389                 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1390                 ch->ch_flags |= (CH_BREAK_SENDING);
1391
1392                 /* flush write operation */
1393                 neo_pci_posting_flush(ch->ch_bd);
1394         }
1395 }
1396
1397 /*
1398  * neo_send_immediate_char.
1399  *
1400  * Sends a specific character as soon as possible to the UART,
1401  * jumping over any bytes that might be in the write queue.
1402  *
1403  * The channel lock MUST be held by the calling function.
1404  */
1405 static void neo_send_immediate_char(struct jsm_channel *ch, unsigned char c)
1406 {
1407         if (!ch)
1408                 return;
1409
1410         writeb(c, &ch->ch_neo_uart->txrx);
1411
1412         /* flush write operation */
1413         neo_pci_posting_flush(ch->ch_bd);
1414 }
1415
1416 struct board_ops jsm_neo_ops = {
1417         .intr                           = neo_intr,
1418         .uart_init                      = neo_uart_init,
1419         .uart_off                       = neo_uart_off,
1420         .param                          = neo_param,
1421         .assert_modem_signals           = neo_assert_modem_signals,
1422         .flush_uart_write               = neo_flush_uart_write,
1423         .flush_uart_read                = neo_flush_uart_read,
1424         .disable_receiver               = neo_disable_receiver,
1425         .enable_receiver                = neo_enable_receiver,
1426         .send_break                     = neo_send_break,
1427         .clear_break                    = neo_clear_break,
1428         .send_start_character           = neo_send_start_character,
1429         .send_stop_character            = neo_send_stop_character,
1430         .copy_data_from_queue_to_uart   = neo_copy_data_from_queue_to_uart,
1431         .get_uart_bytes_left            = neo_get_uart_bytes_left,
1432         .send_immediate_char            = neo_send_immediate_char
1433 };