git.oblomov.eu Git - linux-2.6/blob - drivers/infiniband/hw/ipath/ipath_init_chip.c

   1 /*
   2  * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/pci.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/vmalloc.h>
  37
  38 #include "ipath_kernel.h"
  39 #include "ipath_common.h"
  40
  41 /*
  42  * min buffers we want to have per port, after driver
  43  */
  44 #define IPATH_MIN_USER_PORT_BUFCNT 8
  45
  46 /*
  47  * Number of ports we are configured to use (to allow for more pio
  48  * buffers per port, etc.)  Zero means use chip value.
  49  */
  50 static ushort ipath_cfgports;
  51
  52 module_param_named(cfgports, ipath_cfgports, ushort, S_IRUGO);
  53 MODULE_PARM_DESC(cfgports, "Set max number of ports to use");
  54
  55 /*
  56  * Number of buffers reserved for driver (verbs and layered drivers.)
  57  * Reserved at end of buffer list.   Initialized based on
  58  * number of PIO buffers if not set via module interface.
  59  * The problem with this is that it's global, but we'll use different
  60  * numbers for different chip types.  So the default value is not
  61  * very useful.  I've redefined it for the 1.3 release so that it's
  62  * zero unless set by the user to something else, in which case we
  63  * try to respect it.
  64  */
  65 static ushort ipath_kpiobufs;
  66
  67 static int ipath_set_kpiobufs(const char *val, struct kernel_param *kp);
  68
  69 module_param_call(kpiobufs, ipath_set_kpiobufs, param_get_ushort,
  70                   &ipath_kpiobufs, S_IWUSR | S_IRUGO);
  71 MODULE_PARM_DESC(kpiobufs, "Set number of PIO buffers for driver");
  72
  73 /**
  74  * create_port0_egr - allocate the eager TID buffers
  75  * @dd: the infinipath device
  76  *
  77  * This code is now quite different for user and kernel, because
  78  * the kernel uses skb's, for the accelerated network performance.
  79  * This is the kernel (port0) version.
  80  *
  81  * Allocate the eager TID buffers and program them into infinipath.
  82  * We use the network layer alloc_skb() allocator to allocate the
  83  * memory, and either use the buffers as is for things like verbs
  84  * packets, or pass the buffers up to the ipath layered driver and
  85  * thence the network layer, replacing them as we do so (see
  86  * ipath_rcv_layer()).
  87  */
  88 static int create_port0_egr(struct ipath_devdata *dd)
  89 {
  90         unsigned e, egrcnt;
  91         struct ipath_skbinfo *skbinfo;
  92         int ret;
  93
  94         egrcnt = dd->ipath_p0_rcvegrcnt;
  95
  96         skbinfo = vmalloc(sizeof(*dd->ipath_port0_skbinfo) * egrcnt);
  97         if (skbinfo == NULL) {
  98                 ipath_dev_err(dd, "allocation error for eager TID "
  99                               "skb array\n");
 100                 ret = -ENOMEM;
 101                 goto bail;
 102         }
 103         for (e = 0; e < egrcnt; e++) {
 104                 /*
 105                  * This is a bit tricky in that we allocate extra
 106                  * space for 2 bytes of the 14 byte ethernet header.
 107                  * These two bytes are passed in the ipath header so
 108                  * the rest of the data is word aligned.  We allocate
 109                  * 4 bytes so that the data buffer stays word aligned.
 110                  * See ipath_kreceive() for more details.
 111                  */
 112                 skbinfo[e].skb = ipath_alloc_skb(dd, GFP_KERNEL);
 113                 if (!skbinfo[e].skb) {
 114                         ipath_dev_err(dd, "SKB allocation error for "
 115                                       "eager TID %u\n", e);
 116                         while (e != 0)
 117                                 dev_kfree_skb(skbinfo[--e].skb);
 118                         vfree(skbinfo);
 119                         ret = -ENOMEM;
 120                         goto bail;
 121                 }
 122         }
 123         /*
 124          * After loop above, so we can test non-NULL to see if ready
 125          * to use at receive, etc.
 126          */
 127         dd->ipath_port0_skbinfo = skbinfo;
 128
 129         for (e = 0; e < egrcnt; e++) {
 130                 dd->ipath_port0_skbinfo[e].phys =
 131                   ipath_map_single(dd->pcidev,
 132                                    dd->ipath_port0_skbinfo[e].skb->data,
 133                                    dd->ipath_ibmaxlen, PCI_DMA_FROMDEVICE);
 134                 dd->ipath_f_put_tid(dd, e + (u64 __iomem *)
 135                                     ((char __iomem *) dd->ipath_kregbase +
 136                                      dd->ipath_rcvegrbase),
 137                                     RCVHQ_RCV_TYPE_EAGER,
 138                                     dd->ipath_port0_skbinfo[e].phys);
 139         }
 140
 141         ret = 0;
 142
 143 bail:
 144         return ret;
 145 }
 146
 147 static int bringup_link(struct ipath_devdata *dd)
 148 {
 149         u64 val, ibc;
 150         int ret = 0;
 151
 152         /* hold IBC in reset */
 153         dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
 154         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 155                          dd->ipath_control);
 156
 157         /*
 158          * set initial max size pkt IBC will send, including ICRC; it's the
 159          * PIO buffer size in dwords, less 1; also see ipath_set_mtu()
 160          */
 161         val = (dd->ipath_ibmaxlen >> 2) + 1;
 162         ibc = val << dd->ibcc_mpl_shift;
 163
 164         /* flowcontrolwatermark is in units of KBytes */
 165         ibc |= 0x5ULL << INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT;
 166         /*
 167          * How often flowctrl sent.  More or less in usecs; balance against
 168          * watermark value, so that in theory senders always get a flow
 169          * control update in time to not let the IB link go idle.
 170          */
 171         ibc |= 0x3ULL << INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT;
 172         /* max error tolerance */
 173         ibc |= 0xfULL << INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT;
 174         /* use "real" buffer space for */
 175         ibc |= 4ULL << INFINIPATH_IBCC_CREDITSCALE_SHIFT;
 176         /* IB credit flow control. */
 177         ibc |= 0xfULL << INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT;
 178         /* initially come up waiting for TS1, without sending anything. */
 179         dd->ipath_ibcctrl = ibc;
 180         /*
 181          * Want to start out with both LINKCMD and LINKINITCMD in NOP
 182          * (0 and 0).  Don't put linkinitcmd in ipath_ibcctrl, want that
 183          * to stay a NOP. Flag that we are disabled, for the (unlikely)
 184          * case that some recovery path is trying to bring the link up
 185          * before we are ready.
 186          */
 187         ibc |= INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
 188                 INFINIPATH_IBCC_LINKINITCMD_SHIFT;
 189         dd->ipath_flags |= IPATH_IB_LINK_DISABLED;
 190         ipath_cdbg(VERBOSE, "Writing 0x%llx to ibcctrl\n",
 191                    (unsigned long long) ibc);
 192         ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, ibc);
 193
 194         // be sure chip saw it
 195         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 196
 197         ret = dd->ipath_f_bringup_serdes(dd);
 198
 199         if (ret)
 200                 dev_info(&dd->pcidev->dev, "Could not initialize SerDes, "
 201                          "not usable\n");
 202         else {
 203                 /* enable IBC */
 204                 dd->ipath_control |= INFINIPATH_C_LINKENABLE;
 205                 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 206                                  dd->ipath_control);
 207         }
 208
 209         return ret;
 210 }
 211
 212 static struct ipath_portdata *create_portdata0(struct ipath_devdata *dd)
 213 {
 214         struct ipath_portdata *pd = NULL;
 215
 216         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 217         if (pd) {
 218                 pd->port_dd = dd;
 219                 pd->port_cnt = 1;
 220                 /* The port 0 pkey table is used by the layer interface. */
 221                 pd->port_pkeys[0] = IPATH_DEFAULT_P_KEY;
 222                 pd->port_seq_cnt = 1;
 223         }
 224         return pd;
 225 }
 226
 227 static int init_chip_first(struct ipath_devdata *dd)
 228 {
 229         struct ipath_portdata *pd;
 230         int ret = 0;
 231         u64 val;
 232
 233         /*
 234          * skip cfgports stuff because we are not allocating memory,
 235          * and we don't want problems if the portcnt changed due to
 236          * cfgports.  We do still check and report a difference, if
 237          * not same (should be impossible).
 238          */
 239         dd->ipath_f_config_ports(dd, ipath_cfgports);
 240         if (!ipath_cfgports)
 241                 dd->ipath_cfgports = dd->ipath_portcnt;
 242         else if (ipath_cfgports <= dd->ipath_portcnt) {
 243                 dd->ipath_cfgports = ipath_cfgports;
 244                 ipath_dbg("Configured to use %u ports out of %u in chip\n",
 245                           dd->ipath_cfgports, ipath_read_kreg32(dd,
 246                           dd->ipath_kregs->kr_portcnt));
 247         } else {
 248                 dd->ipath_cfgports = dd->ipath_portcnt;
 249                 ipath_dbg("Tried to configured to use %u ports; chip "
 250                           "only supports %u\n", ipath_cfgports,
 251                           ipath_read_kreg32(dd,
 252                                   dd->ipath_kregs->kr_portcnt));
 253         }
 254         /*
 255          * Allocate full portcnt array, rather than just cfgports, because
 256          * cleanup iterates across all possible ports.
 257          */
 258         dd->ipath_pd = kzalloc(sizeof(*dd->ipath_pd) * dd->ipath_portcnt,
 259                                GFP_KERNEL);
 260
 261         if (!dd->ipath_pd) {
 262                 ipath_dev_err(dd, "Unable to allocate portdata array, "
 263                               "failing\n");
 264                 ret = -ENOMEM;
 265                 goto done;
 266         }
 267
 268         pd = create_portdata0(dd);
 269         if (!pd) {
 270                 ipath_dev_err(dd, "Unable to allocate portdata for port "
 271                               "0, failing\n");
 272                 ret = -ENOMEM;
 273                 goto done;
 274         }
 275         dd->ipath_pd[0] = pd;
 276
 277         dd->ipath_rcvtidcnt =
 278                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
 279         dd->ipath_rcvtidbase =
 280                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
 281         dd->ipath_rcvegrcnt =
 282                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
 283         dd->ipath_rcvegrbase =
 284                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
 285         dd->ipath_palign =
 286                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
 287         dd->ipath_piobufbase =
 288                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufbase);
 289         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiosize);
 290         dd->ipath_piosize2k = val & ~0U;
 291         dd->ipath_piosize4k = val >> 32;
 292         if (dd->ipath_piosize4k == 0 && ipath_mtu4096)
 293                 ipath_mtu4096 = 0; /* 4KB not supported by this chip */
 294         dd->ipath_ibmtu = ipath_mtu4096 ? 4096 : 2048;
 295         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufcnt);
 296         dd->ipath_piobcnt2k = val & ~0U;
 297         dd->ipath_piobcnt4k = val >> 32;
 298         dd->ipath_pio2kbase =
 299                 (u32 __iomem *) (((char __iomem *) dd->ipath_kregbase) +
 300                                  (dd->ipath_piobufbase & 0xffffffff));
 301         if (dd->ipath_piobcnt4k) {
 302                 dd->ipath_pio4kbase = (u32 __iomem *)
 303                         (((char __iomem *) dd->ipath_kregbase) +
 304                          (dd->ipath_piobufbase >> 32));
 305                 /*
 306                  * 4K buffers take 2 pages; we use roundup just to be
 307                  * paranoid; we calculate it once here, rather than on
 308                  * ever buf allocate
 309                  */
 310                 dd->ipath_4kalign = ALIGN(dd->ipath_piosize4k,
 311                                           dd->ipath_palign);
 312                 ipath_dbg("%u 2k(%x) piobufs @ %p, %u 4k(%x) @ %p "
 313                           "(%x aligned)\n",
 314                           dd->ipath_piobcnt2k, dd->ipath_piosize2k,
 315                           dd->ipath_pio2kbase, dd->ipath_piobcnt4k,
 316                           dd->ipath_piosize4k, dd->ipath_pio4kbase,
 317                           dd->ipath_4kalign);
 318         }
 319         else ipath_dbg("%u 2k piobufs @ %p\n",
 320                        dd->ipath_piobcnt2k, dd->ipath_pio2kbase);
 321
 322         spin_lock_init(&dd->ipath_tid_lock);
 323         spin_lock_init(&dd->ipath_sendctrl_lock);
 324         spin_lock_init(&dd->ipath_gpio_lock);
 325         spin_lock_init(&dd->ipath_eep_st_lock);
 326         mutex_init(&dd->ipath_eep_lock);
 327
 328 done:
 329         return ret;
 330 }
 331
 332 /**
 333  * init_chip_reset - re-initialize after a reset, or enable
 334  * @dd: the infinipath device
 335  *
 336  * sanity check at least some of the values after reset, and
 337  * ensure no receive or transmit (explictly, in case reset
 338  * failed
 339  */
 340 static int init_chip_reset(struct ipath_devdata *dd)
 341 {
 342         u32 rtmp;
 343         int i;
 344         unsigned long flags;
 345
 346         /*
 347          * ensure chip does no sends or receives, tail updates, or
 348          * pioavail updates while we re-initialize
 349          */
 350         dd->ipath_rcvctrl &= ~(1ULL << dd->ipath_r_tailupd_shift);
 351         for (i = 0; i < dd->ipath_portcnt; i++) {
 352                 clear_bit(dd->ipath_r_portenable_shift + i,
 353                           &dd->ipath_rcvctrl);
 354                 clear_bit(dd->ipath_r_intravail_shift + i,
 355                           &dd->ipath_rcvctrl);
 356         }
 357         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
 358                 dd->ipath_rcvctrl);
 359
 360         spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
 361         dd->ipath_sendctrl = 0U; /* no sdma, etc */
 362         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
 363         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 364         spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
 365
 366         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
 367
 368         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
 369         if (rtmp != dd->ipath_rcvtidcnt)
 370                 dev_info(&dd->pcidev->dev, "tidcnt was %u before "
 371                          "reset, now %u, using original\n",
 372                          dd->ipath_rcvtidcnt, rtmp);
 373         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
 374         if (rtmp != dd->ipath_rcvtidbase)
 375                 dev_info(&dd->pcidev->dev, "tidbase was %u before "
 376                          "reset, now %u, using original\n",
 377                          dd->ipath_rcvtidbase, rtmp);
 378         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
 379         if (rtmp != dd->ipath_rcvegrcnt)
 380                 dev_info(&dd->pcidev->dev, "egrcnt was %u before "
 381                          "reset, now %u, using original\n",
 382                          dd->ipath_rcvegrcnt, rtmp);
 383         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
 384         if (rtmp != dd->ipath_rcvegrbase)
 385                 dev_info(&dd->pcidev->dev, "egrbase was %u before "
 386                          "reset, now %u, using original\n",
 387                          dd->ipath_rcvegrbase, rtmp);
 388
 389         return 0;
 390 }
 391
 392 static int init_pioavailregs(struct ipath_devdata *dd)
 393 {
 394         int ret;
 395
 396         dd->ipath_pioavailregs_dma = dma_alloc_coherent(
 397                 &dd->pcidev->dev, PAGE_SIZE, &dd->ipath_pioavailregs_phys,
 398                 GFP_KERNEL);
 399         if (!dd->ipath_pioavailregs_dma) {
 400                 ipath_dev_err(dd, "failed to allocate PIOavail reg area "
 401                               "in memory\n");
 402                 ret = -ENOMEM;
 403                 goto done;
 404         }
 405
 406         /*
 407          * we really want L2 cache aligned, but for current CPUs of
 408          * interest, they are the same.
 409          */
 410         dd->ipath_statusp = (u64 *)
 411                 ((char *)dd->ipath_pioavailregs_dma +
 412                  ((2 * L1_CACHE_BYTES +
 413                    dd->ipath_pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES));
 414         /* copy the current value now that it's really allocated */
 415         *dd->ipath_statusp = dd->_ipath_status;
 416         /*
 417          * setup buffer to hold freeze msg, accessible to apps,
 418          * following statusp
 419          */
 420         dd->ipath_freezemsg = (char *)&dd->ipath_statusp[1];
 421         /* and its length */
 422         dd->ipath_freezelen = L1_CACHE_BYTES - sizeof(dd->ipath_statusp[0]);
 423
 424         ret = 0;
 425
 426 done:
 427         return ret;
 428 }
 429
 430 /**
 431  * init_shadow_tids - allocate the shadow TID array
 432  * @dd: the infinipath device
 433  *
 434  * allocate the shadow TID array, so we can ipath_munlock previous
 435  * entries.  It may make more sense to move the pageshadow to the
 436  * port data structure, so we only allocate memory for ports actually
 437  * in use, since we at 8k per port, now.
 438  */
 439 static void init_shadow_tids(struct ipath_devdata *dd)
 440 {
 441         struct page **pages;
 442         dma_addr_t *addrs;
 443
 444         pages = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
 445                         sizeof(struct page *));
 446         if (!pages) {
 447                 ipath_dev_err(dd, "failed to allocate shadow page * "
 448                               "array, no expected sends!\n");
 449                 dd->ipath_pageshadow = NULL;
 450                 return;
 451         }
 452
 453         addrs = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
 454                         sizeof(dma_addr_t));
 455         if (!addrs) {
 456                 ipath_dev_err(dd, "failed to allocate shadow dma handle "
 457                               "array, no expected sends!\n");
 458                 vfree(dd->ipath_pageshadow);
 459                 dd->ipath_pageshadow = NULL;
 460                 return;
 461         }
 462
 463         memset(pages, 0, dd->ipath_cfgports * dd->ipath_rcvtidcnt *
 464                sizeof(struct page *));
 465
 466         dd->ipath_pageshadow = pages;
 467         dd->ipath_physshadow = addrs;
 468 }
 469
 470 static void enable_chip(struct ipath_devdata *dd, int reinit)
 471 {
 472         u32 val;
 473         u64 rcvmask;
 474         unsigned long flags;
 475         int i;
 476
 477         if (!reinit)
 478                 init_waitqueue_head(&ipath_state_wait);
 479
 480         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
 481                          dd->ipath_rcvctrl);
 482
 483         spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
 484         /* Enable PIO send, and update of PIOavail regs to memory. */
 485         dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE |
 486                 INFINIPATH_S_PIOBUFAVAILUPD;
 487
 488         /*
 489          * Set the PIO avail update threshold to host memory
 490          * on chips that support it.
 491          */
 492         if (dd->ipath_pioupd_thresh)
 493                 dd->ipath_sendctrl |= dd->ipath_pioupd_thresh
 494                         << INFINIPATH_S_UPDTHRESH_SHIFT;
 495         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
 496         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 497         spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
 498
 499         /*
 500          * Enable kernel ports' receive and receive interrupt.
 501          * Other ports done as user opens and inits them.
 502          */
 503         rcvmask = 1ULL;
 504         dd->ipath_rcvctrl |= (rcvmask << dd->ipath_r_portenable_shift) |
 505                 (rcvmask << dd->ipath_r_intravail_shift);
 506         if (!(dd->ipath_flags & IPATH_NODMA_RTAIL))
 507                 dd->ipath_rcvctrl |= (1ULL << dd->ipath_r_tailupd_shift);
 508
 509         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
 510                          dd->ipath_rcvctrl);
 511
 512         /*
 513          * now ready for use.  this should be cleared whenever we
 514          * detect a reset, or initiate one.
 515          */
 516         dd->ipath_flags |= IPATH_INITTED;
 517
 518         /*
 519          * Init our shadow copies of head from tail values,
 520          * and write head values to match.
 521          */
 522         val = ipath_read_ureg32(dd, ur_rcvegrindextail, 0);
 523         ipath_write_ureg(dd, ur_rcvegrindexhead, val, 0);
 524
 525         /* Initialize so we interrupt on next packet received */
 526         ipath_write_ureg(dd, ur_rcvhdrhead,
 527                          dd->ipath_rhdrhead_intr_off |
 528                          dd->ipath_pd[0]->port_head, 0);
 529
 530         /*
 531          * by now pioavail updates to memory should have occurred, so
 532          * copy them into our working/shadow registers; this is in
 533          * case something went wrong with abort, but mostly to get the
 534          * initial values of the generation bit correct.
 535          */
 536         for (i = 0; i < dd->ipath_pioavregs; i++) {
 537                 __le64 pioavail;
 538
 539                 /*
 540                  * Chip Errata bug 6641; even and odd qwords>3 are swapped.
 541                  */
 542                 if (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS))
 543                         pioavail = dd->ipath_pioavailregs_dma[i ^ 1];
 544                 else
 545                         pioavail = dd->ipath_pioavailregs_dma[i];
 546                 dd->ipath_pioavailshadow[i] = le64_to_cpu(pioavail) |
 547                         (~dd->ipath_pioavailkernel[i] <<
 548                         INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT);
 549         }
 550         /* can get counters, stats, etc. */
 551         dd->ipath_flags |= IPATH_PRESENT;
 552 }
 553
 554 static int init_housekeeping(struct ipath_devdata *dd, int reinit)
 555 {
 556         char boardn[32];
 557         int ret = 0;
 558
 559         /*
 560          * have to clear shadow copies of registers at init that are
 561          * not otherwise set here, or all kinds of bizarre things
 562          * happen with driver on chip reset
 563          */
 564         dd->ipath_rcvhdrsize = 0;
 565
 566         /*
 567          * Don't clear ipath_flags as 8bit mode was set before
 568          * entering this func. However, we do set the linkstate to
 569          * unknown, so we can watch for a transition.
 570          * PRESENT is set because we want register reads to work,
 571          * and the kernel infrastructure saw it in config space;
 572          * We clear it if we have failures.
 573          */
 574         dd->ipath_flags |= IPATH_LINKUNK | IPATH_PRESENT;
 575         dd->ipath_flags &= ~(IPATH_LINKACTIVE | IPATH_LINKARMED |
 576                              IPATH_LINKDOWN | IPATH_LINKINIT);
 577
 578         ipath_cdbg(VERBOSE, "Try to read spc chip revision\n");
 579         dd->ipath_revision =
 580                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
 581
 582         /*
 583          * set up fundamental info we need to use the chip; we assume
 584          * if the revision reg and these regs are OK, we don't need to
 585          * special case the rest
 586          */
 587         dd->ipath_sregbase =
 588                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_sendregbase);
 589         dd->ipath_cregbase =
 590                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_counterregbase);
 591         dd->ipath_uregbase =
 592                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_userregbase);
 593         ipath_cdbg(VERBOSE, "ipath_kregbase %p, sendbase %x usrbase %x, "
 594                    "cntrbase %x\n", dd->ipath_kregbase, dd->ipath_sregbase,
 595                    dd->ipath_uregbase, dd->ipath_cregbase);
 596         if ((dd->ipath_revision & 0xffffffff) == 0xffffffff
 597             || (dd->ipath_sregbase & 0xffffffff) == 0xffffffff
 598             || (dd->ipath_cregbase & 0xffffffff) == 0xffffffff
 599             || (dd->ipath_uregbase & 0xffffffff) == 0xffffffff) {
 600                 ipath_dev_err(dd, "Register read failures from chip, "
 601                               "giving up initialization\n");
 602                 dd->ipath_flags &= ~IPATH_PRESENT;
 603                 ret = -ENODEV;
 604                 goto done;
 605         }
 606
 607
 608         /* clear diagctrl register, in case diags were running and crashed */
 609         ipath_write_kreg (dd, dd->ipath_kregs->kr_hwdiagctrl, 0);
 610
 611         /* clear the initial reset flag, in case first driver load */
 612         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
 613                          INFINIPATH_E_RESET);
 614
 615         ipath_cdbg(VERBOSE, "Revision %llx (PCI %x)\n",
 616                    (unsigned long long) dd->ipath_revision,
 617                    dd->ipath_pcirev);
 618
 619         if (((dd->ipath_revision >> INFINIPATH_R_SOFTWARE_SHIFT) &
 620              INFINIPATH_R_SOFTWARE_MASK) != IPATH_CHIP_SWVERSION) {
 621                 ipath_dev_err(dd, "Driver only handles version %d, "
 622                               "chip swversion is %d (%llx), failng\n",
 623                               IPATH_CHIP_SWVERSION,
 624                               (int)(dd->ipath_revision >>
 625                                     INFINIPATH_R_SOFTWARE_SHIFT) &
 626                               INFINIPATH_R_SOFTWARE_MASK,
 627                               (unsigned long long) dd->ipath_revision);
 628                 ret = -ENOSYS;
 629                 goto done;
 630         }
 631         dd->ipath_majrev = (u8) ((dd->ipath_revision >>
 632                                   INFINIPATH_R_CHIPREVMAJOR_SHIFT) &
 633                                  INFINIPATH_R_CHIPREVMAJOR_MASK);
 634         dd->ipath_minrev = (u8) ((dd->ipath_revision >>
 635                                   INFINIPATH_R_CHIPREVMINOR_SHIFT) &
 636                                  INFINIPATH_R_CHIPREVMINOR_MASK);
 637         dd->ipath_boardrev = (u8) ((dd->ipath_revision >>
 638                                     INFINIPATH_R_BOARDID_SHIFT) &
 639                                    INFINIPATH_R_BOARDID_MASK);
 640
 641         ret = dd->ipath_f_get_boardname(dd, boardn, sizeof boardn);
 642
 643         snprintf(dd->ipath_boardversion, sizeof(dd->ipath_boardversion),
 644                  "ChipABI %u.%u, %s, InfiniPath%u %u.%u, PCI %u, "
 645                  "SW Compat %u\n",
 646                  IPATH_CHIP_VERS_MAJ, IPATH_CHIP_VERS_MIN, boardn,
 647                  (unsigned)(dd->ipath_revision >> INFINIPATH_R_ARCH_SHIFT) &
 648                  INFINIPATH_R_ARCH_MASK,
 649                  dd->ipath_majrev, dd->ipath_minrev, dd->ipath_pcirev,
 650                  (unsigned)(dd->ipath_revision >>
 651                             INFINIPATH_R_SOFTWARE_SHIFT) &
 652                  INFINIPATH_R_SOFTWARE_MASK);
 653
 654         ipath_dbg("%s", dd->ipath_boardversion);
 655
 656         if (ret)
 657                 goto done;
 658
 659         if (reinit)
 660                 ret = init_chip_reset(dd);
 661         else
 662                 ret = init_chip_first(dd);
 663
 664 done:
 665         return ret;
 666 }
 667
 668 /**
 669  * ipath_init_chip - do the actual initialization sequence on the chip
 670  * @dd: the infinipath device
 671  * @reinit: reinitializing, so don't allocate new memory
 672  *
 673  * Do the actual initialization sequence on the chip.  This is done
 674  * both from the init routine called from the PCI infrastructure, and
 675  * when we reset the chip, or detect that it was reset internally,
 676  * or it's administratively re-enabled.
 677  *
 678  * Memory allocation here and in called routines is only done in
 679  * the first case (reinit == 0).  We have to be careful, because even
 680  * without memory allocation, we need to re-write all the chip registers
 681  * TIDs, etc. after the reset or enable has completed.
 682  */
 683 int ipath_init_chip(struct ipath_devdata *dd, int reinit)
 684 {
 685         int ret = 0;
 686         u32 val32, kpiobufs;
 687         u32 piobufs, uports;
 688         u64 val;
 689         struct ipath_portdata *pd;
 690         gfp_t gfp_flags = GFP_USER | __GFP_COMP;
 691         unsigned long flags;
 692
 693         ret = init_housekeeping(dd, reinit);
 694         if (ret)
 695                 goto done;
 696
 697         /*
 698          * we ignore most issues after reporting them, but have to specially
 699          * handle hardware-disabled chips.
 700          */
 701         if (ret == 2) {
 702                 /* unique error, known to ipath_init_one */
 703                 ret = -EPERM;
 704                 goto done;
 705         }
 706
 707         /*
 708          * We could bump this to allow for full rcvegrcnt + rcvtidcnt,
 709          * but then it no longer nicely fits power of two, and since
 710          * we now use routines that backend onto __get_free_pages, the
 711          * rest would be wasted.
 712          */
 713         dd->ipath_rcvhdrcnt = max(dd->ipath_p0_rcvegrcnt, dd->ipath_rcvegrcnt);
 714         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrcnt,
 715                          dd->ipath_rcvhdrcnt);
 716
 717         /*
 718          * Set up the shadow copies of the piobufavail registers,
 719          * which we compare against the chip registers for now, and
 720          * the in memory DMA'ed copies of the registers.  This has to
 721          * be done early, before we calculate lastport, etc.
 722          */
 723         piobufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
 724         /*
 725          * calc number of pioavail registers, and save it; we have 2
 726          * bits per buffer.
 727          */
 728         dd->ipath_pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2)
 729                 / (sizeof(u64) * BITS_PER_BYTE / 2);
 730         uports = dd->ipath_cfgports ? dd->ipath_cfgports - 1 : 0;
 731         if (ipath_kpiobufs == 0) {
 732                 /* not set by user (this is default) */
 733                 if (piobufs > 144)
 734                         kpiobufs = 32;
 735                 else
 736                         kpiobufs = 16;
 737         }
 738         else
 739                 kpiobufs = ipath_kpiobufs;
 740
 741         if (kpiobufs + (uports * IPATH_MIN_USER_PORT_BUFCNT) > piobufs) {
 742                 int i = (int) piobufs -
 743                         (int) (uports * IPATH_MIN_USER_PORT_BUFCNT);
 744                 if (i < 1)
 745                         i = 1;
 746                 dev_info(&dd->pcidev->dev, "Allocating %d PIO bufs of "
 747                          "%d for kernel leaves too few for %d user ports "
 748                          "(%d each); using %u\n", kpiobufs,
 749                          piobufs, uports, IPATH_MIN_USER_PORT_BUFCNT, i);
 750                 /*
 751                  * shouldn't change ipath_kpiobufs, because could be
 752                  * different for different devices...
 753                  */
 754                 kpiobufs = i;
 755         }
 756         dd->ipath_lastport_piobuf = piobufs - kpiobufs;
 757         dd->ipath_pbufsport =
 758                 uports ? dd->ipath_lastport_piobuf / uports : 0;
 759         val32 = dd->ipath_lastport_piobuf - (dd->ipath_pbufsport * uports);
 760         if (val32 > 0) {
 761                 ipath_dbg("allocating %u pbufs/port leaves %u unused, "
 762                           "add to kernel\n", dd->ipath_pbufsport, val32);
 763                 dd->ipath_lastport_piobuf -= val32;
 764                 kpiobufs += val32;
 765                 ipath_dbg("%u pbufs/port leaves %u unused, add to kernel\n",
 766                           dd->ipath_pbufsport, val32);
 767         }
 768         dd->ipath_lastpioindex = 0;
 769         dd->ipath_lastpioindexl = dd->ipath_piobcnt2k;
 770         ipath_chg_pioavailkernel(dd, 0, piobufs, 1);
 771         ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u "
 772                    "each for %u user ports\n", kpiobufs,
 773                    piobufs, dd->ipath_pbufsport, uports);
 774         if (dd->ipath_pioupd_thresh) {
 775                 if (dd->ipath_pbufsport < dd->ipath_pioupd_thresh)
 776                         dd->ipath_pioupd_thresh = dd->ipath_pbufsport;
 777                 if (kpiobufs < dd->ipath_pioupd_thresh)
 778                         dd->ipath_pioupd_thresh = kpiobufs;
 779         }
 780
 781         dd->ipath_f_early_init(dd);
 782         /*
 783          * Cancel any possible active sends from early driver load.
 784          * Follows early_init because some chips have to initialize
 785          * PIO buffers in early_init to avoid false parity errors.
 786          */
 787         ipath_cancel_sends(dd, 0);
 788
 789         /*
 790          * Early_init sets rcvhdrentsize and rcvhdrsize, so this must be
 791          * done after early_init.
 792          */
 793         dd->ipath_hdrqlast =
 794                 dd->ipath_rcvhdrentsize * (dd->ipath_rcvhdrcnt - 1);
 795         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrentsize,
 796                          dd->ipath_rcvhdrentsize);
 797         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
 798                          dd->ipath_rcvhdrsize);
 799
 800         if (!reinit) {
 801                 ret = init_pioavailregs(dd);
 802                 init_shadow_tids(dd);
 803                 if (ret)
 804                         goto done;
 805         }
 806
 807         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendpioavailaddr,
 808                          dd->ipath_pioavailregs_phys);
 809         /*
 810          * this is to detect s/w errors, which the h/w works around by
 811          * ignoring the low 6 bits of address, if it wasn't aligned.
 812          */
 813         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpioavailaddr);
 814         if (val != dd->ipath_pioavailregs_phys) {
 815                 ipath_dev_err(dd, "Catastrophic software error, "
 816                               "SendPIOAvailAddr written as %lx, "
 817                               "read back as %llx\n",
 818                               (unsigned long) dd->ipath_pioavailregs_phys,
 819                               (unsigned long long) val);
 820                 ret = -EINVAL;
 821                 goto done;
 822         }
 823
 824         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvbthqp, IPATH_KD_QP);
 825
 826         /*
 827          * make sure we are not in freeze, and PIO send enabled, so
 828          * writes to pbc happen
 829          */
 830         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 0ULL);
 831         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 832                          ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
 833         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
 834
 835         spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
 836         dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE;
 837         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
 838         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 839         spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
 840
 841         /*
 842          * before error clears, since we expect serdes pll errors during
 843          * this, the first time after reset
 844          */
 845         if (bringup_link(dd)) {
 846                 dev_info(&dd->pcidev->dev, "Failed to bringup IB link\n");
 847                 ret = -ENETDOWN;
 848                 goto done;
 849         }
 850
 851         /*
 852          * clear any "expected" hwerrs from reset and/or initialization
 853          * clear any that aren't enabled (at least this once), and then
 854          * set the enable mask
 855          */
 856         dd->ipath_f_init_hwerrors(dd);
 857         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 858                          ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
 859         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 860                          dd->ipath_hwerrmask);
 861
 862         /* clear all */
 863         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
 864         /* enable errors that are masked, at least this first time. */
 865         ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
 866                          ~dd->ipath_maskederrs);
 867         dd->ipath_maskederrs = 0; /* don't re-enable ignored in timer */
 868         dd->ipath_errormask =
 869                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_errormask);
 870         /* clear any interrupts up to this point (ints still not enabled) */
 871         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
 872
 873         dd->ipath_f_tidtemplate(dd);
 874
 875         /*
 876          * Set up the port 0 (kernel) rcvhdr q and egr TIDs.  If doing
 877          * re-init, the simplest way to handle this is to free
 878          * existing, and re-allocate.
 879          * Need to re-create rest of port 0 portdata as well.
 880          */
 881         pd = dd->ipath_pd[0];
 882         if (reinit) {
 883                 struct ipath_portdata *npd;
 884
 885                 /*
 886                  * Alloc and init new ipath_portdata for port0,
 887                  * Then free old pd. Could lead to fragmentation, but also
 888                  * makes later support for hot-swap easier.
 889                  */
 890                 npd = create_portdata0(dd);
 891                 if (npd) {
 892                         ipath_free_pddata(dd, pd);
 893                         dd->ipath_pd[0] = npd;
 894                         pd = npd;
 895                 } else {
 896                         ipath_dev_err(dd, "Unable to allocate portdata"
 897                                       " for port 0, failing\n");
 898                         ret = -ENOMEM;
 899                         goto done;
 900                 }
 901         }
 902         ret = ipath_create_rcvhdrq(dd, pd);
 903         if (!ret)
 904                 ret = create_port0_egr(dd);
 905         if (ret) {
 906                 ipath_dev_err(dd, "failed to allocate kernel port's "
 907                               "rcvhdrq and/or egr bufs\n");
 908                 goto done;
 909         }
 910         else
 911                 enable_chip(dd, reinit);
 912
 913         if (!reinit) {
 914                 /*
 915                  * Used when we close a port, for DMA already in flight
 916                  * at close.
 917                  */
 918                 dd->ipath_dummy_hdrq = dma_alloc_coherent(
 919                         &dd->pcidev->dev, dd->ipath_pd[0]->port_rcvhdrq_size,
 920                         &dd->ipath_dummy_hdrq_phys,
 921                         gfp_flags);
 922                 if (!dd->ipath_dummy_hdrq) {
 923                         dev_info(&dd->pcidev->dev,
 924                                 "Couldn't allocate 0x%lx bytes for dummy hdrq\n",
 925                                 dd->ipath_pd[0]->port_rcvhdrq_size);
 926                         /* fallback to just 0'ing */
 927                         dd->ipath_dummy_hdrq_phys = 0UL;
 928                 }
 929         }
 930
 931         /*
 932          * cause retrigger of pending interrupts ignored during init,
 933          * even if we had errors
 934          */
 935         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
 936
 937         if (!dd->ipath_stats_timer_active) {
 938                 /*
 939                  * first init, or after an admin disable/enable
 940                  * set up stats retrieval timer, even if we had errors
 941                  * in last portion of setup
 942                  */
 943                 init_timer(&dd->ipath_stats_timer);
 944                 dd->ipath_stats_timer.function = ipath_get_faststats;
 945                 dd->ipath_stats_timer.data = (unsigned long) dd;
 946                 /* every 5 seconds; */
 947                 dd->ipath_stats_timer.expires = jiffies + 5 * HZ;
 948                 /* takes ~16 seconds to overflow at full IB 4x bandwdith */
 949                 add_timer(&dd->ipath_stats_timer);
 950                 dd->ipath_stats_timer_active = 1;
 951         }
 952
 953         /* Set up HoL state */
 954         init_timer(&dd->ipath_hol_timer);
 955         dd->ipath_hol_timer.function = ipath_hol_event;
 956         dd->ipath_hol_timer.data = (unsigned long)dd;
 957         dd->ipath_hol_state = IPATH_HOL_UP;
 958
 959 done:
 960         if (!ret) {
 961                 *dd->ipath_statusp |= IPATH_STATUS_CHIP_PRESENT;
 962                 if (!dd->ipath_f_intrsetup(dd)) {
 963                         /* now we can enable all interrupts from the chip */
 964                         ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
 965                                          -1LL);
 966                         /* force re-interrupt of any pending interrupts. */
 967                         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear,
 968                                          0ULL);
 969                         /* chip is usable; mark it as initialized */
 970                         *dd->ipath_statusp |= IPATH_STATUS_INITTED;
 971                 } else
 972                         ipath_dev_err(dd, "No interrupts enabled, couldn't "
 973                                       "setup interrupt address\n");
 974
 975                 if (dd->ipath_cfgports > ipath_stats.sps_nports)
 976                         /*
 977                          * sps_nports is a global, so, we set it to
 978                          * the highest number of ports of any of the
 979                          * chips we find; we never decrement it, at
 980                          * least for now.  Since this might have changed
 981                          * over disable/enable or prior to reset, always
 982                          * do the check and potentially adjust.
 983                          */
 984                         ipath_stats.sps_nports = dd->ipath_cfgports;
 985         } else
 986                 ipath_dbg("Failed (%d) to initialize chip\n", ret);
 987
 988         /* if ret is non-zero, we probably should do some cleanup
 989            here... */
 990         return ret;
 991 }
 992
 993 static int ipath_set_kpiobufs(const char *str, struct kernel_param *kp)
 994 {
 995         struct ipath_devdata *dd;
 996         unsigned long flags;
 997         unsigned short val;
 998         int ret;
 999
1000         ret = ipath_parse_ushort(str, &val);
1001
1002         spin_lock_irqsave(&ipath_devs_lock, flags);
1003
1004         if (ret < 0)
1005                 goto bail;
1006
1007         if (val == 0) {
1008                 ret = -EINVAL;
1009                 goto bail;
1010         }
1011
1012         list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
1013                 if (dd->ipath_kregbase)
1014                         continue;
1015                 if (val > (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
1016                            (dd->ipath_cfgports *
1017                             IPATH_MIN_USER_PORT_BUFCNT)))
1018                 {
1019                         ipath_dev_err(
1020                                 dd,
1021                                 "Allocating %d PIO bufs for kernel leaves "
1022                                 "too few for %d user ports (%d each)\n",
1023                                 val, dd->ipath_cfgports - 1,
1024                                 IPATH_MIN_USER_PORT_BUFCNT);
1025                         ret = -EINVAL;
1026                         goto bail;
1027                 }
1028                 dd->ipath_lastport_piobuf =
1029                         dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - val;
1030         }
1031
1032         ipath_kpiobufs = val;
1033         ret = 0;
1034 bail:
1035         spin_unlock_irqrestore(&ipath_devs_lock, flags);
1036
1037         return ret;
1038 }