2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 2003 Maciej W. Rozycki
6 * Copyright (C) 1994 - 2003 Ralf Baechle
7 * Copyright (C) 2001 MIPS Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/config.h>
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/ptrace.h>
18 #include <linux/stddef.h>
23 #include <asm/mipsregs.h>
24 #include <asm/system.h>
27 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
28 * the implementation of the "wait" feature differs between CPU families. This
29 * points to the function that implements CPU specific wait.
30 * The wait instruction stops the pipeline and reduces the power consumption of
33 void (*cpu_wait)(void) = NULL;
35 static void r3081_wait(void)
37 unsigned long cfg = read_c0_conf();
38 write_c0_conf(cfg | R30XX_CONF_HALT);
41 static void r39xx_wait(void)
43 unsigned long cfg = read_c0_conf();
44 write_c0_conf(cfg | TX39_CONF_HALT);
47 static void r4k_wait(void)
49 __asm__(".set\tmips3\n\t"
55 * The Au1xxx wait is available only if we run CONFIG_PM and
56 * the timer setup found we had a 32KHz counter available.
57 * There are still problems with functions that may call au1k_wait
58 * directly, but that will be discovered pretty quickly.
60 extern void (*au1k_wait_ptr)(void);
65 /* using the wait instruction makes CP0 counter unusable */
66 __asm__(".set\tmips3\n\t"
79 static inline void check_wait(void)
81 struct cpuinfo_mips *c = ¤t_cpu_data;
83 printk("Checking for 'wait' instruction... ");
87 cpu_wait = r3081_wait;
88 printk(" available.\n");
91 cpu_wait = r39xx_wait;
92 printk(" available.\n");
113 printk(" available.\n");
119 if (au1k_wait_ptr != NULL) {
120 cpu_wait = au1k_wait_ptr;
121 printk(" available.\n");
124 printk(" unavailable.\n");
129 printk(" unavailable.\n");
134 void __init check_bugs32(void)
140 * Probe whether cpu has config register by trying to play with
141 * alternate cache bit and see whether it matters.
142 * It's used by cpu_probe to distinguish between R3000A and R3081.
144 static inline int cpu_has_confreg(void)
146 #ifdef CONFIG_CPU_R3000
147 extern unsigned long r3k_cache_size(unsigned long);
148 unsigned long size1, size2;
149 unsigned long cfg = read_c0_conf();
151 size1 = r3k_cache_size(ST0_ISC);
152 write_c0_conf(cfg ^ R30XX_CONF_AC);
153 size2 = r3k_cache_size(ST0_ISC);
155 return size1 != size2;
162 * Get the FPU Implementation/Revision.
164 static inline unsigned long cpu_get_fpu_id(void)
166 unsigned long tmp, fpu_id;
168 tmp = read_c0_status();
170 fpu_id = read_32bit_cp1_register(CP1_REVISION);
171 write_c0_status(tmp);
176 * Check the CPU has an FPU the official way.
178 static inline int __cpu_has_fpu(void)
180 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
183 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
186 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
188 switch (c->processor_id & 0xff00) {
190 c->cputype = CPU_R2000;
191 c->isa_level = MIPS_CPU_ISA_I;
192 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
194 c->options |= MIPS_CPU_FPU;
198 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
199 if (cpu_has_confreg())
200 c->cputype = CPU_R3081E;
202 c->cputype = CPU_R3000A;
204 c->cputype = CPU_R3000;
205 c->isa_level = MIPS_CPU_ISA_I;
206 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
208 c->options |= MIPS_CPU_FPU;
212 if (read_c0_config() & CONF_SC) {
213 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
214 c->cputype = CPU_R4400PC;
216 c->cputype = CPU_R4000PC;
218 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
219 c->cputype = CPU_R4400SC;
221 c->cputype = CPU_R4000SC;
224 c->isa_level = MIPS_CPU_ISA_III;
225 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
226 MIPS_CPU_WATCH | MIPS_CPU_VCE |
230 case PRID_IMP_VR41XX:
231 switch (c->processor_id & 0xf0) {
232 #ifndef CONFIG_VR4181
233 case PRID_REV_VR4111:
234 c->cputype = CPU_VR4111;
237 case PRID_REV_VR4181:
238 c->cputype = CPU_VR4181;
241 case PRID_REV_VR4121:
242 c->cputype = CPU_VR4121;
244 case PRID_REV_VR4122:
245 if ((c->processor_id & 0xf) < 0x3)
246 c->cputype = CPU_VR4122;
248 c->cputype = CPU_VR4181A;
250 case PRID_REV_VR4130:
251 if ((c->processor_id & 0xf) < 0x4)
252 c->cputype = CPU_VR4131;
254 c->cputype = CPU_VR4133;
257 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
258 c->cputype = CPU_VR41XX;
261 c->isa_level = MIPS_CPU_ISA_III;
262 c->options = R4K_OPTS;
266 c->cputype = CPU_R4300;
267 c->isa_level = MIPS_CPU_ISA_III;
268 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
273 c->cputype = CPU_R4600;
274 c->isa_level = MIPS_CPU_ISA_III;
275 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
281 * This processor doesn't have an MMU, so it's not
282 * "real easy" to run Linux on it. It is left purely
283 * for documentation. Commented out because it shares
284 * it's c0_prid id number with the TX3900.
286 c->cputype = CPU_R4650;
287 c->isa_level = MIPS_CPU_ISA_III;
288 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
293 c->isa_level = MIPS_CPU_ISA_I;
294 c->options = MIPS_CPU_TLB;
296 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
297 c->cputype = CPU_TX3927;
300 switch (c->processor_id & 0xff) {
301 case PRID_REV_TX3912:
302 c->cputype = CPU_TX3912;
305 case PRID_REV_TX3922:
306 c->cputype = CPU_TX3922;
310 c->cputype = CPU_UNKNOWN;
316 c->cputype = CPU_R4700;
317 c->isa_level = MIPS_CPU_ISA_III;
318 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
323 c->cputype = CPU_TX49XX;
324 c->isa_level = MIPS_CPU_ISA_III;
325 c->options = R4K_OPTS | MIPS_CPU_LLSC;
326 if (!(c->processor_id & 0x08))
327 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
331 c->cputype = CPU_R5000;
332 c->isa_level = MIPS_CPU_ISA_IV;
333 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
338 c->cputype = CPU_R5432;
339 c->isa_level = MIPS_CPU_ISA_IV;
340 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
341 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
345 c->cputype = CPU_R5500;
346 c->isa_level = MIPS_CPU_ISA_IV;
347 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
348 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
351 case PRID_IMP_NEVADA:
352 c->cputype = CPU_NEVADA;
353 c->isa_level = MIPS_CPU_ISA_IV;
354 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
355 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
359 c->cputype = CPU_R6000;
360 c->isa_level = MIPS_CPU_ISA_II;
361 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
365 case PRID_IMP_R6000A:
366 c->cputype = CPU_R6000A;
367 c->isa_level = MIPS_CPU_ISA_II;
368 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
372 case PRID_IMP_RM7000:
373 c->cputype = CPU_RM7000;
374 c->isa_level = MIPS_CPU_ISA_IV;
375 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
378 * Undocumented RM7000: Bit 29 in the info register of
379 * the RM7000 v2.0 indicates if the TLB has 48 or 64
382 * 29 1 => 64 entry JTLB
385 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
387 case PRID_IMP_RM9000:
388 c->cputype = CPU_RM9000;
389 c->isa_level = MIPS_CPU_ISA_IV;
390 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
393 * Bit 29 in the info register of the RM9000
394 * indicates if the TLB has 48 or 64 entries.
396 * 29 1 => 64 entry JTLB
399 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
402 c->cputype = CPU_R8000;
403 c->isa_level = MIPS_CPU_ISA_IV;
404 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
405 MIPS_CPU_FPU | MIPS_CPU_32FPR |
407 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
409 case PRID_IMP_R10000:
410 c->cputype = CPU_R10000;
411 c->isa_level = MIPS_CPU_ISA_IV;
412 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
413 MIPS_CPU_FPU | MIPS_CPU_32FPR |
414 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
418 case PRID_IMP_R12000:
419 c->cputype = CPU_R12000;
420 c->isa_level = MIPS_CPU_ISA_IV;
421 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
422 MIPS_CPU_FPU | MIPS_CPU_32FPR |
423 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
430 static inline void decode_config1(struct cpuinfo_mips *c)
432 unsigned long config0 = read_c0_config();
433 unsigned long config1;
435 if ((config0 & (1 << 31)) == 0)
436 return; /* actually wort a panic() */
438 /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */
439 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
440 MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
441 MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
442 config1 = read_c0_config1();
443 if (config1 & (1 << 3))
444 c->options |= MIPS_CPU_WATCH;
445 if (config1 & (1 << 2))
446 c->options |= MIPS_CPU_MIPS16;
447 if (config1 & (1 << 1))
448 c->options |= MIPS_CPU_EJTAG;
450 c->options |= MIPS_CPU_FPU;
451 c->options |= MIPS_CPU_32FPR;
453 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
455 c->tlbsize = ((config1 >> 25) & 0x3f) + 1;
458 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
461 switch (c->processor_id & 0xff00) {
463 c->cputype = CPU_4KC;
464 c->isa_level = MIPS_CPU_ISA_M32;
467 c->cputype = CPU_4KEC;
468 c->isa_level = MIPS_CPU_ISA_M32;
471 c->cputype = CPU_4KSC;
472 c->isa_level = MIPS_CPU_ISA_M32;
475 c->cputype = CPU_5KC;
476 c->isa_level = MIPS_CPU_ISA_M64;
479 c->cputype = CPU_20KC;
480 c->isa_level = MIPS_CPU_ISA_M64;
483 c->cputype = CPU_24K;
484 c->isa_level = MIPS_CPU_ISA_M32;
487 c->cputype = CPU_25KF;
488 c->isa_level = MIPS_CPU_ISA_M64;
489 /* Probe for L2 cache */
490 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
495 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
498 switch (c->processor_id & 0xff00) {
499 case PRID_IMP_AU1_REV1:
500 case PRID_IMP_AU1_REV2:
501 switch ((c->processor_id >> 24) & 0xff) {
503 c->cputype = CPU_AU1000;
506 c->cputype = CPU_AU1500;
509 c->cputype = CPU_AU1100;
512 c->cputype = CPU_AU1550;
515 panic("Unknown Au Core!");
518 c->isa_level = MIPS_CPU_ISA_M32;
523 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
526 switch (c->processor_id & 0xff00) {
528 c->cputype = CPU_SB1;
529 c->isa_level = MIPS_CPU_ISA_M64;
530 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
531 MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
532 MIPS_CPU_MCHECK | MIPS_CPU_EJTAG |
533 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
534 #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
535 /* FPU in pass1 is known to have issues. */
536 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
542 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
545 switch (c->processor_id & 0xff00) {
546 case PRID_IMP_SR71000:
547 c->cputype = CPU_SR71000;
548 c->isa_level = MIPS_CPU_ISA_M64;
549 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
550 MIPS_CPU_4KTLB | MIPS_CPU_FPU |
551 MIPS_CPU_COUNTER | MIPS_CPU_MCHECK;
558 __init void cpu_probe(void)
560 struct cpuinfo_mips *c = ¤t_cpu_data;
562 c->processor_id = PRID_IMP_UNKNOWN;
563 c->fpu_id = FPIR_IMP_NONE;
564 c->cputype = CPU_UNKNOWN;
566 c->processor_id = read_c0_prid();
567 switch (c->processor_id & 0xff0000) {
568 case PRID_COMP_LEGACY:
574 case PRID_COMP_ALCHEMY:
575 cpu_probe_alchemy(c);
577 case PRID_COMP_SIBYTE:
581 case PRID_COMP_SANDCRAFT:
582 cpu_probe_sandcraft(c);
585 c->cputype = CPU_UNKNOWN;
587 if (c->options & MIPS_CPU_FPU)
588 c->fpu_id = cpu_get_fpu_id();
591 __init void cpu_report(void)
593 struct cpuinfo_mips *c = ¤t_cpu_data;
595 printk("CPU revision is: %08x\n", c->processor_id);
596 if (c->options & MIPS_CPU_FPU)
597 printk("FPU revision is: %08x\n", c->fpu_id);