git.oblomov.eu Git - linux-2.6/blob - arch/sparc/mm/srmmu.c

   1 /*
   2  * srmmu.c:  SRMMU specific routines for memory management.
   3  *
   4  * Copyright (C) 1995 David S. Miller  (davem@caip.rutgers.edu)
   5  * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
   6  * Copyright (C) 1996 Eddie C. Dost    (ecd@skynet.be)
   7  * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   8  * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
   9  */
  10
  11 #include <linux/config.h>
  12 #include <linux/kernel.h>
  13 #include <linux/mm.h>
  14 #include <linux/slab.h>
  15 #include <linux/vmalloc.h>
  16 #include <linux/pagemap.h>
  17 #include <linux/init.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/bootmem.h>
  20 #include <linux/fs.h>
  21 #include <linux/seq_file.h>
  22
  23 #include <asm/bitext.h>
  24 #include <asm/page.h>
  25 #include <asm/pgalloc.h>
  26 #include <asm/pgtable.h>
  27 #include <asm/io.h>
  28 #include <asm/kdebug.h>
  29 #include <asm/vaddrs.h>
  30 #include <asm/traps.h>
  31 #include <asm/smp.h>
  32 #include <asm/mbus.h>
  33 #include <asm/cache.h>
  34 #include <asm/oplib.h>
  35 #include <asm/sbus.h>
  36 #include <asm/asi.h>
  37 #include <asm/msi.h>
  38 #include <asm/a.out.h>
  39 #include <asm/mmu_context.h>
  40 #include <asm/io-unit.h>
  41 #include <asm/cacheflush.h>
  42 #include <asm/tlbflush.h>
  43
  44 /* Now the cpu specific definitions. */
  45 #include <asm/viking.h>
  46 #include <asm/mxcc.h>
  47 #include <asm/ross.h>
  48 #include <asm/tsunami.h>
  49 #include <asm/swift.h>
  50 #include <asm/turbosparc.h>
  51
  52 #include <asm/btfixup.h>
  53
  54 enum mbus_module srmmu_modtype;
  55 unsigned int hwbug_bitmask;
  56 int vac_cache_size;
  57 int vac_line_size;
  58
  59 extern struct resource sparc_iomap;
  60
  61 extern unsigned long last_valid_pfn;
  62
  63 extern unsigned long page_kernel;
  64
  65 pgd_t *srmmu_swapper_pg_dir;
  66
  67 #ifdef CONFIG_SMP
  68 #define FLUSH_BEGIN(mm)
  69 #define FLUSH_END
  70 #else
  71 #define FLUSH_BEGIN(mm) if((mm)->context != NO_CONTEXT) {
  72 #define FLUSH_END       }
  73 #endif
  74
  75 BTFIXUPDEF_CALL(void, flush_page_for_dma, unsigned long)
  76 #define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page)
  77
  78 int flush_page_for_dma_global = 1;
  79
  80 #ifdef CONFIG_SMP
  81 BTFIXUPDEF_CALL(void, local_flush_page_for_dma, unsigned long)
  82 #define local_flush_page_for_dma(page) BTFIXUP_CALL(local_flush_page_for_dma)(page)
  83 #endif
  84
  85 char *srmmu_name;
  86
  87 ctxd_t *srmmu_ctx_table_phys;
  88 ctxd_t *srmmu_context_table;
  89
  90 int viking_mxcc_present;
  91 static DEFINE_SPINLOCK(srmmu_context_spinlock);
  92
  93 int is_hypersparc;
  94
  95 /*
  96  * In general all page table modifications should use the V8 atomic
  97  * swap instruction.  This insures the mmu and the cpu are in sync
  98  * with respect to ref/mod bits in the page tables.
  99  */
 100 static inline unsigned long srmmu_swap(unsigned long *addr, unsigned long value)
 101 {
 102         __asm__ __volatile__("swap [%2], %0" : "=&r" (value) : "0" (value), "r" (addr));
 103         return value;
 104 }
 105
 106 static inline void srmmu_set_pte(pte_t *ptep, pte_t pteval)
 107 {
 108         srmmu_swap((unsigned long *)ptep, pte_val(pteval));
 109 }
 110
 111 /* The very generic SRMMU page table operations. */
 112 static inline int srmmu_device_memory(unsigned long x)
 113 {
 114         return ((x & 0xF0000000) != 0);
 115 }
 116
 117 int srmmu_cache_pagetables;
 118
 119 /* these will be initialized in srmmu_nocache_calcsize() */
 120 unsigned long srmmu_nocache_size;
 121 unsigned long srmmu_nocache_end;
 122
 123 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
 124 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
 125
 126 /* The context table is a nocache user with the biggest alignment needs. */
 127 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
 128
 129 void *srmmu_nocache_pool;
 130 void *srmmu_nocache_bitmap;
 131 static struct bit_map srmmu_nocache_map;
 132
 133 static unsigned long srmmu_pte_pfn(pte_t pte)
 134 {
 135         if (srmmu_device_memory(pte_val(pte))) {
 136                 /* Just return something that will cause
 137                  * pfn_valid() to return false.  This makes
 138                  * copy_one_pte() to just directly copy to
 139                  * PTE over.
 140                  */
 141                 return ~0UL;
 142         }
 143         return (pte_val(pte) & SRMMU_PTE_PMASK) >> (PAGE_SHIFT-4);
 144 }
 145
 146 static struct page *srmmu_pmd_page(pmd_t pmd)
 147 {
 148
 149         if (srmmu_device_memory(pmd_val(pmd)))
 150                 BUG();
 151         return pfn_to_page((pmd_val(pmd) & SRMMU_PTD_PMASK) >> (PAGE_SHIFT-4));
 152 }
 153
 154 static inline unsigned long srmmu_pgd_page(pgd_t pgd)
 155 { return srmmu_device_memory(pgd_val(pgd))?~0:(unsigned long)__nocache_va((pgd_val(pgd) & SRMMU_PTD_PMASK) << 4); }
 156
 157
 158 static inline int srmmu_pte_none(pte_t pte)
 159 { return !(pte_val(pte) & 0xFFFFFFF); }
 160
 161 static inline int srmmu_pte_present(pte_t pte)
 162 { return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE); }
 163
 164 static inline int srmmu_pte_read(pte_t pte)
 165 { return !(pte_val(pte) & SRMMU_NOREAD); }
 166
 167 static inline void srmmu_pte_clear(pte_t *ptep)
 168 { srmmu_set_pte(ptep, __pte(0)); }
 169
 170 static inline int srmmu_pmd_none(pmd_t pmd)
 171 { return !(pmd_val(pmd) & 0xFFFFFFF); }
 172
 173 static inline int srmmu_pmd_bad(pmd_t pmd)
 174 { return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
 175
 176 static inline int srmmu_pmd_present(pmd_t pmd)
 177 { return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
 178
 179 static inline void srmmu_pmd_clear(pmd_t *pmdp) {
 180         int i;
 181         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++)
 182                 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], __pte(0));
 183 }
 184
 185 static inline int srmmu_pgd_none(pgd_t pgd)
 186 { return !(pgd_val(pgd) & 0xFFFFFFF); }
 187
 188 static inline int srmmu_pgd_bad(pgd_t pgd)
 189 { return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
 190
 191 static inline int srmmu_pgd_present(pgd_t pgd)
 192 { return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
 193
 194 static inline void srmmu_pgd_clear(pgd_t * pgdp)
 195 { srmmu_set_pte((pte_t *)pgdp, __pte(0)); }
 196
 197 static inline pte_t srmmu_pte_wrprotect(pte_t pte)
 198 { return __pte(pte_val(pte) & ~SRMMU_WRITE);}
 199
 200 static inline pte_t srmmu_pte_mkclean(pte_t pte)
 201 { return __pte(pte_val(pte) & ~SRMMU_DIRTY);}
 202
 203 static inline pte_t srmmu_pte_mkold(pte_t pte)
 204 { return __pte(pte_val(pte) & ~SRMMU_REF);}
 205
 206 static inline pte_t srmmu_pte_mkwrite(pte_t pte)
 207 { return __pte(pte_val(pte) | SRMMU_WRITE);}
 208
 209 static inline pte_t srmmu_pte_mkdirty(pte_t pte)
 210 { return __pte(pte_val(pte) | SRMMU_DIRTY);}
 211
 212 static inline pte_t srmmu_pte_mkyoung(pte_t pte)
 213 { return __pte(pte_val(pte) | SRMMU_REF);}
 214
 215 /*
 216  * Conversion functions: convert a page and protection to a page entry,
 217  * and a page entry and page directory to the page they refer to.
 218  */
 219 static pte_t srmmu_mk_pte(struct page *page, pgprot_t pgprot)
 220 { return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) | pgprot_val(pgprot)); }
 221
 222 static pte_t srmmu_mk_pte_phys(unsigned long page, pgprot_t pgprot)
 223 { return __pte(((page) >> 4) | pgprot_val(pgprot)); }
 224
 225 static pte_t srmmu_mk_pte_io(unsigned long page, pgprot_t pgprot, int space)
 226 { return __pte(((page) >> 4) | (space << 28) | pgprot_val(pgprot)); }
 227
 228 /* XXX should we hyper_flush_whole_icache here - Anton */
 229 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
 230 { srmmu_set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); }
 231
 232 static inline void srmmu_pgd_set(pgd_t * pgdp, pmd_t * pmdp)
 233 { srmmu_set_pte((pte_t *)pgdp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pmdp) >> 4))); }
 234
 235 static void srmmu_pmd_set(pmd_t *pmdp, pte_t *ptep)
 236 {
 237         unsigned long ptp;      /* Physical address, shifted right by 4 */
 238         int i;
 239
 240         ptp = __nocache_pa((unsigned long) ptep) >> 4;
 241         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
 242                 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
 243                 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
 244         }
 245 }
 246
 247 static void srmmu_pmd_populate(pmd_t *pmdp, struct page *ptep)
 248 {
 249         unsigned long ptp;      /* Physical address, shifted right by 4 */
 250         int i;
 251
 252         ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4);      /* watch for overflow */
 253         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
 254                 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
 255                 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
 256         }
 257 }
 258
 259 static inline pte_t srmmu_pte_modify(pte_t pte, pgprot_t newprot)
 260 { return __pte((pte_val(pte) & SRMMU_CHG_MASK) | pgprot_val(newprot)); }
 261
 262 /* to find an entry in a top-level page table... */
 263 extern inline pgd_t *srmmu_pgd_offset(struct mm_struct * mm, unsigned long address)
 264 { return mm->pgd + (address >> SRMMU_PGDIR_SHIFT); }
 265
 266 /* Find an entry in the second-level page table.. */
 267 static inline pmd_t *srmmu_pmd_offset(pgd_t * dir, unsigned long address)
 268 {
 269         return (pmd_t *) srmmu_pgd_page(*dir) +
 270             ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
 271 }
 272
 273 /* Find an entry in the third-level page table.. */
 274 static inline pte_t *srmmu_pte_offset(pmd_t * dir, unsigned long address)
 275 {
 276         void *pte;
 277
 278         pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4);
 279         return (pte_t *) pte +
 280             ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
 281 }
 282
 283 static unsigned long srmmu_swp_type(swp_entry_t entry)
 284 {
 285         return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK;
 286 }
 287
 288 static unsigned long srmmu_swp_offset(swp_entry_t entry)
 289 {
 290         return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK;
 291 }
 292
 293 static swp_entry_t srmmu_swp_entry(unsigned long type, unsigned long offset)
 294 {
 295         return (swp_entry_t) {
 296                   (type & SRMMU_SWP_TYPE_MASK) << SRMMU_SWP_TYPE_SHIFT
 297                 | (offset & SRMMU_SWP_OFF_MASK) << SRMMU_SWP_OFF_SHIFT };
 298 }
 299
 300 /*
 301  * size: bytes to allocate in the nocache area.
 302  * align: bytes, number to align at.
 303  * Returns the virtual address of the allocated area.
 304  */
 305 static unsigned long __srmmu_get_nocache(int size, int align)
 306 {
 307         int offset;
 308
 309         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
 310                 printk("Size 0x%x too small for nocache request\n", size);
 311                 size = SRMMU_NOCACHE_BITMAP_SHIFT;
 312         }
 313         if (size & (SRMMU_NOCACHE_BITMAP_SHIFT-1)) {
 314                 printk("Size 0x%x unaligned int nocache request\n", size);
 315                 size += SRMMU_NOCACHE_BITMAP_SHIFT-1;
 316         }
 317         BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
 318
 319         offset = bit_map_string_get(&srmmu_nocache_map,
 320                                         size >> SRMMU_NOCACHE_BITMAP_SHIFT,
 321                                         align >> SRMMU_NOCACHE_BITMAP_SHIFT);
 322         if (offset == -1) {
 323                 printk("srmmu: out of nocache %d: %d/%d\n",
 324                     size, (int) srmmu_nocache_size,
 325                     srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
 326                 return 0;
 327         }
 328
 329         return (SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT));
 330 }
 331
 332 unsigned inline long srmmu_get_nocache(int size, int align)
 333 {
 334         unsigned long tmp;
 335
 336         tmp = __srmmu_get_nocache(size, align);
 337
 338         if (tmp)
 339                 memset((void *)tmp, 0, size);
 340
 341         return tmp;
 342 }
 343
 344 void srmmu_free_nocache(unsigned long vaddr, int size)
 345 {
 346         int offset;
 347
 348         if (vaddr < SRMMU_NOCACHE_VADDR) {
 349                 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
 350                     vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
 351                 BUG();
 352         }
 353         if (vaddr+size > srmmu_nocache_end) {
 354                 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
 355                     vaddr, srmmu_nocache_end);
 356                 BUG();
 357         }
 358         if (size & (size-1)) {
 359                 printk("Size 0x%x is not a power of 2\n", size);
 360                 BUG();
 361         }
 362         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
 363                 printk("Size 0x%x is too small\n", size);
 364                 BUG();
 365         }
 366         if (vaddr & (size-1)) {
 367                 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
 368                 BUG();
 369         }
 370
 371         offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
 372         size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 373
 374         bit_map_clear(&srmmu_nocache_map, offset, size);
 375 }
 376
 377 void srmmu_early_allocate_ptable_skeleton(unsigned long start, unsigned long end);
 378
 379 extern unsigned long probe_memory(void);        /* in fault.c */
 380
 381 /*
 382  * Reserve nocache dynamically proportionally to the amount of
 383  * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
 384  */
 385 void srmmu_nocache_calcsize(void)
 386 {
 387         unsigned long sysmemavail = probe_memory() / 1024;
 388         int srmmu_nocache_npages;
 389
 390         srmmu_nocache_npages =
 391                 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
 392
 393  /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
 394         // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
 395         if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
 396                 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
 397
 398         /* anything above 1280 blows up */
 399         if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
 400                 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
 401
 402         srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
 403         srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
 404 }
 405
 406 void srmmu_nocache_init(void)
 407 {
 408         unsigned int bitmap_bits;
 409         pgd_t *pgd;
 410         pmd_t *pmd;
 411         pte_t *pte;
 412         unsigned long paddr, vaddr;
 413         unsigned long pteval;
 414
 415         bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 416
 417         srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size,
 418                 SRMMU_NOCACHE_ALIGN_MAX, 0UL);
 419         memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
 420
 421         srmmu_nocache_bitmap = __alloc_bootmem(bitmap_bits >> 3, SMP_CACHE_BYTES, 0UL);
 422         bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
 423
 424         srmmu_swapper_pg_dir = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 425         memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
 426         init_mm.pgd = srmmu_swapper_pg_dir;
 427
 428         srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
 429
 430         paddr = __pa((unsigned long)srmmu_nocache_pool);
 431         vaddr = SRMMU_NOCACHE_VADDR;
 432
 433         while (vaddr < srmmu_nocache_end) {
 434                 pgd = pgd_offset_k(vaddr);
 435                 pmd = srmmu_pmd_offset(__nocache_fix(pgd), vaddr);
 436                 pte = srmmu_pte_offset(__nocache_fix(pmd), vaddr);
 437
 438                 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
 439
 440                 if (srmmu_cache_pagetables)
 441                         pteval |= SRMMU_CACHE;
 442
 443                 srmmu_set_pte(__nocache_fix(pte), __pte(pteval));
 444
 445                 vaddr += PAGE_SIZE;
 446                 paddr += PAGE_SIZE;
 447         }
 448
 449         flush_cache_all();
 450         flush_tlb_all();
 451 }
 452
 453 static inline pgd_t *srmmu_get_pgd_fast(void)
 454 {
 455         pgd_t *pgd = NULL;
 456
 457         pgd = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 458         if (pgd) {
 459                 pgd_t *init = pgd_offset_k(0);
 460                 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
 461                 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
 462                                                 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
 463         }
 464
 465         return pgd;
 466 }
 467
 468 static void srmmu_free_pgd_fast(pgd_t *pgd)
 469 {
 470         srmmu_free_nocache((unsigned long)pgd, SRMMU_PGD_TABLE_SIZE);
 471 }
 472
 473 static pmd_t *srmmu_pmd_alloc_one(struct mm_struct *mm, unsigned long address)
 474 {
 475         return (pmd_t *)srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
 476 }
 477
 478 static void srmmu_pmd_free(pmd_t * pmd)
 479 {
 480         srmmu_free_nocache((unsigned long)pmd, SRMMU_PMD_TABLE_SIZE);
 481 }
 482
 483 /*
 484  * Hardware needs alignment to 256 only, but we align to whole page size
 485  * to reduce fragmentation problems due to the buddy principle.
 486  * XXX Provide actual fragmentation statistics in /proc.
 487  *
 488  * Alignments up to the page size are the same for physical and virtual
 489  * addresses of the nocache area.
 490  */
 491 static pte_t *
 492 srmmu_pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
 493 {
 494         return (pte_t *)srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
 495 }
 496
 497 static struct page *
 498 srmmu_pte_alloc_one(struct mm_struct *mm, unsigned long address)
 499 {
 500         unsigned long pte;
 501
 502         if ((pte = (unsigned long)srmmu_pte_alloc_one_kernel(mm, address)) == 0)
 503                 return NULL;
 504         return pfn_to_page( __nocache_pa(pte) >> PAGE_SHIFT );
 505 }
 506
 507 static void srmmu_free_pte_fast(pte_t *pte)
 508 {
 509         srmmu_free_nocache((unsigned long)pte, PTE_SIZE);
 510 }
 511
 512 static void srmmu_pte_free(struct page *pte)
 513 {
 514         unsigned long p;
 515
 516         p = (unsigned long)page_address(pte);   /* Cached address (for test) */
 517         if (p == 0)
 518                 BUG();
 519         p = page_to_pfn(pte) << PAGE_SHIFT;     /* Physical address */
 520         p = (unsigned long) __nocache_va(p);    /* Nocached virtual */
 521         srmmu_free_nocache(p, PTE_SIZE);
 522 }
 523
 524 /*
 525  */
 526 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
 527 {
 528         struct ctx_list *ctxp;
 529
 530         ctxp = ctx_free.next;
 531         if(ctxp != &ctx_free) {
 532                 remove_from_ctx_list(ctxp);
 533                 add_to_used_ctxlist(ctxp);
 534                 mm->context = ctxp->ctx_number;
 535                 ctxp->ctx_mm = mm;
 536                 return;
 537         }
 538         ctxp = ctx_used.next;
 539         if(ctxp->ctx_mm == old_mm)
 540                 ctxp = ctxp->next;
 541         if(ctxp == &ctx_used)
 542                 panic("out of mmu contexts");
 543         flush_cache_mm(ctxp->ctx_mm);
 544         flush_tlb_mm(ctxp->ctx_mm);
 545         remove_from_ctx_list(ctxp);
 546         add_to_used_ctxlist(ctxp);
 547         ctxp->ctx_mm->context = NO_CONTEXT;
 548         ctxp->ctx_mm = mm;
 549         mm->context = ctxp->ctx_number;
 550 }
 551
 552 static inline void free_context(int context)
 553 {
 554         struct ctx_list *ctx_old;
 555
 556         ctx_old = ctx_list_pool + context;
 557         remove_from_ctx_list(ctx_old);
 558         add_to_free_ctxlist(ctx_old);
 559 }
 560
 561
 562 static void srmmu_switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
 563     struct task_struct *tsk, int cpu)
 564 {
 565         if(mm->context == NO_CONTEXT) {
 566                 spin_lock(&srmmu_context_spinlock);
 567                 alloc_context(old_mm, mm);
 568                 spin_unlock(&srmmu_context_spinlock);
 569                 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
 570         }
 571
 572         if (is_hypersparc)
 573                 hyper_flush_whole_icache();
 574
 575         srmmu_set_context(mm->context);
 576 }
 577
 578 /* Low level IO area allocation on the SRMMU. */
 579 static inline void srmmu_mapioaddr(unsigned long physaddr,
 580     unsigned long virt_addr, int bus_type)
 581 {
 582         pgd_t *pgdp;
 583         pmd_t *pmdp;
 584         pte_t *ptep;
 585         unsigned long tmp;
 586
 587         physaddr &= PAGE_MASK;
 588         pgdp = pgd_offset_k(virt_addr);
 589         pmdp = srmmu_pmd_offset(pgdp, virt_addr);
 590         ptep = srmmu_pte_offset(pmdp, virt_addr);
 591         tmp = (physaddr >> 4) | SRMMU_ET_PTE;
 592
 593         /*
 594          * I need to test whether this is consistent over all
 595          * sun4m's.  The bus_type represents the upper 4 bits of
 596          * 36-bit physical address on the I/O space lines...
 597          */
 598         tmp |= (bus_type << 28);
 599         tmp |= SRMMU_PRIV;
 600         __flush_page_to_ram(virt_addr);
 601         srmmu_set_pte(ptep, __pte(tmp));
 602 }
 603
 604 static void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
 605     unsigned long xva, unsigned int len)
 606 {
 607         while (len != 0) {
 608                 len -= PAGE_SIZE;
 609                 srmmu_mapioaddr(xpa, xva, bus);
 610                 xva += PAGE_SIZE;
 611                 xpa += PAGE_SIZE;
 612         }
 613         flush_tlb_all();
 614 }
 615
 616 static inline void srmmu_unmapioaddr(unsigned long virt_addr)
 617 {
 618         pgd_t *pgdp;
 619         pmd_t *pmdp;
 620         pte_t *ptep;
 621
 622         pgdp = pgd_offset_k(virt_addr);
 623         pmdp = srmmu_pmd_offset(pgdp, virt_addr);
 624         ptep = srmmu_pte_offset(pmdp, virt_addr);
 625
 626         /* No need to flush uncacheable page. */
 627         srmmu_pte_clear(ptep);
 628 }
 629
 630 static void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
 631 {
 632         while (len != 0) {
 633                 len -= PAGE_SIZE;
 634                 srmmu_unmapioaddr(virt_addr);
 635                 virt_addr += PAGE_SIZE;
 636         }
 637         flush_tlb_all();
 638 }
 639
 640 /*
 641  * On the SRMMU we do not have the problems with limited tlb entries
 642  * for mapping kernel pages, so we just take things from the free page
 643  * pool.  As a side effect we are putting a little too much pressure
 644  * on the gfp() subsystem.  This setup also makes the logic of the
 645  * iommu mapping code a lot easier as we can transparently handle
 646  * mappings on the kernel stack without any special code as we did
 647  * need on the sun4c.
 648  */
 649 struct thread_info *srmmu_alloc_thread_info(void)
 650 {
 651         struct thread_info *ret;
 652
 653         ret = (struct thread_info *)__get_free_pages(GFP_KERNEL,
 654                                                      THREAD_INFO_ORDER);
 655 #ifdef CONFIG_DEBUG_STACK_USAGE
 656         if (ret)
 657                 memset(ret, 0, PAGE_SIZE << THREAD_INFO_ORDER);
 658 #endif /* DEBUG_STACK_USAGE */
 659
 660         return ret;
 661 }
 662
 663 static void srmmu_free_thread_info(struct thread_info *ti)
 664 {
 665         free_pages((unsigned long)ti, THREAD_INFO_ORDER);
 666 }
 667
 668 /* tsunami.S */
 669 extern void tsunami_flush_cache_all(void);
 670 extern void tsunami_flush_cache_mm(struct mm_struct *mm);
 671 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 672 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 673 extern void tsunami_flush_page_to_ram(unsigned long page);
 674 extern void tsunami_flush_page_for_dma(unsigned long page);
 675 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 676 extern void tsunami_flush_tlb_all(void);
 677 extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
 678 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 679 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 680 extern void tsunami_setup_blockops(void);
 681
 682 /*
 683  * Workaround, until we find what's going on with Swift. When low on memory,
 684  * it sometimes loops in fault/handle_mm_fault incl. flush_tlb_page to find
 685  * out it is already in page tables/ fault again on the same instruction.
 686  * I really don't understand it, have checked it and contexts
 687  * are right, flush_tlb_all is done as well, and it faults again...
 688  * Strange. -jj
 689  *
 690  * The following code is a deadwood that may be necessary when
 691  * we start to make precise page flushes again. --zaitcev
 692  */
 693 static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
 694 {
 695 #if 0
 696         static unsigned long last;
 697         unsigned int val;
 698         /* unsigned int n; */
 699
 700         if (address == last) {
 701                 val = srmmu_hwprobe(address);
 702                 if (val != 0 && pte_val(pte) != val) {
 703                         printk("swift_update_mmu_cache: "
 704                             "addr %lx put %08x probed %08x from %p\n",
 705                             address, pte_val(pte), val,
 706                             __builtin_return_address(0));
 707                         srmmu_flush_whole_tlb();
 708                 }
 709         }
 710         last = address;
 711 #endif
 712 }
 713
 714 /* swift.S */
 715 extern void swift_flush_cache_all(void);
 716 extern void swift_flush_cache_mm(struct mm_struct *mm);
 717 extern void swift_flush_cache_range(struct vm_area_struct *vma,
 718                                     unsigned long start, unsigned long end);
 719 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 720 extern void swift_flush_page_to_ram(unsigned long page);
 721 extern void swift_flush_page_for_dma(unsigned long page);
 722 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 723 extern void swift_flush_tlb_all(void);
 724 extern void swift_flush_tlb_mm(struct mm_struct *mm);
 725 extern void swift_flush_tlb_range(struct vm_area_struct *vma,
 726                                   unsigned long start, unsigned long end);
 727 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 728
 729 #if 0  /* P3: deadwood to debug precise flushes on Swift. */
 730 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 731 {
 732         int cctx, ctx1;
 733
 734         page &= PAGE_MASK;
 735         if ((ctx1 = vma->vm_mm->context) != -1) {
 736                 cctx = srmmu_get_context();
 737 /* Is context # ever different from current context? P3 */
 738                 if (cctx != ctx1) {
 739                         printk("flush ctx %02x curr %02x\n", ctx1, cctx);
 740                         srmmu_set_context(ctx1);
 741                         swift_flush_page(page);
 742                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 743                                         "r" (page), "i" (ASI_M_FLUSH_PROBE));
 744                         srmmu_set_context(cctx);
 745                 } else {
 746                          /* Rm. prot. bits from virt. c. */
 747                         /* swift_flush_cache_all(); */
 748                         /* swift_flush_cache_page(vma, page); */
 749                         swift_flush_page(page);
 750
 751                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 752                                 "r" (page), "i" (ASI_M_FLUSH_PROBE));
 753                         /* same as above: srmmu_flush_tlb_page() */
 754                 }
 755         }
 756 }
 757 #endif
 758
 759 /*
 760  * The following are all MBUS based SRMMU modules, and therefore could
 761  * be found in a multiprocessor configuration.  On the whole, these
 762  * chips seems to be much more touchy about DVMA and page tables
 763  * with respect to cache coherency.
 764  */
 765
 766 /* Cypress flushes. */
 767 static void cypress_flush_cache_all(void)
 768 {
 769         volatile unsigned long cypress_sucks;
 770         unsigned long faddr, tagval;
 771
 772         flush_user_windows();
 773         for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
 774                 __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
 775                                      "=r" (tagval) :
 776                                      "r" (faddr), "r" (0x40000),
 777                                      "i" (ASI_M_DATAC_TAG));
 778
 779                 /* If modified and valid, kick it. */
 780                 if((tagval & 0x60) == 0x60)
 781                         cypress_sucks = *(unsigned long *)(0xf0020000 + faddr);
 782         }
 783 }
 784
 785 static void cypress_flush_cache_mm(struct mm_struct *mm)
 786 {
 787         register unsigned long a, b, c, d, e, f, g;
 788         unsigned long flags, faddr;
 789         int octx;
 790
 791         FLUSH_BEGIN(mm)
 792         flush_user_windows();
 793         local_irq_save(flags);
 794         octx = srmmu_get_context();
 795         srmmu_set_context(mm->context);
 796         a = 0x20; b = 0x40; c = 0x60;
 797         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 798
 799         faddr = (0x10000 - 0x100);
 800         goto inside;
 801         do {
 802                 faddr -= 0x100;
 803         inside:
 804                 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 805                                      "sta %%g0, [%0 + %2] %1\n\t"
 806                                      "sta %%g0, [%0 + %3] %1\n\t"
 807                                      "sta %%g0, [%0 + %4] %1\n\t"
 808                                      "sta %%g0, [%0 + %5] %1\n\t"
 809                                      "sta %%g0, [%0 + %6] %1\n\t"
 810                                      "sta %%g0, [%0 + %7] %1\n\t"
 811                                      "sta %%g0, [%0 + %8] %1\n\t" : :
 812                                      "r" (faddr), "i" (ASI_M_FLUSH_CTX),
 813                                      "r" (a), "r" (b), "r" (c), "r" (d),
 814                                      "r" (e), "r" (f), "r" (g));
 815         } while(faddr);
 816         srmmu_set_context(octx);
 817         local_irq_restore(flags);
 818         FLUSH_END
 819 }
 820
 821 static void cypress_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 822 {
 823         struct mm_struct *mm = vma->vm_mm;
 824         register unsigned long a, b, c, d, e, f, g;
 825         unsigned long flags, faddr;
 826         int octx;
 827
 828         FLUSH_BEGIN(mm)
 829         flush_user_windows();
 830         local_irq_save(flags);
 831         octx = srmmu_get_context();
 832         srmmu_set_context(mm->context);
 833         a = 0x20; b = 0x40; c = 0x60;
 834         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 835
 836         start &= SRMMU_REAL_PMD_MASK;
 837         while(start < end) {
 838                 faddr = (start + (0x10000 - 0x100));
 839                 goto inside;
 840                 do {
 841                         faddr -= 0x100;
 842                 inside:
 843                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 844                                              "sta %%g0, [%0 + %2] %1\n\t"
 845                                              "sta %%g0, [%0 + %3] %1\n\t"
 846                                              "sta %%g0, [%0 + %4] %1\n\t"
 847                                              "sta %%g0, [%0 + %5] %1\n\t"
 848                                              "sta %%g0, [%0 + %6] %1\n\t"
 849                                              "sta %%g0, [%0 + %7] %1\n\t"
 850                                              "sta %%g0, [%0 + %8] %1\n\t" : :
 851                                              "r" (faddr),
 852                                              "i" (ASI_M_FLUSH_SEG),
 853                                              "r" (a), "r" (b), "r" (c), "r" (d),
 854                                              "r" (e), "r" (f), "r" (g));
 855                 } while (faddr != start);
 856                 start += SRMMU_REAL_PMD_SIZE;
 857         }
 858         srmmu_set_context(octx);
 859         local_irq_restore(flags);
 860         FLUSH_END
 861 }
 862
 863 static void cypress_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
 864 {
 865         register unsigned long a, b, c, d, e, f, g;
 866         struct mm_struct *mm = vma->vm_mm;
 867         unsigned long flags, line;
 868         int octx;
 869
 870         FLUSH_BEGIN(mm)
 871         flush_user_windows();
 872         local_irq_save(flags);
 873         octx = srmmu_get_context();
 874         srmmu_set_context(mm->context);
 875         a = 0x20; b = 0x40; c = 0x60;
 876         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 877
 878         page &= PAGE_MASK;
 879         line = (page + PAGE_SIZE) - 0x100;
 880         goto inside;
 881         do {
 882                 line -= 0x100;
 883         inside:
 884                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 885                                              "sta %%g0, [%0 + %2] %1\n\t"
 886                                              "sta %%g0, [%0 + %3] %1\n\t"
 887                                              "sta %%g0, [%0 + %4] %1\n\t"
 888                                              "sta %%g0, [%0 + %5] %1\n\t"
 889                                              "sta %%g0, [%0 + %6] %1\n\t"
 890                                              "sta %%g0, [%0 + %7] %1\n\t"
 891                                              "sta %%g0, [%0 + %8] %1\n\t" : :
 892                                              "r" (line),
 893                                              "i" (ASI_M_FLUSH_PAGE),
 894                                              "r" (a), "r" (b), "r" (c), "r" (d),
 895                                              "r" (e), "r" (f), "r" (g));
 896         } while(line != page);
 897         srmmu_set_context(octx);
 898         local_irq_restore(flags);
 899         FLUSH_END
 900 }
 901
 902 /* Cypress is copy-back, at least that is how we configure it. */
 903 static void cypress_flush_page_to_ram(unsigned long page)
 904 {
 905         register unsigned long a, b, c, d, e, f, g;
 906         unsigned long line;
 907
 908         a = 0x20; b = 0x40; c = 0x60; d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 909         page &= PAGE_MASK;
 910         line = (page + PAGE_SIZE) - 0x100;
 911         goto inside;
 912         do {
 913                 line -= 0x100;
 914         inside:
 915                 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 916                                      "sta %%g0, [%0 + %2] %1\n\t"
 917                                      "sta %%g0, [%0 + %3] %1\n\t"
 918                                      "sta %%g0, [%0 + %4] %1\n\t"
 919                                      "sta %%g0, [%0 + %5] %1\n\t"
 920                                      "sta %%g0, [%0 + %6] %1\n\t"
 921                                      "sta %%g0, [%0 + %7] %1\n\t"
 922                                      "sta %%g0, [%0 + %8] %1\n\t" : :
 923                                      "r" (line),
 924                                      "i" (ASI_M_FLUSH_PAGE),
 925                                      "r" (a), "r" (b), "r" (c), "r" (d),
 926                                      "r" (e), "r" (f), "r" (g));
 927         } while(line != page);
 928 }
 929
 930 /* Cypress is also IO cache coherent. */
 931 static void cypress_flush_page_for_dma(unsigned long page)
 932 {
 933 }
 934
 935 /* Cypress has unified L2 VIPT, from which both instructions and data
 936  * are stored.  It does not have an onboard icache of any sort, therefore
 937  * no flush is necessary.
 938  */
 939 static void cypress_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
 940 {
 941 }
 942
 943 static void cypress_flush_tlb_all(void)
 944 {
 945         srmmu_flush_whole_tlb();
 946 }
 947
 948 static void cypress_flush_tlb_mm(struct mm_struct *mm)
 949 {
 950         FLUSH_BEGIN(mm)
 951         __asm__ __volatile__(
 952         "lda    [%0] %3, %%g5\n\t"
 953         "sta    %2, [%0] %3\n\t"
 954         "sta    %%g0, [%1] %4\n\t"
 955         "sta    %%g5, [%0] %3\n"
 956         : /* no outputs */
 957         : "r" (SRMMU_CTX_REG), "r" (0x300), "r" (mm->context),
 958           "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
 959         : "g5");
 960         FLUSH_END
 961 }
 962
 963 static void cypress_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 964 {
 965         struct mm_struct *mm = vma->vm_mm;
 966         unsigned long size;
 967
 968         FLUSH_BEGIN(mm)
 969         start &= SRMMU_PGDIR_MASK;
 970         size = SRMMU_PGDIR_ALIGN(end) - start;
 971         __asm__ __volatile__(
 972                 "lda    [%0] %5, %%g5\n\t"
 973                 "sta    %1, [%0] %5\n"
 974                 "1:\n\t"
 975                 "subcc  %3, %4, %3\n\t"
 976                 "bne    1b\n\t"
 977                 " sta   %%g0, [%2 + %3] %6\n\t"
 978                 "sta    %%g5, [%0] %5\n"
 979         : /* no outputs */
 980         : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (start | 0x200),
 981           "r" (size), "r" (SRMMU_PGDIR_SIZE), "i" (ASI_M_MMUREGS),
 982           "i" (ASI_M_FLUSH_PROBE)
 983         : "g5", "cc");
 984         FLUSH_END
 985 }
 986
 987 static void cypress_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 988 {
 989         struct mm_struct *mm = vma->vm_mm;
 990
 991         FLUSH_BEGIN(mm)
 992         __asm__ __volatile__(
 993         "lda    [%0] %3, %%g5\n\t"
 994         "sta    %1, [%0] %3\n\t"
 995         "sta    %%g0, [%2] %4\n\t"
 996         "sta    %%g5, [%0] %3\n"
 997         : /* no outputs */
 998         : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (page & PAGE_MASK),
 999           "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
1000         : "g5");
1001         FLUSH_END
1002 }
1003
1004 /* viking.S */
1005 extern void viking_flush_cache_all(void);
1006 extern void viking_flush_cache_mm(struct mm_struct *mm);
1007 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
1008                                      unsigned long end);
1009 extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
1010 extern void viking_flush_page_to_ram(unsigned long page);
1011 extern void viking_flush_page_for_dma(unsigned long page);
1012 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
1013 extern void viking_flush_page(unsigned long page);
1014 extern void viking_mxcc_flush_page(unsigned long page);
1015 extern void viking_flush_tlb_all(void);
1016 extern void viking_flush_tlb_mm(struct mm_struct *mm);
1017 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
1018                                    unsigned long end);
1019 extern void viking_flush_tlb_page(struct vm_area_struct *vma,
1020                                   unsigned long page);
1021 extern void sun4dsmp_flush_tlb_all(void);
1022 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
1023 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
1024                                    unsigned long end);
1025 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
1026                                   unsigned long page);
1027
1028 /* hypersparc.S */
1029 extern void hypersparc_flush_cache_all(void);
1030 extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
1031 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
1032 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
1033 extern void hypersparc_flush_page_to_ram(unsigned long page);
1034 extern void hypersparc_flush_page_for_dma(unsigned long page);
1035 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
1036 extern void hypersparc_flush_tlb_all(void);
1037 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
1038 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
1039 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
1040 extern void hypersparc_setup_blockops(void);
1041
1042 /*
1043  * NOTE: All of this startup code assumes the low 16mb (approx.) of
1044  *       kernel mappings are done with one single contiguous chunk of
1045  *       ram.  On small ram machines (classics mainly) we only get
1046  *       around 8mb mapped for us.
1047  */
1048
1049 void __init early_pgtable_allocfail(char *type)
1050 {
1051         prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
1052         prom_halt();
1053 }
1054
1055 void __init srmmu_early_allocate_ptable_skeleton(unsigned long start, unsigned long end)
1056 {
1057         pgd_t *pgdp;
1058         pmd_t *pmdp;
1059         pte_t *ptep;
1060
1061         while(start < end) {
1062                 pgdp = pgd_offset_k(start);
1063                 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1064                         pmdp = (pmd_t *) __srmmu_get_nocache(
1065                             SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1066                         if (pmdp == NULL)
1067                                 early_pgtable_allocfail("pmd");
1068                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1069                         srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1070                 }
1071                 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1072                 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1073                         ptep = (pte_t *)__srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
1074                         if (ptep == NULL)
1075                                 early_pgtable_allocfail("pte");
1076                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
1077                         srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1078                 }
1079                 if (start > (0xffffffffUL - PMD_SIZE))
1080                         break;
1081                 start = (start + PMD_SIZE) & PMD_MASK;
1082         }
1083 }
1084
1085 void __init srmmu_allocate_ptable_skeleton(unsigned long start, unsigned long end)
1086 {
1087         pgd_t *pgdp;
1088         pmd_t *pmdp;
1089         pte_t *ptep;
1090
1091         while(start < end) {
1092                 pgdp = pgd_offset_k(start);
1093                 if(srmmu_pgd_none(*pgdp)) {
1094                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1095                         if (pmdp == NULL)
1096                                 early_pgtable_allocfail("pmd");
1097                         memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
1098                         srmmu_pgd_set(pgdp, pmdp);
1099                 }
1100                 pmdp = srmmu_pmd_offset(pgdp, start);
1101                 if(srmmu_pmd_none(*pmdp)) {
1102                         ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1103                                                              PTE_SIZE);
1104                         if (ptep == NULL)
1105                                 early_pgtable_allocfail("pte");
1106                         memset(ptep, 0, PTE_SIZE);
1107                         srmmu_pmd_set(pmdp, ptep);
1108                 }
1109                 if (start > (0xffffffffUL - PMD_SIZE))
1110                         break;
1111                 start = (start + PMD_SIZE) & PMD_MASK;
1112         }
1113 }
1114
1115 /*
1116  * This is much cleaner than poking around physical address space
1117  * looking at the prom's page table directly which is what most
1118  * other OS's do.  Yuck... this is much better.
1119  */
1120 void __init srmmu_inherit_prom_mappings(unsigned long start,unsigned long end)
1121 {
1122         pgd_t *pgdp;
1123         pmd_t *pmdp;
1124         pte_t *ptep;
1125         int what = 0; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
1126         unsigned long prompte;
1127
1128         while(start <= end) {
1129                 if (start == 0)
1130                         break; /* probably wrap around */
1131                 if(start == 0xfef00000)
1132                         start = KADB_DEBUGGER_BEGVM;
1133                 if(!(prompte = srmmu_hwprobe(start))) {
1134                         start += PAGE_SIZE;
1135                         continue;
1136                 }
1137
1138                 /* A red snapper, see what it really is. */
1139                 what = 0;
1140
1141                 if(!(start & ~(SRMMU_REAL_PMD_MASK))) {
1142                         if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_REAL_PMD_SIZE) == prompte)
1143                                 what = 1;
1144                 }
1145
1146                 if(!(start & ~(SRMMU_PGDIR_MASK))) {
1147                         if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_PGDIR_SIZE) ==
1148                            prompte)
1149                                 what = 2;
1150                 }
1151
1152                 pgdp = pgd_offset_k(start);
1153                 if(what == 2) {
1154                         *(pgd_t *)__nocache_fix(pgdp) = __pgd(prompte);
1155                         start += SRMMU_PGDIR_SIZE;
1156                         continue;
1157                 }
1158                 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1159                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1160                         if (pmdp == NULL)
1161                                 early_pgtable_allocfail("pmd");
1162                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1163                         srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1164                 }
1165                 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1166                 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1167                         ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1168                                                              PTE_SIZE);
1169                         if (ptep == NULL)
1170                                 early_pgtable_allocfail("pte");
1171                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
1172                         srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1173                 }
1174                 if(what == 1) {
1175                         /*
1176                          * We bend the rule where all 16 PTPs in a pmd_t point
1177                          * inside the same PTE page, and we leak a perfectly
1178                          * good hardware PTE piece. Alternatives seem worse.
1179                          */
1180                         unsigned int x; /* Index of HW PMD in soft cluster */
1181                         x = (start >> PMD_SHIFT) & 15;
1182                         *(unsigned long *)__nocache_fix(&pmdp->pmdv[x]) = prompte;
1183                         start += SRMMU_REAL_PMD_SIZE;
1184                         continue;
1185                 }
1186                 ptep = srmmu_pte_offset(__nocache_fix(pmdp), start);
1187                 *(pte_t *)__nocache_fix(ptep) = __pte(prompte);
1188                 start += PAGE_SIZE;
1189         }
1190 }
1191
1192 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
1193
1194 /* Create a third-level SRMMU 16MB page mapping. */
1195 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
1196 {
1197         pgd_t *pgdp = pgd_offset_k(vaddr);
1198         unsigned long big_pte;
1199
1200         big_pte = KERNEL_PTE(phys_base >> 4);
1201         *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte);
1202 }
1203
1204 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
1205 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
1206 {
1207         unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK);
1208         unsigned long vstart = (vbase & SRMMU_PGDIR_MASK);
1209         unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
1210         /* Map "low" memory only */
1211         const unsigned long min_vaddr = PAGE_OFFSET;
1212         const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
1213
1214         if (vstart < min_vaddr || vstart >= max_vaddr)
1215                 return vstart;
1216
1217         if (vend > max_vaddr || vend < min_vaddr)
1218                 vend = max_vaddr;
1219
1220         while(vstart < vend) {
1221                 do_large_mapping(vstart, pstart);
1222                 vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE;
1223         }
1224         return vstart;
1225 }
1226
1227 static inline void memprobe_error(char *msg)
1228 {
1229         prom_printf(msg);
1230         prom_printf("Halting now...\n");
1231         prom_halt();
1232 }
1233
1234 static inline void map_kernel(void)
1235 {
1236         int i;
1237
1238         if (phys_base > 0) {
1239                 do_large_mapping(PAGE_OFFSET, phys_base);
1240         }
1241
1242         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1243                 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
1244         }
1245
1246         BTFIXUPSET_SIMM13(user_ptrs_per_pgd, PAGE_OFFSET / SRMMU_PGDIR_SIZE);
1247 }
1248
1249 /* Paging initialization on the Sparc Reference MMU. */
1250 extern void sparc_context_init(int);
1251
1252 void (*poke_srmmu)(void) __initdata = NULL;
1253
1254 extern unsigned long bootmem_init(unsigned long *pages_avail);
1255
1256 void __init srmmu_paging_init(void)
1257 {
1258         int i, cpunode;
1259         char node_str[128];
1260         pgd_t *pgd;
1261         pmd_t *pmd;
1262         pte_t *pte;
1263         unsigned long pages_avail;
1264
1265         sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
1266
1267         if (sparc_cpu_model == sun4d)
1268                 num_contexts = 65536; /* We know it is Viking */
1269         else {
1270                 /* Find the number of contexts on the srmmu. */
1271                 cpunode = prom_getchild(prom_root_node);
1272                 num_contexts = 0;
1273                 while(cpunode != 0) {
1274                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1275                         if(!strcmp(node_str, "cpu")) {
1276                                 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
1277                                 break;
1278                         }
1279                         cpunode = prom_getsibling(cpunode);
1280                 }
1281         }
1282
1283         if(!num_contexts) {
1284                 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
1285                 prom_halt();
1286         }
1287
1288         pages_avail = 0;
1289         last_valid_pfn = bootmem_init(&pages_avail);
1290
1291         srmmu_nocache_calcsize();
1292         srmmu_nocache_init();
1293         srmmu_inherit_prom_mappings(0xfe400000,(LINUX_OPPROM_ENDVM-PAGE_SIZE));
1294         map_kernel();
1295
1296         /* ctx table has to be physically aligned to its size */
1297         srmmu_context_table = (ctxd_t *)__srmmu_get_nocache(num_contexts*sizeof(ctxd_t), num_contexts*sizeof(ctxd_t));
1298         srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa((unsigned long)srmmu_context_table);
1299
1300         for(i = 0; i < num_contexts; i++)
1301                 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
1302
1303         flush_cache_all();
1304         srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
1305         flush_tlb_all();
1306         poke_srmmu();
1307
1308 #ifdef CONFIG_SUN_IO
1309         srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
1310         srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
1311 #endif
1312
1313         srmmu_allocate_ptable_skeleton(
1314                 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
1315         srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
1316
1317         pgd = pgd_offset_k(PKMAP_BASE);
1318         pmd = srmmu_pmd_offset(pgd, PKMAP_BASE);
1319         pte = srmmu_pte_offset(pmd, PKMAP_BASE);
1320         pkmap_page_table = pte;
1321
1322         flush_cache_all();
1323         flush_tlb_all();
1324
1325         sparc_context_init(num_contexts);
1326
1327         kmap_init();
1328
1329         {
1330                 unsigned long zones_size[MAX_NR_ZONES];
1331                 unsigned long zholes_size[MAX_NR_ZONES];
1332                 unsigned long npages;
1333                 int znum;
1334
1335                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1336                         zones_size[znum] = zholes_size[znum] = 0;
1337
1338                 npages = max_low_pfn - pfn_base;
1339
1340                 zones_size[ZONE_DMA] = npages;
1341                 zholes_size[ZONE_DMA] = npages - pages_avail;
1342
1343                 npages = highend_pfn - max_low_pfn;
1344                 zones_size[ZONE_HIGHMEM] = npages;
1345                 zholes_size[ZONE_HIGHMEM] = npages - calc_highpages();
1346
1347                 free_area_init_node(0, &contig_page_data, zones_size,
1348                                     pfn_base, zholes_size);
1349         }
1350 }
1351
1352 static void srmmu_mmu_info(struct seq_file *m)
1353 {
1354         seq_printf(m,
1355                    "MMU type\t: %s\n"
1356                    "contexts\t: %d\n"
1357                    "nocache total\t: %ld\n"
1358                    "nocache used\t: %d\n",
1359                    srmmu_name,
1360                    num_contexts,
1361                    srmmu_nocache_size,
1362                    srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
1363 }
1364
1365 static void srmmu_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
1366 {
1367 }
1368
1369 static void srmmu_destroy_context(struct mm_struct *mm)
1370 {
1371
1372         if(mm->context != NO_CONTEXT) {
1373                 flush_cache_mm(mm);
1374                 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
1375                 flush_tlb_mm(mm);
1376                 spin_lock(&srmmu_context_spinlock);
1377                 free_context(mm->context);
1378                 spin_unlock(&srmmu_context_spinlock);
1379                 mm->context = NO_CONTEXT;
1380         }
1381 }
1382
1383 /* Init various srmmu chip types. */
1384 static void __init srmmu_is_bad(void)
1385 {
1386         prom_printf("Could not determine SRMMU chip type.\n");
1387         prom_halt();
1388 }
1389
1390 static void __init init_vac_layout(void)
1391 {
1392         int nd, cache_lines;
1393         char node_str[128];
1394 #ifdef CONFIG_SMP
1395         int cpu = 0;
1396         unsigned long max_size = 0;
1397         unsigned long min_line_size = 0x10000000;
1398 #endif
1399
1400         nd = prom_getchild(prom_root_node);
1401         while((nd = prom_getsibling(nd)) != 0) {
1402                 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1403                 if(!strcmp(node_str, "cpu")) {
1404                         vac_line_size = prom_getint(nd, "cache-line-size");
1405                         if (vac_line_size == -1) {
1406                                 prom_printf("can't determine cache-line-size, "
1407                                             "halting.\n");
1408                                 prom_halt();
1409                         }
1410                         cache_lines = prom_getint(nd, "cache-nlines");
1411                         if (cache_lines == -1) {
1412                                 prom_printf("can't determine cache-nlines, halting.\n");
1413                                 prom_halt();
1414                         }
1415
1416                         vac_cache_size = cache_lines * vac_line_size;
1417 #ifdef CONFIG_SMP
1418                         if(vac_cache_size > max_size)
1419                                 max_size = vac_cache_size;
1420                         if(vac_line_size < min_line_size)
1421                                 min_line_size = vac_line_size;
1422                         cpu++;
1423                         if (cpu >= NR_CPUS || !cpu_online(cpu))
1424                                 break;
1425 #else
1426                         break;
1427 #endif
1428                 }
1429         }
1430         if(nd == 0) {
1431                 prom_printf("No CPU nodes found, halting.\n");
1432                 prom_halt();
1433         }
1434 #ifdef CONFIG_SMP
1435         vac_cache_size = max_size;
1436         vac_line_size = min_line_size;
1437 #endif
1438         printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1439                (int)vac_cache_size, (int)vac_line_size);
1440 }
1441
1442 static void __init poke_hypersparc(void)
1443 {
1444         volatile unsigned long clear;
1445         unsigned long mreg = srmmu_get_mmureg();
1446
1447         hyper_flush_unconditional_combined();
1448
1449         mreg &= ~(HYPERSPARC_CWENABLE);
1450         mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1451         mreg |= (HYPERSPARC_CMODE);
1452
1453         srmmu_set_mmureg(mreg);
1454
1455 #if 0 /* XXX I think this is bad news... -DaveM */
1456         hyper_clear_all_tags();
1457 #endif
1458
1459         put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1460         hyper_flush_whole_icache();
1461         clear = srmmu_get_faddr();
1462         clear = srmmu_get_fstatus();
1463 }
1464
1465 static void __init init_hypersparc(void)
1466 {
1467         srmmu_name = "ROSS HyperSparc";
1468         srmmu_modtype = HyperSparc;
1469
1470         init_vac_layout();
1471
1472         is_hypersparc = 1;
1473
1474         BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1475         BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1476         BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1477         BTFIXUPSET_CALL(flush_cache_all, hypersparc_flush_cache_all, BTFIXUPCALL_NORM);
1478         BTFIXUPSET_CALL(flush_cache_mm, hypersparc_flush_cache_mm, BTFIXUPCALL_NORM);
1479         BTFIXUPSET_CALL(flush_cache_range, hypersparc_flush_cache_range, BTFIXUPCALL_NORM);
1480         BTFIXUPSET_CALL(flush_cache_page, hypersparc_flush_cache_page, BTFIXUPCALL_NORM);
1481
1482         BTFIXUPSET_CALL(flush_tlb_all, hypersparc_flush_tlb_all, BTFIXUPCALL_NORM);
1483         BTFIXUPSET_CALL(flush_tlb_mm, hypersparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1484         BTFIXUPSET_CALL(flush_tlb_range, hypersparc_flush_tlb_range, BTFIXUPCALL_NORM);
1485         BTFIXUPSET_CALL(flush_tlb_page, hypersparc_flush_tlb_page, BTFIXUPCALL_NORM);
1486
1487         BTFIXUPSET_CALL(__flush_page_to_ram, hypersparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1488         BTFIXUPSET_CALL(flush_sig_insns, hypersparc_flush_sig_insns, BTFIXUPCALL_NORM);
1489         BTFIXUPSET_CALL(flush_page_for_dma, hypersparc_flush_page_for_dma, BTFIXUPCALL_NOP);
1490
1491
1492         poke_srmmu = poke_hypersparc;
1493
1494         hypersparc_setup_blockops();
1495 }
1496
1497 static void __init poke_cypress(void)
1498 {
1499         unsigned long mreg = srmmu_get_mmureg();
1500         unsigned long faddr, tagval;
1501         volatile unsigned long cypress_sucks;
1502         volatile unsigned long clear;
1503
1504         clear = srmmu_get_faddr();
1505         clear = srmmu_get_fstatus();
1506
1507         if (!(mreg & CYPRESS_CENABLE)) {
1508                 for(faddr = 0x0; faddr < 0x10000; faddr += 20) {
1509                         __asm__ __volatile__("sta %%g0, [%0 + %1] %2\n\t"
1510                                              "sta %%g0, [%0] %2\n\t" : :
1511                                              "r" (faddr), "r" (0x40000),
1512                                              "i" (ASI_M_DATAC_TAG));
1513                 }
1514         } else {
1515                 for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
1516                         __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
1517                                              "=r" (tagval) :
1518                                              "r" (faddr), "r" (0x40000),
1519                                              "i" (ASI_M_DATAC_TAG));
1520
1521                         /* If modified and valid, kick it. */
1522                         if((tagval & 0x60) == 0x60)
1523                                 cypress_sucks = *(unsigned long *)
1524                                                         (0xf0020000 + faddr);
1525                 }
1526         }
1527
1528         /* And one more, for our good neighbor, Mr. Broken Cypress. */
1529         clear = srmmu_get_faddr();
1530         clear = srmmu_get_fstatus();
1531
1532         mreg |= (CYPRESS_CENABLE | CYPRESS_CMODE);
1533         srmmu_set_mmureg(mreg);
1534 }
1535
1536 static void __init init_cypress_common(void)
1537 {
1538         init_vac_layout();
1539
1540         BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1541         BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1542         BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1543         BTFIXUPSET_CALL(flush_cache_all, cypress_flush_cache_all, BTFIXUPCALL_NORM);
1544         BTFIXUPSET_CALL(flush_cache_mm, cypress_flush_cache_mm, BTFIXUPCALL_NORM);
1545         BTFIXUPSET_CALL(flush_cache_range, cypress_flush_cache_range, BTFIXUPCALL_NORM);
1546         BTFIXUPSET_CALL(flush_cache_page, cypress_flush_cache_page, BTFIXUPCALL_NORM);
1547
1548         BTFIXUPSET_CALL(flush_tlb_all, cypress_flush_tlb_all, BTFIXUPCALL_NORM);
1549         BTFIXUPSET_CALL(flush_tlb_mm, cypress_flush_tlb_mm, BTFIXUPCALL_NORM);
1550         BTFIXUPSET_CALL(flush_tlb_page, cypress_flush_tlb_page, BTFIXUPCALL_NORM);
1551         BTFIXUPSET_CALL(flush_tlb_range, cypress_flush_tlb_range, BTFIXUPCALL_NORM);
1552
1553
1554         BTFIXUPSET_CALL(__flush_page_to_ram, cypress_flush_page_to_ram, BTFIXUPCALL_NORM);
1555         BTFIXUPSET_CALL(flush_sig_insns, cypress_flush_sig_insns, BTFIXUPCALL_NOP);
1556         BTFIXUPSET_CALL(flush_page_for_dma, cypress_flush_page_for_dma, BTFIXUPCALL_NOP);
1557
1558         poke_srmmu = poke_cypress;
1559 }
1560
1561 static void __init init_cypress_604(void)
1562 {
1563         srmmu_name = "ROSS Cypress-604(UP)";
1564         srmmu_modtype = Cypress;
1565         init_cypress_common();
1566 }
1567
1568 static void __init init_cypress_605(unsigned long mrev)
1569 {
1570         srmmu_name = "ROSS Cypress-605(MP)";
1571         if(mrev == 0xe) {
1572                 srmmu_modtype = Cypress_vE;
1573                 hwbug_bitmask |= HWBUG_COPYBACK_BROKEN;
1574         } else {
1575                 if(mrev == 0xd) {
1576                         srmmu_modtype = Cypress_vD;
1577                         hwbug_bitmask |= HWBUG_ASIFLUSH_BROKEN;
1578                 } else {
1579                         srmmu_modtype = Cypress;
1580                 }
1581         }
1582         init_cypress_common();
1583 }
1584
1585 static void __init poke_swift(void)
1586 {
1587         unsigned long mreg;
1588
1589         /* Clear any crap from the cache or else... */
1590         swift_flush_cache_all();
1591
1592         /* Enable I & D caches */
1593         mreg = srmmu_get_mmureg();
1594         mreg |= (SWIFT_IE | SWIFT_DE);
1595         /*
1596          * The Swift branch folding logic is completely broken.  At
1597          * trap time, if things are just right, if can mistakenly
1598          * think that a trap is coming from kernel mode when in fact
1599          * it is coming from user mode (it mis-executes the branch in
1600          * the trap code).  So you see things like crashme completely
1601          * hosing your machine which is completely unacceptable.  Turn
1602          * this shit off... nice job Fujitsu.
1603          */
1604         mreg &= ~(SWIFT_BF);
1605         srmmu_set_mmureg(mreg);
1606 }
1607
1608 #define SWIFT_MASKID_ADDR  0x10003018
1609 static void __init init_swift(void)
1610 {
1611         unsigned long swift_rev;
1612
1613         __asm__ __volatile__("lda [%1] %2, %0\n\t"
1614                              "srl %0, 0x18, %0\n\t" :
1615                              "=r" (swift_rev) :
1616                              "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1617         srmmu_name = "Fujitsu Swift";
1618         switch(swift_rev) {
1619         case 0x11:
1620         case 0x20:
1621         case 0x23:
1622         case 0x30:
1623                 srmmu_modtype = Swift_lots_o_bugs;
1624                 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1625                 /*
1626                  * Gee george, I wonder why Sun is so hush hush about
1627                  * this hardware bug... really braindamage stuff going
1628                  * on here.  However I think we can find a way to avoid
1629                  * all of the workaround overhead under Linux.  Basically,
1630                  * any page fault can cause kernel pages to become user
1631                  * accessible (the mmu gets confused and clears some of
1632                  * the ACC bits in kernel ptes).  Aha, sounds pretty
1633                  * horrible eh?  But wait, after extensive testing it appears
1634                  * that if you use pgd_t level large kernel pte's (like the
1635                  * 4MB pages on the Pentium) the bug does not get tripped
1636                  * at all.  This avoids almost all of the major overhead.
1637                  * Welcome to a world where your vendor tells you to,
1638                  * "apply this kernel patch" instead of "sorry for the
1639                  * broken hardware, send it back and we'll give you
1640                  * properly functioning parts"
1641                  */
1642                 break;
1643         case 0x25:
1644         case 0x31:
1645                 srmmu_modtype = Swift_bad_c;
1646                 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1647                 /*
1648                  * You see Sun allude to this hardware bug but never
1649                  * admit things directly, they'll say things like,
1650                  * "the Swift chip cache problems" or similar.
1651                  */
1652                 break;
1653         default:
1654                 srmmu_modtype = Swift_ok;
1655                 break;
1656         };
1657
1658         BTFIXUPSET_CALL(flush_cache_all, swift_flush_cache_all, BTFIXUPCALL_NORM);
1659         BTFIXUPSET_CALL(flush_cache_mm, swift_flush_cache_mm, BTFIXUPCALL_NORM);
1660         BTFIXUPSET_CALL(flush_cache_page, swift_flush_cache_page, BTFIXUPCALL_NORM);
1661         BTFIXUPSET_CALL(flush_cache_range, swift_flush_cache_range, BTFIXUPCALL_NORM);
1662
1663
1664         BTFIXUPSET_CALL(flush_tlb_all, swift_flush_tlb_all, BTFIXUPCALL_NORM);
1665         BTFIXUPSET_CALL(flush_tlb_mm, swift_flush_tlb_mm, BTFIXUPCALL_NORM);
1666         BTFIXUPSET_CALL(flush_tlb_page, swift_flush_tlb_page, BTFIXUPCALL_NORM);
1667         BTFIXUPSET_CALL(flush_tlb_range, swift_flush_tlb_range, BTFIXUPCALL_NORM);
1668
1669         BTFIXUPSET_CALL(__flush_page_to_ram, swift_flush_page_to_ram, BTFIXUPCALL_NORM);
1670         BTFIXUPSET_CALL(flush_sig_insns, swift_flush_sig_insns, BTFIXUPCALL_NORM);
1671         BTFIXUPSET_CALL(flush_page_for_dma, swift_flush_page_for_dma, BTFIXUPCALL_NORM);
1672
1673         BTFIXUPSET_CALL(update_mmu_cache, swift_update_mmu_cache, BTFIXUPCALL_NORM);
1674
1675         flush_page_for_dma_global = 0;
1676
1677         /*
1678          * Are you now convinced that the Swift is one of the
1679          * biggest VLSI abortions of all time?  Bravo Fujitsu!
1680          * Fujitsu, the !#?!%$'d up processor people.  I bet if
1681          * you examined the microcode of the Swift you'd find
1682          * XXX's all over the place.
1683          */
1684         poke_srmmu = poke_swift;
1685 }
1686
1687 static void turbosparc_flush_cache_all(void)
1688 {
1689         flush_user_windows();
1690         turbosparc_idflash_clear();
1691 }
1692
1693 static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1694 {
1695         FLUSH_BEGIN(mm)
1696         flush_user_windows();
1697         turbosparc_idflash_clear();
1698         FLUSH_END
1699 }
1700
1701 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1702 {
1703         FLUSH_BEGIN(vma->vm_mm)
1704         flush_user_windows();
1705         turbosparc_idflash_clear();
1706         FLUSH_END
1707 }
1708
1709 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1710 {
1711         FLUSH_BEGIN(vma->vm_mm)
1712         flush_user_windows();
1713         if (vma->vm_flags & VM_EXEC)
1714                 turbosparc_flush_icache();
1715         turbosparc_flush_dcache();
1716         FLUSH_END
1717 }
1718
1719 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
1720 static void turbosparc_flush_page_to_ram(unsigned long page)
1721 {
1722 #ifdef TURBOSPARC_WRITEBACK
1723         volatile unsigned long clear;
1724
1725         if (srmmu_hwprobe(page))
1726                 turbosparc_flush_page_cache(page);
1727         clear = srmmu_get_fstatus();
1728 #endif
1729 }
1730
1731 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1732 {
1733 }
1734
1735 static void turbosparc_flush_page_for_dma(unsigned long page)
1736 {
1737         turbosparc_flush_dcache();
1738 }
1739
1740 static void turbosparc_flush_tlb_all(void)
1741 {
1742         srmmu_flush_whole_tlb();
1743 }
1744
1745 static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1746 {
1747         FLUSH_BEGIN(mm)
1748         srmmu_flush_whole_tlb();
1749         FLUSH_END
1750 }
1751
1752 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1753 {
1754         FLUSH_BEGIN(vma->vm_mm)
1755         srmmu_flush_whole_tlb();
1756         FLUSH_END
1757 }
1758
1759 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1760 {
1761         FLUSH_BEGIN(vma->vm_mm)
1762         srmmu_flush_whole_tlb();
1763         FLUSH_END
1764 }
1765
1766
1767 static void __init poke_turbosparc(void)
1768 {
1769         unsigned long mreg = srmmu_get_mmureg();
1770         unsigned long ccreg;
1771
1772         /* Clear any crap from the cache or else... */
1773         turbosparc_flush_cache_all();
1774         mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* Temporarily disable I & D caches */
1775         mreg &= ~(TURBOSPARC_PCENABLE);         /* Don't check parity */
1776         srmmu_set_mmureg(mreg);
1777
1778         ccreg = turbosparc_get_ccreg();
1779
1780 #ifdef TURBOSPARC_WRITEBACK
1781         ccreg |= (TURBOSPARC_SNENABLE);         /* Do DVMA snooping in Dcache */
1782         ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1783                         /* Write-back D-cache, emulate VLSI
1784                          * abortion number three, not number one */
1785 #else
1786         /* For now let's play safe, optimize later */
1787         ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1788                         /* Do DVMA snooping in Dcache, Write-thru D-cache */
1789         ccreg &= ~(TURBOSPARC_uS2);
1790                         /* Emulate VLSI abortion number three, not number one */
1791 #endif
1792
1793         switch (ccreg & 7) {
1794         case 0: /* No SE cache */
1795         case 7: /* Test mode */
1796                 break;
1797         default:
1798                 ccreg |= (TURBOSPARC_SCENABLE);
1799         }
1800         turbosparc_set_ccreg (ccreg);
1801
1802         mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1803         mreg |= (TURBOSPARC_ICSNOOP);           /* Icache snooping on */
1804         srmmu_set_mmureg(mreg);
1805 }
1806
1807 static void __init init_turbosparc(void)
1808 {
1809         srmmu_name = "Fujitsu TurboSparc";
1810         srmmu_modtype = TurboSparc;
1811
1812         BTFIXUPSET_CALL(flush_cache_all, turbosparc_flush_cache_all, BTFIXUPCALL_NORM);
1813         BTFIXUPSET_CALL(flush_cache_mm, turbosparc_flush_cache_mm, BTFIXUPCALL_NORM);
1814         BTFIXUPSET_CALL(flush_cache_page, turbosparc_flush_cache_page, BTFIXUPCALL_NORM);
1815         BTFIXUPSET_CALL(flush_cache_range, turbosparc_flush_cache_range, BTFIXUPCALL_NORM);
1816
1817         BTFIXUPSET_CALL(flush_tlb_all, turbosparc_flush_tlb_all, BTFIXUPCALL_NORM);
1818         BTFIXUPSET_CALL(flush_tlb_mm, turbosparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1819         BTFIXUPSET_CALL(flush_tlb_page, turbosparc_flush_tlb_page, BTFIXUPCALL_NORM);
1820         BTFIXUPSET_CALL(flush_tlb_range, turbosparc_flush_tlb_range, BTFIXUPCALL_NORM);
1821
1822         BTFIXUPSET_CALL(__flush_page_to_ram, turbosparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1823
1824         BTFIXUPSET_CALL(flush_sig_insns, turbosparc_flush_sig_insns, BTFIXUPCALL_NOP);
1825         BTFIXUPSET_CALL(flush_page_for_dma, turbosparc_flush_page_for_dma, BTFIXUPCALL_NORM);
1826
1827         poke_srmmu = poke_turbosparc;
1828 }
1829
1830 static void __init poke_tsunami(void)
1831 {
1832         unsigned long mreg = srmmu_get_mmureg();
1833
1834         tsunami_flush_icache();
1835         tsunami_flush_dcache();
1836         mreg &= ~TSUNAMI_ITD;
1837         mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1838         srmmu_set_mmureg(mreg);
1839 }
1840
1841 static void __init init_tsunami(void)
1842 {
1843         /*
1844          * Tsunami's pretty sane, Sun and TI actually got it
1845          * somewhat right this time.  Fujitsu should have
1846          * taken some lessons from them.
1847          */
1848
1849         srmmu_name = "TI Tsunami";
1850         srmmu_modtype = Tsunami;
1851
1852         BTFIXUPSET_CALL(flush_cache_all, tsunami_flush_cache_all, BTFIXUPCALL_NORM);
1853         BTFIXUPSET_CALL(flush_cache_mm, tsunami_flush_cache_mm, BTFIXUPCALL_NORM);
1854         BTFIXUPSET_CALL(flush_cache_page, tsunami_flush_cache_page, BTFIXUPCALL_NORM);
1855         BTFIXUPSET_CALL(flush_cache_range, tsunami_flush_cache_range, BTFIXUPCALL_NORM);
1856
1857
1858         BTFIXUPSET_CALL(flush_tlb_all, tsunami_flush_tlb_all, BTFIXUPCALL_NORM);
1859         BTFIXUPSET_CALL(flush_tlb_mm, tsunami_flush_tlb_mm, BTFIXUPCALL_NORM);
1860         BTFIXUPSET_CALL(flush_tlb_page, tsunami_flush_tlb_page, BTFIXUPCALL_NORM);
1861         BTFIXUPSET_CALL(flush_tlb_range, tsunami_flush_tlb_range, BTFIXUPCALL_NORM);
1862
1863         BTFIXUPSET_CALL(__flush_page_to_ram, tsunami_flush_page_to_ram, BTFIXUPCALL_NOP);
1864         BTFIXUPSET_CALL(flush_sig_insns, tsunami_flush_sig_insns, BTFIXUPCALL_NORM);
1865         BTFIXUPSET_CALL(flush_page_for_dma, tsunami_flush_page_for_dma, BTFIXUPCALL_NORM);
1866
1867         poke_srmmu = poke_tsunami;
1868
1869         tsunami_setup_blockops();
1870 }
1871
1872 static void __init poke_viking(void)
1873 {
1874         unsigned long mreg = srmmu_get_mmureg();
1875         static int smp_catch;
1876
1877         if(viking_mxcc_present) {
1878                 unsigned long mxcc_control = mxcc_get_creg();
1879
1880                 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1881                 mxcc_control &= ~(MXCC_CTL_RRC);
1882                 mxcc_set_creg(mxcc_control);
1883
1884                 /*
1885                  * We don't need memory parity checks.
1886                  * XXX This is a mess, have to dig out later. ecd.
1887                 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1888                  */
1889
1890                 /* We do cache ptables on MXCC. */
1891                 mreg |= VIKING_TCENABLE;
1892         } else {
1893                 unsigned long bpreg;
1894
1895                 mreg &= ~(VIKING_TCENABLE);
1896                 if(smp_catch++) {
1897                         /* Must disable mixed-cmd mode here for other cpu's. */
1898                         bpreg = viking_get_bpreg();
1899                         bpreg &= ~(VIKING_ACTION_MIX);
1900                         viking_set_bpreg(bpreg);
1901
1902                         /* Just in case PROM does something funny. */
1903                         msi_set_sync();
1904                 }
1905         }
1906
1907         mreg |= VIKING_SPENABLE;
1908         mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1909         mreg |= VIKING_SBENABLE;
1910         mreg &= ~(VIKING_ACENABLE);
1911         srmmu_set_mmureg(mreg);
1912
1913 #ifdef CONFIG_SMP
1914         /* Avoid unnecessary cross calls. */
1915         BTFIXUPCOPY_CALL(flush_cache_all, local_flush_cache_all);
1916         BTFIXUPCOPY_CALL(flush_cache_mm, local_flush_cache_mm);
1917         BTFIXUPCOPY_CALL(flush_cache_range, local_flush_cache_range);
1918         BTFIXUPCOPY_CALL(flush_cache_page, local_flush_cache_page);
1919         BTFIXUPCOPY_CALL(__flush_page_to_ram, local_flush_page_to_ram);
1920         BTFIXUPCOPY_CALL(flush_sig_insns, local_flush_sig_insns);
1921         BTFIXUPCOPY_CALL(flush_page_for_dma, local_flush_page_for_dma);
1922         btfixup();
1923 #endif
1924 }
1925
1926 static void __init init_viking(void)
1927 {
1928         unsigned long mreg = srmmu_get_mmureg();
1929
1930         /* Ahhh, the viking.  SRMMU VLSI abortion number two... */
1931         if(mreg & VIKING_MMODE) {
1932                 srmmu_name = "TI Viking";
1933                 viking_mxcc_present = 0;
1934                 msi_set_sync();
1935
1936                 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1937                 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1938                 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1939
1940                 /*
1941                  * We need this to make sure old viking takes no hits
1942                  * on it's cache for dma snoops to workaround the
1943                  * "load from non-cacheable memory" interrupt bug.
1944                  * This is only necessary because of the new way in
1945                  * which we use the IOMMU.
1946                  */
1947                 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page, BTFIXUPCALL_NORM);
1948
1949                 flush_page_for_dma_global = 0;
1950         } else {
1951                 srmmu_name = "TI Viking/MXCC";
1952                 viking_mxcc_present = 1;
1953
1954                 srmmu_cache_pagetables = 1;
1955
1956                 /* MXCC vikings lack the DMA snooping bug. */
1957                 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page_for_dma, BTFIXUPCALL_NOP);
1958         }
1959
1960         BTFIXUPSET_CALL(flush_cache_all, viking_flush_cache_all, BTFIXUPCALL_NORM);
1961         BTFIXUPSET_CALL(flush_cache_mm, viking_flush_cache_mm, BTFIXUPCALL_NORM);
1962         BTFIXUPSET_CALL(flush_cache_page, viking_flush_cache_page, BTFIXUPCALL_NORM);
1963         BTFIXUPSET_CALL(flush_cache_range, viking_flush_cache_range, BTFIXUPCALL_NORM);
1964
1965 #ifdef CONFIG_SMP
1966         if (sparc_cpu_model == sun4d) {
1967                 BTFIXUPSET_CALL(flush_tlb_all, sun4dsmp_flush_tlb_all, BTFIXUPCALL_NORM);
1968                 BTFIXUPSET_CALL(flush_tlb_mm, sun4dsmp_flush_tlb_mm, BTFIXUPCALL_NORM);
1969                 BTFIXUPSET_CALL(flush_tlb_page, sun4dsmp_flush_tlb_page, BTFIXUPCALL_NORM);
1970                 BTFIXUPSET_CALL(flush_tlb_range, sun4dsmp_flush_tlb_range, BTFIXUPCALL_NORM);
1971         } else
1972 #endif
1973         {
1974                 BTFIXUPSET_CALL(flush_tlb_all, viking_flush_tlb_all, BTFIXUPCALL_NORM);
1975                 BTFIXUPSET_CALL(flush_tlb_mm, viking_flush_tlb_mm, BTFIXUPCALL_NORM);
1976                 BTFIXUPSET_CALL(flush_tlb_page, viking_flush_tlb_page, BTFIXUPCALL_NORM);
1977                 BTFIXUPSET_CALL(flush_tlb_range, viking_flush_tlb_range, BTFIXUPCALL_NORM);
1978         }
1979
1980         BTFIXUPSET_CALL(__flush_page_to_ram, viking_flush_page_to_ram, BTFIXUPCALL_NOP);
1981         BTFIXUPSET_CALL(flush_sig_insns, viking_flush_sig_insns, BTFIXUPCALL_NOP);
1982
1983         poke_srmmu = poke_viking;
1984 }
1985
1986 /* Probe for the srmmu chip version. */
1987 static void __init get_srmmu_type(void)
1988 {
1989         unsigned long mreg, psr;
1990         unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1991
1992         srmmu_modtype = SRMMU_INVAL_MOD;
1993         hwbug_bitmask = 0;
1994
1995         mreg = srmmu_get_mmureg(); psr = get_psr();
1996         mod_typ = (mreg & 0xf0000000) >> 28;
1997         mod_rev = (mreg & 0x0f000000) >> 24;
1998         psr_typ = (psr >> 28) & 0xf;
1999         psr_vers = (psr >> 24) & 0xf;
2000
2001         /* First, check for HyperSparc or Cypress. */
2002         if(mod_typ == 1) {
2003                 switch(mod_rev) {
2004                 case 7:
2005                         /* UP or MP Hypersparc */
2006                         init_hypersparc();
2007                         break;
2008                 case 0:
2009                 case 2:
2010                         /* Uniprocessor Cypress */
2011                         init_cypress_604();
2012                         break;
2013                 case 10:
2014                 case 11:
2015                 case 12:
2016                         /* _REALLY OLD_ Cypress MP chips... */
2017                 case 13:
2018                 case 14:
2019                 case 15:
2020                         /* MP Cypress mmu/cache-controller */
2021                         init_cypress_605(mod_rev);
2022                         break;
2023                 default:
2024                         /* Some other Cypress revision, assume a 605. */
2025                         init_cypress_605(mod_rev);
2026                         break;
2027                 };
2028                 return;
2029         }
2030
2031         /*
2032          * Now Fujitsu TurboSparc. It might happen that it is
2033          * in Swift emulation mode, so we will check later...
2034          */
2035         if (psr_typ == 0 && psr_vers == 5) {
2036                 init_turbosparc();
2037                 return;
2038         }
2039
2040         /* Next check for Fujitsu Swift. */
2041         if(psr_typ == 0 && psr_vers == 4) {
2042                 int cpunode;
2043                 char node_str[128];
2044
2045                 /* Look if it is not a TurboSparc emulating Swift... */
2046                 cpunode = prom_getchild(prom_root_node);
2047                 while((cpunode = prom_getsibling(cpunode)) != 0) {
2048                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
2049                         if(!strcmp(node_str, "cpu")) {
2050                                 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
2051                                     prom_getintdefault(cpunode, "psr-version", 1) == 5) {
2052                                         init_turbosparc();
2053                                         return;
2054                                 }
2055                                 break;
2056                         }
2057                 }
2058
2059                 init_swift();
2060                 return;
2061         }
2062
2063         /* Now the Viking family of srmmu. */
2064         if(psr_typ == 4 &&
2065            ((psr_vers == 0) ||
2066             ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
2067                 init_viking();
2068                 return;
2069         }
2070
2071         /* Finally the Tsunami. */
2072         if(psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
2073                 init_tsunami();
2074                 return;
2075         }
2076
2077         /* Oh well */
2078         srmmu_is_bad();
2079 }
2080
2081 /* don't laugh, static pagetables */
2082 static void srmmu_check_pgt_cache(int low, int high)
2083 {
2084 }
2085
2086 extern unsigned long spwin_mmu_patchme, fwin_mmu_patchme,
2087         tsetup_mmu_patchme, rtrap_mmu_patchme;
2088
2089 extern unsigned long spwin_srmmu_stackchk, srmmu_fwin_stackchk,
2090         tsetup_srmmu_stackchk, srmmu_rett_stackchk;
2091
2092 extern unsigned long srmmu_fault;
2093
2094 #define PATCH_BRANCH(insn, dest) do { \
2095                 iaddr = &(insn); \
2096                 daddr = &(dest); \
2097                 *iaddr = SPARC_BRANCH((unsigned long) daddr, (unsigned long) iaddr); \
2098         } while(0)
2099
2100 static void __init patch_window_trap_handlers(void)
2101 {
2102         unsigned long *iaddr, *daddr;
2103
2104         PATCH_BRANCH(spwin_mmu_patchme, spwin_srmmu_stackchk);
2105         PATCH_BRANCH(fwin_mmu_patchme, srmmu_fwin_stackchk);
2106         PATCH_BRANCH(tsetup_mmu_patchme, tsetup_srmmu_stackchk);
2107         PATCH_BRANCH(rtrap_mmu_patchme, srmmu_rett_stackchk);
2108         PATCH_BRANCH(sparc_ttable[SP_TRAP_TFLT].inst_three, srmmu_fault);
2109         PATCH_BRANCH(sparc_ttable[SP_TRAP_DFLT].inst_three, srmmu_fault);
2110         PATCH_BRANCH(sparc_ttable[SP_TRAP_DACC].inst_three, srmmu_fault);
2111 }
2112
2113 #ifdef CONFIG_SMP
2114 /* Local cross-calls. */
2115 static void smp_flush_page_for_dma(unsigned long page)
2116 {
2117         xc1((smpfunc_t) BTFIXUP_CALL(local_flush_page_for_dma), page);
2118         local_flush_page_for_dma(page);
2119 }
2120
2121 #endif
2122
2123 static pte_t srmmu_pgoff_to_pte(unsigned long pgoff)
2124 {
2125         return __pte((pgoff << SRMMU_PTE_FILE_SHIFT) | SRMMU_FILE);
2126 }
2127
2128 static unsigned long srmmu_pte_to_pgoff(pte_t pte)
2129 {
2130         return pte_val(pte) >> SRMMU_PTE_FILE_SHIFT;
2131 }
2132
2133 /* Load up routines and constants for sun4m and sun4d mmu */
2134 void __init ld_mmu_srmmu(void)
2135 {
2136         extern void ld_mmu_iommu(void);
2137         extern void ld_mmu_iounit(void);
2138         extern void ___xchg32_sun4md(void);
2139
2140         BTFIXUPSET_SIMM13(pgdir_shift, SRMMU_PGDIR_SHIFT);
2141         BTFIXUPSET_SETHI(pgdir_size, SRMMU_PGDIR_SIZE);
2142         BTFIXUPSET_SETHI(pgdir_mask, SRMMU_PGDIR_MASK);
2143
2144         BTFIXUPSET_SIMM13(ptrs_per_pmd, SRMMU_PTRS_PER_PMD);
2145         BTFIXUPSET_SIMM13(ptrs_per_pgd, SRMMU_PTRS_PER_PGD);
2146
2147         BTFIXUPSET_INT(page_none, pgprot_val(SRMMU_PAGE_NONE));
2148         BTFIXUPSET_INT(page_shared, pgprot_val(SRMMU_PAGE_SHARED));
2149         BTFIXUPSET_INT(page_copy, pgprot_val(SRMMU_PAGE_COPY));
2150         BTFIXUPSET_INT(page_readonly, pgprot_val(SRMMU_PAGE_RDONLY));
2151         BTFIXUPSET_INT(page_kernel, pgprot_val(SRMMU_PAGE_KERNEL));
2152         page_kernel = pgprot_val(SRMMU_PAGE_KERNEL);
2153         pg_iobits = SRMMU_VALID | SRMMU_WRITE | SRMMU_REF;
2154
2155         /* Functions */
2156 #ifndef CONFIG_SMP
2157         BTFIXUPSET_CALL(___xchg32, ___xchg32_sun4md, BTFIXUPCALL_SWAPG1G2);
2158 #endif
2159         BTFIXUPSET_CALL(do_check_pgt_cache, srmmu_check_pgt_cache, BTFIXUPCALL_NOP);
2160
2161         BTFIXUPSET_CALL(set_pte, srmmu_set_pte, BTFIXUPCALL_SWAPO0O1);
2162         BTFIXUPSET_CALL(switch_mm, srmmu_switch_mm, BTFIXUPCALL_NORM);
2163
2164         BTFIXUPSET_CALL(pte_pfn, srmmu_pte_pfn, BTFIXUPCALL_NORM);
2165         BTFIXUPSET_CALL(pmd_page, srmmu_pmd_page, BTFIXUPCALL_NORM);
2166         BTFIXUPSET_CALL(pgd_page, srmmu_pgd_page, BTFIXUPCALL_NORM);
2167
2168         BTFIXUPSET_SETHI(none_mask, 0xF0000000);
2169
2170         BTFIXUPSET_CALL(pte_present, srmmu_pte_present, BTFIXUPCALL_NORM);
2171         BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_SWAPO0G0);
2172         BTFIXUPSET_CALL(pte_read, srmmu_pte_read, BTFIXUPCALL_NORM);
2173
2174         BTFIXUPSET_CALL(pmd_bad, srmmu_pmd_bad, BTFIXUPCALL_NORM);
2175         BTFIXUPSET_CALL(pmd_present, srmmu_pmd_present, BTFIXUPCALL_NORM);
2176         BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_SWAPO0G0);
2177
2178         BTFIXUPSET_CALL(pgd_none, srmmu_pgd_none, BTFIXUPCALL_NORM);
2179         BTFIXUPSET_CALL(pgd_bad, srmmu_pgd_bad, BTFIXUPCALL_NORM);
2180         BTFIXUPSET_CALL(pgd_present, srmmu_pgd_present, BTFIXUPCALL_NORM);
2181         BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_SWAPO0G0);
2182
2183         BTFIXUPSET_CALL(mk_pte, srmmu_mk_pte, BTFIXUPCALL_NORM);
2184         BTFIXUPSET_CALL(mk_pte_phys, srmmu_mk_pte_phys, BTFIXUPCALL_NORM);
2185         BTFIXUPSET_CALL(mk_pte_io, srmmu_mk_pte_io, BTFIXUPCALL_NORM);
2186         BTFIXUPSET_CALL(pgd_set, srmmu_pgd_set, BTFIXUPCALL_NORM);
2187         BTFIXUPSET_CALL(pmd_set, srmmu_pmd_set, BTFIXUPCALL_NORM);
2188         BTFIXUPSET_CALL(pmd_populate, srmmu_pmd_populate, BTFIXUPCALL_NORM);
2189
2190         BTFIXUPSET_INT(pte_modify_mask, SRMMU_CHG_MASK);
2191         BTFIXUPSET_CALL(pmd_offset, srmmu_pmd_offset, BTFIXUPCALL_NORM);
2192         BTFIXUPSET_CALL(pte_offset_kernel, srmmu_pte_offset, BTFIXUPCALL_NORM);
2193
2194         BTFIXUPSET_CALL(free_pte_fast, srmmu_free_pte_fast, BTFIXUPCALL_NORM);
2195         BTFIXUPSET_CALL(pte_free, srmmu_pte_free, BTFIXUPCALL_NORM);
2196         BTFIXUPSET_CALL(pte_alloc_one_kernel, srmmu_pte_alloc_one_kernel, BTFIXUPCALL_NORM);
2197         BTFIXUPSET_CALL(pte_alloc_one, srmmu_pte_alloc_one, BTFIXUPCALL_NORM);
2198         BTFIXUPSET_CALL(free_pmd_fast, srmmu_pmd_free, BTFIXUPCALL_NORM);
2199         BTFIXUPSET_CALL(pmd_alloc_one, srmmu_pmd_alloc_one, BTFIXUPCALL_NORM);
2200         BTFIXUPSET_CALL(free_pgd_fast, srmmu_free_pgd_fast, BTFIXUPCALL_NORM);
2201         BTFIXUPSET_CALL(get_pgd_fast, srmmu_get_pgd_fast, BTFIXUPCALL_NORM);
2202
2203         BTFIXUPSET_HALF(pte_writei, SRMMU_WRITE);
2204         BTFIXUPSET_HALF(pte_dirtyi, SRMMU_DIRTY);
2205         BTFIXUPSET_HALF(pte_youngi, SRMMU_REF);
2206         BTFIXUPSET_HALF(pte_filei, SRMMU_FILE);
2207         BTFIXUPSET_HALF(pte_wrprotecti, SRMMU_WRITE);
2208         BTFIXUPSET_HALF(pte_mkcleani, SRMMU_DIRTY);
2209         BTFIXUPSET_HALF(pte_mkoldi, SRMMU_REF);
2210         BTFIXUPSET_CALL(pte_mkwrite, srmmu_pte_mkwrite, BTFIXUPCALL_ORINT(SRMMU_WRITE));
2211         BTFIXUPSET_CALL(pte_mkdirty, srmmu_pte_mkdirty, BTFIXUPCALL_ORINT(SRMMU_DIRTY));
2212         BTFIXUPSET_CALL(pte_mkyoung, srmmu_pte_mkyoung, BTFIXUPCALL_ORINT(SRMMU_REF));
2213         BTFIXUPSET_CALL(update_mmu_cache, srmmu_update_mmu_cache, BTFIXUPCALL_NOP);
2214         BTFIXUPSET_CALL(destroy_context, srmmu_destroy_context, BTFIXUPCALL_NORM);
2215
2216         BTFIXUPSET_CALL(sparc_mapiorange, srmmu_mapiorange, BTFIXUPCALL_NORM);
2217         BTFIXUPSET_CALL(sparc_unmapiorange, srmmu_unmapiorange, BTFIXUPCALL_NORM);
2218
2219         BTFIXUPSET_CALL(__swp_type, srmmu_swp_type, BTFIXUPCALL_NORM);
2220         BTFIXUPSET_CALL(__swp_offset, srmmu_swp_offset, BTFIXUPCALL_NORM);
2221         BTFIXUPSET_CALL(__swp_entry, srmmu_swp_entry, BTFIXUPCALL_NORM);
2222
2223         BTFIXUPSET_CALL(mmu_info, srmmu_mmu_info, BTFIXUPCALL_NORM);
2224
2225         BTFIXUPSET_CALL(alloc_thread_info, srmmu_alloc_thread_info, BTFIXUPCALL_NORM);
2226         BTFIXUPSET_CALL(free_thread_info, srmmu_free_thread_info, BTFIXUPCALL_NORM);
2227
2228         BTFIXUPSET_CALL(pte_to_pgoff, srmmu_pte_to_pgoff, BTFIXUPCALL_NORM);
2229         BTFIXUPSET_CALL(pgoff_to_pte, srmmu_pgoff_to_pte, BTFIXUPCALL_NORM);
2230
2231         get_srmmu_type();
2232         patch_window_trap_handlers();
2233
2234 #ifdef CONFIG_SMP
2235         /* El switcheroo... */
2236
2237         BTFIXUPCOPY_CALL(local_flush_cache_all, flush_cache_all);
2238         BTFIXUPCOPY_CALL(local_flush_cache_mm, flush_cache_mm);
2239         BTFIXUPCOPY_CALL(local_flush_cache_range, flush_cache_range);
2240         BTFIXUPCOPY_CALL(local_flush_cache_page, flush_cache_page);
2241         BTFIXUPCOPY_CALL(local_flush_tlb_all, flush_tlb_all);
2242         BTFIXUPCOPY_CALL(local_flush_tlb_mm, flush_tlb_mm);
2243         BTFIXUPCOPY_CALL(local_flush_tlb_range, flush_tlb_range);
2244         BTFIXUPCOPY_CALL(local_flush_tlb_page, flush_tlb_page);
2245         BTFIXUPCOPY_CALL(local_flush_page_to_ram, __flush_page_to_ram);
2246         BTFIXUPCOPY_CALL(local_flush_sig_insns, flush_sig_insns);
2247         BTFIXUPCOPY_CALL(local_flush_page_for_dma, flush_page_for_dma);
2248
2249         BTFIXUPSET_CALL(flush_cache_all, smp_flush_cache_all, BTFIXUPCALL_NORM);
2250         BTFIXUPSET_CALL(flush_cache_mm, smp_flush_cache_mm, BTFIXUPCALL_NORM);
2251         BTFIXUPSET_CALL(flush_cache_range, smp_flush_cache_range, BTFIXUPCALL_NORM);
2252         BTFIXUPSET_CALL(flush_cache_page, smp_flush_cache_page, BTFIXUPCALL_NORM);
2253         if (sparc_cpu_model != sun4d) {
2254                 BTFIXUPSET_CALL(flush_tlb_all, smp_flush_tlb_all, BTFIXUPCALL_NORM);
2255                 BTFIXUPSET_CALL(flush_tlb_mm, smp_flush_tlb_mm, BTFIXUPCALL_NORM);
2256                 BTFIXUPSET_CALL(flush_tlb_range, smp_flush_tlb_range, BTFIXUPCALL_NORM);
2257                 BTFIXUPSET_CALL(flush_tlb_page, smp_flush_tlb_page, BTFIXUPCALL_NORM);
2258         }
2259         BTFIXUPSET_CALL(__flush_page_to_ram, smp_flush_page_to_ram, BTFIXUPCALL_NORM);
2260         BTFIXUPSET_CALL(flush_sig_insns, smp_flush_sig_insns, BTFIXUPCALL_NORM);
2261         BTFIXUPSET_CALL(flush_page_for_dma, smp_flush_page_for_dma, BTFIXUPCALL_NORM);
2262 #endif
2263
2264         if (sparc_cpu_model == sun4d)
2265                 ld_mmu_iounit();
2266         else
2267                 ld_mmu_iommu();
2268 #ifdef CONFIG_SMP
2269         if (sparc_cpu_model == sun4d)
2270                 sun4d_init_smp();
2271         else
2272                 sun4m_init_smp();
2273 #endif
2274 }