1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2004-2005 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *******************************************************************/
21 #define FDMI_DID 0xfffffaU
22 #define NameServer_DID 0xfffffcU
23 #define SCR_DID 0xfffffdU
24 #define Fabric_DID 0xfffffeU
25 #define Bcast_DID 0xffffffU
26 #define Mask_DID 0xffffffU
27 #define CT_DID_MASK 0xffff00U
28 #define Fabric_DID_MASK 0xfff000U
29 #define WELL_KNOWN_DID_MASK 0xfffff0U
31 #define PT2PT_LocalID 1
32 #define PT2PT_RemoteID 2
34 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
35 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
36 #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */
37 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
39 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
42 #define FCELSSIZE 1024 /* maximum ELS transfer size */
44 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
45 #define LPFC_IP_RING 1 /* ring 1 for IP commands */
46 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
47 #define LPFC_FCP_NEXT_RING 3
49 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
50 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
51 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 IP command ring entries */
52 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 IP response ring entries */
53 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
54 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
55 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
56 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
57 #define SLI2_IOCB_CMD_R3_ENTRIES 0
58 #define SLI2_IOCB_RSP_R3_ENTRIES 0
59 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
60 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
62 /* Common Transport structures and definitions */
65 /* Structure is in Big Endian format */
73 union CtCommandResponse {
74 /* Structure is in Big Endian format */
82 struct lpfc_sli_ct_request {
83 /* Structure is in Big Endian format */
84 union CtRevisionId RevisionId;
89 union CtCommandResponse CommandResponse;
98 uint8_t PortType; /* for GID_PT requests */
101 uint8_t Fc4Type; /* for GID_FT requests */
104 uint32_t PortId; /* For RFT_ID requests */
106 #ifdef __BIG_ENDIAN_BITFIELD
109 uint32_t fcpReg:1; /* Type 8 */
111 uint32_t ipReg:1; /* Type 5 */
113 #else /* __LITTLE_ENDIAN_BITFIELD */
115 uint32_t fcpReg:1; /* Type 8 */
118 uint32_t ipReg:1; /* Type 5 */
125 uint32_t PortId; /* For RNN_ID requests */
128 struct rsnn { /* For RSNN_ID requests */
131 uint8_t symbname[255];
136 #define SLI_CT_REVISION 1
137 #define GID_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 260)
138 #define RFT_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 228)
139 #define RNN_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 252)
140 #define RSNN_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request))
146 #define SLI_CT_MANAGEMENT_SERVICE 0xFA
147 #define SLI_CT_TIME_SERVICE 0xFB
148 #define SLI_CT_DIRECTORY_SERVICE 0xFC
149 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
152 * Directory Service Subtypes
155 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02
161 #define SLI_CT_RESPONSE_FS_RJT 0x8001
162 #define SLI_CT_RESPONSE_FS_ACC 0x8002
168 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0
169 #define SLI_CT_INVALID_COMMAND 0x01
170 #define SLI_CT_INVALID_VERSION 0x02
171 #define SLI_CT_LOGICAL_ERROR 0x03
172 #define SLI_CT_INVALID_IU_SIZE 0x04
173 #define SLI_CT_LOGICAL_BUSY 0x05
174 #define SLI_CT_PROTOCOL_ERROR 0x07
175 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
176 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b
177 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
178 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
179 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
180 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
181 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
182 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
183 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
184 #define SLI_CT_VENDOR_UNIQUE 0xff
187 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
190 #define SLI_CT_NO_PORT_ID 0x01
191 #define SLI_CT_NO_PORT_NAME 0x02
192 #define SLI_CT_NO_NODE_NAME 0x03
193 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04
194 #define SLI_CT_NO_IP_ADDRESS 0x05
195 #define SLI_CT_NO_IPA 0x06
196 #define SLI_CT_NO_FC4_TYPES 0x07
197 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
198 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
199 #define SLI_CT_NO_PORT_TYPE 0x0A
200 #define SLI_CT_ACCESS_DENIED 0x10
201 #define SLI_CT_INVALID_PORT_ID 0x11
202 #define SLI_CT_DATABASE_EMPTY 0x12
205 * Name Server Command Codes
208 #define SLI_CTNS_GA_NXT 0x0100
209 #define SLI_CTNS_GPN_ID 0x0112
210 #define SLI_CTNS_GNN_ID 0x0113
211 #define SLI_CTNS_GCS_ID 0x0114
212 #define SLI_CTNS_GFT_ID 0x0117
213 #define SLI_CTNS_GSPN_ID 0x0118
214 #define SLI_CTNS_GPT_ID 0x011A
215 #define SLI_CTNS_GID_PN 0x0121
216 #define SLI_CTNS_GID_NN 0x0131
217 #define SLI_CTNS_GIP_NN 0x0135
218 #define SLI_CTNS_GIPA_NN 0x0136
219 #define SLI_CTNS_GSNN_NN 0x0139
220 #define SLI_CTNS_GNN_IP 0x0153
221 #define SLI_CTNS_GIPA_IP 0x0156
222 #define SLI_CTNS_GID_FT 0x0171
223 #define SLI_CTNS_GID_PT 0x01A1
224 #define SLI_CTNS_RPN_ID 0x0212
225 #define SLI_CTNS_RNN_ID 0x0213
226 #define SLI_CTNS_RCS_ID 0x0214
227 #define SLI_CTNS_RFT_ID 0x0217
228 #define SLI_CTNS_RSPN_ID 0x0218
229 #define SLI_CTNS_RPT_ID 0x021A
230 #define SLI_CTNS_RIP_NN 0x0235
231 #define SLI_CTNS_RIPA_NN 0x0236
232 #define SLI_CTNS_RSNN_NN 0x0239
233 #define SLI_CTNS_DA_ID 0x0300
239 #define SLI_CTPT_N_PORT 0x01
240 #define SLI_CTPT_NL_PORT 0x02
241 #define SLI_CTPT_FNL_PORT 0x03
242 #define SLI_CTPT_IP 0x04
243 #define SLI_CTPT_FCP 0x08
244 #define SLI_CTPT_NX_PORT 0x7F
245 #define SLI_CTPT_F_PORT 0x81
246 #define SLI_CTPT_FL_PORT 0x82
247 #define SLI_CTPT_E_PORT 0x84
249 #define SLI_CT_LAST_ENTRY 0x80000000
251 /* Fibre Channel Service Parameter definitions */
253 #define FC_PH_4_0 6 /* FC-PH version 4.0 */
254 #define FC_PH_4_1 7 /* FC-PH version 4.1 */
255 #define FC_PH_4_2 8 /* FC-PH version 4.2 */
256 #define FC_PH_4_3 9 /* FC-PH version 4.3 */
258 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */
259 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */
260 #define FC_PH3 0x20 /* FC-PH-3 version */
262 #define FF_FRAME_SIZE 2048
267 #ifdef __BIG_ENDIAN_BITFIELD
268 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
269 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
271 #else /* __LITTLE_ENDIAN_BITFIELD */
272 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
274 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
277 #define NAME_IEEE 0x1 /* IEEE name - nameType */
278 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */
279 #define NAME_FC_TYPE 0x3 /* FC native name type */
280 #define NAME_IP_TYPE 0x4 /* IP address */
281 #define NAME_CCITT_TYPE 0xC
282 #define NAME_CCITT_GR_TYPE 0xE
283 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
285 uint8_t IEEE[6]; /* FC IEEE address */
292 uint8_t fcphHigh; /* FC Word 0, byte 0 */
295 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */
297 #ifdef __BIG_ENDIAN_BITFIELD
298 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */
299 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
300 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */
301 uint16_t fPort:1; /* FC Word 1, bit 28 */
302 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
303 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
304 uint16_t multicast:1; /* FC Word 1, bit 25 */
305 uint16_t broadcast:1; /* FC Word 1, bit 24 */
307 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
308 uint16_t simplex:1; /* FC Word 1, bit 22 */
309 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
310 uint16_t dhd:1; /* FC Word 1, bit 18 */
311 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
312 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
313 #else /* __LITTLE_ENDIAN_BITFIELD */
314 uint16_t broadcast:1; /* FC Word 1, bit 24 */
315 uint16_t multicast:1; /* FC Word 1, bit 25 */
316 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
317 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
318 uint16_t fPort:1; /* FC Word 1, bit 28 */
319 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */
320 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
321 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */
323 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
324 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
325 uint16_t dhd:1; /* FC Word 1, bit 18 */
326 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
327 uint16_t simplex:1; /* FC Word 1, bit 22 */
328 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
331 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
332 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
335 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
337 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
338 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
340 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
342 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
345 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
349 #ifdef __BIG_ENDIAN_BITFIELD
350 uint8_t classValid:1; /* FC Word 0, bit 31 */
351 uint8_t intermix:1; /* FC Word 0, bit 30 */
352 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
353 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
354 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
355 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
356 #else /* __LITTLE_ENDIAN_BITFIELD */
357 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
358 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
359 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
360 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
361 uint8_t intermix:1; /* FC Word 0, bit 30 */
362 uint8_t classValid:1; /* FC Word 0, bit 31 */
366 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
368 #ifdef __BIG_ENDIAN_BITFIELD
369 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
370 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
371 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
372 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
373 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
374 #else /* __LITTLE_ENDIAN_BITFIELD */
375 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
376 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
377 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
378 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
379 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
382 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
384 #ifdef __BIG_ENDIAN_BITFIELD
385 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
386 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
387 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
388 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
389 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
390 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
391 #else /* __LITTLE_ENDIAN_BITFIELD */
392 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
393 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
394 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
395 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
396 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
397 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
400 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
401 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
402 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
404 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
405 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
406 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
407 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
409 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
410 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
411 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
412 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
415 struct serv_parm { /* Structure is in Big Endian format */
417 struct lpfc_name portName;
418 struct lpfc_name nodeName;
419 struct class_parms cls1;
420 struct class_parms cls2;
421 struct class_parms cls3;
422 struct class_parms cls4;
423 uint8_t vendorVersion[16];
427 * Extended Link Service LS_COMMAND codes (Payload Word 0)
429 #ifdef __BIG_ENDIAN_BITFIELD
430 #define ELS_CMD_MASK 0xffff0000
431 #define ELS_RSP_MASK 0xff000000
432 #define ELS_CMD_LS_RJT 0x01000000
433 #define ELS_CMD_ACC 0x02000000
434 #define ELS_CMD_PLOGI 0x03000000
435 #define ELS_CMD_FLOGI 0x04000000
436 #define ELS_CMD_LOGO 0x05000000
437 #define ELS_CMD_ABTX 0x06000000
438 #define ELS_CMD_RCS 0x07000000
439 #define ELS_CMD_RES 0x08000000
440 #define ELS_CMD_RSS 0x09000000
441 #define ELS_CMD_RSI 0x0A000000
442 #define ELS_CMD_ESTS 0x0B000000
443 #define ELS_CMD_ESTC 0x0C000000
444 #define ELS_CMD_ADVC 0x0D000000
445 #define ELS_CMD_RTV 0x0E000000
446 #define ELS_CMD_RLS 0x0F000000
447 #define ELS_CMD_ECHO 0x10000000
448 #define ELS_CMD_TEST 0x11000000
449 #define ELS_CMD_RRQ 0x12000000
450 #define ELS_CMD_PRLI 0x20100014
451 #define ELS_CMD_PRLO 0x21100014
452 #define ELS_CMD_PDISC 0x50000000
453 #define ELS_CMD_FDISC 0x51000000
454 #define ELS_CMD_ADISC 0x52000000
455 #define ELS_CMD_FARP 0x54000000
456 #define ELS_CMD_FARPR 0x55000000
457 #define ELS_CMD_FAN 0x60000000
458 #define ELS_CMD_RSCN 0x61040000
459 #define ELS_CMD_SCR 0x62000000
460 #define ELS_CMD_RNID 0x78000000
461 #else /* __LITTLE_ENDIAN_BITFIELD */
462 #define ELS_CMD_MASK 0xffff
463 #define ELS_RSP_MASK 0xff
464 #define ELS_CMD_LS_RJT 0x01
465 #define ELS_CMD_ACC 0x02
466 #define ELS_CMD_PLOGI 0x03
467 #define ELS_CMD_FLOGI 0x04
468 #define ELS_CMD_LOGO 0x05
469 #define ELS_CMD_ABTX 0x06
470 #define ELS_CMD_RCS 0x07
471 #define ELS_CMD_RES 0x08
472 #define ELS_CMD_RSS 0x09
473 #define ELS_CMD_RSI 0x0A
474 #define ELS_CMD_ESTS 0x0B
475 #define ELS_CMD_ESTC 0x0C
476 #define ELS_CMD_ADVC 0x0D
477 #define ELS_CMD_RTV 0x0E
478 #define ELS_CMD_RLS 0x0F
479 #define ELS_CMD_ECHO 0x10
480 #define ELS_CMD_TEST 0x11
481 #define ELS_CMD_RRQ 0x12
482 #define ELS_CMD_PRLI 0x14001020
483 #define ELS_CMD_PRLO 0x14001021
484 #define ELS_CMD_PDISC 0x50
485 #define ELS_CMD_FDISC 0x51
486 #define ELS_CMD_ADISC 0x52
487 #define ELS_CMD_FARP 0x54
488 #define ELS_CMD_FARPR 0x55
489 #define ELS_CMD_FAN 0x60
490 #define ELS_CMD_RSCN 0x0461
491 #define ELS_CMD_SCR 0x62
492 #define ELS_CMD_RNID 0x78
496 * LS_RJT Payload Definition
499 struct ls_rjt { /* Structure is in Big Endian format */
503 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
505 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
506 /* LS_RJT reason codes */
507 #define LSRJT_INVALID_CMD 0x01
508 #define LSRJT_LOGICAL_ERR 0x03
509 #define LSRJT_LOGICAL_BSY 0x05
510 #define LSRJT_PROTOCOL_ERR 0x07
511 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
512 #define LSRJT_CMD_UNSUPPORTED 0x0B
513 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
515 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
516 /* LS_RJT reason explanation */
517 #define LSEXP_NOTHING_MORE 0x00
518 #define LSEXP_SPARM_OPTIONS 0x01
519 #define LSEXP_SPARM_ICTL 0x03
520 #define LSEXP_SPARM_RCTL 0x05
521 #define LSEXP_SPARM_RCV_SIZE 0x07
522 #define LSEXP_SPARM_CONCUR_SEQ 0x09
523 #define LSEXP_SPARM_CREDIT 0x0B
524 #define LSEXP_INVALID_PNAME 0x0D
525 #define LSEXP_INVALID_NNAME 0x0E
526 #define LSEXP_INVALID_CSP 0x0F
527 #define LSEXP_INVALID_ASSOC_HDR 0x11
528 #define LSEXP_ASSOC_HDR_REQ 0x13
529 #define LSEXP_INVALID_O_SID 0x15
530 #define LSEXP_INVALID_OX_RX 0x17
531 #define LSEXP_CMD_IN_PROGRESS 0x19
532 #define LSEXP_INVALID_NPORT_ID 0x1F
533 #define LSEXP_INVALID_SEQ_ID 0x21
534 #define LSEXP_INVALID_XCHG 0x23
535 #define LSEXP_INACTIVE_XCHG 0x25
536 #define LSEXP_RQ_REQUIRED 0x27
537 #define LSEXP_OUT_OF_RESOURCE 0x29
538 #define LSEXP_CANT_GIVE_DATA 0x2A
539 #define LSEXP_REQ_UNSUPPORTED 0x2C
540 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
546 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
549 typedef struct _LOGO { /* Structure is in Big Endian format */
551 uint32_t nPortId32; /* Access nPortId as a word */
553 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
554 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
555 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
556 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
559 struct lpfc_name portName; /* N_port name field */
563 * FCP Login (PRLI Request / ACC) Payload Definition
566 #define PRLX_PAGE_LEN 0x10
567 #define TPRLO_PAGE_LEN 0x14
569 typedef struct _PRLI { /* Structure is in Big Endian format */
570 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
572 #define PRLI_FCP_TYPE 0x08
573 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
575 #ifdef __BIG_ENDIAN_BITFIELD
576 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
577 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
578 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
580 /* ACC = imagePairEstablished */
581 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
582 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
583 #else /* __LITTLE_ENDIAN_BITFIELD */
584 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
585 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
586 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
587 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
588 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
589 /* ACC = imagePairEstablished */
592 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
593 #define PRLI_NO_RESOURCES 0x2
594 #define PRLI_INIT_INCOMPLETE 0x3
595 #define PRLI_NO_SUCH_PA 0x4
596 #define PRLI_PREDEF_CONFIG 0x5
597 #define PRLI_PARTIAL_SUCCESS 0x6
598 #define PRLI_INVALID_PAGE_CNT 0x7
599 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
601 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
603 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
605 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
606 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
608 #ifdef __BIG_ENDIAN_BITFIELD
609 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
610 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
611 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
612 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
613 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
614 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
615 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
616 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
617 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
618 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
619 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
620 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
621 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
622 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
623 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
624 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
625 #else /* __LITTLE_ENDIAN_BITFIELD */
626 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
627 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
628 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
629 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
630 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
631 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
632 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
633 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
634 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
635 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
636 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
637 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
638 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
639 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
640 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
641 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
646 * FCP Logout (PRLO Request / ACC) Payload Definition
649 typedef struct _PRLO { /* Structure is in Big Endian format */
650 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
652 #define PRLO_FCP_TYPE 0x08
653 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
655 #ifdef __BIG_ENDIAN_BITFIELD
656 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
657 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
658 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
659 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
660 #else /* __LITTLE_ENDIAN_BITFIELD */
661 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
662 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
663 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
664 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
667 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
668 #define PRLO_NO_SUCH_IMAGE 0x4
669 #define PRLO_INVALID_PAGE_CNT 0x7
671 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
673 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
675 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
677 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
680 typedef struct _ADISC { /* Structure is in Big Endian format */
682 struct lpfc_name portName;
683 struct lpfc_name nodeName;
687 typedef struct _FARP { /* Structure is in Big Endian format */
690 #define FARP_NO_ACTION 0 /* FARP information enclosed, no
692 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
693 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
694 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
695 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
697 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
701 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
702 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
703 struct lpfc_name OportName;
704 struct lpfc_name OnodeName;
705 struct lpfc_name RportName;
706 struct lpfc_name RnodeName;
711 typedef struct _FAN { /* Structure is in Big Endian format */
713 struct lpfc_name FportName;
714 struct lpfc_name FnodeName;
717 typedef struct _SCR { /* Structure is in Big Endian format */
722 #define SCR_FUNC_FABRIC 0x01
723 #define SCR_FUNC_NPORT 0x02
724 #define SCR_FUNC_FULL 0x03
725 #define SCR_CLEAR 0xff
728 typedef struct _RNID_TOP_DISC {
729 struct lpfc_name portName;
733 #define RNID_HOST 0xa
734 #define RNID_DRIVER 0xd
736 uint32_t attachedNodes;
738 #define RNID_IPV4 0x1
739 #define RNID_IPV6 0x2
744 #define RNID_TD_SUPPORT 0x1
745 #define RNID_LP_VALID 0x2
748 typedef struct _RNID { /* Structure is in Big Endian format */
750 #define RNID_TOPOLOGY_DISC 0xdf
754 struct lpfc_name portName;
755 struct lpfc_name nodeName;
757 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
761 typedef struct _RRQ { /* Structure is in Big Endian format */
765 uint8_t resv[32]; /* optional association hdr */
768 /* This is used for RSCN command */
769 typedef struct _D_ID { /* Structure is in Big Endian format */
773 #ifdef __BIG_ENDIAN_BITFIELD
778 #else /* __LITTLE_ENDIAN_BITFIELD */
789 * Structure to define all ELS Payload types
792 typedef struct _ELS_PKT { /* Structure is in Big Endian format */
793 uint8_t elsCode; /* FC Word 0, bit 24:31 */
798 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
799 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
800 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
801 PRLI prli; /* Payload for PRLI/ACC */
802 PRLO prlo; /* Payload for PRLO/ACC */
803 ADISC adisc; /* Payload for ADISC/ACC */
804 FARP farp; /* Payload for FARP/ACC */
805 FAN fan; /* Payload for FAN */
806 SCR scr; /* Payload for SCR/ACC */
807 RRQ rrq; /* Payload for RRQ */
808 RNID rnid; /* Payload for RNID */
809 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
815 * HBA MAnagement Operations Command Codes
817 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
818 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
819 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
820 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
821 #define SLI_MGMT_RHBA 0x200 /* Register HBA */
822 #define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */
823 #define SLI_MGMT_RPRT 0x210 /* Register Port */
824 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */
825 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */
826 #define SLI_MGMT_DPRT 0x310 /* De-register Port */
829 * Management Service Subtypes
831 #define SLI_CT_FDMI_Subtypes 0x10
834 * HBA Management Service Reject Code
836 #define REJECT_CODE 0x9 /* Unable to perform command request */
839 * HBA Management Service Reject Reason Code
840 * Please refer to the Reason Codes above
844 * HBA Attribute Types
846 #define NODE_NAME 0x1
847 #define MANUFACTURER 0x2
848 #define SERIAL_NUMBER 0x3
850 #define MODEL_DESCRIPTION 0x5
851 #define HARDWARE_VERSION 0x6
852 #define DRIVER_VERSION 0x7
853 #define OPTION_ROM_VERSION 0x8
854 #define FIRMWARE_VERSION 0x9
855 #define OS_NAME_VERSION 0xa
856 #define MAX_CT_PAYLOAD_LEN 0xb
859 * Port Attrubute Types
861 #define SUPPORTED_FC4_TYPES 0x1
862 #define SUPPORTED_SPEED 0x2
863 #define PORT_SPEED 0x3
864 #define MAX_FRAME_SIZE 0x4
865 #define OS_DEVICE_NAME 0x5
866 #define HOST_NAME 0x6
868 union AttributesDef {
869 /* Structure is in Big Endian format */
871 uint32_t AttrType:16;
879 * HBA Attribute Entry (8 - 260 bytes)
882 union AttributesDef ad;
884 uint32_t VendorSpecific;
885 uint8_t Manufacturer[64];
886 uint8_t SerialNumber[64];
888 uint8_t ModelDescription[256];
889 uint8_t HardwareVersion[256];
890 uint8_t DriverVersion[256];
891 uint8_t OptionROMVersion[256];
892 uint8_t FirmwareVersion[256];
893 struct lpfc_name NodeName;
894 uint8_t SupportFC4Types[32];
895 uint32_t SupportSpeed;
897 uint32_t MaxFrameSize;
898 uint8_t OsDeviceName[256];
899 uint8_t OsNameVersion[256];
900 uint32_t MaxCTPayloadLen;
901 uint8_t HostName[256];
906 * HBA Attribute Block
909 uint32_t EntryCnt; /* Number of HBA attribute entries */
910 ATTRIBUTE_ENTRY Entry; /* Variable-length array */
917 struct lpfc_name PortName;
924 struct lpfc_name PortName;
928 * Registered Port List Format
932 PORT_ENTRY pe; /* Variable-length array */
940 REG_PORT_LIST rpl; /* variable-length array */
941 /* ATTRIBUTE_BLOCK ab; */
945 * Register HBA Attributes (RHAT)
948 struct lpfc_name HBA_PortName;
953 * Register Port Attributes (RPA)
956 struct lpfc_name PortName;
958 } REG_PORT_ATTRIBUTE;
961 * Get Registered HBA List (GRHL) Accept Payload Format
964 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */
965 struct lpfc_name HBA_PortName; /* Variable-length array */
969 * Get Registered Port List (GRPL) Accept Payload Format
972 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */
973 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */
977 * Get Port Attributes (GPAT) Accept Payload Format
986 * Begin HBA configuration parameters.
987 * The PCI configuration register BAR assignments are:
988 * BAR0, offset 0x10 - SLIM base memory address
989 * BAR1, offset 0x14 - SLIM base memory high address
990 * BAR2, offset 0x18 - REGISTER base memory address
991 * BAR3, offset 0x1c - REGISTER base memory high address
992 * BAR4, offset 0x20 - BIU I/O registers
993 * BAR5, offset 0x24 - REGISTER base io high address
996 /* Number of rings currently used and available. */
997 #define MAX_CONFIGURED_RINGS 3
1000 /* IOCB / Mailbox is owned by FireFly */
1003 /* IOCB / Mailbox is owned by Host */
1006 /* Number of 4-byte words in an IOCB. */
1007 #define IOCB_WORD_SZ 8
1009 /* defines for type field in fc header */
1010 #define FC_ELS_DATA 0x1
1011 #define FC_LLC_SNAP 0x5
1012 #define FC_FCP_DATA 0x8
1013 #define FC_COMMON_TRANSPORT_ULP 0x20
1015 /* defines for rctl field in fc header */
1016 #define FC_DEV_DATA 0x0
1017 #define FC_UNSOL_CTL 0x2
1018 #define FC_SOL_CTL 0x3
1019 #define FC_UNSOL_DATA 0x4
1020 #define FC_FCP_CMND 0x6
1021 #define FC_ELS_REQ 0x22
1022 #define FC_ELS_RSP 0x23
1024 /* network headers for Dfctl field */
1025 #define FC_NET_HDR 0x20
1027 /* Start FireFly Register definitions */
1028 #define PCI_VENDOR_ID_EMULEX 0x10df
1029 #define PCI_DEVICE_ID_FIREFLY 0x1ae5
1030 #define PCI_DEVICE_ID_SUPERFLY 0xf700
1031 #define PCI_DEVICE_ID_DRAGONFLY 0xf800
1032 #define PCI_DEVICE_ID_RFLY 0xf095
1033 #define PCI_DEVICE_ID_PFLY 0xf098
1034 #define PCI_DEVICE_ID_TFLY 0xf0a5
1035 #define PCI_DEVICE_ID_CENTAUR 0xf900
1036 #define PCI_DEVICE_ID_PEGASUS 0xf980
1037 #define PCI_DEVICE_ID_THOR 0xfa00
1038 #define PCI_DEVICE_ID_VIPER 0xfb00
1039 #define PCI_DEVICE_ID_HELIOS 0xfd00
1040 #define PCI_DEVICE_ID_BMID 0xf0d5
1041 #define PCI_DEVICE_ID_BSMB 0xf0d1
1042 #define PCI_DEVICE_ID_ZEPHYR 0xfe00
1043 #define PCI_DEVICE_ID_ZMID 0xf0e5
1044 #define PCI_DEVICE_ID_ZSMB 0xf0e1
1045 #define PCI_DEVICE_ID_LP101 0xf0a1
1046 #define PCI_DEVICE_ID_LP10000S 0xfc00
1048 #define JEDEC_ID_ADDRESS 0x0080001c
1049 #define FIREFLY_JEDEC_ID 0x1ACC
1050 #define SUPERFLY_JEDEC_ID 0x0020
1051 #define DRAGONFLY_JEDEC_ID 0x0021
1052 #define DRAGONFLY_V2_JEDEC_ID 0x0025
1053 #define CENTAUR_2G_JEDEC_ID 0x0026
1054 #define CENTAUR_1G_JEDEC_ID 0x0028
1055 #define PEGASUS_ORION_JEDEC_ID 0x0036
1056 #define PEGASUS_JEDEC_ID 0x0038
1057 #define THOR_JEDEC_ID 0x0012
1058 #define HELIOS_JEDEC_ID 0x0364
1059 #define ZEPHYR_JEDEC_ID 0x0577
1060 #define VIPER_JEDEC_ID 0x4838
1062 #define JEDEC_ID_MASK 0x0FFFF000
1063 #define JEDEC_ID_SHIFT 12
1064 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1066 typedef struct { /* FireFly BIU registers */
1067 uint32_t hostAtt; /* See definitions for Host Attention
1069 uint32_t chipAtt; /* See definitions for Chip Attention
1071 uint32_t hostStatus; /* See definitions for Host Status register */
1072 uint32_t hostControl; /* See definitions for Host Control register */
1073 uint32_t buiConfig; /* See definitions for BIU configuration
1077 /* IO Register size in bytes */
1078 #define FF_REG_AREA_SIZE 256
1080 /* Host Attention Register */
1082 #define HA_REG_OFFSET 0 /* Byte offset from register base address */
1084 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1085 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1086 #define HA_R0ATT 0x00000008 /* Bit 3 */
1087 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1088 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1089 #define HA_R1ATT 0x00000080 /* Bit 7 */
1090 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1091 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1092 #define HA_R2ATT 0x00000800 /* Bit 11 */
1093 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1094 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1095 #define HA_R3ATT 0x00008000 /* Bit 15 */
1096 #define HA_LATT 0x20000000 /* Bit 29 */
1097 #define HA_MBATT 0x40000000 /* Bit 30 */
1098 #define HA_ERATT 0x80000000 /* Bit 31 */
1100 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1101 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1102 #define HA_RXATT 0x00000008 /* Bit 3 */
1103 #define HA_RXMASK 0x0000000f
1105 /* Chip Attention Register */
1107 #define CA_REG_OFFSET 4 /* Byte offset from register base address */
1109 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1110 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1111 #define CA_R0ATT 0x00000008 /* Bit 3 */
1112 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1113 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1114 #define CA_R1ATT 0x00000080 /* Bit 7 */
1115 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1116 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1117 #define CA_R2ATT 0x00000800 /* Bit 11 */
1118 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1119 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1120 #define CA_R3ATT 0x00008000 /* Bit 15 */
1121 #define CA_MBATT 0x40000000 /* Bit 30 */
1123 /* Host Status Register */
1125 #define HS_REG_OFFSET 8 /* Byte offset from register base address */
1127 #define HS_MBRDY 0x00400000 /* Bit 22 */
1128 #define HS_FFRDY 0x00800000 /* Bit 23 */
1129 #define HS_FFER8 0x01000000 /* Bit 24 */
1130 #define HS_FFER7 0x02000000 /* Bit 25 */
1131 #define HS_FFER6 0x04000000 /* Bit 26 */
1132 #define HS_FFER5 0x08000000 /* Bit 27 */
1133 #define HS_FFER4 0x10000000 /* Bit 28 */
1134 #define HS_FFER3 0x20000000 /* Bit 29 */
1135 #define HS_FFER2 0x40000000 /* Bit 30 */
1136 #define HS_FFER1 0x80000000 /* Bit 31 */
1137 #define HS_FFERM 0xFF000000 /* Mask for error bits 31:24 */
1139 /* Host Control Register */
1141 #define HC_REG_OFFSET 12 /* Word offset from register base address */
1143 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1144 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1145 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1146 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1147 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1148 #define HC_INITHBI 0x02000000 /* Bit 25 */
1149 #define HC_INITMB 0x04000000 /* Bit 26 */
1150 #define HC_INITFF 0x08000000 /* Bit 27 */
1151 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1152 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1154 /* Mailbox Commands */
1155 #define MBX_SHUTDOWN 0x00 /* terminate testing */
1156 #define MBX_LOAD_SM 0x01
1157 #define MBX_READ_NV 0x02
1158 #define MBX_WRITE_NV 0x03
1159 #define MBX_RUN_BIU_DIAG 0x04
1160 #define MBX_INIT_LINK 0x05
1161 #define MBX_DOWN_LINK 0x06
1162 #define MBX_CONFIG_LINK 0x07
1163 #define MBX_CONFIG_RING 0x09
1164 #define MBX_RESET_RING 0x0A
1165 #define MBX_READ_CONFIG 0x0B
1166 #define MBX_READ_RCONFIG 0x0C
1167 #define MBX_READ_SPARM 0x0D
1168 #define MBX_READ_STATUS 0x0E
1169 #define MBX_READ_RPI 0x0F
1170 #define MBX_READ_XRI 0x10
1171 #define MBX_READ_REV 0x11
1172 #define MBX_READ_LNK_STAT 0x12
1173 #define MBX_REG_LOGIN 0x13
1174 #define MBX_UNREG_LOGIN 0x14
1175 #define MBX_READ_LA 0x15
1176 #define MBX_CLEAR_LA 0x16
1177 #define MBX_DUMP_MEMORY 0x17
1178 #define MBX_DUMP_CONTEXT 0x18
1179 #define MBX_RUN_DIAGS 0x19
1180 #define MBX_RESTART 0x1A
1181 #define MBX_UPDATE_CFG 0x1B
1182 #define MBX_DOWN_LOAD 0x1C
1183 #define MBX_DEL_LD_ENTRY 0x1D
1184 #define MBX_RUN_PROGRAM 0x1E
1185 #define MBX_SET_MASK 0x20
1186 #define MBX_SET_SLIM 0x21
1187 #define MBX_UNREG_D_ID 0x23
1188 #define MBX_CONFIG_FARP 0x25
1190 #define MBX_LOAD_AREA 0x81
1191 #define MBX_RUN_BIU_DIAG64 0x84
1192 #define MBX_CONFIG_PORT 0x88
1193 #define MBX_READ_SPARM64 0x8D
1194 #define MBX_READ_RPI64 0x8F
1195 #define MBX_REG_LOGIN64 0x93
1196 #define MBX_READ_LA64 0x95
1198 #define MBX_FLASH_WR_ULA 0x98
1199 #define MBX_SET_DEBUG 0x99
1200 #define MBX_LOAD_EXP_ROM 0x9C
1202 #define MBX_MAX_CMDS 0x9D
1203 #define MBX_SLI2_CMD_MASK 0x80
1207 #define CMD_RCV_SEQUENCE_CX 0x01
1208 #define CMD_XMIT_SEQUENCE_CR 0x02
1209 #define CMD_XMIT_SEQUENCE_CX 0x03
1210 #define CMD_XMIT_BCAST_CN 0x04
1211 #define CMD_XMIT_BCAST_CX 0x05
1212 #define CMD_QUE_RING_BUF_CN 0x06
1213 #define CMD_QUE_XRI_BUF_CX 0x07
1214 #define CMD_IOCB_CONTINUE_CN 0x08
1215 #define CMD_RET_XRI_BUF_CX 0x09
1216 #define CMD_ELS_REQUEST_CR 0x0A
1217 #define CMD_ELS_REQUEST_CX 0x0B
1218 #define CMD_RCV_ELS_REQ_CX 0x0D
1219 #define CMD_ABORT_XRI_CN 0x0E
1220 #define CMD_ABORT_XRI_CX 0x0F
1221 #define CMD_CLOSE_XRI_CN 0x10
1222 #define CMD_CLOSE_XRI_CX 0x11
1223 #define CMD_CREATE_XRI_CR 0x12
1224 #define CMD_CREATE_XRI_CX 0x13
1225 #define CMD_GET_RPI_CN 0x14
1226 #define CMD_XMIT_ELS_RSP_CX 0x15
1227 #define CMD_GET_RPI_CR 0x16
1228 #define CMD_XRI_ABORTED_CX 0x17
1229 #define CMD_FCP_IWRITE_CR 0x18
1230 #define CMD_FCP_IWRITE_CX 0x19
1231 #define CMD_FCP_IREAD_CR 0x1A
1232 #define CMD_FCP_IREAD_CX 0x1B
1233 #define CMD_FCP_ICMND_CR 0x1C
1234 #define CMD_FCP_ICMND_CX 0x1D
1236 #define CMD_ADAPTER_MSG 0x20
1237 #define CMD_ADAPTER_DUMP 0x22
1239 /* SLI_2 IOCB Command Set */
1241 #define CMD_RCV_SEQUENCE64_CX 0x81
1242 #define CMD_XMIT_SEQUENCE64_CR 0x82
1243 #define CMD_XMIT_SEQUENCE64_CX 0x83
1244 #define CMD_XMIT_BCAST64_CN 0x84
1245 #define CMD_XMIT_BCAST64_CX 0x85
1246 #define CMD_QUE_RING_BUF64_CN 0x86
1247 #define CMD_QUE_XRI_BUF64_CX 0x87
1248 #define CMD_IOCB_CONTINUE64_CN 0x88
1249 #define CMD_RET_XRI_BUF64_CX 0x89
1250 #define CMD_ELS_REQUEST64_CR 0x8A
1251 #define CMD_ELS_REQUEST64_CX 0x8B
1252 #define CMD_ABORT_MXRI64_CN 0x8C
1253 #define CMD_RCV_ELS_REQ64_CX 0x8D
1254 #define CMD_XMIT_ELS_RSP64_CX 0x95
1255 #define CMD_FCP_IWRITE64_CR 0x98
1256 #define CMD_FCP_IWRITE64_CX 0x99
1257 #define CMD_FCP_IREAD64_CR 0x9A
1258 #define CMD_FCP_IREAD64_CX 0x9B
1259 #define CMD_FCP_ICMND64_CR 0x9C
1260 #define CMD_FCP_ICMND64_CX 0x9D
1262 #define CMD_GEN_REQUEST64_CR 0xC2
1263 #define CMD_GEN_REQUEST64_CX 0xC3
1265 #define CMD_MAX_IOCB_CMD 0xE6
1266 #define CMD_IOCB_MASK 0xff
1268 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1270 #define LPFC_MAX_ADPTMSG 32 /* max msg data */
1274 #define MBX_SUCCESS 0
1275 #define MBXERR_NUM_RINGS 1
1276 #define MBXERR_NUM_IOCBS 2
1277 #define MBXERR_IOCBS_EXCEEDED 3
1278 #define MBXERR_BAD_RING_NUMBER 4
1279 #define MBXERR_MASK_ENTRIES_RANGE 5
1280 #define MBXERR_MASKS_EXCEEDED 6
1281 #define MBXERR_BAD_PROFILE 7
1282 #define MBXERR_BAD_DEF_CLASS 8
1283 #define MBXERR_BAD_MAX_RESPONDER 9
1284 #define MBXERR_BAD_MAX_ORIGINATOR 10
1285 #define MBXERR_RPI_REGISTERED 11
1286 #define MBXERR_RPI_FULL 12
1287 #define MBXERR_NO_RESOURCES 13
1288 #define MBXERR_BAD_RCV_LENGTH 14
1289 #define MBXERR_DMA_ERROR 15
1290 #define MBXERR_ERROR 16
1291 #define MBX_NOT_FINISHED 255
1293 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1294 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1297 * Begin Structure Definitions for Mailbox Commands
1301 #ifdef __BIG_ENDIAN_BITFIELD
1306 #else /* __LITTLE_ENDIAN_BITFIELD */
1315 uint32_t bdeAddress;
1316 #ifdef __BIG_ENDIAN_BITFIELD
1317 uint32_t bdeReserved:4;
1318 uint32_t bdeAddrHigh:4;
1319 uint32_t bdeSize:24;
1320 #else /* __LITTLE_ENDIAN_BITFIELD */
1321 uint32_t bdeSize:24;
1322 uint32_t bdeAddrHigh:4;
1323 uint32_t bdeReserved:4;
1327 struct ulp_bde64 { /* SLI-2 */
1331 #ifdef __BIG_ENDIAN_BITFIELD
1332 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
1334 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
1335 #else /* __LITTLE_ENDIAN_BITFIELD */
1336 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
1337 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
1341 #define BUFF_USE_RSVD 0x01 /* bdeFlags */
1342 #define BUFF_USE_INTRPT 0x02 /* Not Implemented with LP6000 */
1343 #define BUFF_USE_CMND 0x04 /* Optional, 1=cmd/rsp 0=data buffer */
1344 #define BUFF_USE_RCV 0x08 /* "" "", 1=rcv buffer, 0=xmit
1346 #define BUFF_TYPE_32BIT 0x10 /* "" "", 1=32 bit addr 0=64 bit
1348 #define BUFF_TYPE_SPECIAL 0x20 /* Not Implemented with LP6000 */
1349 #define BUFF_TYPE_BDL 0x40 /* Optional, may be set in BDL */
1350 #define BUFF_TYPE_INVALID 0x80 /* "" "" */
1356 #define BDE64_SIZE_WORD 0
1357 #define BPL64_SIZE_WORD 0x40
1359 typedef struct ULP_BDL { /* SLI-2 */
1360 #ifdef __BIG_ENDIAN_BITFIELD
1361 uint32_t bdeFlags:8; /* BDL Flags */
1362 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1363 #else /* __LITTLE_ENDIAN_BITFIELD */
1364 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1365 uint32_t bdeFlags:8; /* BDL Flags */
1368 uint32_t addrLow; /* Address 0:31 */
1369 uint32_t addrHigh; /* Address 32:63 */
1370 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
1373 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
1376 #ifdef __BIG_ENDIAN_BITFIELD
1378 uint32_t acknowledgment:1;
1380 uint32_t erase_or_prog:1;
1381 uint32_t update_flash:1;
1382 uint32_t update_ram:1;
1384 uint32_t load_cmplt:1;
1385 #else /* __LITTLE_ENDIAN_BITFIELD */
1386 uint32_t load_cmplt:1;
1388 uint32_t update_ram:1;
1389 uint32_t update_flash:1;
1390 uint32_t erase_or_prog:1;
1392 uint32_t acknowledgment:1;
1396 uint32_t dl_to_adr_low;
1397 uint32_t dl_to_adr_high;
1400 uint32_t dl_from_mbx_offset;
1401 struct ulp_bde dl_from_bde;
1402 struct ulp_bde64 dl_from_bde64;
1407 /* Structure for MB Command READ_NVPARM (02) */
1410 uint32_t rsvd1[3]; /* Read as all one's */
1411 uint32_t rsvd2; /* Read as all zero's */
1412 uint32_t portname[2]; /* N_PORT name */
1413 uint32_t nodename[2]; /* NODE name */
1415 #ifdef __BIG_ENDIAN_BITFIELD
1416 uint32_t pref_DID:24;
1417 uint32_t hardAL_PA:8;
1418 #else /* __LITTLE_ENDIAN_BITFIELD */
1419 uint32_t hardAL_PA:8;
1420 uint32_t pref_DID:24;
1423 uint32_t rsvd3[21]; /* Read as all one's */
1426 /* Structure for MB Command WRITE_NVPARMS (03) */
1429 uint32_t rsvd1[3]; /* Must be all one's */
1430 uint32_t rsvd2; /* Must be all zero's */
1431 uint32_t portname[2]; /* N_PORT name */
1432 uint32_t nodename[2]; /* NODE name */
1434 #ifdef __BIG_ENDIAN_BITFIELD
1435 uint32_t pref_DID:24;
1436 uint32_t hardAL_PA:8;
1437 #else /* __LITTLE_ENDIAN_BITFIELD */
1438 uint32_t hardAL_PA:8;
1439 uint32_t pref_DID:24;
1442 uint32_t rsvd3[21]; /* Must be all one's */
1445 /* Structure for MB Command RUN_BIU_DIAG (04) */
1446 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
1452 struct ulp_bde xmit_bde;
1453 struct ulp_bde rcv_bde;
1456 struct ulp_bde64 xmit_bde64;
1457 struct ulp_bde64 rcv_bde64;
1462 /* Structure for MB Command INIT_LINK (05) */
1465 #ifdef __BIG_ENDIAN_BITFIELD
1467 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1468 #else /* __LITTLE_ENDIAN_BITFIELD */
1469 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1473 #ifdef __BIG_ENDIAN_BITFIELD
1474 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1476 uint16_t link_flags;
1477 #else /* __LITTLE_ENDIAN_BITFIELD */
1478 uint16_t link_flags;
1480 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1483 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
1484 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
1485 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
1486 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
1487 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
1488 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
1490 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
1491 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
1493 uint32_t link_speed;
1494 #define LINK_SPEED_AUTO 0 /* Auto selection */
1495 #define LINK_SPEED_1G 1 /* 1 Gigabaud */
1496 #define LINK_SPEED_2G 2 /* 2 Gigabaud */
1497 #define LINK_SPEED_4G 4 /* 4 Gigabaud */
1498 #define LINK_SPEED_8G 8 /* 4 Gigabaud */
1499 #define LINK_SPEED_10G 16 /* 10 Gigabaud */
1503 /* Structure for MB Command DOWN_LINK (06) */
1509 /* Structure for MB Command CONFIG_LINK (07) */
1512 #ifdef __BIG_ENDIAN_BITFIELD
1515 uint32_t cr_delay:6;
1516 uint32_t cr_count:8;
1519 #else /* __LITTLE_ENDIAN_BITFIELD */
1522 uint32_t cr_count:8;
1523 uint32_t cr_delay:6;
1537 #ifdef __BIG_ENDIAN_BITFIELD
1538 uint32_t rrq_enable:1;
1539 uint32_t rrq_immed:1;
1541 uint32_t ack0_enable:1;
1542 #else /* __LITTLE_ENDIAN_BITFIELD */
1543 uint32_t ack0_enable:1;
1545 uint32_t rrq_immed:1;
1546 uint32_t rrq_enable:1;
1550 /* Structure for MB Command PART_SLIM (08)
1551 * will be removed since SLI1 is no longer supported!
1554 #ifdef __BIG_ENDIAN_BITFIELD
1559 #else /* __LITTLE_ENDIAN_BITFIELD */
1568 #ifdef __BIG_ENDIAN_BITFIELD
1569 uint32_t unused1:24;
1571 #else /* __LITTLE_ENDIAN_BITFIELD */
1573 uint32_t unused1:24;
1576 RING_DEF ringdef[4];
1580 /* Structure for MB Command CONFIG_RING (09) */
1583 #ifdef __BIG_ENDIAN_BITFIELD
1586 uint32_t recvNotify:1;
1591 #else /* __LITTLE_ENDIAN_BITFIELD */
1596 uint32_t recvNotify:1;
1601 #ifdef __BIG_ENDIAN_BITFIELD
1602 uint16_t maxRespXchg;
1603 uint16_t maxOrigXchg;
1604 #else /* __LITTLE_ENDIAN_BITFIELD */
1605 uint16_t maxOrigXchg;
1606 uint16_t maxRespXchg;
1612 /* Structure for MB Command RESET_RING (10) */
1618 /* Structure for MB Command READ_CONFIG (11) */
1621 #ifdef __BIG_ENDIAN_BITFIELD
1624 uint32_t cr_delay:6;
1625 uint32_t cr_count:8;
1628 #else /* __LITTLE_ENDIAN_BITFIELD */
1631 uint32_t cr_count:8;
1632 uint32_t cr_delay:6;
1637 #ifdef __BIG_ENDIAN_BITFIELD
1638 uint32_t topology:8;
1640 #else /* __LITTLE_ENDIAN_BITFIELD */
1642 uint32_t topology:8;
1645 /* Defines for topology (defined previously) */
1646 #ifdef __BIG_ENDIAN_BITFIELD
1651 #else /* __LITTLE_ENDIAN_BITFIELD */
1664 #define LMT_RESERVED 0x0 /* Not used */
1665 #define LMT_266_10bit 0x1 /* 265.625 Mbaud 10 bit iface */
1666 #define LMT_532_10bit 0x2 /* 531.25 Mbaud 10 bit iface */
1667 #define LMT_1063_20bit 0x3 /* 1062.5 Mbaud 20 bit iface */
1668 #define LMT_1063_10bit 0x4 /* 1062.5 Mbaud 10 bit iface */
1669 #define LMT_2125_10bit 0x8 /* 2125 Mbaud 10 bit iface */
1670 #define LMT_4250_10bit 0x40 /* 4250 Mbaud 10 bit iface */
1678 uint32_t avail_iocb;
1680 uint32_t default_rpi;
1683 /* Structure for MB Command READ_RCONFIG (12) */
1686 #ifdef __BIG_ENDIAN_BITFIELD
1688 uint32_t recvNotify:1;
1693 #else /* __LITTLE_ENDIAN_BITFIELD */
1698 uint32_t recvNotify:1;
1702 #ifdef __BIG_ENDIAN_BITFIELD
1705 #else /* __LITTLE_ENDIAN_BITFIELD */
1712 #ifdef __BIG_ENDIAN_BITFIELD
1713 uint16_t cmdRingOffset;
1714 uint16_t cmdEntryCnt;
1715 uint16_t rspRingOffset;
1716 uint16_t rspEntryCnt;
1717 uint16_t nextCmdOffset;
1719 uint16_t nextRspOffset;
1721 #else /* __LITTLE_ENDIAN_BITFIELD */
1722 uint16_t cmdEntryCnt;
1723 uint16_t cmdRingOffset;
1724 uint16_t rspEntryCnt;
1725 uint16_t rspRingOffset;
1727 uint16_t nextCmdOffset;
1729 uint16_t nextRspOffset;
1733 /* Structure for MB Command READ_SPARM (13) */
1734 /* Structure for MB Command READ_SPARM64 (0x8D) */
1740 struct ulp_bde sp; /* This BDE points to struct serv_parm
1742 struct ulp_bde64 sp64;
1746 /* Structure for MB Command READ_STATUS (14) */
1749 #ifdef __BIG_ENDIAN_BITFIELD
1751 uint32_t clrCounters:1;
1752 uint16_t activeXriCnt;
1753 uint16_t activeRpiCnt;
1754 #else /* __LITTLE_ENDIAN_BITFIELD */
1755 uint32_t clrCounters:1;
1757 uint16_t activeRpiCnt;
1758 uint16_t activeXriCnt;
1761 uint32_t xmitByteCnt;
1762 uint32_t rcvByteCnt;
1763 uint32_t xmitFrameCnt;
1764 uint32_t rcvFrameCnt;
1765 uint32_t xmitSeqCnt;
1767 uint32_t totalOrigExchanges;
1768 uint32_t totalRespExchanges;
1769 uint32_t rcvPbsyCnt;
1770 uint32_t rcvFbsyCnt;
1773 /* Structure for MB Command READ_RPI (15) */
1774 /* Structure for MB Command READ_RPI64 (0x8F) */
1777 #ifdef __BIG_ENDIAN_BITFIELD
1782 #else /* __LITTLE_ENDIAN_BITFIELD */
1791 struct ulp_bde64 sp64;
1796 /* Structure for MB Command READ_XRI (16) */
1799 #ifdef __BIG_ENDIAN_BITFIELD
1816 uint32_t exchOrig:1;
1817 #else /* __LITTLE_ENDIAN_BITFIELD */
1832 uint32_t exchOrig:1;
1838 /* Structure for MB Command READ_REV (17) */
1841 #ifdef __BIG_ENDIAN_BITFIELD
1846 #else /* __LITTLE_ENDIAN_BITFIELD */
1858 #ifdef __BIG_ENDIAN_BITFIELD
1863 uint16_t ProgFixLvl:2;
1864 uint16_t ProgDistType:2;
1866 #else /* __LITTLE_ENDIAN_BITFIELD */
1868 uint16_t ProgDistType:2;
1869 uint16_t ProgFixLvl:2;
1879 #ifdef __BIG_ENDIAN_BITFIELD
1880 uint8_t feaLevelHigh;
1881 uint8_t feaLevelLow;
1884 #else /* __LITTLE_ENDIAN_BITFIELD */
1887 uint8_t feaLevelLow;
1888 uint8_t feaLevelHigh;
1891 uint32_t postKernRev;
1893 uint8_t opFwName[16];
1895 uint8_t sli1FwName[16];
1897 uint8_t sli2FwName[16];
1899 uint32_t RandomData[7];
1902 /* Structure for MB Command READ_LINK_STAT (18) */
1906 uint32_t linkFailureCnt;
1907 uint32_t lossSyncCnt;
1909 uint32_t lossSignalCnt;
1910 uint32_t primSeqErrCnt;
1911 uint32_t invalidXmitWord;
1913 uint32_t primSeqTimeout;
1914 uint32_t elasticOverrun;
1915 uint32_t arbTimeout;
1918 /* Structure for MB Command REG_LOGIN (19) */
1919 /* Structure for MB Command REG_LOGIN64 (0x93) */
1922 #ifdef __BIG_ENDIAN_BITFIELD
1927 #else /* __LITTLE_ENDIAN_BITFIELD */
1936 struct ulp_bde64 sp64;
1941 /* Word 30 contents for REG_LOGIN */
1944 #ifdef __BIG_ENDIAN_BITFIELD
1946 uint16_t wd30_class:4;
1948 #else /* __LITTLE_ENDIAN_BITFIELD */
1950 uint16_t wd30_class:4;
1957 /* Structure for MB Command UNREG_LOGIN (20) */
1960 #ifdef __BIG_ENDIAN_BITFIELD
1963 #else /* __LITTLE_ENDIAN_BITFIELD */
1969 /* Structure for MB Command UNREG_D_ID (0x23) */
1975 /* Structure for MB Command READ_LA (21) */
1976 /* Structure for MB Command READ_LA64 (0x95) */
1979 uint32_t eventTag; /* Event tag */
1980 #ifdef __BIG_ENDIAN_BITFIELD
1985 #else /* __LITTLE_ENDIAN_BITFIELD */
1992 #define AT_RESERVED 0x00 /* Reserved - attType */
1993 #define AT_LINK_UP 0x01 /* Link is up */
1994 #define AT_LINK_DOWN 0x02 /* Link is down */
1996 #ifdef __BIG_ENDIAN_BITFIELD
1997 uint8_t granted_AL_PA;
2001 #else /* __LITTLE_ENDIAN_BITFIELD */
2005 uint8_t granted_AL_PA;
2008 #define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2009 #define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
2012 struct ulp_bde lilpBde; /* This BDE points to a 128 byte buffer
2014 /* store the LILP AL_PA position map into */
2015 struct ulp_bde64 lilpBde64;
2018 #ifdef __BIG_ENDIAN_BITFIELD
2022 uint32_t DlnkSpeed:8;
2026 #else /* __LITTLE_ENDIAN_BITFIELD */
2030 uint32_t DlnkSpeed:8;
2036 #ifdef __BIG_ENDIAN_BITFIELD
2040 uint32_t UlnkSpeed:8;
2044 #else /* __LITTLE_ENDIAN_BITFIELD */
2048 uint32_t UlnkSpeed:8;
2054 #define LA_UNKNW_LINK 0x0 /* lnkSpeed */
2055 #define LA_1GHZ_LINK 0x04 /* lnkSpeed */
2056 #define LA_2GHZ_LINK 0x08 /* lnkSpeed */
2057 #define LA_4GHZ_LINK 0x10 /* lnkSpeed */
2058 #define LA_8GHZ_LINK 0x20 /* lnkSpeed */
2059 #define LA_10GHZ_LINK 0x40 /* lnkSpeed */
2063 /* Structure for MB Command CLEAR_LA (22) */
2066 uint32_t eventTag; /* Event tag */
2070 /* Structure for MB Command DUMP */
2073 #ifdef __BIG_ENDIAN_BITFIELD
2079 uint32_t entry_index:16;
2080 uint32_t region_id:16;
2081 #else /* __LITTLE_ENDIAN_BITFIELD */
2087 uint32_t region_id:16;
2088 uint32_t entry_index:16;
2093 uint32_t resp_offset;
2096 #define DMP_MEM_REG 0x1
2097 #define DMP_NV_PARAMS 0x2
2099 #define DMP_REGION_VPD 0xe
2100 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
2101 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
2102 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
2104 /* Structure for MB Command CONFIG_PORT (0x88) */
2108 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
2109 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
2110 uint32_t hbainit[5];
2113 /* SLI-2 Port Control Block */
2116 #define SLIMOFF 0x30 /* WORD */
2118 typedef struct _SLI2_RDSC {
2119 uint32_t cmdEntries;
2120 uint32_t cmdAddrLow;
2121 uint32_t cmdAddrHigh;
2123 uint32_t rspEntries;
2124 uint32_t rspAddrLow;
2125 uint32_t rspAddrHigh;
2128 typedef struct _PCB {
2129 #ifdef __BIG_ENDIAN_BITFIELD
2131 #define TYPE_NATIVE_SLI2 0x01;
2133 #define FEATURE_INITIAL_SLI2 0x01;
2136 #else /* __LITTLE_ENDIAN_BITFIELD */
2140 #define FEATURE_INITIAL_SLI2 0x01;
2142 #define TYPE_NATIVE_SLI2 0x01;
2145 uint32_t mailBoxSize;
2147 uint32_t mbAddrHigh;
2149 uint32_t hgpAddrLow;
2150 uint32_t hgpAddrHigh;
2152 uint32_t pgpAddrLow;
2153 uint32_t pgpAddrHigh;
2154 SLI2_RDSC rdsc[MAX_RINGS];
2159 #ifdef __BIG_ENDIAN_BITFIELD
2161 uint32_t discardFarp:1;
2162 uint32_t IPEnable:1;
2163 uint32_t nodeName:1;
2164 uint32_t portName:1;
2165 uint32_t filterEnable:1;
2166 #else /* __LITTLE_ENDIAN_BITFIELD */
2167 uint32_t filterEnable:1;
2168 uint32_t portName:1;
2169 uint32_t nodeName:1;
2170 uint32_t IPEnable:1;
2171 uint32_t discardFarp:1;
2175 uint8_t portname[8]; /* Used to be struct lpfc_name */
2176 uint8_t nodename[8];
2183 /* Union of all Mailbox Command types */
2184 #define MAILBOX_CMD_WSIZE 32
2185 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
2188 uint32_t varWords[MAILBOX_CMD_WSIZE - 1];
2189 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
2190 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
2191 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
2192 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
2193 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
2194 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
2195 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
2196 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
2197 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
2198 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
2199 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
2200 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
2201 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
2202 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
2203 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
2204 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
2205 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
2206 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
2207 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
2208 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
2209 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */
2210 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
2211 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
2212 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
2213 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) NEW_FEATURE */
2214 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
2218 * SLI-2 specific structures
2231 typedef struct _SLI2_DESC {
2232 struct lpfc_hgp host[MAX_RINGS];
2233 uint32_t unused1[16];
2234 struct lpfc_pgp port[MAX_RINGS];
2242 #ifdef __BIG_ENDIAN_BITFIELD
2245 uint8_t mbxReserved:6;
2247 uint8_t mbxOwner:1; /* Low order bit first word */
2248 #else /* __LITTLE_ENDIAN_BITFIELD */
2249 uint8_t mbxOwner:1; /* Low order bit first word */
2251 uint8_t mbxReserved:6;
2261 * Begin Structure Definitions for IOCB Commands
2265 #ifdef __BIG_ENDIAN_BITFIELD
2269 uint8_t statLocalError;
2270 #else /* __LITTLE_ENDIAN_BITFIELD */
2271 uint8_t statLocalError;
2276 /* statRsn P/F_RJT reason codes */
2277 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
2278 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
2279 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
2280 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
2281 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */
2282 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
2283 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */
2284 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
2285 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
2286 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
2287 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */
2288 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */
2289 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
2290 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
2291 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
2292 #define RJT_BAD_PARM 0x10 /* Param. field invalid */
2293 #define RJT_XCHG_ERR 0x11 /* Exchange error */
2294 #define RJT_PROT_ERR 0x12 /* Protocol error */
2295 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */
2296 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
2297 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
2298 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
2299 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
2300 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
2301 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
2302 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
2304 #define IOERR_SUCCESS 0x00 /* statLocalError */
2305 #define IOERR_MISSING_CONTINUE 0x01
2306 #define IOERR_SEQUENCE_TIMEOUT 0x02
2307 #define IOERR_INTERNAL_ERROR 0x03
2308 #define IOERR_INVALID_RPI 0x04
2309 #define IOERR_NO_XRI 0x05
2310 #define IOERR_ILLEGAL_COMMAND 0x06
2311 #define IOERR_XCHG_DROPPED 0x07
2312 #define IOERR_ILLEGAL_FIELD 0x08
2313 #define IOERR_BAD_CONTINUE 0x09
2314 #define IOERR_TOO_MANY_BUFFERS 0x0A
2315 #define IOERR_RCV_BUFFER_WAITING 0x0B
2316 #define IOERR_NO_CONNECTION 0x0C
2317 #define IOERR_TX_DMA_FAILED 0x0D
2318 #define IOERR_RX_DMA_FAILED 0x0E
2319 #define IOERR_ILLEGAL_FRAME 0x0F
2320 #define IOERR_EXTRA_DATA 0x10
2321 #define IOERR_NO_RESOURCES 0x11
2322 #define IOERR_RESERVED 0x12
2323 #define IOERR_ILLEGAL_LENGTH 0x13
2324 #define IOERR_UNSUPPORTED_FEATURE 0x14
2325 #define IOERR_ABORT_IN_PROGRESS 0x15
2326 #define IOERR_ABORT_REQUESTED 0x16
2327 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
2328 #define IOERR_LOOP_OPEN_FAILURE 0x18
2329 #define IOERR_RING_RESET 0x19
2330 #define IOERR_LINK_DOWN 0x1A
2331 #define IOERR_CORRUPTED_DATA 0x1B
2332 #define IOERR_CORRUPTED_RPI 0x1C
2333 #define IOERR_OUT_OF_ORDER_DATA 0x1D
2334 #define IOERR_OUT_OF_ORDER_ACK 0x1E
2335 #define IOERR_DUP_FRAME 0x1F
2336 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
2337 #define IOERR_BAD_HOST_ADDRESS 0x21
2338 #define IOERR_RCV_HDRBUF_WAITING 0x22
2339 #define IOERR_MISSING_HDR_BUFFER 0x23
2340 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
2341 #define IOERR_ABORTMULT_REQUESTED 0x25
2342 #define IOERR_BUFFER_SHORTAGE 0x28
2343 #define IOERR_DEFAULT 0x29
2344 #define IOERR_CNT 0x2A
2346 #define IOERR_DRVR_MASK 0x100
2347 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
2348 #define IOERR_SLI_BRESET 0x102
2349 #define IOERR_SLI_ABORTED 0x103
2354 #ifdef __BIG_ENDIAN_BITFIELD
2355 uint8_t Rctl; /* R_CTL field */
2356 uint8_t Type; /* TYPE field */
2357 uint8_t Dfctl; /* DF_CTL field */
2358 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
2359 #else /* __LITTLE_ENDIAN_BITFIELD */
2360 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
2361 uint8_t Dfctl; /* DF_CTL field */
2362 uint8_t Type; /* TYPE field */
2363 uint8_t Rctl; /* R_CTL field */
2366 #define BC 0x02 /* Broadcast Received - Fctl */
2367 #define SI 0x04 /* Sequence Initiative */
2368 #define LA 0x08 /* Ignore Link Attention state */
2369 #define LS 0x80 /* Last Sequence */
2374 /* IOCB Command template for a generic response */
2376 uint32_t reserved[4];
2380 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
2382 struct ulp_bde xrsqbde[2];
2383 uint32_t xrsqRo; /* Starting Relative Offset */
2384 WORD5 w5; /* Header control/status word */
2387 /* IOCB Command template for ELS_REQUEST */
2389 struct ulp_bde elsReq;
2390 struct ulp_bde elsRsp;
2392 #ifdef __BIG_ENDIAN_BITFIELD
2393 uint32_t word4Rsvd:7;
2396 uint32_t word5Rsvd:8;
2397 uint32_t remoteID:24;
2398 #else /* __LITTLE_ENDIAN_BITFIELD */
2401 uint32_t word4Rsvd:7;
2402 uint32_t remoteID:24;
2403 uint32_t word5Rsvd:8;
2407 /* IOCB Command template for RCV_ELS_REQ */
2409 struct ulp_bde elsReq[2];
2412 #ifdef __BIG_ENDIAN_BITFIELD
2413 uint32_t word5Rsvd:8;
2414 uint32_t remoteID:24;
2415 #else /* __LITTLE_ENDIAN_BITFIELD */
2416 uint32_t remoteID:24;
2417 uint32_t word5Rsvd:8;
2421 /* IOCB Command template for ABORT / CLOSE_XRI */
2425 #define ABORT_TYPE_ABTX 0x00000000
2426 #define ABORT_TYPE_ABTS 0x00000001
2428 #ifdef __BIG_ENDIAN_BITFIELD
2429 uint16_t abortContextTag; /* ulpContext from command to abort/close */
2430 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
2431 #else /* __LITTLE_ENDIAN_BITFIELD */
2432 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
2433 uint16_t abortContextTag; /* ulpContext from command to abort/close */
2437 /* IOCB Command template for ABORT_MXRI64 */
2445 /* IOCB Command template for GET_RPI */
2449 #ifdef __BIG_ENDIAN_BITFIELD
2450 uint32_t word5Rsvd:8;
2451 uint32_t remoteID:24;
2452 #else /* __LITTLE_ENDIAN_BITFIELD */
2453 uint32_t remoteID:24;
2454 uint32_t word5Rsvd:8;
2458 /* IOCB Command template for all FCP Initiator commands */
2460 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
2461 struct ulp_bde fcpi_rsp; /* Rcv buffer */
2463 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
2466 /* IOCB Command template for all FCP Target commands */
2468 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
2469 uint32_t fcpt_Offset;
2470 uint32_t fcpt_Length; /* transfer ready for IWRITE */
2473 /* SLI-2 IOCB structure definitions */
2475 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
2478 uint32_t xrsqRo; /* Starting Relative Offset */
2479 WORD5 w5; /* Header control/status word */
2482 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
2484 struct ulp_bde64 rcvBde;
2486 uint32_t xrsqRo; /* Starting Relative Offset */
2487 WORD5 w5; /* Header control/status word */
2490 /* IOCB Command template for ELS_REQUEST64 */
2493 #ifdef __BIG_ENDIAN_BITFIELD
2494 uint32_t word4Rsvd:7;
2497 uint32_t word5Rsvd:8;
2498 uint32_t remoteID:24;
2499 #else /* __LITTLE_ENDIAN_BITFIELD */
2502 uint32_t word4Rsvd:7;
2503 uint32_t remoteID:24;
2504 uint32_t word5Rsvd:8;
2508 /* IOCB Command template for GEN_REQUEST64 */
2511 uint32_t xrsqRo; /* Starting Relative Offset */
2512 WORD5 w5; /* Header control/status word */
2515 /* IOCB Command template for RCV_ELS_REQ64 */
2517 struct ulp_bde64 elsReq;
2521 #ifdef __BIG_ENDIAN_BITFIELD
2522 uint32_t word5Rsvd:8;
2523 uint32_t remoteID:24;
2524 #else /* __LITTLE_ENDIAN_BITFIELD */
2525 uint32_t remoteID:24;
2526 uint32_t word5Rsvd:8;
2530 /* IOCB Command template for all 64 bit FCP Initiator commands */
2534 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
2537 /* IOCB Command template for all 64 bit FCP Target commands */
2540 uint32_t fcpt_Offset;
2541 uint32_t fcpt_Length; /* transfer ready for IWRITE */
2544 typedef struct _IOCB { /* IOCB structure */
2546 GENERIC_RSP grsp; /* Generic response */
2547 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
2548 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
2549 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
2550 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
2551 A_MXRI64 amxri; /* abort multiple xri command overlay */
2552 GET_RPI getrpi; /* GET_RPI template */
2553 FCPI_FIELDS fcpi; /* FCP Initiator template */
2554 FCPT_FIELDS fcpt; /* FCP target template */
2556 /* SLI-2 structures */
2558 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
2560 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
2561 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
2562 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
2563 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
2564 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
2565 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
2567 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
2571 #ifdef __BIG_ENDIAN_BITFIELD
2572 uint16_t ulpContext; /* High order bits word 6 */
2573 uint16_t ulpIoTag; /* Low order bits word 6 */
2574 #else /* __LITTLE_ENDIAN_BITFIELD */
2575 uint16_t ulpIoTag; /* Low order bits word 6 */
2576 uint16_t ulpContext; /* High order bits word 6 */
2580 #ifdef __BIG_ENDIAN_BITFIELD
2581 uint16_t ulpContext; /* High order bits word 6 */
2582 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
2583 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
2584 #else /* __LITTLE_ENDIAN_BITFIELD */
2585 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
2586 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
2587 uint16_t ulpContext; /* High order bits word 6 */
2591 #define ulpContext un1.t1.ulpContext
2592 #define ulpIoTag un1.t1.ulpIoTag
2593 #define ulpIoTag0 un1.t2.ulpIoTag0
2595 #ifdef __BIG_ENDIAN_BITFIELD
2596 uint32_t ulpTimeout:8;
2598 uint32_t ulpFCP2Rcvy:1;
2601 uint32_t ulpClass:3;
2602 uint32_t ulpCommand:8;
2603 uint32_t ulpStatus:4;
2604 uint32_t ulpBdeCount:2;
2606 uint32_t ulpOwner:1; /* Low order bit word 7 */
2607 #else /* __LITTLE_ENDIAN_BITFIELD */
2608 uint32_t ulpOwner:1; /* Low order bit word 7 */
2610 uint32_t ulpBdeCount:2;
2611 uint32_t ulpStatus:4;
2612 uint32_t ulpCommand:8;
2613 uint32_t ulpClass:3;
2616 uint32_t ulpFCP2Rcvy:1;
2618 uint32_t ulpTimeout:8;
2621 #define PARM_UNUSED 0 /* PU field (Word 4) not used */
2622 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
2623 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
2624 #define CLASS1 0 /* Class 1 */
2625 #define CLASS2 1 /* Class 2 */
2626 #define CLASS3 2 /* Class 3 */
2627 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
2629 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
2630 #define IOSTAT_FCP_RSP_ERROR 0x1
2631 #define IOSTAT_REMOTE_STOP 0x2
2632 #define IOSTAT_LOCAL_REJECT 0x3
2633 #define IOSTAT_NPORT_RJT 0x4
2634 #define IOSTAT_FABRIC_RJT 0x5
2635 #define IOSTAT_NPORT_BSY 0x6
2636 #define IOSTAT_FABRIC_BSY 0x7
2637 #define IOSTAT_INTERMED_RSP 0x8
2638 #define IOSTAT_LS_RJT 0x9
2639 #define IOSTAT_BA_RJT 0xA
2640 #define IOSTAT_RSVD1 0xB
2641 #define IOSTAT_RSVD2 0xC
2642 #define IOSTAT_RSVD3 0xD
2643 #define IOSTAT_RSVD4 0xE
2644 #define IOSTAT_RSVD5 0xF
2645 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
2646 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
2647 #define IOSTAT_CNT 0x11
2652 #define SLI1_SLIM_SIZE (4 * 1024)
2654 /* Up to 498 IOCBs will fit into 16k
2655 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
2657 #define SLI2_SLIM_SIZE (16 * 1024)
2659 /* Maximum IOCBs that will fit in SLI2 slim */
2660 #define MAX_SLI2_IOCB 498
2662 struct lpfc_sli2_slim {
2665 IOCB_t IOCBs[MAX_SLI2_IOCB];
2668 /*******************************************************************
2669 This macro check PCI device to allow special handling for LC HBAs.
2672 device : struct pci_dev 's device field
2676 *******************************************************************/
2678 lpfc_is_LC_HBA(unsigned short device)
2680 if ((device == PCI_DEVICE_ID_TFLY) ||
2681 (device == PCI_DEVICE_ID_PFLY) ||
2682 (device == PCI_DEVICE_ID_LP101) ||
2683 (device == PCI_DEVICE_ID_BMID) ||
2684 (device == PCI_DEVICE_ID_BSMB) ||
2685 (device == PCI_DEVICE_ID_ZMID) ||
2686 (device == PCI_DEVICE_ID_ZSMB) ||
2687 (device == PCI_DEVICE_ID_RFLY))