Merge branch 'fix/asoc' into for-linus
[linux-2.6] / arch / mips / kernel / cpu-probe.c
1 /*
2  * Processor capabilities determination functions.
3  *
4  * Copyright (C) xxxx  the Anonymous
5  * Copyright (C) 1994 - 2006 Ralf Baechle
6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
7  * Copyright (C) 2001, 2004  MIPS Inc.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License
11  * as published by the Free Software Foundation; either version
12  * 2 of the License, or (at your option) any later version.
13  */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/stddef.h>
18
19 #include <asm/bugs.h>
20 #include <asm/cpu.h>
21 #include <asm/fpu.h>
22 #include <asm/mipsregs.h>
23 #include <asm/system.h>
24 #include <asm/watch.h>
25
26 /*
27  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
28  * the implementation of the "wait" feature differs between CPU families. This
29  * points to the function that implements CPU specific wait.
30  * The wait instruction stops the pipeline and reduces the power consumption of
31  * the CPU very much.
32  */
33 void (*cpu_wait)(void) = NULL;
34
35 static void r3081_wait(void)
36 {
37         unsigned long cfg = read_c0_conf();
38         write_c0_conf(cfg | R30XX_CONF_HALT);
39 }
40
41 static void r39xx_wait(void)
42 {
43         local_irq_disable();
44         if (!need_resched())
45                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
46         local_irq_enable();
47 }
48
49 extern void r4k_wait(void);
50
51 /*
52  * This variant is preferable as it allows testing need_resched and going to
53  * sleep depending on the outcome atomically.  Unfortunately the "It is
54  * implementation-dependent whether the pipeline restarts when a non-enabled
55  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
56  * using this version a gamble.
57  */
58 void r4k_wait_irqoff(void)
59 {
60         local_irq_disable();
61         if (!need_resched())
62                 __asm__("       .set    push            \n"
63                         "       .set    mips3           \n"
64                         "       wait                    \n"
65                         "       .set    pop             \n");
66         local_irq_enable();
67         __asm__("       .globl __pastwait       \n"
68                 "__pastwait:                    \n");
69         return;
70 }
71
72 /*
73  * The RM7000 variant has to handle erratum 38.  The workaround is to not
74  * have any pending stores when the WAIT instruction is executed.
75  */
76 static void rm7k_wait_irqoff(void)
77 {
78         local_irq_disable();
79         if (!need_resched())
80                 __asm__(
81                 "       .set    push                                    \n"
82                 "       .set    mips3                                   \n"
83                 "       .set    noat                                    \n"
84                 "       mfc0    $1, $12                                 \n"
85                 "       sync                                            \n"
86                 "       mtc0    $1, $12         # stalls until W stage  \n"
87                 "       wait                                            \n"
88                 "       mtc0    $1, $12         # stalls until W stage  \n"
89                 "       .set    pop                                     \n");
90         local_irq_enable();
91 }
92
93 /* The Au1xxx wait is available only if using 32khz counter or
94  * external timer source, but specifically not CP0 Counter. */
95 int allow_au1k_wait;
96
97 static void au1k_wait(void)
98 {
99         if (!allow_au1k_wait)
100                 return;
101
102         /* using the wait instruction makes CP0 counter unusable */
103         __asm__("       .set    mips3                   \n"
104                 "       cache   0x14, 0(%0)             \n"
105                 "       cache   0x14, 32(%0)            \n"
106                 "       sync                            \n"
107                 "       nop                             \n"
108                 "       wait                            \n"
109                 "       nop                             \n"
110                 "       nop                             \n"
111                 "       nop                             \n"
112                 "       nop                             \n"
113                 "       .set    mips0                   \n"
114                 : : "r" (au1k_wait));
115 }
116
117 static int __initdata nowait = 0;
118
119 static int __init wait_disable(char *s)
120 {
121         nowait = 1;
122
123         return 1;
124 }
125
126 __setup("nowait", wait_disable);
127
128 void __init check_wait(void)
129 {
130         struct cpuinfo_mips *c = &current_cpu_data;
131
132         if (nowait) {
133                 printk("Wait instruction disabled.\n");
134                 return;
135         }
136
137         switch (c->cputype) {
138         case CPU_R3081:
139         case CPU_R3081E:
140                 cpu_wait = r3081_wait;
141                 break;
142         case CPU_TX3927:
143                 cpu_wait = r39xx_wait;
144                 break;
145         case CPU_R4200:
146 /*      case CPU_R4300: */
147         case CPU_R4600:
148         case CPU_R4640:
149         case CPU_R4650:
150         case CPU_R4700:
151         case CPU_R5000:
152         case CPU_R5500:
153         case CPU_NEVADA:
154         case CPU_4KC:
155         case CPU_4KEC:
156         case CPU_4KSC:
157         case CPU_5KC:
158         case CPU_25KF:
159         case CPU_PR4450:
160         case CPU_BCM3302:
161         case CPU_CAVIUM_OCTEON:
162                 cpu_wait = r4k_wait;
163                 break;
164
165         case CPU_RM7000:
166                 cpu_wait = rm7k_wait_irqoff;
167                 break;
168
169         case CPU_24K:
170         case CPU_34K:
171         case CPU_1004K:
172                 cpu_wait = r4k_wait;
173                 if (read_c0_config7() & MIPS_CONF7_WII)
174                         cpu_wait = r4k_wait_irqoff;
175                 break;
176
177         case CPU_74K:
178                 cpu_wait = r4k_wait;
179                 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
180                         cpu_wait = r4k_wait_irqoff;
181                 break;
182
183         case CPU_TX49XX:
184                 cpu_wait = r4k_wait_irqoff;
185                 break;
186         case CPU_ALCHEMY:
187                 cpu_wait = au1k_wait;
188                 break;
189         case CPU_20KC:
190                 /*
191                  * WAIT on Rev1.0 has E1, E2, E3 and E16.
192                  * WAIT on Rev2.0 and Rev3.0 has E16.
193                  * Rev3.1 WAIT is nop, why bother
194                  */
195                 if ((c->processor_id & 0xff) <= 0x64)
196                         break;
197
198                 /*
199                  * Another rev is incremeting c0_count at a reduced clock
200                  * rate while in WAIT mode.  So we basically have the choice
201                  * between using the cp0 timer as clocksource or avoiding
202                  * the WAIT instruction.  Until more details are known,
203                  * disable the use of WAIT for 20Kc entirely.
204                    cpu_wait = r4k_wait;
205                  */
206                 break;
207         case CPU_RM9000:
208                 if ((c->processor_id & 0x00ff) >= 0x40)
209                         cpu_wait = r4k_wait;
210                 break;
211         default:
212                 break;
213         }
214 }
215
216 static inline void check_errata(void)
217 {
218         struct cpuinfo_mips *c = &current_cpu_data;
219
220         switch (c->cputype) {
221         case CPU_34K:
222                 /*
223                  * Erratum "RPS May Cause Incorrect Instruction Execution"
224                  * This code only handles VPE0, any SMP/SMTC/RTOS code
225                  * making use of VPE1 will be responsable for that VPE.
226                  */
227                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
228                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
229                 break;
230         default:
231                 break;
232         }
233 }
234
235 void __init check_bugs32(void)
236 {
237         check_errata();
238 }
239
240 /*
241  * Probe whether cpu has config register by trying to play with
242  * alternate cache bit and see whether it matters.
243  * It's used by cpu_probe to distinguish between R3000A and R3081.
244  */
245 static inline int cpu_has_confreg(void)
246 {
247 #ifdef CONFIG_CPU_R3000
248         extern unsigned long r3k_cache_size(unsigned long);
249         unsigned long size1, size2;
250         unsigned long cfg = read_c0_conf();
251
252         size1 = r3k_cache_size(ST0_ISC);
253         write_c0_conf(cfg ^ R30XX_CONF_AC);
254         size2 = r3k_cache_size(ST0_ISC);
255         write_c0_conf(cfg);
256         return size1 != size2;
257 #else
258         return 0;
259 #endif
260 }
261
262 /*
263  * Get the FPU Implementation/Revision.
264  */
265 static inline unsigned long cpu_get_fpu_id(void)
266 {
267         unsigned long tmp, fpu_id;
268
269         tmp = read_c0_status();
270         __enable_fpu();
271         fpu_id = read_32bit_cp1_register(CP1_REVISION);
272         write_c0_status(tmp);
273         return fpu_id;
274 }
275
276 /*
277  * Check the CPU has an FPU the official way.
278  */
279 static inline int __cpu_has_fpu(void)
280 {
281         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
282 }
283
284 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
285                 | MIPS_CPU_COUNTER)
286
287 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
288 {
289         switch (c->processor_id & 0xff00) {
290         case PRID_IMP_R2000:
291                 c->cputype = CPU_R2000;
292                 __cpu_name[cpu] = "R2000";
293                 c->isa_level = MIPS_CPU_ISA_I;
294                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
295                              MIPS_CPU_NOFPUEX;
296                 if (__cpu_has_fpu())
297                         c->options |= MIPS_CPU_FPU;
298                 c->tlbsize = 64;
299                 break;
300         case PRID_IMP_R3000:
301                 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
302                         if (cpu_has_confreg()) {
303                                 c->cputype = CPU_R3081E;
304                                 __cpu_name[cpu] = "R3081";
305                         } else {
306                                 c->cputype = CPU_R3000A;
307                                 __cpu_name[cpu] = "R3000A";
308                         }
309                         break;
310                 } else {
311                         c->cputype = CPU_R3000;
312                         __cpu_name[cpu] = "R3000";
313                 }
314                 c->isa_level = MIPS_CPU_ISA_I;
315                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
316                              MIPS_CPU_NOFPUEX;
317                 if (__cpu_has_fpu())
318                         c->options |= MIPS_CPU_FPU;
319                 c->tlbsize = 64;
320                 break;
321         case PRID_IMP_R4000:
322                 if (read_c0_config() & CONF_SC) {
323                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
324                                 c->cputype = CPU_R4400PC;
325                                 __cpu_name[cpu] = "R4400PC";
326                         } else {
327                                 c->cputype = CPU_R4000PC;
328                                 __cpu_name[cpu] = "R4000PC";
329                         }
330                 } else {
331                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
332                                 c->cputype = CPU_R4400SC;
333                                 __cpu_name[cpu] = "R4400SC";
334                         } else {
335                                 c->cputype = CPU_R4000SC;
336                                 __cpu_name[cpu] = "R4000SC";
337                         }
338                 }
339
340                 c->isa_level = MIPS_CPU_ISA_III;
341                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
342                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
343                              MIPS_CPU_LLSC;
344                 c->tlbsize = 48;
345                 break;
346         case PRID_IMP_VR41XX:
347                 switch (c->processor_id & 0xf0) {
348                 case PRID_REV_VR4111:
349                         c->cputype = CPU_VR4111;
350                         __cpu_name[cpu] = "NEC VR4111";
351                         break;
352                 case PRID_REV_VR4121:
353                         c->cputype = CPU_VR4121;
354                         __cpu_name[cpu] = "NEC VR4121";
355                         break;
356                 case PRID_REV_VR4122:
357                         if ((c->processor_id & 0xf) < 0x3) {
358                                 c->cputype = CPU_VR4122;
359                                 __cpu_name[cpu] = "NEC VR4122";
360                         } else {
361                                 c->cputype = CPU_VR4181A;
362                                 __cpu_name[cpu] = "NEC VR4181A";
363                         }
364                         break;
365                 case PRID_REV_VR4130:
366                         if ((c->processor_id & 0xf) < 0x4) {
367                                 c->cputype = CPU_VR4131;
368                                 __cpu_name[cpu] = "NEC VR4131";
369                         } else {
370                                 c->cputype = CPU_VR4133;
371                                 __cpu_name[cpu] = "NEC VR4133";
372                         }
373                         break;
374                 default:
375                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
376                         c->cputype = CPU_VR41XX;
377                         __cpu_name[cpu] = "NEC Vr41xx";
378                         break;
379                 }
380                 c->isa_level = MIPS_CPU_ISA_III;
381                 c->options = R4K_OPTS;
382                 c->tlbsize = 32;
383                 break;
384         case PRID_IMP_R4300:
385                 c->cputype = CPU_R4300;
386                 __cpu_name[cpu] = "R4300";
387                 c->isa_level = MIPS_CPU_ISA_III;
388                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
389                              MIPS_CPU_LLSC;
390                 c->tlbsize = 32;
391                 break;
392         case PRID_IMP_R4600:
393                 c->cputype = CPU_R4600;
394                 __cpu_name[cpu] = "R4600";
395                 c->isa_level = MIPS_CPU_ISA_III;
396                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
397                              MIPS_CPU_LLSC;
398                 c->tlbsize = 48;
399                 break;
400         #if 0
401         case PRID_IMP_R4650:
402                 /*
403                  * This processor doesn't have an MMU, so it's not
404                  * "real easy" to run Linux on it. It is left purely
405                  * for documentation.  Commented out because it shares
406                  * it's c0_prid id number with the TX3900.
407                  */
408                 c->cputype = CPU_R4650;
409                 __cpu_name[cpu] = "R4650";
410                 c->isa_level = MIPS_CPU_ISA_III;
411                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
412                 c->tlbsize = 48;
413                 break;
414         #endif
415         case PRID_IMP_TX39:
416                 c->isa_level = MIPS_CPU_ISA_I;
417                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
418
419                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
420                         c->cputype = CPU_TX3927;
421                         __cpu_name[cpu] = "TX3927";
422                         c->tlbsize = 64;
423                 } else {
424                         switch (c->processor_id & 0xff) {
425                         case PRID_REV_TX3912:
426                                 c->cputype = CPU_TX3912;
427                                 __cpu_name[cpu] = "TX3912";
428                                 c->tlbsize = 32;
429                                 break;
430                         case PRID_REV_TX3922:
431                                 c->cputype = CPU_TX3922;
432                                 __cpu_name[cpu] = "TX3922";
433                                 c->tlbsize = 64;
434                                 break;
435                         }
436                 }
437                 break;
438         case PRID_IMP_R4700:
439                 c->cputype = CPU_R4700;
440                 __cpu_name[cpu] = "R4700";
441                 c->isa_level = MIPS_CPU_ISA_III;
442                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
443                              MIPS_CPU_LLSC;
444                 c->tlbsize = 48;
445                 break;
446         case PRID_IMP_TX49:
447                 c->cputype = CPU_TX49XX;
448                 __cpu_name[cpu] = "R49XX";
449                 c->isa_level = MIPS_CPU_ISA_III;
450                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
451                 if (!(c->processor_id & 0x08))
452                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
453                 c->tlbsize = 48;
454                 break;
455         case PRID_IMP_R5000:
456                 c->cputype = CPU_R5000;
457                 __cpu_name[cpu] = "R5000";
458                 c->isa_level = MIPS_CPU_ISA_IV;
459                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
460                              MIPS_CPU_LLSC;
461                 c->tlbsize = 48;
462                 break;
463         case PRID_IMP_R5432:
464                 c->cputype = CPU_R5432;
465                 __cpu_name[cpu] = "R5432";
466                 c->isa_level = MIPS_CPU_ISA_IV;
467                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
468                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
469                 c->tlbsize = 48;
470                 break;
471         case PRID_IMP_R5500:
472                 c->cputype = CPU_R5500;
473                 __cpu_name[cpu] = "R5500";
474                 c->isa_level = MIPS_CPU_ISA_IV;
475                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
476                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
477                 c->tlbsize = 48;
478                 break;
479         case PRID_IMP_NEVADA:
480                 c->cputype = CPU_NEVADA;
481                 __cpu_name[cpu] = "Nevada";
482                 c->isa_level = MIPS_CPU_ISA_IV;
483                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
484                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
485                 c->tlbsize = 48;
486                 break;
487         case PRID_IMP_R6000:
488                 c->cputype = CPU_R6000;
489                 __cpu_name[cpu] = "R6000";
490                 c->isa_level = MIPS_CPU_ISA_II;
491                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
492                              MIPS_CPU_LLSC;
493                 c->tlbsize = 32;
494                 break;
495         case PRID_IMP_R6000A:
496                 c->cputype = CPU_R6000A;
497                 __cpu_name[cpu] = "R6000A";
498                 c->isa_level = MIPS_CPU_ISA_II;
499                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
500                              MIPS_CPU_LLSC;
501                 c->tlbsize = 32;
502                 break;
503         case PRID_IMP_RM7000:
504                 c->cputype = CPU_RM7000;
505                 __cpu_name[cpu] = "RM7000";
506                 c->isa_level = MIPS_CPU_ISA_IV;
507                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
508                              MIPS_CPU_LLSC;
509                 /*
510                  * Undocumented RM7000:  Bit 29 in the info register of
511                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
512                  * entries.
513                  *
514                  * 29      1 =>    64 entry JTLB
515                  *         0 =>    48 entry JTLB
516                  */
517                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
518                 break;
519         case PRID_IMP_RM9000:
520                 c->cputype = CPU_RM9000;
521                 __cpu_name[cpu] = "RM9000";
522                 c->isa_level = MIPS_CPU_ISA_IV;
523                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
524                              MIPS_CPU_LLSC;
525                 /*
526                  * Bit 29 in the info register of the RM9000
527                  * indicates if the TLB has 48 or 64 entries.
528                  *
529                  * 29      1 =>    64 entry JTLB
530                  *         0 =>    48 entry JTLB
531                  */
532                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
533                 break;
534         case PRID_IMP_R8000:
535                 c->cputype = CPU_R8000;
536                 __cpu_name[cpu] = "RM8000";
537                 c->isa_level = MIPS_CPU_ISA_IV;
538                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
539                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
540                              MIPS_CPU_LLSC;
541                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
542                 break;
543         case PRID_IMP_R10000:
544                 c->cputype = CPU_R10000;
545                 __cpu_name[cpu] = "R10000";
546                 c->isa_level = MIPS_CPU_ISA_IV;
547                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
548                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
549                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
550                              MIPS_CPU_LLSC;
551                 c->tlbsize = 64;
552                 break;
553         case PRID_IMP_R12000:
554                 c->cputype = CPU_R12000;
555                 __cpu_name[cpu] = "R12000";
556                 c->isa_level = MIPS_CPU_ISA_IV;
557                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
558                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
559                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
560                              MIPS_CPU_LLSC;
561                 c->tlbsize = 64;
562                 break;
563         case PRID_IMP_R14000:
564                 c->cputype = CPU_R14000;
565                 __cpu_name[cpu] = "R14000";
566                 c->isa_level = MIPS_CPU_ISA_IV;
567                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
568                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
569                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
570                              MIPS_CPU_LLSC;
571                 c->tlbsize = 64;
572                 break;
573         case PRID_IMP_LOONGSON2:
574                 c->cputype = CPU_LOONGSON2;
575                 __cpu_name[cpu] = "ICT Loongson-2";
576                 c->isa_level = MIPS_CPU_ISA_III;
577                 c->options = R4K_OPTS |
578                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
579                              MIPS_CPU_32FPR;
580                 c->tlbsize = 64;
581                 break;
582         }
583 }
584
585 static char unknown_isa[] __cpuinitdata = KERN_ERR \
586         "Unsupported ISA type, c0.config0: %d.";
587
588 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
589 {
590         unsigned int config0;
591         int isa;
592
593         config0 = read_c0_config();
594
595         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
596                 c->options |= MIPS_CPU_TLB;
597         isa = (config0 & MIPS_CONF_AT) >> 13;
598         switch (isa) {
599         case 0:
600                 switch ((config0 & MIPS_CONF_AR) >> 10) {
601                 case 0:
602                         c->isa_level = MIPS_CPU_ISA_M32R1;
603                         break;
604                 case 1:
605                         c->isa_level = MIPS_CPU_ISA_M32R2;
606                         break;
607                 default:
608                         goto unknown;
609                 }
610                 break;
611         case 2:
612                 switch ((config0 & MIPS_CONF_AR) >> 10) {
613                 case 0:
614                         c->isa_level = MIPS_CPU_ISA_M64R1;
615                         break;
616                 case 1:
617                         c->isa_level = MIPS_CPU_ISA_M64R2;
618                         break;
619                 default:
620                         goto unknown;
621                 }
622                 break;
623         default:
624                 goto unknown;
625         }
626
627         return config0 & MIPS_CONF_M;
628
629 unknown:
630         panic(unknown_isa, config0);
631 }
632
633 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
634 {
635         unsigned int config1;
636
637         config1 = read_c0_config1();
638
639         if (config1 & MIPS_CONF1_MD)
640                 c->ases |= MIPS_ASE_MDMX;
641         if (config1 & MIPS_CONF1_WR)
642                 c->options |= MIPS_CPU_WATCH;
643         if (config1 & MIPS_CONF1_CA)
644                 c->ases |= MIPS_ASE_MIPS16;
645         if (config1 & MIPS_CONF1_EP)
646                 c->options |= MIPS_CPU_EJTAG;
647         if (config1 & MIPS_CONF1_FP) {
648                 c->options |= MIPS_CPU_FPU;
649                 c->options |= MIPS_CPU_32FPR;
650         }
651         if (cpu_has_tlb)
652                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
653
654         return config1 & MIPS_CONF_M;
655 }
656
657 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
658 {
659         unsigned int config2;
660
661         config2 = read_c0_config2();
662
663         if (config2 & MIPS_CONF2_SL)
664                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
665
666         return config2 & MIPS_CONF_M;
667 }
668
669 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
670 {
671         unsigned int config3;
672
673         config3 = read_c0_config3();
674
675         if (config3 & MIPS_CONF3_SM)
676                 c->ases |= MIPS_ASE_SMARTMIPS;
677         if (config3 & MIPS_CONF3_DSP)
678                 c->ases |= MIPS_ASE_DSP;
679         if (config3 & MIPS_CONF3_VINT)
680                 c->options |= MIPS_CPU_VINT;
681         if (config3 & MIPS_CONF3_VEIC)
682                 c->options |= MIPS_CPU_VEIC;
683         if (config3 & MIPS_CONF3_MT)
684                 c->ases |= MIPS_ASE_MIPSMT;
685         if (config3 & MIPS_CONF3_ULRI)
686                 c->options |= MIPS_CPU_ULRI;
687
688         return config3 & MIPS_CONF_M;
689 }
690
691 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
692 {
693         int ok;
694
695         /* MIPS32 or MIPS64 compliant CPU.  */
696         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
697                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
698
699         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
700
701         ok = decode_config0(c);                 /* Read Config registers.  */
702         BUG_ON(!ok);                            /* Arch spec violation!  */
703         if (ok)
704                 ok = decode_config1(c);
705         if (ok)
706                 ok = decode_config2(c);
707         if (ok)
708                 ok = decode_config3(c);
709
710         mips_probe_watch_registers(c);
711 }
712
713 #ifdef CONFIG_CPU_MIPSR2
714 extern void spram_config(void);
715 #else
716 static inline void spram_config(void) {}
717 #endif
718
719 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
720 {
721         decode_configs(c);
722         switch (c->processor_id & 0xff00) {
723         case PRID_IMP_4KC:
724                 c->cputype = CPU_4KC;
725                 __cpu_name[cpu] = "MIPS 4Kc";
726                 break;
727         case PRID_IMP_4KEC:
728                 c->cputype = CPU_4KEC;
729                 __cpu_name[cpu] = "MIPS 4KEc";
730                 break;
731         case PRID_IMP_4KECR2:
732                 c->cputype = CPU_4KEC;
733                 __cpu_name[cpu] = "MIPS 4KEc";
734                 break;
735         case PRID_IMP_4KSC:
736         case PRID_IMP_4KSD:
737                 c->cputype = CPU_4KSC;
738                 __cpu_name[cpu] = "MIPS 4KSc";
739                 break;
740         case PRID_IMP_5KC:
741                 c->cputype = CPU_5KC;
742                 __cpu_name[cpu] = "MIPS 5Kc";
743                 break;
744         case PRID_IMP_20KC:
745                 c->cputype = CPU_20KC;
746                 __cpu_name[cpu] = "MIPS 20Kc";
747                 break;
748         case PRID_IMP_24K:
749         case PRID_IMP_24KE:
750                 c->cputype = CPU_24K;
751                 __cpu_name[cpu] = "MIPS 24Kc";
752                 break;
753         case PRID_IMP_25KF:
754                 c->cputype = CPU_25KF;
755                 __cpu_name[cpu] = "MIPS 25Kc";
756                 break;
757         case PRID_IMP_34K:
758                 c->cputype = CPU_34K;
759                 __cpu_name[cpu] = "MIPS 34Kc";
760                 break;
761         case PRID_IMP_74K:
762                 c->cputype = CPU_74K;
763                 __cpu_name[cpu] = "MIPS 74Kc";
764                 break;
765         case PRID_IMP_1004K:
766                 c->cputype = CPU_1004K;
767                 __cpu_name[cpu] = "MIPS 1004Kc";
768                 break;
769         }
770
771         spram_config();
772 }
773
774 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
775 {
776         decode_configs(c);
777         switch (c->processor_id & 0xff00) {
778         case PRID_IMP_AU1_REV1:
779         case PRID_IMP_AU1_REV2:
780                 c->cputype = CPU_ALCHEMY;
781                 switch ((c->processor_id >> 24) & 0xff) {
782                 case 0:
783                         __cpu_name[cpu] = "Au1000";
784                         break;
785                 case 1:
786                         __cpu_name[cpu] = "Au1500";
787                         break;
788                 case 2:
789                         __cpu_name[cpu] = "Au1100";
790                         break;
791                 case 3:
792                         __cpu_name[cpu] = "Au1550";
793                         break;
794                 case 4:
795                         __cpu_name[cpu] = "Au1200";
796                         if ((c->processor_id & 0xff) == 2)
797                                 __cpu_name[cpu] = "Au1250";
798                         break;
799                 case 5:
800                         __cpu_name[cpu] = "Au1210";
801                         break;
802                 default:
803                         __cpu_name[cpu] = "Au1xxx";
804                         break;
805                 }
806                 break;
807         }
808 }
809
810 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
811 {
812         decode_configs(c);
813
814         switch (c->processor_id & 0xff00) {
815         case PRID_IMP_SB1:
816                 c->cputype = CPU_SB1;
817                 __cpu_name[cpu] = "SiByte SB1";
818                 /* FPU in pass1 is known to have issues. */
819                 if ((c->processor_id & 0xff) < 0x02)
820                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
821                 break;
822         case PRID_IMP_SB1A:
823                 c->cputype = CPU_SB1A;
824                 __cpu_name[cpu] = "SiByte SB1A";
825                 break;
826         }
827 }
828
829 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
830 {
831         decode_configs(c);
832         switch (c->processor_id & 0xff00) {
833         case PRID_IMP_SR71000:
834                 c->cputype = CPU_SR71000;
835                 __cpu_name[cpu] = "Sandcraft SR71000";
836                 c->scache.ways = 8;
837                 c->tlbsize = 64;
838                 break;
839         }
840 }
841
842 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
843 {
844         decode_configs(c);
845         switch (c->processor_id & 0xff00) {
846         case PRID_IMP_PR4450:
847                 c->cputype = CPU_PR4450;
848                 __cpu_name[cpu] = "Philips PR4450";
849                 c->isa_level = MIPS_CPU_ISA_M32R1;
850                 break;
851         }
852 }
853
854 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
855 {
856         decode_configs(c);
857         switch (c->processor_id & 0xff00) {
858         case PRID_IMP_BCM3302:
859                 c->cputype = CPU_BCM3302;
860                 __cpu_name[cpu] = "Broadcom BCM3302";
861                 break;
862         case PRID_IMP_BCM4710:
863                 c->cputype = CPU_BCM4710;
864                 __cpu_name[cpu] = "Broadcom BCM4710";
865                 break;
866         }
867 }
868
869 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
870 {
871         decode_configs(c);
872         switch (c->processor_id & 0xff00) {
873         case PRID_IMP_CAVIUM_CN38XX:
874         case PRID_IMP_CAVIUM_CN31XX:
875         case PRID_IMP_CAVIUM_CN30XX:
876         case PRID_IMP_CAVIUM_CN58XX:
877         case PRID_IMP_CAVIUM_CN56XX:
878         case PRID_IMP_CAVIUM_CN50XX:
879         case PRID_IMP_CAVIUM_CN52XX:
880                 c->cputype = CPU_CAVIUM_OCTEON;
881                 __cpu_name[cpu] = "Cavium Octeon";
882                 break;
883         default:
884                 printk(KERN_INFO "Unknown Octeon chip!\n");
885                 c->cputype = CPU_UNKNOWN;
886                 break;
887         }
888 }
889
890 const char *__cpu_name[NR_CPUS];
891
892 __cpuinit void cpu_probe(void)
893 {
894         struct cpuinfo_mips *c = &current_cpu_data;
895         unsigned int cpu = smp_processor_id();
896
897         c->processor_id = PRID_IMP_UNKNOWN;
898         c->fpu_id       = FPIR_IMP_NONE;
899         c->cputype      = CPU_UNKNOWN;
900
901         c->processor_id = read_c0_prid();
902         switch (c->processor_id & 0xff0000) {
903         case PRID_COMP_LEGACY:
904                 cpu_probe_legacy(c, cpu);
905                 break;
906         case PRID_COMP_MIPS:
907                 cpu_probe_mips(c, cpu);
908                 break;
909         case PRID_COMP_ALCHEMY:
910                 cpu_probe_alchemy(c, cpu);
911                 break;
912         case PRID_COMP_SIBYTE:
913                 cpu_probe_sibyte(c, cpu);
914                 break;
915         case PRID_COMP_BROADCOM:
916                 cpu_probe_broadcom(c, cpu);
917                 break;
918         case PRID_COMP_SANDCRAFT:
919                 cpu_probe_sandcraft(c, cpu);
920                 break;
921         case PRID_COMP_NXP:
922                 cpu_probe_nxp(c, cpu);
923                 break;
924         case PRID_COMP_CAVIUM:
925                 cpu_probe_cavium(c, cpu);
926                 break;
927         }
928
929         BUG_ON(!__cpu_name[cpu]);
930         BUG_ON(c->cputype == CPU_UNKNOWN);
931
932         /*
933          * Platform code can force the cpu type to optimize code
934          * generation. In that case be sure the cpu type is correctly
935          * manually setup otherwise it could trigger some nasty bugs.
936          */
937         BUG_ON(current_cpu_type() != c->cputype);
938
939         if (c->options & MIPS_CPU_FPU) {
940                 c->fpu_id = cpu_get_fpu_id();
941
942                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
943                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
944                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
945                     c->isa_level == MIPS_CPU_ISA_M64R2) {
946                         if (c->fpu_id & MIPS_FPIR_3D)
947                                 c->ases |= MIPS_ASE_MIPS3D;
948                 }
949         }
950
951         if (cpu_has_mips_r2)
952                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
953         else
954                 c->srsets = 1;
955 }
956
957 __cpuinit void cpu_report(void)
958 {
959         struct cpuinfo_mips *c = &current_cpu_data;
960
961         printk(KERN_INFO "CPU revision is: %08x (%s)\n",
962                c->processor_id, cpu_name_string());
963         if (c->options & MIPS_CPU_FPU)
964                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
965 }