Merge with /pub/scm/linux/kernel/git/torvalds/linux-2.6.git
[linux-2.6] / arch / powerpc / platforms / powermac / smp.c
1 /*
2  * SMP support for power macintosh.
3  *
4  * We support both the old "powersurge" SMP architecture
5  * and the current Core99 (G4 PowerMac) machines.
6  *
7  * Note that we don't support the very first rev. of
8  * Apple/DayStar 2 CPUs board, the one with the funky
9  * watchdog. Hopefully, none of these should be there except
10  * maybe internally to Apple. I should probably still add some
11  * code to detect this card though and disable SMP. --BenH.
12  *
13  * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
14  * and Ben Herrenschmidt <benh@kernel.crashing.org>.
15  *
16  * Support for DayStar quad CPU cards
17  * Copyright (C) XLR8, Inc. 1994-2000
18  *
19  *  This program is free software; you can redistribute it and/or
20  *  modify it under the terms of the GNU General Public License
21  *  as published by the Free Software Foundation; either version
22  *  2 of the License, or (at your option) any later version.
23  */
24 #include <linux/config.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/smp.h>
28 #include <linux/smp_lock.h>
29 #include <linux/interrupt.h>
30 #include <linux/kernel_stat.h>
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/spinlock.h>
34 #include <linux/errno.h>
35 #include <linux/hardirq.h>
36 #include <linux/cpu.h>
37 #include <linux/compiler.h>
38
39 #include <asm/ptrace.h>
40 #include <asm/atomic.h>
41 #include <asm/irq.h>
42 #include <asm/page.h>
43 #include <asm/pgtable.h>
44 #include <asm/sections.h>
45 #include <asm/io.h>
46 #include <asm/prom.h>
47 #include <asm/smp.h>
48 #include <asm/machdep.h>
49 #include <asm/pmac_feature.h>
50 #include <asm/time.h>
51 #include <asm/mpic.h>
52 #include <asm/cacheflush.h>
53 #include <asm/keylargo.h>
54 #include <asm/pmac_low_i2c.h>
55
56 #undef DEBUG
57
58 #ifdef DEBUG
59 #define DBG(fmt...) udbg_printf(fmt)
60 #else
61 #define DBG(fmt...)
62 #endif
63
64 extern void __secondary_start_pmac_0(void);
65
66 #ifdef CONFIG_PPC32
67
68 /* Sync flag for HW tb sync */
69 static volatile int sec_tb_reset = 0;
70
71 /*
72  * Powersurge (old powermac SMP) support.
73  */
74
75 /* Addresses for powersurge registers */
76 #define HAMMERHEAD_BASE         0xf8000000
77 #define HHEAD_CONFIG            0x90
78 #define HHEAD_SEC_INTR          0xc0
79
80 /* register for interrupting the primary processor on the powersurge */
81 /* N.B. this is actually the ethernet ROM! */
82 #define PSURGE_PRI_INTR         0xf3019000
83
84 /* register for storing the start address for the secondary processor */
85 /* N.B. this is the PCI config space address register for the 1st bridge */
86 #define PSURGE_START            0xf2800000
87
88 /* Daystar/XLR8 4-CPU card */
89 #define PSURGE_QUAD_REG_ADDR    0xf8800000
90
91 #define PSURGE_QUAD_IRQ_SET     0
92 #define PSURGE_QUAD_IRQ_CLR     1
93 #define PSURGE_QUAD_IRQ_PRIMARY 2
94 #define PSURGE_QUAD_CKSTOP_CTL  3
95 #define PSURGE_QUAD_PRIMARY_ARB 4
96 #define PSURGE_QUAD_BOARD_ID    6
97 #define PSURGE_QUAD_WHICH_CPU   7
98 #define PSURGE_QUAD_CKSTOP_RDBK 8
99 #define PSURGE_QUAD_RESET_CTL   11
100
101 #define PSURGE_QUAD_OUT(r, v)   (out_8(quad_base + ((r) << 4) + 4, (v)))
102 #define PSURGE_QUAD_IN(r)       (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
103 #define PSURGE_QUAD_BIS(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
104 #define PSURGE_QUAD_BIC(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
105
106 /* virtual addresses for the above */
107 static volatile u8 __iomem *hhead_base;
108 static volatile u8 __iomem *quad_base;
109 static volatile u32 __iomem *psurge_pri_intr;
110 static volatile u8 __iomem *psurge_sec_intr;
111 static volatile u32 __iomem *psurge_start;
112
113 /* values for psurge_type */
114 #define PSURGE_NONE             -1
115 #define PSURGE_DUAL             0
116 #define PSURGE_QUAD_OKEE        1
117 #define PSURGE_QUAD_COTTON      2
118 #define PSURGE_QUAD_ICEGRASS    3
119
120 /* what sort of powersurge board we have */
121 static int psurge_type = PSURGE_NONE;
122
123 /*
124  * Set and clear IPIs for powersurge.
125  */
126 static inline void psurge_set_ipi(int cpu)
127 {
128         if (psurge_type == PSURGE_NONE)
129                 return;
130         if (cpu == 0)
131                 in_be32(psurge_pri_intr);
132         else if (psurge_type == PSURGE_DUAL)
133                 out_8(psurge_sec_intr, 0);
134         else
135                 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu);
136 }
137
138 static inline void psurge_clr_ipi(int cpu)
139 {
140         if (cpu > 0) {
141                 switch(psurge_type) {
142                 case PSURGE_DUAL:
143                         out_8(psurge_sec_intr, ~0);
144                 case PSURGE_NONE:
145                         break;
146                 default:
147                         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu);
148                 }
149         }
150 }
151
152 /*
153  * On powersurge (old SMP powermac architecture) we don't have
154  * separate IPIs for separate messages like openpic does.  Instead
155  * we have a bitmap for each processor, where a 1 bit means that
156  * the corresponding message is pending for that processor.
157  * Ideally each cpu's entry would be in a different cache line.
158  *  -- paulus.
159  */
160 static unsigned long psurge_smp_message[NR_CPUS];
161
162 void psurge_smp_message_recv(struct pt_regs *regs)
163 {
164         int cpu = smp_processor_id();
165         int msg;
166
167         /* clear interrupt */
168         psurge_clr_ipi(cpu);
169
170         if (num_online_cpus() < 2)
171                 return;
172
173         /* make sure there is a message there */
174         for (msg = 0; msg < 4; msg++)
175                 if (test_and_clear_bit(msg, &psurge_smp_message[cpu]))
176                         smp_message_recv(msg, regs);
177 }
178
179 irqreturn_t psurge_primary_intr(int irq, void *d, struct pt_regs *regs)
180 {
181         psurge_smp_message_recv(regs);
182         return IRQ_HANDLED;
183 }
184
185 static void smp_psurge_message_pass(int target, int msg)
186 {
187         int i;
188
189         if (num_online_cpus() < 2)
190                 return;
191
192         for (i = 0; i < NR_CPUS; i++) {
193                 if (!cpu_online(i))
194                         continue;
195                 if (target == MSG_ALL
196                     || (target == MSG_ALL_BUT_SELF && i != smp_processor_id())
197                     || target == i) {
198                         set_bit(msg, &psurge_smp_message[i]);
199                         psurge_set_ipi(i);
200                 }
201         }
202 }
203
204 /*
205  * Determine a quad card presence. We read the board ID register, we
206  * force the data bus to change to something else, and we read it again.
207  * It it's stable, then the register probably exist (ugh !)
208  */
209 static int __init psurge_quad_probe(void)
210 {
211         int type;
212         unsigned int i;
213
214         type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID);
215         if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS
216             || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
217                 return PSURGE_DUAL;
218
219         /* looks OK, try a slightly more rigorous test */
220         /* bogus is not necessarily cacheline-aligned,
221            though I don't suppose that really matters.  -- paulus */
222         for (i = 0; i < 100; i++) {
223                 volatile u32 bogus[8];
224                 bogus[(0+i)%8] = 0x00000000;
225                 bogus[(1+i)%8] = 0x55555555;
226                 bogus[(2+i)%8] = 0xFFFFFFFF;
227                 bogus[(3+i)%8] = 0xAAAAAAAA;
228                 bogus[(4+i)%8] = 0x33333333;
229                 bogus[(5+i)%8] = 0xCCCCCCCC;
230                 bogus[(6+i)%8] = 0xCCCCCCCC;
231                 bogus[(7+i)%8] = 0x33333333;
232                 wmb();
233                 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");
234                 mb();
235                 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
236                         return PSURGE_DUAL;
237         }
238         return type;
239 }
240
241 static void __init psurge_quad_init(void)
242 {
243         int procbits;
244
245         if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);
246         procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU);
247         if (psurge_type == PSURGE_QUAD_ICEGRASS)
248                 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
249         else
250                 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits);
251         mdelay(33);
252         out_8(psurge_sec_intr, ~0);
253         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits);
254         PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
255         if (psurge_type != PSURGE_QUAD_ICEGRASS)
256                 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits);
257         PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits);
258         mdelay(33);
259         PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits);
260         mdelay(33);
261         PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits);
262         mdelay(33);
263 }
264
265 static int __init smp_psurge_probe(void)
266 {
267         int i, ncpus;
268
269         /* We don't do SMP on the PPC601 -- paulus */
270         if (PVR_VER(mfspr(SPRN_PVR)) == 1)
271                 return 1;
272
273         /*
274          * The powersurge cpu board can be used in the generation
275          * of powermacs that have a socket for an upgradeable cpu card,
276          * including the 7500, 8500, 9500, 9600.
277          * The device tree doesn't tell you if you have 2 cpus because
278          * OF doesn't know anything about the 2nd processor.
279          * Instead we look for magic bits in magic registers,
280          * in the hammerhead memory controller in the case of the
281          * dual-cpu powersurge board.  -- paulus.
282          */
283         if (find_devices("hammerhead") == NULL)
284                 return 1;
285
286         hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
287         quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
288         psurge_sec_intr = hhead_base + HHEAD_SEC_INTR;
289
290         psurge_type = psurge_quad_probe();
291         if (psurge_type != PSURGE_DUAL) {
292                 psurge_quad_init();
293                 /* All released cards using this HW design have 4 CPUs */
294                 ncpus = 4;
295         } else {
296                 iounmap(quad_base);
297                 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
298                         /* not a dual-cpu card */
299                         iounmap(hhead_base);
300                         psurge_type = PSURGE_NONE;
301                         return 1;
302                 }
303                 ncpus = 2;
304         }
305
306         psurge_start = ioremap(PSURGE_START, 4);
307         psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
308
309         /*
310          * This is necessary because OF doesn't know about the
311          * secondary cpu(s), and thus there aren't nodes in the
312          * device tree for them, and smp_setup_cpu_maps hasn't
313          * set their bits in cpu_possible_map and cpu_present_map.
314          */
315         if (ncpus > NR_CPUS)
316                 ncpus = NR_CPUS;
317         for (i = 1; i < ncpus ; ++i) {
318                 cpu_set(i, cpu_present_map);
319                 cpu_set(i, cpu_possible_map);
320                 set_hard_smp_processor_id(i, i);
321         }
322
323         if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
324
325         return ncpus;
326 }
327
328 static void __init smp_psurge_kick_cpu(int nr)
329 {
330         unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8;
331         unsigned long a;
332
333         /* may need to flush here if secondary bats aren't setup */
334         for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
335                 asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
336         asm volatile("sync");
337
338         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
339
340         out_be32(psurge_start, start);
341         mb();
342
343         psurge_set_ipi(nr);
344         udelay(10);
345         psurge_clr_ipi(nr);
346
347         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
348 }
349
350 /*
351  * With the dual-cpu powersurge board, the decrementers and timebases
352  * of both cpus are frozen after the secondary cpu is started up,
353  * until we give the secondary cpu another interrupt.  This routine
354  * uses this to get the timebases synchronized.
355  *  -- paulus.
356  */
357 static void __init psurge_dual_sync_tb(int cpu_nr)
358 {
359         int t;
360
361         set_dec(tb_ticks_per_jiffy);
362         /* XXX fixme */
363         set_tb(0, 0);
364         last_jiffy_stamp(cpu_nr) = 0;
365
366         if (cpu_nr > 0) {
367                 mb();
368                 sec_tb_reset = 1;
369                 return;
370         }
371
372         /* wait for the secondary to have reset its TB before proceeding */
373         for (t = 10000000; t > 0 && !sec_tb_reset; --t)
374                 ;
375
376         /* now interrupt the secondary, starting both TBs */
377         psurge_set_ipi(1);
378 }
379
380 static struct irqaction psurge_irqaction = {
381         .handler = psurge_primary_intr,
382         .flags = SA_INTERRUPT,
383         .mask = CPU_MASK_NONE,
384         .name = "primary IPI",
385 };
386
387 static void __init smp_psurge_setup_cpu(int cpu_nr)
388 {
389
390         if (cpu_nr == 0) {
391                 /* If we failed to start the second CPU, we should still
392                  * send it an IPI to start the timebase & DEC or we might
393                  * have them stuck.
394                  */
395                 if (num_online_cpus() < 2) {
396                         if (psurge_type == PSURGE_DUAL)
397                                 psurge_set_ipi(1);
398                         return;
399                 }
400                 /* reset the entry point so if we get another intr we won't
401                  * try to startup again */
402                 out_be32(psurge_start, 0x100);
403                 if (setup_irq(30, &psurge_irqaction))
404                         printk(KERN_ERR "Couldn't get primary IPI interrupt");
405         }
406
407         if (psurge_type == PSURGE_DUAL)
408                 psurge_dual_sync_tb(cpu_nr);
409 }
410
411 void __init smp_psurge_take_timebase(void)
412 {
413         /* Dummy implementation */
414 }
415
416 void __init smp_psurge_give_timebase(void)
417 {
418         /* Dummy implementation */
419 }
420
421 /* PowerSurge-style Macs */
422 struct smp_ops_t psurge_smp_ops = {
423         .message_pass   = smp_psurge_message_pass,
424         .probe          = smp_psurge_probe,
425         .kick_cpu       = smp_psurge_kick_cpu,
426         .setup_cpu      = smp_psurge_setup_cpu,
427         .give_timebase  = smp_psurge_give_timebase,
428         .take_timebase  = smp_psurge_take_timebase,
429 };
430 #endif /* CONFIG_PPC32 - actually powersurge support */
431
432 #ifdef CONFIG_PPC64
433 /*
434  * G5s enable/disable the timebase via an i2c-connected clock chip.
435  */
436 static struct device_node *pmac_tb_clock_chip_host;
437 static u8 pmac_tb_pulsar_addr;
438 static void (*pmac_tb_freeze)(int freeze);
439 static DEFINE_SPINLOCK(timebase_lock);
440 static unsigned long timebase;
441
442 static void smp_core99_cypress_tb_freeze(int freeze)
443 {
444         u8 data;
445         int rc;
446
447         /* Strangely, the device-tree says address is 0xd2, but darwin
448          * accesses 0xd0 ...
449          */
450         pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_combined);
451         rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
452                                0xd0 | pmac_low_i2c_read,
453                                0x81, &data, 1);
454         if (rc != 0)
455                 goto bail;
456
457         data = (data & 0xf3) | (freeze ? 0x00 : 0x0c);
458
459         pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_stdsub);
460         rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
461                                0xd0 | pmac_low_i2c_write,
462                                0x81, &data, 1);
463
464  bail:
465         if (rc != 0) {
466                 printk("Cypress Timebase %s rc: %d\n",
467                        freeze ? "freeze" : "unfreeze", rc);
468                 panic("Timebase freeze failed !\n");
469         }
470 }
471
472
473 static void smp_core99_pulsar_tb_freeze(int freeze)
474 {
475         u8 data;
476         int rc;
477
478         pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_combined);
479         rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
480                                pmac_tb_pulsar_addr | pmac_low_i2c_read,
481                                0x2e, &data, 1);
482         if (rc != 0)
483                 goto bail;
484
485         data = (data & 0x88) | (freeze ? 0x11 : 0x22);
486
487         pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_stdsub);
488         rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
489                                pmac_tb_pulsar_addr | pmac_low_i2c_write,
490                                0x2e, &data, 1);
491  bail:
492         if (rc != 0) {
493                 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n",
494                        freeze ? "freeze" : "unfreeze", rc);
495                 panic("Timebase freeze failed !\n");
496         }
497 }
498
499
500 static void smp_core99_give_timebase(void)
501 {
502         /* Open i2c bus for synchronous access */
503         if (pmac_low_i2c_open(pmac_tb_clock_chip_host, 0))
504                 panic("Can't open i2c for TB sync !\n");
505
506         spin_lock(&timebase_lock);
507         (*pmac_tb_freeze)(1);
508         mb();
509         timebase = get_tb();
510         spin_unlock(&timebase_lock);
511
512         while (timebase)
513                 barrier();
514
515         spin_lock(&timebase_lock);
516         (*pmac_tb_freeze)(0);
517         spin_unlock(&timebase_lock);
518
519         /* Close i2c bus */
520         pmac_low_i2c_close(pmac_tb_clock_chip_host);
521 }
522
523
524 static void __devinit smp_core99_take_timebase(void)
525 {
526         while (!timebase)
527                 barrier();
528         spin_lock(&timebase_lock);
529         set_tb(timebase >> 32, timebase & 0xffffffff);
530         timebase = 0;
531         spin_unlock(&timebase_lock);
532 }
533
534 static void __init smp_core99_setup(int ncpus)
535 {
536         struct device_node *cc = NULL;  
537         struct device_node *p;
538         u32 *reg;
539         int ok;
540
541         /* HW sync only on these platforms */
542         if (!machine_is_compatible("PowerMac7,2") &&
543             !machine_is_compatible("PowerMac7,3") &&
544             !machine_is_compatible("RackMac3,1"))
545                 return;
546
547         /* Look for the clock chip */
548         while ((cc = of_find_node_by_name(cc, "i2c-hwclock")) != NULL) {
549                 p = of_get_parent(cc);
550                 ok = p && device_is_compatible(p, "uni-n-i2c");
551                 of_node_put(p);
552                 if (!ok)
553                         continue;
554
555                 reg = (u32 *)get_property(cc, "reg", NULL);
556                 if (reg == NULL)
557                         continue;
558
559                 switch (*reg) {
560                 case 0xd2:
561                         if (device_is_compatible(cc, "pulsar-legacy-slewing")) {
562                                 pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
563                                 pmac_tb_pulsar_addr = 0xd2;
564                                 printk(KERN_INFO "Timebase clock is Pulsar chip\n");
565                         } else if (device_is_compatible(cc, "cy28508")) {
566                                 pmac_tb_freeze = smp_core99_cypress_tb_freeze;
567                                 printk(KERN_INFO "Timebase clock is Cypress chip\n");
568                         }
569                         break;
570                 case 0xd4:
571                         pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
572                         pmac_tb_pulsar_addr = 0xd4;
573                         printk(KERN_INFO "Timebase clock is Pulsar chip\n");
574                         break;
575                 }
576                 if (pmac_tb_freeze != NULL) {
577                         pmac_tb_clock_chip_host = of_get_parent(cc);
578                         of_node_put(cc);
579                         break;
580                 }
581         }
582         if (pmac_tb_freeze == NULL) {
583                 smp_ops->give_timebase = smp_generic_give_timebase;
584                 smp_ops->take_timebase = smp_generic_take_timebase;
585         }
586 }
587
588 /* nothing to do here, caches are already set up by service processor */
589 static inline void __devinit core99_init_caches(int cpu)
590 {
591 }
592
593 #else /* CONFIG_PPC64 */
594
595 /*
596  * SMP G4 powermacs use a GPIO to enable/disable the timebase.
597  */
598
599 static unsigned int core99_tb_gpio;     /* Timebase freeze GPIO */
600
601 static unsigned int pri_tb_hi, pri_tb_lo;
602 static unsigned int pri_tb_stamp;
603
604 /* not __init, called in sleep/wakeup code */
605 void smp_core99_give_timebase(void)
606 {
607         unsigned long flags;
608         unsigned int t;
609
610         /* wait for the secondary to be in take_timebase */
611         for (t = 100000; t > 0 && !sec_tb_reset; --t)
612                 udelay(10);
613         if (!sec_tb_reset) {
614                 printk(KERN_WARNING "Timeout waiting sync on second CPU\n");
615                 return;
616         }
617
618         /* freeze the timebase and read it */
619         /* disable interrupts so the timebase is disabled for the
620            shortest possible time */
621         local_irq_save(flags);
622         pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4);
623         pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
624         mb();
625         pri_tb_hi = get_tbu();
626         pri_tb_lo = get_tbl();
627         pri_tb_stamp = last_jiffy_stamp(smp_processor_id());
628         mb();
629
630         /* tell the secondary we're ready */
631         sec_tb_reset = 2;
632         mb();
633
634         /* wait for the secondary to have taken it */
635         /* note: can't use udelay here, since it needs the timebase running */
636         for (t = 10000000; t > 0 && sec_tb_reset; --t)
637                 barrier();
638         if (sec_tb_reset)
639                 /* XXX BUG_ON here? */
640                 printk(KERN_WARNING "Timeout waiting sync(2) on second CPU\n");
641
642         /* Now, restart the timebase by leaving the GPIO to an open collector */
643         pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0);
644         pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
645         local_irq_restore(flags);
646 }
647
648 /* not __init, called in sleep/wakeup code */
649 void smp_core99_take_timebase(void)
650 {
651         unsigned long flags;
652
653         /* tell the primary we're here */
654         sec_tb_reset = 1;
655         mb();
656
657         /* wait for the primary to set pri_tb_hi/lo */
658         while (sec_tb_reset < 2)
659                 mb();
660
661         /* set our stuff the same as the primary */
662         local_irq_save(flags);
663         set_dec(1);
664         set_tb(pri_tb_hi, pri_tb_lo);
665         last_jiffy_stamp(smp_processor_id()) = pri_tb_stamp;
666         mb();
667
668         /* tell the primary we're done */
669         sec_tb_reset = 0;
670         mb();
671         local_irq_restore(flags);
672 }
673
674 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
675 volatile static long int core99_l2_cache;
676 volatile static long int core99_l3_cache;
677
678 static void __devinit core99_init_caches(int cpu)
679 {
680         if (!cpu_has_feature(CPU_FTR_L2CR))
681                 return;
682
683         if (cpu == 0) {
684                 core99_l2_cache = _get_L2CR();
685                 printk("CPU0: L2CR is %lx\n", core99_l2_cache);
686         } else {
687                 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR());
688                 _set_L2CR(0);
689                 _set_L2CR(core99_l2_cache);
690                 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache);
691         }
692
693         if (!cpu_has_feature(CPU_FTR_L3CR))
694                 return;
695
696         if (cpu == 0){
697                 core99_l3_cache = _get_L3CR();
698                 printk("CPU0: L3CR is %lx\n", core99_l3_cache);
699         } else {
700                 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
701                 _set_L3CR(0);
702                 _set_L3CR(core99_l3_cache);
703                 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache);
704         }
705 }
706
707 static void __init smp_core99_setup(int ncpus)
708 {
709         struct device_node *cpu;
710         u32 *tbprop = NULL;
711         int i;
712
713         core99_tb_gpio = KL_GPIO_TB_ENABLE;     /* default value */
714         cpu = of_find_node_by_type(NULL, "cpu");
715         if (cpu != NULL) {
716                 tbprop = (u32 *)get_property(cpu, "timebase-enable", NULL);
717                 if (tbprop)
718                         core99_tb_gpio = *tbprop;
719                 of_node_put(cpu);
720         }
721
722         /* XXX should get this from reg properties */
723         for (i = 1; i < ncpus; ++i)
724                 smp_hw_index[i] = i;
725         powersave_nap = 0;
726 }
727 #endif
728
729 static int __init smp_core99_probe(void)
730 {
731         struct device_node *cpus;
732         int ncpus = 0;
733
734         if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
735
736         /* Count CPUs in the device-tree */
737         for (cpus = NULL; (cpus = of_find_node_by_type(cpus, "cpu")) != NULL;)
738                 ++ncpus;
739
740         printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus);
741
742         /* Nothing more to do if less than 2 of them */
743         if (ncpus <= 1)
744                 return 1;
745
746         smp_core99_setup(ncpus);
747         mpic_request_ipis();
748         core99_init_caches(0);
749
750         return ncpus;
751 }
752
753 static void __devinit smp_core99_kick_cpu(int nr)
754 {
755         unsigned int save_vector;
756         unsigned long new_vector;
757         unsigned long flags;
758         volatile unsigned int *vector
759                  = ((volatile unsigned int *)(KERNELBASE+0x100));
760
761         if (nr < 0 || nr > 3)
762                 return;
763         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu", 0x346);
764
765         local_irq_save(flags);
766         local_irq_disable();
767
768         /* Save reset vector */
769         save_vector = *vector;
770
771         /* Setup fake reset vector that does    
772          *   b __secondary_start_pmac_0 + nr*8 - KERNELBASE
773          */
774         new_vector = (unsigned long) __secondary_start_pmac_0 + nr * 8;
775         *vector = 0x48000002 + new_vector - KERNELBASE;
776
777         /* flush data cache and inval instruction cache */
778         flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
779
780         /* Put some life in our friend */
781         pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
782
783         /* FIXME: We wait a bit for the CPU to take the exception, I should
784          * instead wait for the entry code to set something for me. Well,
785          * ideally, all that crap will be done in prom.c and the CPU left
786          * in a RAM-based wait loop like CHRP.
787          */
788         mdelay(1);
789
790         /* Restore our exception vector */
791         *vector = save_vector;
792         flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
793
794         local_irq_restore(flags);
795         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
796 }
797
798 static void __devinit smp_core99_setup_cpu(int cpu_nr)
799 {
800         /* Setup L2/L3 */
801         if (cpu_nr != 0)
802                 core99_init_caches(cpu_nr);
803
804         /* Setup openpic */
805         mpic_setup_this_cpu();
806
807         if (cpu_nr == 0) {
808 #ifdef CONFIG_POWER4
809                 extern void g5_phy_disable_cpu1(void);
810
811                 /* If we didn't start the second CPU, we must take
812                  * it off the bus
813                  */
814                 if (machine_is_compatible("MacRISC4") &&
815                     num_online_cpus() < 2)              
816                         g5_phy_disable_cpu1();
817 #endif /* CONFIG_POWER4 */
818                 if (ppc_md.progress) ppc_md.progress("core99_setup_cpu 0 done", 0x349);
819         }
820 }
821
822
823 #if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32)
824
825 int smp_core99_cpu_disable(void)
826 {
827         cpu_clear(smp_processor_id(), cpu_online_map);
828
829         /* XXX reset cpu affinity here */
830         mpic_cpu_set_priority(0xf);
831         asm volatile("mtdec %0" : : "r" (0x7fffffff));
832         mb();
833         udelay(20);
834         asm volatile("mtdec %0" : : "r" (0x7fffffff));
835         return 0;
836 }
837
838 extern void low_cpu_die(void) __attribute__((noreturn)); /* in sleep.S */
839 static int cpu_dead[NR_CPUS];
840
841 void cpu_die(void)
842 {
843         local_irq_disable();
844         cpu_dead[smp_processor_id()] = 1;
845         mb();
846         low_cpu_die();
847 }
848
849 void smp_core99_cpu_die(unsigned int cpu)
850 {
851         int timeout;
852
853         timeout = 1000;
854         while (!cpu_dead[cpu]) {
855                 if (--timeout == 0) {
856                         printk("CPU %u refused to die!\n", cpu);
857                         break;
858                 }
859                 msleep(1);
860         }
861         cpu_dead[cpu] = 0;
862 }
863
864 #endif
865
866 /* Core99 Macs (dual G4s and G5s) */
867 struct smp_ops_t core99_smp_ops = {
868         .message_pass   = smp_mpic_message_pass,
869         .probe          = smp_core99_probe,
870         .kick_cpu       = smp_core99_kick_cpu,
871         .setup_cpu      = smp_core99_setup_cpu,
872         .give_timebase  = smp_core99_give_timebase,
873         .take_timebase  = smp_core99_take_timebase,
874 #if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32)
875         .cpu_disable    = smp_core99_cpu_disable,
876         .cpu_die        = smp_core99_cpu_die,
877 #endif
878 };