1 /* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */
3 Written/copyright 1999-2001 by Donald Becker.
4 Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com)
5 Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com)
6 Portions copyright 2004 Harald Welte <laforge@gnumonks.org>
8 This software may be used and distributed according to the terms of
9 the GNU General Public License (GPL), incorporated herein by reference.
10 Drivers based on or derived from this code fall under the GPL and must
11 retain the authorship, copyright and license notice. This file is not
12 a complete program and may only be used when the entire operating
13 system is licensed under the GPL. License for under other terms may be
14 available. Contact the original author for details.
16 The original author may be reached as becker@scyld.com, or at
17 Scyld Computing Corporation
18 410 Severn Ave., Suite 210
21 Support information and updates available at
22 http://www.scyld.com/network/netsemi.html
23 [link no longer provides useful info -jgarzik]
27 * big endian support with CFG:BEM instead of cpu_to_le32
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/string.h>
33 #include <linux/timer.h>
34 #include <linux/errno.h>
35 #include <linux/ioport.h>
36 #include <linux/slab.h>
37 #include <linux/interrupt.h>
38 #include <linux/pci.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
41 #include <linux/skbuff.h>
42 #include <linux/init.h>
43 #include <linux/spinlock.h>
44 #include <linux/ethtool.h>
45 #include <linux/delay.h>
46 #include <linux/rtnetlink.h>
47 #include <linux/mii.h>
48 #include <linux/crc32.h>
49 #include <linux/bitops.h>
50 #include <linux/prefetch.h>
51 #include <asm/processor.h> /* Processor type for cache alignment. */
54 #include <asm/uaccess.h>
56 #define DRV_NAME "natsemi"
57 #define DRV_VERSION "2.1"
58 #define DRV_RELDATE "Sept 11, 2006"
62 /* Updated to recommendations in pci-skeleton v2.03. */
64 /* The user-configurable values.
65 These may be modified when a driver module is loaded.*/
67 #define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \
72 static int debug = -1;
76 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
77 This chip uses a 512 element hash table based on the Ethernet CRC. */
78 static const int multicast_filter_limit = 100;
80 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
81 Setting to > 1518 effectively disables this feature. */
82 static int rx_copybreak;
84 static int dspcfg_workaround = 1;
86 /* Used to pass the media type, etc.
87 Both 'options[]' and 'full_duplex[]' should exist for driver
89 The media type is usually passed in 'options[]'.
91 #define MAX_UNITS 8 /* More are supported, limit only on options */
92 static int options[MAX_UNITS];
93 static int full_duplex[MAX_UNITS];
95 /* Operational parameters that are set at compile time. */
97 /* Keep the ring sizes a power of two for compile efficiency.
98 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
99 Making the Tx ring too large decreases the effectiveness of channel
100 bonding and packet priority.
101 There are no ill effects from too-large receive rings. */
102 #define TX_RING_SIZE 16
103 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
104 #define RX_RING_SIZE 32
106 /* Operational parameters that usually are not changed. */
107 /* Time in jiffies before concluding the transmitter is hung. */
108 #define TX_TIMEOUT (2*HZ)
110 #define NATSEMI_HW_TIMEOUT 400
111 #define NATSEMI_TIMER_FREQ 3*HZ
112 #define NATSEMI_PG0_NREGS 64
113 #define NATSEMI_RFDR_NREGS 8
114 #define NATSEMI_PG1_NREGS 4
115 #define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \
117 #define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */
118 #define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32))
121 * The nic writes 32-bit values, even if the upper bytes of
122 * a 32-bit value are beyond the end of the buffer.
124 #define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */
125 #define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */
126 #define NATSEMI_LONGPKT 1518 /* limit for normal packets */
127 #define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */
129 /* These identify the driver base version and may not be removed. */
130 static const char version[] __devinitdata =
131 KERN_INFO DRV_NAME " dp8381x driver, version "
132 DRV_VERSION ", " DRV_RELDATE "\n"
133 KERN_INFO " originally by Donald Becker <becker@scyld.com>\n"
134 KERN_INFO " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n";
136 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
137 MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver");
138 MODULE_LICENSE("GPL");
140 module_param(mtu, int, 0);
141 module_param(debug, int, 0);
142 module_param(rx_copybreak, int, 0);
143 module_param(dspcfg_workaround, int, 1);
144 module_param_array(options, int, NULL, 0);
145 module_param_array(full_duplex, int, NULL, 0);
146 MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)");
147 MODULE_PARM_DESC(debug, "DP8381x default debug level");
148 MODULE_PARM_DESC(rx_copybreak,
149 "DP8381x copy breakpoint for copy-only-tiny-frames");
150 MODULE_PARM_DESC(dspcfg_workaround, "DP8381x: control DspCfg workaround");
151 MODULE_PARM_DESC(options,
152 "DP8381x: Bits 0-3: media type, bit 17: full duplex");
153 MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)");
158 I. Board Compatibility
160 This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC.
161 It also works with other chips in in the DP83810 series.
163 II. Board-specific settings
165 This driver requires the PCI interrupt line to be valid.
166 It honors the EEPROM-set values.
168 III. Driver operation
172 This driver uses two statically allocated fixed-size descriptor lists
173 formed into rings by a branch from the final descriptor to the beginning of
174 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
175 The NatSemi design uses a 'next descriptor' pointer that the driver forms
178 IIIb/c. Transmit/Receive Structure
180 This driver uses a zero-copy receive and transmit scheme.
181 The driver allocates full frame size skbuffs for the Rx ring buffers at
182 open() time and passes the skb->data field to the chip as receive data
183 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
184 a fresh skbuff is allocated and the frame is copied to the new skbuff.
185 When the incoming frame is larger, the skbuff is passed directly up the
186 protocol stack. Buffers consumed this way are replaced by newly allocated
187 skbuffs in a later phase of receives.
189 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
190 using a full-sized skbuff for small frames vs. the copying costs of larger
191 frames. New boards are typically used in generously configured machines
192 and the underfilled buffers have negligible impact compared to the benefit of
193 a single allocation size, so the default value of zero results in never
194 copying packets. When copying is done, the cost is usually mitigated by using
195 a combined copy/checksum routine. Copying also preloads the cache, which is
196 most useful with small frames.
198 A subtle aspect of the operation is that unaligned buffers are not permitted
199 by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't
200 longword aligned for further processing. On copies frames are put into the
201 skbuff at an offset of "+2", 16-byte aligning the IP header.
203 IIId. Synchronization
205 Most operations are synchronized on the np->lock irq spinlock, except the
206 performance critical codepaths:
208 The rx process only runs in the interrupt handler. Access from outside
209 the interrupt handler is only permitted after disable_irq().
211 The rx process usually runs under the netif_tx_lock. If np->intr_tx_reap
212 is set, then access is permitted under spin_lock_irq(&np->lock).
214 Thus configuration functions that want to access everything must call
215 disable_irq(dev->irq);
216 netif_tx_lock_bh(dev);
217 spin_lock_irq(&np->lock);
221 NatSemi PCI network controllers are very uncommon.
225 http://www.scyld.com/expert/100mbps.html
226 http://www.scyld.com/expert/NWay.html
227 Datasheet is available from:
228 http://www.national.com/pf/DP/DP83815.html
238 * Support for fibre connections on Am79C874:
239 * This phy needs a special setup when connected to a fibre cable.
240 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
242 #define PHYID_AM79C874 0x0022561b
245 MII_MCTRL = 0x15, /* mode control register */
246 MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */
247 MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */
251 NATSEMI_FLAG_IGNORE_PHY = 0x1,
254 /* array of board data directly indexed by pci_tbl[x].driver_data */
255 static const struct {
258 unsigned int eeprom_size;
259 } natsemi_pci_info[] __devinitdata = {
260 { "Aculab E1/T1 PMXc cPCI carrier card", NATSEMI_FLAG_IGNORE_PHY, 128 },
261 { "NatSemi DP8381[56]", 0, 24 },
264 static const struct pci_device_id natsemi_pci_tbl[] __devinitdata = {
265 { PCI_VENDOR_ID_NS, 0x0020, 0x12d9, 0x000c, 0, 0, 0 },
266 { PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
267 { } /* terminate list */
269 MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
271 /* Offsets to the device registers.
272 Unlike software-only systems, device drivers interact with complex hardware.
273 It's not useful to define symbolic names for every register bit in the
276 enum register_offsets {
284 IntrHoldoff = 0x1C, /* DP83816 only */
311 /* These are from the spec, around page 78... on a separate table.
312 * The meaning of these registers depend on the value of PGSEL. */
319 /* the values for the 'magic' registers above (PGSEL=1) */
320 #define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
321 #define TSTDAT_VAL 0x0
322 #define DSPCFG_VAL 0x5040
323 #define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
324 #define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
325 #define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */
326 #define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
328 /* misc PCI space registers */
329 enum pci_register_offsets {
343 enum ChipConfig_bits {
347 CfgAnegEnable = 0x2000,
349 CfgAnegFull = 0x8000,
350 CfgAnegDone = 0x8000000,
351 CfgFullDuplex = 0x20000000,
352 CfgSpeed100 = 0x40000000,
353 CfgLink = 0x80000000,
359 EE_ChipSelect = 0x08,
366 enum PCIBusCfg_bits {
370 /* Bits in the interrupt status/mask registers. */
371 enum IntrStatus_bits {
375 IntrRxEarly = 0x0008,
377 IntrRxOverrun = 0x0020,
382 IntrTxUnderrun = 0x0400,
387 IntrHighBits = 0x8000,
388 RxStatusFIFOOver = 0x10000,
389 IntrPCIErr = 0xf00000,
390 RxResetDone = 0x1000000,
391 TxResetDone = 0x2000000,
392 IntrAbnormalSummary = 0xCD20,
396 * Default Interrupts:
397 * Rx OK, Rx Packet Error, Rx Overrun,
398 * Tx OK, Tx Packet Error, Tx Underrun,
399 * MIB Service, Phy Interrupt, High Bits,
400 * Rx Status FIFO overrun,
401 * Received Target Abort, Received Master Abort,
402 * Signalled System Error, Received Parity Error
404 #define DEFAULT_INTR 0x00f1cd65
409 TxMxdmaMask = 0x700000,
411 TxMxdma_4 = 0x100000,
412 TxMxdma_8 = 0x200000,
413 TxMxdma_16 = 0x300000,
414 TxMxdma_32 = 0x400000,
415 TxMxdma_64 = 0x500000,
416 TxMxdma_128 = 0x600000,
417 TxMxdma_256 = 0x700000,
418 TxCollRetry = 0x800000,
419 TxAutoPad = 0x10000000,
420 TxMacLoop = 0x20000000,
421 TxHeartIgn = 0x40000000,
422 TxCarrierIgn = 0x80000000
427 * - 256 byte DMA burst length
428 * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free)
429 * - 64 bytes initial drain threshold (i.e. begin actual transmission
430 * when 64 byte are in the fifo)
431 * - on tx underruns, increase drain threshold by 64.
432 * - at most use a drain threshold of 1472 bytes: The sum of the fill
433 * threshold and the drain threshold must be less than 2016 bytes.
436 #define TX_FLTH_VAL ((512/32) << 8)
437 #define TX_DRTH_VAL_START (64/32)
438 #define TX_DRTH_VAL_INC 2
439 #define TX_DRTH_VAL_LIMIT (1472/32)
443 RxMxdmaMask = 0x700000,
445 RxMxdma_4 = 0x100000,
446 RxMxdma_8 = 0x200000,
447 RxMxdma_16 = 0x300000,
448 RxMxdma_32 = 0x400000,
449 RxMxdma_64 = 0x500000,
450 RxMxdma_128 = 0x600000,
451 RxMxdma_256 = 0x700000,
452 RxAcceptLong = 0x8000000,
453 RxAcceptTx = 0x10000000,
454 RxAcceptRunt = 0x40000000,
455 RxAcceptErr = 0x80000000
457 #define RX_DRTH_VAL (128/8)
475 WakeMagicSecure = 0x400,
476 SecureHack = 0x100000,
478 WokeUnicast = 0x800000,
479 WokeMulticast = 0x1000000,
480 WokeBroadcast = 0x2000000,
482 WokePMatch0 = 0x8000000,
483 WokePMatch1 = 0x10000000,
484 WokePMatch2 = 0x20000000,
485 WokePMatch3 = 0x40000000,
486 WokeMagic = 0x80000000,
487 WakeOptsSummary = 0x7ff
490 enum RxFilterAddr_bits {
491 RFCRAddressMask = 0x3ff,
492 AcceptMulticast = 0x00200000,
493 AcceptMyPhys = 0x08000000,
494 AcceptAllPhys = 0x10000000,
495 AcceptAllMulticast = 0x20000000,
496 AcceptBroadcast = 0x40000000,
497 RxFilterEnable = 0x80000000
500 enum StatsCtrl_bits {
507 enum MIntrCtrl_bits {
515 #define PHY_ADDR_NONE 32
516 #define PHY_ADDR_INTERNAL 1
518 /* values we might find in the silicon revision register */
519 #define SRR_DP83815_C 0x0302
520 #define SRR_DP83815_D 0x0403
521 #define SRR_DP83816_A4 0x0504
522 #define SRR_DP83816_A5 0x0505
524 /* The Rx and Tx buffer descriptors. */
525 /* Note that using only 32 bit fields simplifies conversion to big-endian
534 /* Bits in network_desc.status */
535 enum desc_status_bits {
536 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
537 DescNoCRC=0x10000000, DescPktOK=0x08000000,
540 DescTxAbort=0x04000000, DescTxFIFO=0x02000000,
541 DescTxCarrier=0x01000000, DescTxDefer=0x00800000,
542 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000,
543 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000,
545 DescRxAbort=0x04000000, DescRxOver=0x02000000,
546 DescRxDest=0x01800000, DescRxLong=0x00400000,
547 DescRxRunt=0x00200000, DescRxInvalid=0x00100000,
548 DescRxCRC=0x00080000, DescRxAlign=0x00040000,
549 DescRxLoop=0x00020000, DesRxColl=0x00010000,
552 struct netdev_private {
553 /* Descriptor rings first for alignment */
555 struct netdev_desc *rx_ring;
556 struct netdev_desc *tx_ring;
557 /* The addresses of receive-in-place skbuffs */
558 struct sk_buff *rx_skbuff[RX_RING_SIZE];
559 dma_addr_t rx_dma[RX_RING_SIZE];
560 /* address of a sent-in-place packet/buffer, for later free() */
561 struct sk_buff *tx_skbuff[TX_RING_SIZE];
562 dma_addr_t tx_dma[TX_RING_SIZE];
563 struct net_device *dev;
564 struct napi_struct napi;
565 struct net_device_stats stats;
566 /* Media monitoring timer */
567 struct timer_list timer;
568 /* Frequently used values: keep some adjacent for cache effect */
569 struct pci_dev *pci_dev;
570 struct netdev_desc *rx_head_desc;
571 /* Producer/consumer ring indices */
572 unsigned int cur_rx, dirty_rx;
573 unsigned int cur_tx, dirty_tx;
574 /* Based on MTU+slack. */
575 unsigned int rx_buf_sz;
577 /* Interrupt status */
579 /* Do not touch the nic registers */
581 /* Don't pay attention to the reported link state. */
583 /* external phy that is used: only valid if dev->if_port != PORT_TP */
585 int phy_addr_external;
586 unsigned int full_duplex;
590 /* FIFO and PCI burst thresholds */
591 u32 tx_config, rx_config;
592 /* original contents of ClkRun register */
594 /* silicon revision */
596 /* expected DSPCFG value */
598 int dspcfg_workaround;
599 /* parms saved in ethtool format */
600 u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
601 u8 duplex; /* Duplex, half or full */
602 u8 autoneg; /* Autonegotiation enabled */
603 /* MII transceiver section */
612 static void move_int_phy(struct net_device *dev, int addr);
613 static int eeprom_read(void __iomem *ioaddr, int location);
614 static int mdio_read(struct net_device *dev, int reg);
615 static void mdio_write(struct net_device *dev, int reg, u16 data);
616 static void init_phy_fixup(struct net_device *dev);
617 static int miiport_read(struct net_device *dev, int phy_id, int reg);
618 static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data);
619 static int find_mii(struct net_device *dev);
620 static void natsemi_reset(struct net_device *dev);
621 static void natsemi_reload_eeprom(struct net_device *dev);
622 static void natsemi_stop_rxtx(struct net_device *dev);
623 static int netdev_open(struct net_device *dev);
624 static void do_cable_magic(struct net_device *dev);
625 static void undo_cable_magic(struct net_device *dev);
626 static void check_link(struct net_device *dev);
627 static void netdev_timer(unsigned long data);
628 static void dump_ring(struct net_device *dev);
629 static void tx_timeout(struct net_device *dev);
630 static int alloc_ring(struct net_device *dev);
631 static void refill_rx(struct net_device *dev);
632 static void init_ring(struct net_device *dev);
633 static void drain_tx(struct net_device *dev);
634 static void drain_ring(struct net_device *dev);
635 static void free_ring(struct net_device *dev);
636 static void reinit_ring(struct net_device *dev);
637 static void init_registers(struct net_device *dev);
638 static int start_tx(struct sk_buff *skb, struct net_device *dev);
639 static irqreturn_t intr_handler(int irq, void *dev_instance);
640 static void netdev_error(struct net_device *dev, int intr_status);
641 static int natsemi_poll(struct napi_struct *napi, int budget);
642 static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do);
643 static void netdev_tx_done(struct net_device *dev);
644 static int natsemi_change_mtu(struct net_device *dev, int new_mtu);
645 #ifdef CONFIG_NET_POLL_CONTROLLER
646 static void natsemi_poll_controller(struct net_device *dev);
648 static void __set_rx_mode(struct net_device *dev);
649 static void set_rx_mode(struct net_device *dev);
650 static void __get_stats(struct net_device *dev);
651 static struct net_device_stats *get_stats(struct net_device *dev);
652 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
653 static int netdev_set_wol(struct net_device *dev, u32 newval);
654 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur);
655 static int netdev_set_sopass(struct net_device *dev, u8 *newval);
656 static int netdev_get_sopass(struct net_device *dev, u8 *data);
657 static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
658 static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
659 static void enable_wol_mode(struct net_device *dev, int enable_intr);
660 static int netdev_close(struct net_device *dev);
661 static int netdev_get_regs(struct net_device *dev, u8 *buf);
662 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
663 static const struct ethtool_ops ethtool_ops;
665 #define NATSEMI_ATTR(_name) \
666 static ssize_t natsemi_show_##_name(struct device *dev, \
667 struct device_attribute *attr, char *buf); \
668 static ssize_t natsemi_set_##_name(struct device *dev, \
669 struct device_attribute *attr, \
670 const char *buf, size_t count); \
671 static DEVICE_ATTR(_name, 0644, natsemi_show_##_name, natsemi_set_##_name)
673 #define NATSEMI_CREATE_FILE(_dev, _name) \
674 device_create_file(&_dev->dev, &dev_attr_##_name)
675 #define NATSEMI_REMOVE_FILE(_dev, _name) \
676 device_remove_file(&_dev->dev, &dev_attr_##_name)
678 NATSEMI_ATTR(dspcfg_workaround);
680 static ssize_t natsemi_show_dspcfg_workaround(struct device *dev,
681 struct device_attribute *attr,
684 struct netdev_private *np = netdev_priv(to_net_dev(dev));
686 return sprintf(buf, "%s\n", np->dspcfg_workaround ? "on" : "off");
689 static ssize_t natsemi_set_dspcfg_workaround(struct device *dev,
690 struct device_attribute *attr,
691 const char *buf, size_t count)
693 struct netdev_private *np = netdev_priv(to_net_dev(dev));
697 /* Find out the new setting */
698 if (!strncmp("on", buf, count - 1) || !strncmp("1", buf, count - 1))
700 else if (!strncmp("off", buf, count - 1)
701 || !strncmp("0", buf, count - 1))
706 spin_lock_irqsave(&np->lock, flags);
708 np->dspcfg_workaround = new_setting;
710 spin_unlock_irqrestore(&np->lock, flags);
715 static inline void __iomem *ns_ioaddr(struct net_device *dev)
717 return (void __iomem *) dev->base_addr;
720 static inline void natsemi_irq_enable(struct net_device *dev)
722 writel(1, ns_ioaddr(dev) + IntrEnable);
723 readl(ns_ioaddr(dev) + IntrEnable);
726 static inline void natsemi_irq_disable(struct net_device *dev)
728 writel(0, ns_ioaddr(dev) + IntrEnable);
729 readl(ns_ioaddr(dev) + IntrEnable);
732 static void move_int_phy(struct net_device *dev, int addr)
734 struct netdev_private *np = netdev_priv(dev);
735 void __iomem *ioaddr = ns_ioaddr(dev);
739 * The internal phy is visible on the external mii bus. Therefore we must
740 * move it away before we can send commands to an external phy.
741 * There are two addresses we must avoid:
742 * - the address on the external phy that is used for transmission.
743 * - the address that we want to access. User space can access phys
744 * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independant from the
745 * phy that is used for transmission.
750 if (target == np->phy_addr_external)
752 writew(target, ioaddr + PhyCtrl);
753 readw(ioaddr + PhyCtrl);
757 static void __devinit natsemi_init_media (struct net_device *dev)
759 struct netdev_private *np = netdev_priv(dev);
763 netif_carrier_on(dev);
765 netif_carrier_off(dev);
767 /* get the initial settings from hardware */
768 tmp = mdio_read(dev, MII_BMCR);
769 np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10;
770 np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF;
771 np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE;
772 np->advertising= mdio_read(dev, MII_ADVERTISE);
774 if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL
775 && netif_msg_probe(np)) {
776 printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s "
778 pci_name(np->pci_dev),
779 (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)?
780 "enabled, advertise" : "disabled, force",
782 (ADVERTISE_100FULL|ADVERTISE_100HALF))?
785 (ADVERTISE_100FULL|ADVERTISE_10FULL))?
788 if (netif_msg_probe(np))
790 "natsemi %s: Transceiver status %#04x advertising %#04x.\n",
791 pci_name(np->pci_dev), mdio_read(dev, MII_BMSR),
796 static int __devinit natsemi_probe1 (struct pci_dev *pdev,
797 const struct pci_device_id *ent)
799 struct net_device *dev;
800 struct netdev_private *np;
801 int i, option, irq, chip_idx = ent->driver_data;
802 static int find_cnt = -1;
803 unsigned long iostart, iosize;
804 void __iomem *ioaddr;
805 const int pcibar = 1; /* PCI base address register */
809 /* when built into the kernel, we only print version if device is found */
811 static int printed_version;
812 if (!printed_version++)
816 i = pci_enable_device(pdev);
819 /* natsemi has a non-standard PM control register
820 * in PCI config space. Some boards apparently need
821 * to be brought to D0 in this manner.
823 pci_read_config_dword(pdev, PCIPM, &tmp);
824 if (tmp & PCI_PM_CTRL_STATE_MASK) {
825 /* D0 state, disable PME assertion */
826 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
827 pci_write_config_dword(pdev, PCIPM, newtmp);
831 iostart = pci_resource_start(pdev, pcibar);
832 iosize = pci_resource_len(pdev, pcibar);
835 pci_set_master(pdev);
837 dev = alloc_etherdev(sizeof (struct netdev_private));
840 SET_MODULE_OWNER(dev);
841 SET_NETDEV_DEV(dev, &pdev->dev);
843 i = pci_request_regions(pdev, DRV_NAME);
845 goto err_pci_request_regions;
847 ioaddr = ioremap(iostart, iosize);
853 /* Work around the dropped serial bit. */
854 prev_eedata = eeprom_read(ioaddr, 6);
855 for (i = 0; i < 3; i++) {
856 int eedata = eeprom_read(ioaddr, i + 7);
857 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15);
858 dev->dev_addr[i*2+1] = eedata >> 7;
859 prev_eedata = eedata;
862 dev->base_addr = (unsigned long __force) ioaddr;
865 np = netdev_priv(dev);
866 netif_napi_add(dev, &np->napi, natsemi_poll, 64);
869 pci_set_drvdata(pdev, dev);
871 spin_lock_init(&np->lock);
872 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG;
875 np->eeprom_size = natsemi_pci_info[chip_idx].eeprom_size;
876 if (natsemi_pci_info[chip_idx].flags & NATSEMI_FLAG_IGNORE_PHY)
880 np->dspcfg_workaround = dspcfg_workaround;
883 * - If configured to ignore the PHY set up for external.
884 * - If the nic was configured to use an external phy and if find_mii
885 * finds a phy: use external port, first phy that replies.
886 * - Otherwise: internal port.
887 * Note that the phy address for the internal phy doesn't matter:
888 * The address would be used to access a phy over the mii bus, but
889 * the internal phy is accessed through mapped registers.
891 if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy)
892 dev->if_port = PORT_MII;
894 dev->if_port = PORT_TP;
895 /* Reset the chip to erase previous misconfiguration. */
896 natsemi_reload_eeprom(dev);
899 if (dev->if_port != PORT_TP) {
900 np->phy_addr_external = find_mii(dev);
901 /* If we're ignoring the PHY it doesn't matter if we can't
903 if (!np->ignore_phy && np->phy_addr_external == PHY_ADDR_NONE) {
904 dev->if_port = PORT_TP;
905 np->phy_addr_external = PHY_ADDR_INTERNAL;
908 np->phy_addr_external = PHY_ADDR_INTERNAL;
911 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
913 option = dev->mem_start;
915 /* The lower four bits are the media type. */
921 "natsemi %s: ignoring user supplied media type %d",
922 pci_name(np->pci_dev), option & 15);
924 if (find_cnt < MAX_UNITS && full_duplex[find_cnt])
927 /* The chip-specific entries in the device structure. */
928 dev->open = &netdev_open;
929 dev->hard_start_xmit = &start_tx;
930 dev->stop = &netdev_close;
931 dev->get_stats = &get_stats;
932 dev->set_multicast_list = &set_rx_mode;
933 dev->change_mtu = &natsemi_change_mtu;
934 dev->do_ioctl = &netdev_ioctl;
935 dev->tx_timeout = &tx_timeout;
936 dev->watchdog_timeo = TX_TIMEOUT;
938 #ifdef CONFIG_NET_POLL_CONTROLLER
939 dev->poll_controller = &natsemi_poll_controller;
941 SET_ETHTOOL_OPS(dev, ðtool_ops);
946 natsemi_init_media(dev);
948 /* save the silicon revision for later querying */
949 np->srr = readl(ioaddr + SiliconRev);
950 if (netif_msg_hw(np))
951 printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n",
952 pci_name(np->pci_dev), np->srr);
954 i = register_netdev(dev);
956 goto err_register_netdev;
958 if (NATSEMI_CREATE_FILE(pdev, dspcfg_workaround))
959 goto err_create_file;
961 if (netif_msg_drv(np)) {
962 printk(KERN_INFO "natsemi %s: %s at %#08lx (%s), ",
963 dev->name, natsemi_pci_info[chip_idx].name, iostart,
964 pci_name(np->pci_dev));
965 for (i = 0; i < ETH_ALEN-1; i++)
966 printk("%02x:", dev->dev_addr[i]);
967 printk("%02x, IRQ %d", dev->dev_addr[i], irq);
968 if (dev->if_port == PORT_TP)
969 printk(", port TP.\n");
970 else if (np->ignore_phy)
971 printk(", port MII, ignoring PHY\n");
973 printk(", port MII, phy ad %d.\n", np->phy_addr_external);
978 unregister_netdev(dev);
984 pci_release_regions(pdev);
985 pci_set_drvdata(pdev, NULL);
987 err_pci_request_regions:
993 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
994 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */
996 /* Delay between EEPROM clock transitions.
997 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
998 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
999 made udelay() unreliable.
1000 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
1003 #define eeprom_delay(ee_addr) readl(ee_addr)
1005 #define EE_Write0 (EE_ChipSelect)
1006 #define EE_Write1 (EE_ChipSelect | EE_DataIn)
1008 /* The EEPROM commands include the alway-set leading bit. */
1010 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
1013 static int eeprom_read(void __iomem *addr, int location)
1017 void __iomem *ee_addr = addr + EECtrl;
1018 int read_cmd = location | EE_ReadCmd;
1020 writel(EE_Write0, ee_addr);
1022 /* Shift the read command bits out. */
1023 for (i = 10; i >= 0; i--) {
1024 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
1025 writel(dataval, ee_addr);
1026 eeprom_delay(ee_addr);
1027 writel(dataval | EE_ShiftClk, ee_addr);
1028 eeprom_delay(ee_addr);
1030 writel(EE_ChipSelect, ee_addr);
1031 eeprom_delay(ee_addr);
1033 for (i = 0; i < 16; i++) {
1034 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
1035 eeprom_delay(ee_addr);
1036 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
1037 writel(EE_ChipSelect, ee_addr);
1038 eeprom_delay(ee_addr);
1041 /* Terminate the EEPROM access. */
1042 writel(EE_Write0, ee_addr);
1047 /* MII transceiver control section.
1048 * The 83815 series has an internal transceiver, and we present the
1049 * internal management registers as if they were MII connected.
1050 * External Phy registers are referenced through the MII interface.
1053 /* clock transitions >= 20ns (25MHz)
1054 * One readl should be good to PCI @ 100MHz
1056 #define mii_delay(ioaddr) readl(ioaddr + EECtrl)
1058 static int mii_getbit (struct net_device *dev)
1061 void __iomem *ioaddr = ns_ioaddr(dev);
1063 writel(MII_ShiftClk, ioaddr + EECtrl);
1064 data = readl(ioaddr + EECtrl);
1065 writel(0, ioaddr + EECtrl);
1067 return (data & MII_Data)? 1 : 0;
1070 static void mii_send_bits (struct net_device *dev, u32 data, int len)
1073 void __iomem *ioaddr = ns_ioaddr(dev);
1075 for (i = (1 << (len-1)); i; i >>= 1)
1077 u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0);
1078 writel(mdio_val, ioaddr + EECtrl);
1080 writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl);
1083 writel(0, ioaddr + EECtrl);
1087 static int miiport_read(struct net_device *dev, int phy_id, int reg)
1094 mii_send_bits (dev, 0xffffffff, 32);
1095 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1096 /* ST,OP = 0110'b for read operation */
1097 cmd = (0x06 << 10) | (phy_id << 5) | reg;
1098 mii_send_bits (dev, cmd, 14);
1100 if (mii_getbit (dev))
1103 for (i = 0; i < 16; i++) {
1105 retval |= mii_getbit (dev);
1112 static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data)
1117 mii_send_bits (dev, 0xffffffff, 32);
1118 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1119 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1120 cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data;
1121 mii_send_bits (dev, cmd, 32);
1126 static int mdio_read(struct net_device *dev, int reg)
1128 struct netdev_private *np = netdev_priv(dev);
1129 void __iomem *ioaddr = ns_ioaddr(dev);
1131 /* The 83815 series has two ports:
1132 * - an internal transceiver
1133 * - an external mii bus
1135 if (dev->if_port == PORT_TP)
1136 return readw(ioaddr+BasicControl+(reg<<2));
1138 return miiport_read(dev, np->phy_addr_external, reg);
1141 static void mdio_write(struct net_device *dev, int reg, u16 data)
1143 struct netdev_private *np = netdev_priv(dev);
1144 void __iomem *ioaddr = ns_ioaddr(dev);
1146 /* The 83815 series has an internal transceiver; handle separately */
1147 if (dev->if_port == PORT_TP)
1148 writew(data, ioaddr+BasicControl+(reg<<2));
1150 miiport_write(dev, np->phy_addr_external, reg, data);
1153 static void init_phy_fixup(struct net_device *dev)
1155 struct netdev_private *np = netdev_priv(dev);
1156 void __iomem *ioaddr = ns_ioaddr(dev);
1161 /* restore stuff lost when power was out */
1162 tmp = mdio_read(dev, MII_BMCR);
1163 if (np->autoneg == AUTONEG_ENABLE) {
1164 /* renegotiate if something changed */
1165 if ((tmp & BMCR_ANENABLE) == 0
1166 || np->advertising != mdio_read(dev, MII_ADVERTISE))
1168 /* turn on autonegotiation and force negotiation */
1169 tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
1170 mdio_write(dev, MII_ADVERTISE, np->advertising);
1173 /* turn off auto negotiation, set speed and duplexity */
1174 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
1175 if (np->speed == SPEED_100)
1176 tmp |= BMCR_SPEED100;
1177 if (np->duplex == DUPLEX_FULL)
1178 tmp |= BMCR_FULLDPLX;
1180 * Note: there is no good way to inform the link partner
1181 * that our capabilities changed. The user has to unplug
1182 * and replug the network cable after some changes, e.g.
1183 * after switching from 10HD, autoneg off to 100 HD,
1187 mdio_write(dev, MII_BMCR, tmp);
1188 readl(ioaddr + ChipConfig);
1191 /* find out what phy this is */
1192 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1193 + mdio_read(dev, MII_PHYSID2);
1195 /* handle external phys here */
1197 case PHYID_AM79C874:
1198 /* phy specific configuration for fibre/tp operation */
1199 tmp = mdio_read(dev, MII_MCTRL);
1200 tmp &= ~(MII_FX_SEL | MII_EN_SCRM);
1201 if (dev->if_port == PORT_FIBRE)
1205 mdio_write(dev, MII_MCTRL, tmp);
1210 cfg = readl(ioaddr + ChipConfig);
1211 if (cfg & CfgExtPhy)
1214 /* On page 78 of the spec, they recommend some settings for "optimum
1215 performance" to be done in sequence. These settings optimize some
1216 of the 100Mbit autodetection circuitry. They say we only want to
1217 do this for rev C of the chip, but engineers at NSC (Bradley
1218 Kennedy) recommends always setting them. If you don't, you get
1219 errors on some autonegotiations that make the device unusable.
1221 It seems that the DSP needs a few usec to reinitialize after
1222 the start of the phy. Just retry writing these values until they
1225 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1228 writew(1, ioaddr + PGSEL);
1229 writew(PMDCSR_VAL, ioaddr + PMDCSR);
1230 writew(TSTDAT_VAL, ioaddr + TSTDAT);
1231 np->dspcfg = (np->srr <= SRR_DP83815_C)?
1232 DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG));
1233 writew(np->dspcfg, ioaddr + DSPCFG);
1234 writew(SDCFG_VAL, ioaddr + SDCFG);
1235 writew(0, ioaddr + PGSEL);
1236 readl(ioaddr + ChipConfig);
1239 writew(1, ioaddr + PGSEL);
1240 dspcfg = readw(ioaddr + DSPCFG);
1241 writew(0, ioaddr + PGSEL);
1242 if (np->dspcfg == dspcfg)
1246 if (netif_msg_link(np)) {
1247 if (i==NATSEMI_HW_TIMEOUT) {
1249 "%s: DSPCFG mismatch after retrying for %d usec.\n",
1253 "%s: DSPCFG accepted after %d usec.\n",
1258 * Enable PHY Specific event based interrupts. Link state change
1259 * and Auto-Negotiation Completion are among the affected.
1260 * Read the intr status to clear it (needed for wake events).
1262 readw(ioaddr + MIntrStatus);
1263 writew(MICRIntEn, ioaddr + MIntrCtrl);
1266 static int switch_port_external(struct net_device *dev)
1268 struct netdev_private *np = netdev_priv(dev);
1269 void __iomem *ioaddr = ns_ioaddr(dev);
1272 cfg = readl(ioaddr + ChipConfig);
1273 if (cfg & CfgExtPhy)
1276 if (netif_msg_link(np)) {
1277 printk(KERN_INFO "%s: switching to external transceiver.\n",
1281 /* 1) switch back to external phy */
1282 writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig);
1283 readl(ioaddr + ChipConfig);
1286 /* 2) reset the external phy: */
1287 /* resetting the external PHY has been known to cause a hub supplying
1288 * power over Ethernet to kill the power. We don't want to kill
1289 * power to this computer, so we avoid resetting the phy.
1292 /* 3) reinit the phy fixup, it got lost during power down. */
1293 move_int_phy(dev, np->phy_addr_external);
1294 init_phy_fixup(dev);
1299 static int switch_port_internal(struct net_device *dev)
1301 struct netdev_private *np = netdev_priv(dev);
1302 void __iomem *ioaddr = ns_ioaddr(dev);
1307 cfg = readl(ioaddr + ChipConfig);
1308 if (!(cfg &CfgExtPhy))
1311 if (netif_msg_link(np)) {
1312 printk(KERN_INFO "%s: switching to internal transceiver.\n",
1315 /* 1) switch back to internal phy: */
1316 cfg = cfg & ~(CfgExtPhy | CfgPhyDis);
1317 writel(cfg, ioaddr + ChipConfig);
1318 readl(ioaddr + ChipConfig);
1321 /* 2) reset the internal phy: */
1322 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1323 writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));
1324 readl(ioaddr + ChipConfig);
1326 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1327 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1328 if (!(bmcr & BMCR_RESET))
1332 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) {
1334 "%s: phy reset did not complete in %d usec.\n",
1337 /* 3) reinit the phy fixup, it got lost during power down. */
1338 init_phy_fixup(dev);
1343 /* Scan for a PHY on the external mii bus.
1344 * There are two tricky points:
1345 * - Do not scan while the internal phy is enabled. The internal phy will
1346 * crash: e.g. reads from the DSPCFG register will return odd values and
1347 * the nasty random phy reset code will reset the nic every few seconds.
1348 * - The internal phy must be moved around, an external phy could
1349 * have the same address as the internal phy.
1351 static int find_mii(struct net_device *dev)
1353 struct netdev_private *np = netdev_priv(dev);
1358 /* Switch to external phy */
1359 did_switch = switch_port_external(dev);
1361 /* Scan the possible phy addresses:
1363 * PHY address 0 means that the phy is in isolate mode. Not yet
1364 * supported due to lack of test hardware. User space should
1365 * handle it through ethtool.
1367 for (i = 1; i <= 31; i++) {
1368 move_int_phy(dev, i);
1369 tmp = miiport_read(dev, i, MII_BMSR);
1370 if (tmp != 0xffff && tmp != 0x0000) {
1371 /* found something! */
1372 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1373 + mdio_read(dev, MII_PHYSID2);
1374 if (netif_msg_probe(np)) {
1375 printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n",
1376 pci_name(np->pci_dev), np->mii, i);
1381 /* And switch back to internal phy: */
1383 switch_port_internal(dev);
1387 /* CFG bits [13:16] [18:23] */
1388 #define CFG_RESET_SAVE 0xfde000
1389 /* WCSR bits [0:4] [9:10] */
1390 #define WCSR_RESET_SAVE 0x61f
1391 /* RFCR bits [20] [22] [27:31] */
1392 #define RFCR_RESET_SAVE 0xf8500000;
1394 static void natsemi_reset(struct net_device *dev)
1402 struct netdev_private *np = netdev_priv(dev);
1403 void __iomem *ioaddr = ns_ioaddr(dev);
1406 * Resetting the chip causes some registers to be lost.
1407 * Natsemi suggests NOT reloading the EEPROM while live, so instead
1408 * we save the state that would have been loaded from EEPROM
1409 * on a normal power-up (see the spec EEPROM map). This assumes
1410 * whoever calls this will follow up with init_registers() eventually.
1414 cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE;
1416 wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;
1418 rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;
1420 for (i = 0; i < 3; i++) {
1421 writel(i*2, ioaddr + RxFilterAddr);
1422 pmatch[i] = readw(ioaddr + RxFilterData);
1425 for (i = 0; i < 3; i++) {
1426 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1427 sopass[i] = readw(ioaddr + RxFilterData);
1430 /* now whack the chip */
1431 writel(ChipReset, ioaddr + ChipCmd);
1432 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1433 if (!(readl(ioaddr + ChipCmd) & ChipReset))
1437 if (i==NATSEMI_HW_TIMEOUT) {
1438 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n",
1440 } else if (netif_msg_hw(np)) {
1441 printk(KERN_DEBUG "%s: reset completed in %d usec.\n",
1446 cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE;
1447 /* turn on external phy if it was selected */
1448 if (dev->if_port == PORT_TP)
1449 cfg &= ~(CfgExtPhy | CfgPhyDis);
1451 cfg |= (CfgExtPhy | CfgPhyDis);
1452 writel(cfg, ioaddr + ChipConfig);
1454 wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;
1455 writel(wcsr, ioaddr + WOLCmd);
1457 rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;
1458 /* restore PMATCH */
1459 for (i = 0; i < 3; i++) {
1460 writel(i*2, ioaddr + RxFilterAddr);
1461 writew(pmatch[i], ioaddr + RxFilterData);
1463 for (i = 0; i < 3; i++) {
1464 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1465 writew(sopass[i], ioaddr + RxFilterData);
1468 writel(rfcr, ioaddr + RxFilterAddr);
1471 static void reset_rx(struct net_device *dev)
1474 struct netdev_private *np = netdev_priv(dev);
1475 void __iomem *ioaddr = ns_ioaddr(dev);
1477 np->intr_status &= ~RxResetDone;
1479 writel(RxReset, ioaddr + ChipCmd);
1481 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1482 np->intr_status |= readl(ioaddr + IntrStatus);
1483 if (np->intr_status & RxResetDone)
1487 if (i==NATSEMI_HW_TIMEOUT) {
1488 printk(KERN_WARNING "%s: RX reset did not complete in %d usec.\n",
1490 } else if (netif_msg_hw(np)) {
1491 printk(KERN_WARNING "%s: RX reset took %d usec.\n",
1496 static void natsemi_reload_eeprom(struct net_device *dev)
1498 struct netdev_private *np = netdev_priv(dev);
1499 void __iomem *ioaddr = ns_ioaddr(dev);
1502 writel(EepromReload, ioaddr + PCIBusCfg);
1503 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1505 if (!(readl(ioaddr + PCIBusCfg) & EepromReload))
1508 if (i==NATSEMI_HW_TIMEOUT) {
1509 printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n",
1510 pci_name(np->pci_dev), i*50);
1511 } else if (netif_msg_hw(np)) {
1512 printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n",
1513 pci_name(np->pci_dev), i*50);
1517 static void natsemi_stop_rxtx(struct net_device *dev)
1519 void __iomem * ioaddr = ns_ioaddr(dev);
1520 struct netdev_private *np = netdev_priv(dev);
1523 writel(RxOff | TxOff, ioaddr + ChipCmd);
1524 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) {
1525 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
1529 if (i==NATSEMI_HW_TIMEOUT) {
1530 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n",
1532 } else if (netif_msg_hw(np)) {
1533 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n",
1538 static int netdev_open(struct net_device *dev)
1540 struct netdev_private *np = netdev_priv(dev);
1541 void __iomem * ioaddr = ns_ioaddr(dev);
1544 /* Reset the chip, just in case. */
1547 i = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev);
1550 if (netif_msg_ifup(np))
1551 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
1552 dev->name, dev->irq);
1553 i = alloc_ring(dev);
1555 free_irq(dev->irq, dev);
1558 napi_enable(&np->napi);
1561 spin_lock_irq(&np->lock);
1562 init_registers(dev);
1563 /* now set the MAC address according to dev->dev_addr */
1564 for (i = 0; i < 3; i++) {
1565 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i];
1567 writel(i*2, ioaddr + RxFilterAddr);
1568 writew(mac, ioaddr + RxFilterData);
1570 writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
1571 spin_unlock_irq(&np->lock);
1573 netif_start_queue(dev);
1575 if (netif_msg_ifup(np))
1576 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n",
1577 dev->name, (int)readl(ioaddr + ChipCmd));
1579 /* Set the timer to check for link beat. */
1580 init_timer(&np->timer);
1581 np->timer.expires = jiffies + NATSEMI_TIMER_FREQ;
1582 np->timer.data = (unsigned long)dev;
1583 np->timer.function = &netdev_timer; /* timer handler */
1584 add_timer(&np->timer);
1589 static void do_cable_magic(struct net_device *dev)
1591 struct netdev_private *np = netdev_priv(dev);
1592 void __iomem *ioaddr = ns_ioaddr(dev);
1594 if (dev->if_port != PORT_TP)
1597 if (np->srr >= SRR_DP83816_A5)
1601 * 100 MBit links with short cables can trip an issue with the chip.
1602 * The problem manifests as lots of CRC errors and/or flickering
1603 * activity LED while idle. This process is based on instructions
1604 * from engineers at National.
1606 if (readl(ioaddr + ChipConfig) & CfgSpeed100) {
1609 writew(1, ioaddr + PGSEL);
1611 * coefficient visibility should already be enabled via
1614 data = readw(ioaddr + TSTDAT) & 0xff;
1616 * the value must be negative, and within certain values
1617 * (these values all come from National)
1619 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) {
1620 struct netdev_private *np = netdev_priv(dev);
1622 /* the bug has been triggered - fix the coefficient */
1623 writew(TSTDAT_FIXED, ioaddr + TSTDAT);
1624 /* lock the value */
1625 data = readw(ioaddr + DSPCFG);
1626 np->dspcfg = data | DSPCFG_LOCK;
1627 writew(np->dspcfg, ioaddr + DSPCFG);
1629 writew(0, ioaddr + PGSEL);
1633 static void undo_cable_magic(struct net_device *dev)
1636 struct netdev_private *np = netdev_priv(dev);
1637 void __iomem * ioaddr = ns_ioaddr(dev);
1639 if (dev->if_port != PORT_TP)
1642 if (np->srr >= SRR_DP83816_A5)
1645 writew(1, ioaddr + PGSEL);
1646 /* make sure the lock bit is clear */
1647 data = readw(ioaddr + DSPCFG);
1648 np->dspcfg = data & ~DSPCFG_LOCK;
1649 writew(np->dspcfg, ioaddr + DSPCFG);
1650 writew(0, ioaddr + PGSEL);
1653 static void check_link(struct net_device *dev)
1655 struct netdev_private *np = netdev_priv(dev);
1656 void __iomem * ioaddr = ns_ioaddr(dev);
1657 int duplex = np->duplex;
1660 /* If we are ignoring the PHY then don't try reading it. */
1662 goto propagate_state;
1664 /* The link status field is latched: it remains low after a temporary
1665 * link failure until it's read. We need the current link status,
1668 mdio_read(dev, MII_BMSR);
1669 bmsr = mdio_read(dev, MII_BMSR);
1671 if (!(bmsr & BMSR_LSTATUS)) {
1672 if (netif_carrier_ok(dev)) {
1673 if (netif_msg_link(np))
1674 printk(KERN_NOTICE "%s: link down.\n",
1676 netif_carrier_off(dev);
1677 undo_cable_magic(dev);
1681 if (!netif_carrier_ok(dev)) {
1682 if (netif_msg_link(np))
1683 printk(KERN_NOTICE "%s: link up.\n", dev->name);
1684 netif_carrier_on(dev);
1685 do_cable_magic(dev);
1688 duplex = np->full_duplex;
1690 if (bmsr & BMSR_ANEGCOMPLETE) {
1691 int tmp = mii_nway_result(
1692 np->advertising & mdio_read(dev, MII_LPA));
1693 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
1695 } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX)
1700 /* if duplex is set then bit 28 must be set, too */
1701 if (duplex ^ !!(np->rx_config & RxAcceptTx)) {
1702 if (netif_msg_link(np))
1704 "%s: Setting %s-duplex based on negotiated "
1705 "link capability.\n", dev->name,
1706 duplex ? "full" : "half");
1708 np->rx_config |= RxAcceptTx;
1709 np->tx_config |= TxCarrierIgn | TxHeartIgn;
1711 np->rx_config &= ~RxAcceptTx;
1712 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn);
1714 writel(np->tx_config, ioaddr + TxConfig);
1715 writel(np->rx_config, ioaddr + RxConfig);
1719 static void init_registers(struct net_device *dev)
1721 struct netdev_private *np = netdev_priv(dev);
1722 void __iomem * ioaddr = ns_ioaddr(dev);
1724 init_phy_fixup(dev);
1726 /* clear any interrupts that are pending, such as wake events */
1727 readl(ioaddr + IntrStatus);
1729 writel(np->ring_dma, ioaddr + RxRingPtr);
1730 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
1731 ioaddr + TxRingPtr);
1733 /* Initialize other registers.
1734 * Configure the PCI bus bursts and FIFO thresholds.
1735 * Configure for standard, in-spec Ethernet.
1736 * Start with half-duplex. check_link will update
1737 * to the correct settings.
1740 /* DRTH: 2: start tx if 64 bytes are in the fifo
1741 * FLTH: 0x10: refill with next packet if 512 bytes are free
1742 * MXDMA: 0: up to 256 byte bursts.
1743 * MXDMA must be <= FLTH
1747 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 |
1748 TX_FLTH_VAL | TX_DRTH_VAL_START;
1749 writel(np->tx_config, ioaddr + TxConfig);
1751 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo
1752 * MXDMA 0: up to 256 byte bursts
1754 np->rx_config = RxMxdma_256 | RX_DRTH_VAL;
1755 /* if receive ring now has bigger buffers than normal, enable jumbo */
1756 if (np->rx_buf_sz > NATSEMI_LONGPKT)
1757 np->rx_config |= RxAcceptLong;
1759 writel(np->rx_config, ioaddr + RxConfig);
1762 * The PME bit is initialized from the EEPROM contents.
1763 * PCI cards probably have PME disabled, but motherboard
1764 * implementations may have PME set to enable WakeOnLan.
1765 * With PME set the chip will scan incoming packets but
1766 * nothing will be written to memory. */
1767 np->SavedClkRun = readl(ioaddr + ClkRun);
1768 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
1769 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) {
1770 printk(KERN_NOTICE "%s: Wake-up event %#08x\n",
1771 dev->name, readl(ioaddr + WOLCmd));
1777 /* Enable interrupts by setting the interrupt mask. */
1778 writel(DEFAULT_INTR, ioaddr + IntrMask);
1779 natsemi_irq_enable(dev);
1781 writel(RxOn | TxOn, ioaddr + ChipCmd);
1782 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
1788 * 1) check for link changes. Usually they are handled by the MII interrupt
1789 * but it doesn't hurt to check twice.
1790 * 2) check for sudden death of the NIC:
1791 * It seems that a reference set for this chip went out with incorrect info,
1792 * and there exist boards that aren't quite right. An unexpected voltage
1793 * drop can cause the PHY to get itself in a weird state (basically reset).
1794 * NOTE: this only seems to affect revC chips. The user can disable
1795 * this check via dspcfg_workaround sysfs option.
1796 * 3) check of death of the RX path due to OOM
1798 static void netdev_timer(unsigned long data)
1800 struct net_device *dev = (struct net_device *)data;
1801 struct netdev_private *np = netdev_priv(dev);
1802 void __iomem * ioaddr = ns_ioaddr(dev);
1803 int next_tick = 5*HZ;
1805 if (netif_msg_timer(np)) {
1806 /* DO NOT read the IntrStatus register,
1807 * a read clears any pending interrupts.
1809 printk(KERN_DEBUG "%s: Media selection timer tick.\n",
1813 if (dev->if_port == PORT_TP) {
1816 spin_lock_irq(&np->lock);
1817 /* check for a nasty random phy-reset - use dspcfg as a flag */
1818 writew(1, ioaddr+PGSEL);
1819 dspcfg = readw(ioaddr+DSPCFG);
1820 writew(0, ioaddr+PGSEL);
1821 if (np->dspcfg_workaround && dspcfg != np->dspcfg) {
1822 if (!netif_queue_stopped(dev)) {
1823 spin_unlock_irq(&np->lock);
1824 if (netif_msg_drv(np))
1825 printk(KERN_NOTICE "%s: possible phy reset: "
1826 "re-initializing\n", dev->name);
1827 disable_irq(dev->irq);
1828 spin_lock_irq(&np->lock);
1829 natsemi_stop_rxtx(dev);
1832 init_registers(dev);
1833 spin_unlock_irq(&np->lock);
1834 enable_irq(dev->irq);
1838 spin_unlock_irq(&np->lock);
1841 /* init_registers() calls check_link() for the above case */
1843 spin_unlock_irq(&np->lock);
1846 spin_lock_irq(&np->lock);
1848 spin_unlock_irq(&np->lock);
1851 disable_irq(dev->irq);
1854 enable_irq(dev->irq);
1856 writel(RxOn, ioaddr + ChipCmd);
1861 mod_timer(&np->timer, jiffies + next_tick);
1864 static void dump_ring(struct net_device *dev)
1866 struct netdev_private *np = netdev_priv(dev);
1868 if (netif_msg_pktdata(np)) {
1870 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring);
1871 for (i = 0; i < TX_RING_SIZE; i++) {
1872 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1873 i, np->tx_ring[i].next_desc,
1874 np->tx_ring[i].cmd_status,
1875 np->tx_ring[i].addr);
1877 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1878 for (i = 0; i < RX_RING_SIZE; i++) {
1879 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1880 i, np->rx_ring[i].next_desc,
1881 np->rx_ring[i].cmd_status,
1882 np->rx_ring[i].addr);
1887 static void tx_timeout(struct net_device *dev)
1889 struct netdev_private *np = netdev_priv(dev);
1890 void __iomem * ioaddr = ns_ioaddr(dev);
1892 disable_irq(dev->irq);
1893 spin_lock_irq(&np->lock);
1894 if (!np->hands_off) {
1895 if (netif_msg_tx_err(np))
1897 "%s: Transmit timed out, status %#08x,"
1899 dev->name, readl(ioaddr + IntrStatus));
1904 init_registers(dev);
1907 "%s: tx_timeout while in hands_off state?\n",
1910 spin_unlock_irq(&np->lock);
1911 enable_irq(dev->irq);
1913 dev->trans_start = jiffies;
1914 np->stats.tx_errors++;
1915 netif_wake_queue(dev);
1918 static int alloc_ring(struct net_device *dev)
1920 struct netdev_private *np = netdev_priv(dev);
1921 np->rx_ring = pci_alloc_consistent(np->pci_dev,
1922 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1926 np->tx_ring = &np->rx_ring[RX_RING_SIZE];
1930 static void refill_rx(struct net_device *dev)
1932 struct netdev_private *np = netdev_priv(dev);
1934 /* Refill the Rx ring buffers. */
1935 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1936 struct sk_buff *skb;
1937 int entry = np->dirty_rx % RX_RING_SIZE;
1938 if (np->rx_skbuff[entry] == NULL) {
1939 unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING;
1940 skb = dev_alloc_skb(buflen);
1941 np->rx_skbuff[entry] = skb;
1943 break; /* Better luck next round. */
1944 skb->dev = dev; /* Mark as being used by this device. */
1945 np->rx_dma[entry] = pci_map_single(np->pci_dev,
1946 skb->data, buflen, PCI_DMA_FROMDEVICE);
1947 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]);
1949 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz);
1951 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) {
1952 if (netif_msg_rx_err(np))
1953 printk(KERN_WARNING "%s: going OOM.\n", dev->name);
1958 static void set_bufsize(struct net_device *dev)
1960 struct netdev_private *np = netdev_priv(dev);
1961 if (dev->mtu <= ETH_DATA_LEN)
1962 np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS;
1964 np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS;
1967 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1968 static void init_ring(struct net_device *dev)
1970 struct netdev_private *np = netdev_priv(dev);
1974 np->dirty_tx = np->cur_tx = 0;
1975 for (i = 0; i < TX_RING_SIZE; i++) {
1976 np->tx_skbuff[i] = NULL;
1977 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1978 +sizeof(struct netdev_desc)
1979 *((i+1)%TX_RING_SIZE+RX_RING_SIZE));
1980 np->tx_ring[i].cmd_status = 0;
1985 np->cur_rx = RX_RING_SIZE;
1989 np->rx_head_desc = &np->rx_ring[0];
1991 /* Please be carefull before changing this loop - at least gcc-2.95.1
1992 * miscompiles it otherwise.
1994 /* Initialize all Rx descriptors. */
1995 for (i = 0; i < RX_RING_SIZE; i++) {
1996 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1997 +sizeof(struct netdev_desc)
1998 *((i+1)%RX_RING_SIZE));
1999 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2000 np->rx_skbuff[i] = NULL;
2006 static void drain_tx(struct net_device *dev)
2008 struct netdev_private *np = netdev_priv(dev);
2011 for (i = 0; i < TX_RING_SIZE; i++) {
2012 if (np->tx_skbuff[i]) {
2013 pci_unmap_single(np->pci_dev,
2014 np->tx_dma[i], np->tx_skbuff[i]->len,
2016 dev_kfree_skb(np->tx_skbuff[i]);
2017 np->stats.tx_dropped++;
2019 np->tx_skbuff[i] = NULL;
2023 static void drain_rx(struct net_device *dev)
2025 struct netdev_private *np = netdev_priv(dev);
2026 unsigned int buflen = np->rx_buf_sz;
2029 /* Free all the skbuffs in the Rx queue. */
2030 for (i = 0; i < RX_RING_SIZE; i++) {
2031 np->rx_ring[i].cmd_status = 0;
2032 np->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */
2033 if (np->rx_skbuff[i]) {
2034 pci_unmap_single(np->pci_dev,
2035 np->rx_dma[i], buflen,
2036 PCI_DMA_FROMDEVICE);
2037 dev_kfree_skb(np->rx_skbuff[i]);
2039 np->rx_skbuff[i] = NULL;
2043 static void drain_ring(struct net_device *dev)
2049 static void free_ring(struct net_device *dev)
2051 struct netdev_private *np = netdev_priv(dev);
2052 pci_free_consistent(np->pci_dev,
2053 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
2054 np->rx_ring, np->ring_dma);
2057 static void reinit_rx(struct net_device *dev)
2059 struct netdev_private *np = netdev_priv(dev);
2064 np->cur_rx = RX_RING_SIZE;
2065 np->rx_head_desc = &np->rx_ring[0];
2066 /* Initialize all Rx descriptors. */
2067 for (i = 0; i < RX_RING_SIZE; i++)
2068 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2073 static void reinit_ring(struct net_device *dev)
2075 struct netdev_private *np = netdev_priv(dev);
2080 np->dirty_tx = np->cur_tx = 0;
2081 for (i=0;i<TX_RING_SIZE;i++)
2082 np->tx_ring[i].cmd_status = 0;
2087 static int start_tx(struct sk_buff *skb, struct net_device *dev)
2089 struct netdev_private *np = netdev_priv(dev);
2090 void __iomem * ioaddr = ns_ioaddr(dev);
2092 unsigned long flags;
2094 /* Note: Ordering is important here, set the field with the
2095 "ownership" bit last, and only then increment cur_tx. */
2097 /* Calculate the next Tx descriptor entry. */
2098 entry = np->cur_tx % TX_RING_SIZE;
2100 np->tx_skbuff[entry] = skb;
2101 np->tx_dma[entry] = pci_map_single(np->pci_dev,
2102 skb->data,skb->len, PCI_DMA_TODEVICE);
2104 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]);
2106 spin_lock_irqsave(&np->lock, flags);
2108 if (!np->hands_off) {
2109 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
2110 /* StrongARM: Explicitly cache flush np->tx_ring and
2111 * skb->data,skb->len. */
2114 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
2115 netdev_tx_done(dev);
2116 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1)
2117 netif_stop_queue(dev);
2119 /* Wake the potentially-idle transmit channel. */
2120 writel(TxOn, ioaddr + ChipCmd);
2122 dev_kfree_skb_irq(skb);
2123 np->stats.tx_dropped++;
2125 spin_unlock_irqrestore(&np->lock, flags);
2127 dev->trans_start = jiffies;
2129 if (netif_msg_tx_queued(np)) {
2130 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
2131 dev->name, np->cur_tx, entry);
2136 static void netdev_tx_done(struct net_device *dev)
2138 struct netdev_private *np = netdev_priv(dev);
2140 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
2141 int entry = np->dirty_tx % TX_RING_SIZE;
2142 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn))
2144 if (netif_msg_tx_done(np))
2146 "%s: tx frame #%d finished, status %#08x.\n",
2147 dev->name, np->dirty_tx,
2148 le32_to_cpu(np->tx_ring[entry].cmd_status));
2149 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) {
2150 np->stats.tx_packets++;
2151 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
2152 } else { /* Various Tx errors */
2154 le32_to_cpu(np->tx_ring[entry].cmd_status);
2155 if (tx_status & (DescTxAbort|DescTxExcColl))
2156 np->stats.tx_aborted_errors++;
2157 if (tx_status & DescTxFIFO)
2158 np->stats.tx_fifo_errors++;
2159 if (tx_status & DescTxCarrier)
2160 np->stats.tx_carrier_errors++;
2161 if (tx_status & DescTxOOWCol)
2162 np->stats.tx_window_errors++;
2163 np->stats.tx_errors++;
2165 pci_unmap_single(np->pci_dev,np->tx_dma[entry],
2166 np->tx_skbuff[entry]->len,
2168 /* Free the original skb. */
2169 dev_kfree_skb_irq(np->tx_skbuff[entry]);
2170 np->tx_skbuff[entry] = NULL;
2172 if (netif_queue_stopped(dev)
2173 && np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
2174 /* The ring is no longer full, wake queue. */
2175 netif_wake_queue(dev);
2179 /* The interrupt handler doesn't actually handle interrupts itself, it
2180 * schedules a NAPI poll if there is anything to do. */
2181 static irqreturn_t intr_handler(int irq, void *dev_instance)
2183 struct net_device *dev = dev_instance;
2184 struct netdev_private *np = netdev_priv(dev);
2185 void __iomem * ioaddr = ns_ioaddr(dev);
2187 /* Reading IntrStatus automatically acknowledges so don't do
2188 * that while interrupts are disabled, (for example, while a
2189 * poll is scheduled). */
2190 if (np->hands_off || !readl(ioaddr + IntrEnable))
2193 np->intr_status = readl(ioaddr + IntrStatus);
2195 if (!np->intr_status)
2198 if (netif_msg_intr(np))
2200 "%s: Interrupt, status %#08x, mask %#08x.\n",
2201 dev->name, np->intr_status,
2202 readl(ioaddr + IntrMask));
2204 prefetch(&np->rx_skbuff[np->cur_rx % RX_RING_SIZE]);
2206 if (netif_rx_schedule_prep(dev, &np->napi)) {
2207 /* Disable interrupts and register for poll */
2208 natsemi_irq_disable(dev);
2209 __netif_rx_schedule(dev, &np->napi);
2212 "%s: Ignoring interrupt, status %#08x, mask %#08x.\n",
2213 dev->name, np->intr_status,
2214 readl(ioaddr + IntrMask));
2219 /* This is the NAPI poll routine. As well as the standard RX handling
2220 * it also handles all other interrupts that the chip might raise.
2222 static int natsemi_poll(struct napi_struct *napi, int budget)
2224 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
2225 struct net_device *dev = np->dev;
2226 void __iomem * ioaddr = ns_ioaddr(dev);
2230 if (netif_msg_intr(np))
2232 "%s: Poll, status %#08x, mask %#08x.\n",
2233 dev->name, np->intr_status,
2234 readl(ioaddr + IntrMask));
2236 /* netdev_rx() may read IntrStatus again if the RX state
2237 * machine falls over so do it first. */
2238 if (np->intr_status &
2239 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver |
2240 IntrRxErr | IntrRxOverrun)) {
2241 netdev_rx(dev, &work_done, budget);
2244 if (np->intr_status &
2245 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) {
2246 spin_lock(&np->lock);
2247 netdev_tx_done(dev);
2248 spin_unlock(&np->lock);
2251 /* Abnormal error summary/uncommon events handlers. */
2252 if (np->intr_status & IntrAbnormalSummary)
2253 netdev_error(dev, np->intr_status);
2255 if (work_done >= budget)
2258 np->intr_status = readl(ioaddr + IntrStatus);
2259 } while (np->intr_status);
2261 netif_rx_complete(dev, napi);
2263 /* Reenable interrupts providing nothing is trying to shut
2265 spin_lock(&np->lock);
2266 if (!np->hands_off && netif_running(dev))
2267 natsemi_irq_enable(dev);
2268 spin_unlock(&np->lock);
2273 /* This routine is logically part of the interrupt handler, but separated
2274 for clarity and better register allocation. */
2275 static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do)
2277 struct netdev_private *np = netdev_priv(dev);
2278 int entry = np->cur_rx % RX_RING_SIZE;
2279 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
2280 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2281 unsigned int buflen = np->rx_buf_sz;
2282 void __iomem * ioaddr = ns_ioaddr(dev);
2284 /* If the driver owns the next entry it's a new packet. Send it up. */
2285 while (desc_status < 0) { /* e.g. & DescOwn */
2287 if (netif_msg_rx_status(np))
2289 " netdev_rx() entry %d status was %#08x.\n",
2290 entry, desc_status);
2294 if (*work_done >= work_to_do)
2299 pkt_len = (desc_status & DescSizeMask) - 4;
2300 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){
2301 if (desc_status & DescMore) {
2302 unsigned long flags;
2304 if (netif_msg_rx_err(np))
2306 "%s: Oversized(?) Ethernet "
2307 "frame spanned multiple "
2308 "buffers, entry %#08x "
2309 "status %#08x.\n", dev->name,
2310 np->cur_rx, desc_status);
2311 np->stats.rx_length_errors++;
2313 /* The RX state machine has probably
2314 * locked up beneath us. Follow the
2315 * reset procedure documented in
2318 spin_lock_irqsave(&np->lock, flags);
2321 writel(np->ring_dma, ioaddr + RxRingPtr);
2323 spin_unlock_irqrestore(&np->lock, flags);
2325 /* We'll enable RX on exit from this
2330 /* There was an error. */
2331 np->stats.rx_errors++;
2332 if (desc_status & (DescRxAbort|DescRxOver))
2333 np->stats.rx_over_errors++;
2334 if (desc_status & (DescRxLong|DescRxRunt))
2335 np->stats.rx_length_errors++;
2336 if (desc_status & (DescRxInvalid|DescRxAlign))
2337 np->stats.rx_frame_errors++;
2338 if (desc_status & DescRxCRC)
2339 np->stats.rx_crc_errors++;
2341 } else if (pkt_len > np->rx_buf_sz) {
2342 /* if this is the tail of a double buffer
2343 * packet, we've already counted the error
2344 * on the first part. Ignore the second half.
2347 struct sk_buff *skb;
2348 /* Omit CRC size. */
2349 /* Check if the packet is long enough to accept
2350 * without copying to a minimally-sized skbuff. */
2351 if (pkt_len < rx_copybreak
2352 && (skb = dev_alloc_skb(pkt_len + RX_OFFSET)) != NULL) {
2353 /* 16 byte align the IP header */
2354 skb_reserve(skb, RX_OFFSET);
2355 pci_dma_sync_single_for_cpu(np->pci_dev,
2358 PCI_DMA_FROMDEVICE);
2359 skb_copy_to_linear_data(skb,
2360 np->rx_skbuff[entry]->data, pkt_len);
2361 skb_put(skb, pkt_len);
2362 pci_dma_sync_single_for_device(np->pci_dev,
2365 PCI_DMA_FROMDEVICE);
2367 pci_unmap_single(np->pci_dev, np->rx_dma[entry],
2368 buflen, PCI_DMA_FROMDEVICE);
2369 skb_put(skb = np->rx_skbuff[entry], pkt_len);
2370 np->rx_skbuff[entry] = NULL;
2372 skb->protocol = eth_type_trans(skb, dev);
2373 netif_receive_skb(skb);
2374 dev->last_rx = jiffies;
2375 np->stats.rx_packets++;
2376 np->stats.rx_bytes += pkt_len;
2378 entry = (++np->cur_rx) % RX_RING_SIZE;
2379 np->rx_head_desc = &np->rx_ring[entry];
2380 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2384 /* Restart Rx engine if stopped. */
2386 mod_timer(&np->timer, jiffies + 1);
2388 writel(RxOn, ioaddr + ChipCmd);
2391 static void netdev_error(struct net_device *dev, int intr_status)
2393 struct netdev_private *np = netdev_priv(dev);
2394 void __iomem * ioaddr = ns_ioaddr(dev);
2396 spin_lock(&np->lock);
2397 if (intr_status & LinkChange) {
2398 u16 lpa = mdio_read(dev, MII_LPA);
2399 if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE
2400 && netif_msg_link(np)) {
2402 "%s: Autonegotiation advertising"
2403 " %#04x partner %#04x.\n", dev->name,
2404 np->advertising, lpa);
2407 /* read MII int status to clear the flag */
2408 readw(ioaddr + MIntrStatus);
2411 if (intr_status & StatsMax) {
2414 if (intr_status & IntrTxUnderrun) {
2415 if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) {
2416 np->tx_config += TX_DRTH_VAL_INC;
2417 if (netif_msg_tx_err(np))
2419 "%s: increased tx threshold, txcfg %#08x.\n",
2420 dev->name, np->tx_config);
2422 if (netif_msg_tx_err(np))
2424 "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n",
2425 dev->name, np->tx_config);
2427 writel(np->tx_config, ioaddr + TxConfig);
2429 if (intr_status & WOLPkt && netif_msg_wol(np)) {
2430 int wol_status = readl(ioaddr + WOLCmd);
2431 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n",
2432 dev->name, wol_status);
2434 if (intr_status & RxStatusFIFOOver) {
2435 if (netif_msg_rx_err(np) && netif_msg_intr(np)) {
2436 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n",
2439 np->stats.rx_fifo_errors++;
2440 np->stats.rx_errors++;
2442 /* Hmmmmm, it's not clear how to recover from PCI faults. */
2443 if (intr_status & IntrPCIErr) {
2444 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name,
2445 intr_status & IntrPCIErr);
2446 np->stats.tx_fifo_errors++;
2447 np->stats.tx_errors++;
2448 np->stats.rx_fifo_errors++;
2449 np->stats.rx_errors++;
2451 spin_unlock(&np->lock);
2454 static void __get_stats(struct net_device *dev)
2456 void __iomem * ioaddr = ns_ioaddr(dev);
2457 struct netdev_private *np = netdev_priv(dev);
2459 /* The chip only need report frame silently dropped. */
2460 np->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
2461 np->stats.rx_missed_errors += readl(ioaddr + RxMissed);
2464 static struct net_device_stats *get_stats(struct net_device *dev)
2466 struct netdev_private *np = netdev_priv(dev);
2468 /* The chip only need report frame silently dropped. */
2469 spin_lock_irq(&np->lock);
2470 if (netif_running(dev) && !np->hands_off)
2472 spin_unlock_irq(&np->lock);
2477 #ifdef CONFIG_NET_POLL_CONTROLLER
2478 static void natsemi_poll_controller(struct net_device *dev)
2480 disable_irq(dev->irq);
2481 intr_handler(dev->irq, dev);
2482 enable_irq(dev->irq);
2486 #define HASH_TABLE 0x200
2487 static void __set_rx_mode(struct net_device *dev)
2489 void __iomem * ioaddr = ns_ioaddr(dev);
2490 struct netdev_private *np = netdev_priv(dev);
2491 u8 mc_filter[64]; /* Multicast hash filter */
2494 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
2495 rx_mode = RxFilterEnable | AcceptBroadcast
2496 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys;
2497 } else if ((dev->mc_count > multicast_filter_limit)
2498 || (dev->flags & IFF_ALLMULTI)) {
2499 rx_mode = RxFilterEnable | AcceptBroadcast
2500 | AcceptAllMulticast | AcceptMyPhys;
2502 struct dev_mc_list *mclist;
2504 memset(mc_filter, 0, sizeof(mc_filter));
2505 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2506 i++, mclist = mclist->next) {
2507 int i = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 23) & 0x1ff;
2508 mc_filter[i/8] |= (1 << (i & 0x07));
2510 rx_mode = RxFilterEnable | AcceptBroadcast
2511 | AcceptMulticast | AcceptMyPhys;
2512 for (i = 0; i < 64; i += 2) {
2513 writel(HASH_TABLE + i, ioaddr + RxFilterAddr);
2514 writel((mc_filter[i + 1] << 8) + mc_filter[i],
2515 ioaddr + RxFilterData);
2518 writel(rx_mode, ioaddr + RxFilterAddr);
2519 np->cur_rx_mode = rx_mode;
2522 static int natsemi_change_mtu(struct net_device *dev, int new_mtu)
2524 if (new_mtu < 64 || new_mtu > NATSEMI_RX_LIMIT-NATSEMI_HEADERS)
2529 /* synchronized against open : rtnl_lock() held by caller */
2530 if (netif_running(dev)) {
2531 struct netdev_private *np = netdev_priv(dev);
2532 void __iomem * ioaddr = ns_ioaddr(dev);
2534 disable_irq(dev->irq);
2535 spin_lock(&np->lock);
2537 natsemi_stop_rxtx(dev);
2538 /* drain rx queue */
2540 /* change buffers */
2543 writel(np->ring_dma, ioaddr + RxRingPtr);
2544 /* restart engines */
2545 writel(RxOn | TxOn, ioaddr + ChipCmd);
2546 spin_unlock(&np->lock);
2547 enable_irq(dev->irq);
2552 static void set_rx_mode(struct net_device *dev)
2554 struct netdev_private *np = netdev_priv(dev);
2555 spin_lock_irq(&np->lock);
2558 spin_unlock_irq(&np->lock);
2561 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2563 struct netdev_private *np = netdev_priv(dev);
2564 strncpy(info->driver, DRV_NAME, ETHTOOL_BUSINFO_LEN);
2565 strncpy(info->version, DRV_VERSION, ETHTOOL_BUSINFO_LEN);
2566 strncpy(info->bus_info, pci_name(np->pci_dev), ETHTOOL_BUSINFO_LEN);
2569 static int get_regs_len(struct net_device *dev)
2571 return NATSEMI_REGS_SIZE;
2574 static int get_eeprom_len(struct net_device *dev)
2576 struct netdev_private *np = netdev_priv(dev);
2577 return np->eeprom_size;
2580 static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2582 struct netdev_private *np = netdev_priv(dev);
2583 spin_lock_irq(&np->lock);
2584 netdev_get_ecmd(dev, ecmd);
2585 spin_unlock_irq(&np->lock);
2589 static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2591 struct netdev_private *np = netdev_priv(dev);
2593 spin_lock_irq(&np->lock);
2594 res = netdev_set_ecmd(dev, ecmd);
2595 spin_unlock_irq(&np->lock);
2599 static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2601 struct netdev_private *np = netdev_priv(dev);
2602 spin_lock_irq(&np->lock);
2603 netdev_get_wol(dev, &wol->supported, &wol->wolopts);
2604 netdev_get_sopass(dev, wol->sopass);
2605 spin_unlock_irq(&np->lock);
2608 static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2610 struct netdev_private *np = netdev_priv(dev);
2612 spin_lock_irq(&np->lock);
2613 netdev_set_wol(dev, wol->wolopts);
2614 res = netdev_set_sopass(dev, wol->sopass);
2615 spin_unlock_irq(&np->lock);
2619 static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2621 struct netdev_private *np = netdev_priv(dev);
2622 regs->version = NATSEMI_REGS_VER;
2623 spin_lock_irq(&np->lock);
2624 netdev_get_regs(dev, buf);
2625 spin_unlock_irq(&np->lock);
2628 static u32 get_msglevel(struct net_device *dev)
2630 struct netdev_private *np = netdev_priv(dev);
2631 return np->msg_enable;
2634 static void set_msglevel(struct net_device *dev, u32 val)
2636 struct netdev_private *np = netdev_priv(dev);
2637 np->msg_enable = val;
2640 static int nway_reset(struct net_device *dev)
2644 /* if autoneg is off, it's an error */
2645 tmp = mdio_read(dev, MII_BMCR);
2646 if (tmp & BMCR_ANENABLE) {
2647 tmp |= (BMCR_ANRESTART);
2648 mdio_write(dev, MII_BMCR, tmp);
2654 static u32 get_link(struct net_device *dev)
2656 /* LSTATUS is latched low until a read - so read twice */
2657 mdio_read(dev, MII_BMSR);
2658 return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
2661 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
2663 struct netdev_private *np = netdev_priv(dev);
2667 eebuf = kmalloc(np->eeprom_size, GFP_KERNEL);
2671 eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16);
2672 spin_lock_irq(&np->lock);
2673 res = netdev_get_eeprom(dev, eebuf);
2674 spin_unlock_irq(&np->lock);
2676 memcpy(data, eebuf+eeprom->offset, eeprom->len);
2681 static const struct ethtool_ops ethtool_ops = {
2682 .get_drvinfo = get_drvinfo,
2683 .get_regs_len = get_regs_len,
2684 .get_eeprom_len = get_eeprom_len,
2685 .get_settings = get_settings,
2686 .set_settings = set_settings,
2689 .get_regs = get_regs,
2690 .get_msglevel = get_msglevel,
2691 .set_msglevel = set_msglevel,
2692 .nway_reset = nway_reset,
2693 .get_link = get_link,
2694 .get_eeprom = get_eeprom,
2697 static int netdev_set_wol(struct net_device *dev, u32 newval)
2699 struct netdev_private *np = netdev_priv(dev);
2700 void __iomem * ioaddr = ns_ioaddr(dev);
2701 u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;
2703 /* translate to bitmasks this chip understands */
2704 if (newval & WAKE_PHY)
2706 if (newval & WAKE_UCAST)
2707 data |= WakeUnicast;
2708 if (newval & WAKE_MCAST)
2709 data |= WakeMulticast;
2710 if (newval & WAKE_BCAST)
2711 data |= WakeBroadcast;
2712 if (newval & WAKE_ARP)
2714 if (newval & WAKE_MAGIC)
2716 if (np->srr >= SRR_DP83815_D) {
2717 if (newval & WAKE_MAGICSECURE) {
2718 data |= WakeMagicSecure;
2722 writel(data, ioaddr + WOLCmd);
2727 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
2729 struct netdev_private *np = netdev_priv(dev);
2730 void __iomem * ioaddr = ns_ioaddr(dev);
2731 u32 regval = readl(ioaddr + WOLCmd);
2733 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
2734 | WAKE_ARP | WAKE_MAGIC);
2736 if (np->srr >= SRR_DP83815_D) {
2737 /* SOPASS works on revD and higher */
2738 *supported |= WAKE_MAGICSECURE;
2742 /* translate from chip bitmasks */
2743 if (regval & WakePhy)
2745 if (regval & WakeUnicast)
2747 if (regval & WakeMulticast)
2749 if (regval & WakeBroadcast)
2751 if (regval & WakeArp)
2753 if (regval & WakeMagic)
2755 if (regval & WakeMagicSecure) {
2756 /* this can be on in revC, but it's broken */
2757 *cur |= WAKE_MAGICSECURE;
2763 static int netdev_set_sopass(struct net_device *dev, u8 *newval)
2765 struct netdev_private *np = netdev_priv(dev);
2766 void __iomem * ioaddr = ns_ioaddr(dev);
2767 u16 *sval = (u16 *)newval;
2770 if (np->srr < SRR_DP83815_D) {
2774 /* enable writing to these registers by disabling the RX filter */
2775 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2776 addr &= ~RxFilterEnable;
2777 writel(addr, ioaddr + RxFilterAddr);
2779 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */
2780 writel(addr | 0xa, ioaddr + RxFilterAddr);
2781 writew(sval[0], ioaddr + RxFilterData);
2783 writel(addr | 0xc, ioaddr + RxFilterAddr);
2784 writew(sval[1], ioaddr + RxFilterData);
2786 writel(addr | 0xe, ioaddr + RxFilterAddr);
2787 writew(sval[2], ioaddr + RxFilterData);
2789 /* re-enable the RX filter */
2790 writel(addr | RxFilterEnable, ioaddr + RxFilterAddr);
2795 static int netdev_get_sopass(struct net_device *dev, u8 *data)
2797 struct netdev_private *np = netdev_priv(dev);
2798 void __iomem * ioaddr = ns_ioaddr(dev);
2799 u16 *sval = (u16 *)data;
2802 if (np->srr < SRR_DP83815_D) {
2803 sval[0] = sval[1] = sval[2] = 0;
2807 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */
2808 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2810 writel(addr | 0xa, ioaddr + RxFilterAddr);
2811 sval[0] = readw(ioaddr + RxFilterData);
2813 writel(addr | 0xc, ioaddr + RxFilterAddr);
2814 sval[1] = readw(ioaddr + RxFilterData);
2816 writel(addr | 0xe, ioaddr + RxFilterAddr);
2817 sval[2] = readw(ioaddr + RxFilterData);
2819 writel(addr, ioaddr + RxFilterAddr);
2824 static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2826 struct netdev_private *np = netdev_priv(dev);
2829 ecmd->port = dev->if_port;
2830 ecmd->speed = np->speed;
2831 ecmd->duplex = np->duplex;
2832 ecmd->autoneg = np->autoneg;
2833 ecmd->advertising = 0;
2834 if (np->advertising & ADVERTISE_10HALF)
2835 ecmd->advertising |= ADVERTISED_10baseT_Half;
2836 if (np->advertising & ADVERTISE_10FULL)
2837 ecmd->advertising |= ADVERTISED_10baseT_Full;
2838 if (np->advertising & ADVERTISE_100HALF)
2839 ecmd->advertising |= ADVERTISED_100baseT_Half;
2840 if (np->advertising & ADVERTISE_100FULL)
2841 ecmd->advertising |= ADVERTISED_100baseT_Full;
2842 ecmd->supported = (SUPPORTED_Autoneg |
2843 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2844 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2845 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE);
2846 ecmd->phy_address = np->phy_addr_external;
2848 * We intentionally report the phy address of the external
2849 * phy, even if the internal phy is used. This is necessary
2850 * to work around a deficiency of the ethtool interface:
2851 * It's only possible to query the settings of the active
2853 * # ethtool -s ethX port mii
2854 * actually sends an ioctl to switch to port mii with the
2855 * settings that are used for the current active port.
2856 * If we would report a different phy address in this
2858 * # ethtool -s ethX port tp;ethtool -s ethX port mii
2859 * would unintentionally change the phy address.
2861 * Fortunately the phy address doesn't matter with the
2865 /* set information based on active port type */
2866 switch (ecmd->port) {
2869 ecmd->advertising |= ADVERTISED_TP;
2870 ecmd->transceiver = XCVR_INTERNAL;
2873 ecmd->advertising |= ADVERTISED_MII;
2874 ecmd->transceiver = XCVR_EXTERNAL;
2877 ecmd->advertising |= ADVERTISED_FIBRE;
2878 ecmd->transceiver = XCVR_EXTERNAL;
2882 /* if autonegotiation is on, try to return the active speed/duplex */
2883 if (ecmd->autoneg == AUTONEG_ENABLE) {
2884 ecmd->advertising |= ADVERTISED_Autoneg;
2885 tmp = mii_nway_result(
2886 np->advertising & mdio_read(dev, MII_LPA));
2887 if (tmp == LPA_100FULL || tmp == LPA_100HALF)
2888 ecmd->speed = SPEED_100;
2890 ecmd->speed = SPEED_10;
2891 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
2892 ecmd->duplex = DUPLEX_FULL;
2894 ecmd->duplex = DUPLEX_HALF;
2897 /* ignore maxtxpkt, maxrxpkt for now */
2902 static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2904 struct netdev_private *np = netdev_priv(dev);
2906 if (ecmd->port != PORT_TP && ecmd->port != PORT_MII && ecmd->port != PORT_FIBRE)
2908 if (ecmd->transceiver != XCVR_INTERNAL && ecmd->transceiver != XCVR_EXTERNAL)
2910 if (ecmd->autoneg == AUTONEG_ENABLE) {
2911 if ((ecmd->advertising & (ADVERTISED_10baseT_Half |
2912 ADVERTISED_10baseT_Full |
2913 ADVERTISED_100baseT_Half |
2914 ADVERTISED_100baseT_Full)) == 0) {
2917 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2918 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2920 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2927 * If we're ignoring the PHY then autoneg and the internal
2928 * transciever are really not going to work so don't let the
2931 if (np->ignore_phy && (ecmd->autoneg == AUTONEG_ENABLE ||
2932 ecmd->port == PORT_TP))
2936 * maxtxpkt, maxrxpkt: ignored for now.
2939 * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always
2940 * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and
2941 * selects based on ecmd->port.
2943 * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre
2944 * phys that are connected to the mii bus. It's used to apply fibre
2948 /* WHEW! now lets bang some bits */
2950 /* save the parms */
2951 dev->if_port = ecmd->port;
2952 np->autoneg = ecmd->autoneg;
2953 np->phy_addr_external = ecmd->phy_address & PhyAddrMask;
2954 if (np->autoneg == AUTONEG_ENABLE) {
2955 /* advertise only what has been requested */
2956 np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2957 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2958 np->advertising |= ADVERTISE_10HALF;
2959 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2960 np->advertising |= ADVERTISE_10FULL;
2961 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2962 np->advertising |= ADVERTISE_100HALF;
2963 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2964 np->advertising |= ADVERTISE_100FULL;
2966 np->speed = ecmd->speed;
2967 np->duplex = ecmd->duplex;
2968 /* user overriding the initial full duplex parm? */
2969 if (np->duplex == DUPLEX_HALF)
2970 np->full_duplex = 0;
2973 /* get the right phy enabled */
2974 if (ecmd->port == PORT_TP)
2975 switch_port_internal(dev);
2977 switch_port_external(dev);
2979 /* set parms and see how this affected our link status */
2980 init_phy_fixup(dev);
2985 static int netdev_get_regs(struct net_device *dev, u8 *buf)
2990 u32 *rbuf = (u32 *)buf;
2991 void __iomem * ioaddr = ns_ioaddr(dev);
2993 /* read non-mii page 0 of registers */
2994 for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) {
2995 rbuf[i] = readl(ioaddr + i*4);
2998 /* read current mii registers */
2999 for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++)
3000 rbuf[i] = mdio_read(dev, i & 0x1f);
3002 /* read only the 'magic' registers from page 1 */
3003 writew(1, ioaddr + PGSEL);
3004 rbuf[i++] = readw(ioaddr + PMDCSR);
3005 rbuf[i++] = readw(ioaddr + TSTDAT);
3006 rbuf[i++] = readw(ioaddr + DSPCFG);
3007 rbuf[i++] = readw(ioaddr + SDCFG);
3008 writew(0, ioaddr + PGSEL);
3010 /* read RFCR indexed registers */
3011 rfcr = readl(ioaddr + RxFilterAddr);
3012 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) {
3013 writel(j*2, ioaddr + RxFilterAddr);
3014 rbuf[i++] = readw(ioaddr + RxFilterData);
3016 writel(rfcr, ioaddr + RxFilterAddr);
3018 /* the interrupt status is clear-on-read - see if we missed any */
3019 if (rbuf[4] & rbuf[5]) {
3021 "%s: shoot, we dropped an interrupt (%#08x)\n",
3022 dev->name, rbuf[4] & rbuf[5]);
3028 #define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \
3029 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \
3030 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \
3031 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \
3032 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \
3033 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \
3034 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \
3035 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) )
3037 static int netdev_get_eeprom(struct net_device *dev, u8 *buf)
3040 u16 *ebuf = (u16 *)buf;
3041 void __iomem * ioaddr = ns_ioaddr(dev);
3042 struct netdev_private *np = netdev_priv(dev);
3044 /* eeprom_read reads 16 bits, and indexes by 16 bits */
3045 for (i = 0; i < np->eeprom_size/2; i++) {
3046 ebuf[i] = eeprom_read(ioaddr, i);
3047 /* The EEPROM itself stores data bit-swapped, but eeprom_read
3048 * reads it back "sanely". So we swap it back here in order to
3049 * present it to userland as it is stored. */
3050 ebuf[i] = SWAP_BITS(ebuf[i]);
3055 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3057 struct mii_ioctl_data *data = if_mii(rq);
3058 struct netdev_private *np = netdev_priv(dev);
3061 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
3062 case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
3063 data->phy_id = np->phy_addr_external;
3066 case SIOCGMIIREG: /* Read MII PHY register. */
3067 case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
3068 /* The phy_id is not enough to uniquely identify
3069 * the intended target. Therefore the command is sent to
3070 * the given mii on the current port.
3072 if (dev->if_port == PORT_TP) {
3073 if ((data->phy_id & 0x1f) == np->phy_addr_external)
3074 data->val_out = mdio_read(dev,
3075 data->reg_num & 0x1f);
3079 move_int_phy(dev, data->phy_id & 0x1f);
3080 data->val_out = miiport_read(dev, data->phy_id & 0x1f,
3081 data->reg_num & 0x1f);
3085 case SIOCSMIIREG: /* Write MII PHY register. */
3086 case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
3087 if (!capable(CAP_NET_ADMIN))
3089 if (dev->if_port == PORT_TP) {
3090 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3091 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3092 np->advertising = data->val_in;
3093 mdio_write(dev, data->reg_num & 0x1f,
3097 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3098 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3099 np->advertising = data->val_in;
3101 move_int_phy(dev, data->phy_id & 0x1f);
3102 miiport_write(dev, data->phy_id & 0x1f,
3103 data->reg_num & 0x1f,
3112 static void enable_wol_mode(struct net_device *dev, int enable_intr)
3114 void __iomem * ioaddr = ns_ioaddr(dev);
3115 struct netdev_private *np = netdev_priv(dev);
3117 if (netif_msg_wol(np))
3118 printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
3121 /* For WOL we must restart the rx process in silent mode.
3122 * Write NULL to the RxRingPtr. Only possible if
3123 * rx process is stopped
3125 writel(0, ioaddr + RxRingPtr);
3127 /* read WoL status to clear */
3128 readl(ioaddr + WOLCmd);
3130 /* PME on, clear status */
3131 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
3133 /* and restart the rx process */
3134 writel(RxOn, ioaddr + ChipCmd);
3137 /* enable the WOL interrupt.
3138 * Could be used to send a netlink message.
3140 writel(WOLPkt | LinkChange, ioaddr + IntrMask);
3141 natsemi_irq_enable(dev);
3145 static int netdev_close(struct net_device *dev)
3147 void __iomem * ioaddr = ns_ioaddr(dev);
3148 struct netdev_private *np = netdev_priv(dev);
3150 if (netif_msg_ifdown(np))
3152 "%s: Shutting down ethercard, status was %#04x.\n",
3153 dev->name, (int)readl(ioaddr + ChipCmd));
3154 if (netif_msg_pktdata(np))
3156 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
3157 dev->name, np->cur_tx, np->dirty_tx,
3158 np->cur_rx, np->dirty_rx);
3160 napi_disable(&np->napi);
3163 * FIXME: what if someone tries to close a device
3164 * that is suspended?
3165 * Should we reenable the nic to switch to
3166 * the final WOL settings?
3169 del_timer_sync(&np->timer);
3170 disable_irq(dev->irq);
3171 spin_lock_irq(&np->lock);
3172 natsemi_irq_disable(dev);
3174 spin_unlock_irq(&np->lock);
3175 enable_irq(dev->irq);
3177 free_irq(dev->irq, dev);
3179 /* Interrupt disabled, interrupt handler released,
3180 * queue stopped, timer deleted, rtnl_lock held
3181 * All async codepaths that access the driver are disabled.
3183 spin_lock_irq(&np->lock);
3185 readl(ioaddr + IntrMask);
3186 readw(ioaddr + MIntrStatus);
3189 writel(StatsFreeze, ioaddr + StatsCtrl);
3191 /* Stop the chip's Tx and Rx processes. */
3192 natsemi_stop_rxtx(dev);
3195 spin_unlock_irq(&np->lock);
3197 /* clear the carrier last - an interrupt could reenable it otherwise */
3198 netif_carrier_off(dev);
3199 netif_stop_queue(dev);
3206 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3208 /* restart the NIC in WOL mode.
3209 * The nic must be stopped for this.
3211 enable_wol_mode(dev, 0);
3213 /* Restore PME enable bit unmolested */
3214 writel(np->SavedClkRun, ioaddr + ClkRun);
3221 static void __devexit natsemi_remove1 (struct pci_dev *pdev)
3223 struct net_device *dev = pci_get_drvdata(pdev);
3224 void __iomem * ioaddr = ns_ioaddr(dev);
3226 NATSEMI_REMOVE_FILE(pdev, dspcfg_workaround);
3227 unregister_netdev (dev);
3228 pci_release_regions (pdev);
3231 pci_set_drvdata(pdev, NULL);
3237 * The ns83815 chip doesn't have explicit RxStop bits.
3238 * Kicking the Rx or Tx process for a new packet reenables the Rx process
3239 * of the nic, thus this function must be very careful:
3241 * suspend/resume synchronization:
3243 * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler,
3244 * start_tx, tx_timeout
3246 * No function accesses the hardware without checking np->hands_off.
3247 * the check occurs under spin_lock_irq(&np->lock);
3249 * * netdev_ioctl: noncritical access.
3250 * * netdev_open: cannot happen due to the device_detach
3251 * * netdev_close: doesn't hurt.
3252 * * netdev_timer: timer stopped by natsemi_suspend.
3253 * * intr_handler: doesn't acquire the spinlock. suspend calls
3254 * disable_irq() to enforce synchronization.
3255 * * natsemi_poll: checks before reenabling interrupts. suspend
3256 * sets hands_off, disables interrupts and then waits with
3259 * Interrupts must be disabled, otherwise hands_off can cause irq storms.
3262 static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state)
3264 struct net_device *dev = pci_get_drvdata (pdev);
3265 struct netdev_private *np = netdev_priv(dev);
3266 void __iomem * ioaddr = ns_ioaddr(dev);
3269 if (netif_running (dev)) {
3270 del_timer_sync(&np->timer);
3272 disable_irq(dev->irq);
3273 spin_lock_irq(&np->lock);
3275 natsemi_irq_disable(dev);
3277 natsemi_stop_rxtx(dev);
3278 netif_stop_queue(dev);
3280 spin_unlock_irq(&np->lock);
3281 enable_irq(dev->irq);
3283 napi_disable(&np->napi);
3285 /* Update the error counts. */
3288 /* pci_power_off(pdev, -1); */
3291 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3292 /* Restore PME enable bit */
3294 /* restart the NIC in WOL mode.
3295 * The nic must be stopped for this.
3296 * FIXME: use the WOL interrupt
3298 enable_wol_mode(dev, 0);
3300 /* Restore PME enable bit unmolested */
3301 writel(np->SavedClkRun, ioaddr + ClkRun);
3305 netif_device_detach(dev);
3311 static int natsemi_resume (struct pci_dev *pdev)
3313 struct net_device *dev = pci_get_drvdata (pdev);
3314 struct netdev_private *np = netdev_priv(dev);
3317 if (netif_device_present(dev))
3319 if (netif_running(dev)) {
3320 BUG_ON(!np->hands_off);
3321 pci_enable_device(pdev);
3322 /* pci_power_on(pdev); */
3324 napi_enable(&np->napi);
3328 disable_irq(dev->irq);
3329 spin_lock_irq(&np->lock);
3331 init_registers(dev);
3332 netif_device_attach(dev);
3333 spin_unlock_irq(&np->lock);
3334 enable_irq(dev->irq);
3336 mod_timer(&np->timer, jiffies + 1*HZ);
3338 netif_device_attach(dev);
3344 #endif /* CONFIG_PM */
3346 static struct pci_driver natsemi_driver = {
3348 .id_table = natsemi_pci_tbl,
3349 .probe = natsemi_probe1,
3350 .remove = __devexit_p(natsemi_remove1),
3352 .suspend = natsemi_suspend,
3353 .resume = natsemi_resume,
3357 static int __init natsemi_init_mod (void)
3359 /* when a module, this is printed whether or not devices are found in probe */
3364 return pci_register_driver(&natsemi_driver);
3367 static void __exit natsemi_exit_mod (void)
3369 pci_unregister_driver (&natsemi_driver);
3372 module_init(natsemi_init_mod);
3373 module_exit(natsemi_exit_mod);