2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
14 config RWSEM_GENERIC_SPINLOCK
17 config RWSEM_XCHGADD_ALGORITHM
22 select HAVE_FUNCTION_GRAPH_TRACER
23 select HAVE_FUNCTION_TRACER
25 select HAVE_KERNEL_GZIP
26 select HAVE_KERNEL_BZIP2
27 select HAVE_KERNEL_LZMA
29 select ARCH_WANT_OPTIONAL_GPIOLIB
38 config GENERIC_FIND_NEXT_BIT
41 config GENERIC_HWEIGHT
44 config GENERIC_HARDIRQS
47 config GENERIC_IRQ_PROBE
53 config FORCE_MAX_ZONEORDER
57 config GENERIC_CALIBRATE_DELAY
60 config LOCKDEP_SUPPORT
63 config STACKTRACE_SUPPORT
66 config TRACE_IRQFLAGS_SUPPORT
71 source "kernel/Kconfig.preempt"
73 source "kernel/Kconfig.freezer"
75 menu "Blackfin Processor Options"
77 comment "Processor and Board Settings"
86 BF512 Processor Support.
91 BF514 Processor Support.
96 BF516 Processor Support.
101 BF518 Processor Support.
106 BF522 Processor Support.
111 BF523 Processor Support.
116 BF524 Processor Support.
121 BF525 Processor Support.
126 BF526 Processor Support.
131 BF527 Processor Support.
136 BF531 Processor Support.
141 BF532 Processor Support.
146 BF533 Processor Support.
151 BF534 Processor Support.
156 BF536 Processor Support.
161 BF537 Processor Support.
166 BF538 Processor Support.
171 BF539 Processor Support.
176 BF542 Processor Support.
181 BF542 Processor Support.
186 BF544 Processor Support.
191 BF544 Processor Support.
196 BF547 Processor Support.
201 BF547 Processor Support.
206 BF548 Processor Support.
211 BF548 Processor Support.
216 BF549 Processor Support.
221 BF549 Processor Support.
226 BF561 Processor Support.
233 bool "Symmetric multi-processing support"
235 This enables support for systems with more than one CPU,
236 like the dual core BF561. If you have a system with only one
237 CPU, say N. If you have a system with more than one CPU, say Y.
239 If you don't know what to do here, say N.
253 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
254 default 2 if (BF537 || BF536 || BF534)
255 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
256 default 4 if (BF538 || BF539)
260 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
261 default 3 if (BF537 || BF536 || BF534 || BF54xM)
262 default 5 if (BF561 || BF538 || BF539)
263 default 6 if (BF533 || BF532 || BF531)
267 default BF_REV_0_0 if (BF51x || BF52x)
268 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
269 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
273 depends on (BF51x || BF52x || (BF54x && !BF54xM))
277 depends on (BF52x || (BF54x && !BF54xM))
281 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
285 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
289 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
293 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
297 depends on (BF533 || BF532 || BF531)
309 depends on (BF512 || BF514 || BF516 || BF518)
314 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
319 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
324 depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
329 depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
332 config MEM_GENERIC_BOARD
334 depends on GENERIC_BOARD
337 config MEM_MT48LC64M4A2FB_7E
339 depends on (BFIN533_STAMP)
342 config MEM_MT48LC16M16A2TG_75
344 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
345 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
346 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
349 config MEM_MT48LC32M8A2_75
351 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
354 config MEM_MT48LC8M32B2B5_7
356 depends on (BFIN561_BLUETECHNIX_CM)
359 config MEM_MT48LC32M16A2TG_75
361 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
364 config MEM_MT48LC32M8A2_75
366 depends on (BFIN518F_EZBRD)
369 source "arch/blackfin/mach-bf518/Kconfig"
370 source "arch/blackfin/mach-bf527/Kconfig"
371 source "arch/blackfin/mach-bf533/Kconfig"
372 source "arch/blackfin/mach-bf561/Kconfig"
373 source "arch/blackfin/mach-bf537/Kconfig"
374 source "arch/blackfin/mach-bf538/Kconfig"
375 source "arch/blackfin/mach-bf548/Kconfig"
377 menu "Board customizations"
380 bool "Default bootloader kernel arguments"
383 string "Initial kernel command string"
384 depends on CMDLINE_BOOL
385 default "console=ttyBF0,57600"
387 If you don't have a boot loader capable of passing a command line string
388 to the kernel, you may specify one here. As a minimum, you should specify
389 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
392 hex "Kernel load address for booting"
394 range 0x1000 0x20000000
396 This option allows you to set the load address of the kernel.
397 This can be useful if you are on a board which has a small amount
398 of memory or you wish to reserve some memory at the beginning of
401 Note that you need to keep this value above 4k (0x1000) as this
402 memory region is used to capture NULL pointer references as well
403 as some core kernel functions.
406 hex "Kernel ROM Base"
409 range 0x20000000 0x20400000 if !(BF54x || BF561)
410 range 0x20000000 0x30000000 if (BF54x || BF561)
413 comment "Clock/PLL Setup"
416 int "Frequency of the crystal on the board in Hz"
417 default "10000000" if BFIN532_IP0X
418 default "11059200" if BFIN533_STAMP
419 default "24576000" if PNAV10
420 default "25000000" # most people use this
421 default "27000000" if BFIN533_EZKIT
422 default "30000000" if BFIN561_EZKIT
424 The frequency of CLKIN crystal oscillator on the board in Hz.
425 Warning: This value should match the crystal on the board. Otherwise,
426 peripherals won't work properly.
428 config BFIN_KERNEL_CLOCK
429 bool "Re-program Clocks while Kernel boots?"
432 This option decides if kernel clocks are re-programed from the
433 bootloader settings. If the clocks are not set, the SDRAM settings
434 are also not changed, and the Bootloader does 100% of the hardware
439 depends on BFIN_KERNEL_CLOCK
444 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
447 If this is set the clock will be divided by 2, before it goes to the PLL.
451 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
453 default "22" if BFIN533_EZKIT
454 default "45" if BFIN533_STAMP
455 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
456 default "22" if BFIN533_BLUETECHNIX_CM
457 default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
458 default "20" if BFIN561_EZKIT
459 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
461 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
462 PLL Frequency = (Crystal Frequency) * (this setting)
465 prompt "Core Clock Divider"
466 depends on BFIN_KERNEL_CLOCK
469 This sets the frequency of the core. It can be 1, 2, 4 or 8
470 Core Frequency = (PLL frequency) / (this setting)
486 int "System Clock Divider"
487 depends on BFIN_KERNEL_CLOCK
491 This sets the frequency of the system clock (including SDRAM or DDR).
492 This can be between 1 and 15
493 System Clock = (PLL frequency) / (this setting)
496 prompt "DDR SDRAM Chip Type"
497 depends on BFIN_KERNEL_CLOCK
499 default MEM_MT46V32M16_5B
501 config MEM_MT46V32M16_6T
504 config MEM_MT46V32M16_5B
509 prompt "DDR/SDRAM Timing"
510 depends on BFIN_KERNEL_CLOCK
511 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
513 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
514 The calculated SDRAM timing parameters may not be 100%
515 accurate - This option is therefore marked experimental.
517 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
518 bool "Calculate Timings (EXPERIMENTAL)"
519 depends on EXPERIMENTAL
521 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
522 bool "Provide accurate Timings based on target SCLK"
524 Please consult the Blackfin Hardware Reference Manuals as well
525 as the memory device datasheet.
526 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
529 menu "Memory Init Control"
530 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
547 config MEM_EBIU_DDRQUE
564 # Max & Min Speeds for various Chips
568 default 400000000 if BF512
569 default 400000000 if BF514
570 default 400000000 if BF516
571 default 400000000 if BF518
572 default 600000000 if BF522
573 default 400000000 if BF523
574 default 400000000 if BF524
575 default 600000000 if BF525
576 default 400000000 if BF526
577 default 600000000 if BF527
578 default 400000000 if BF531
579 default 400000000 if BF532
580 default 750000000 if BF533
581 default 500000000 if BF534
582 default 400000000 if BF536
583 default 600000000 if BF537
584 default 533333333 if BF538
585 default 533333333 if BF539
586 default 600000000 if BF542
587 default 533333333 if BF544
588 default 600000000 if BF547
589 default 600000000 if BF548
590 default 533333333 if BF549
591 default 600000000 if BF561
605 comment "Kernel Timer/Scheduler"
607 source kernel/Kconfig.hz
613 config GENERIC_CLOCKEVENTS
614 bool "Generic clock events"
615 depends on GENERIC_TIME
619 prompt "Kernel Tick Source"
620 depends on GENERIC_CLOCKEVENTS
621 default TICKSOURCE_CORETMR
623 config TICKSOURCE_GPTMR0
624 bool "Gptimer0 (SCLK domain)"
628 config TICKSOURCE_CORETMR
629 bool "Core timer (CCLK domain)"
633 config CYCLES_CLOCKSOURCE
634 bool "Use 'CYCLES' as a clocksource"
635 depends on GENERIC_CLOCKEVENTS
636 depends on !BFIN_SCRATCH_REG_CYCLES
639 If you say Y here, you will enable support for using the 'cycles'
640 registers as a clock source. Doing so means you will be unable to
641 safely write to the 'cycles' register during runtime. You will
642 still be able to read it (such as for performance monitoring), but
643 writing the registers will most likely crash the kernel.
645 config GPTMR0_CLOCKSOURCE
646 bool "Use GPTimer0 as a clocksource (higher rating)"
647 depends on GENERIC_CLOCKEVENTS
648 depends on !TICKSOURCE_GPTMR0
650 source kernel/time/Kconfig
655 prompt "Blackfin Exception Scratch Register"
656 default BFIN_SCRATCH_REG_RETN
658 Select the resource to reserve for the Exception handler:
659 - RETN: Non-Maskable Interrupt (NMI)
660 - RETE: Exception Return (JTAG/ICE)
661 - CYCLES: Performance counter
663 If you are unsure, please select "RETN".
665 config BFIN_SCRATCH_REG_RETN
668 Use the RETN register in the Blackfin exception handler
669 as a stack scratch register. This means you cannot
670 safely use NMI on the Blackfin while running Linux, but
671 you can debug the system with a JTAG ICE and use the
672 CYCLES performance registers.
674 If you are unsure, please select "RETN".
676 config BFIN_SCRATCH_REG_RETE
679 Use the RETE register in the Blackfin exception handler
680 as a stack scratch register. This means you cannot
681 safely use a JTAG ICE while debugging a Blackfin board,
682 but you can safely use the CYCLES performance registers
685 If you are unsure, please select "RETN".
687 config BFIN_SCRATCH_REG_CYCLES
690 Use the CYCLES register in the Blackfin exception handler
691 as a stack scratch register. This means you cannot
692 safely use the CYCLES performance registers on a Blackfin
693 board at anytime, but you can debug the system with a JTAG
696 If you are unsure, please select "RETN".
703 menu "Blackfin Kernel Optimizations"
706 comment "Memory Optimizations"
709 bool "Locate interrupt entry code in L1 Memory"
712 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
713 into L1 instruction memory. (less latency)
715 config EXCPT_IRQ_SYSC_L1
716 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
719 If enabled, the entire ASM lowlevel exception and interrupt entry code
720 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
724 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
727 If enabled, the frequently called do_irq dispatcher function is linked
728 into L1 instruction memory. (less latency)
730 config CORE_TIMER_IRQ_L1
731 bool "Locate frequently called timer_interrupt() function in L1 Memory"
734 If enabled, the frequently called timer_interrupt() function is linked
735 into L1 instruction memory. (less latency)
738 bool "Locate frequently idle function in L1 Memory"
741 If enabled, the frequently called idle function is linked
742 into L1 instruction memory. (less latency)
745 bool "Locate kernel schedule function in L1 Memory"
748 If enabled, the frequently called kernel schedule is linked
749 into L1 instruction memory. (less latency)
751 config ARITHMETIC_OPS_L1
752 bool "Locate kernel owned arithmetic functions in L1 Memory"
755 If enabled, arithmetic functions are linked
756 into L1 instruction memory. (less latency)
759 bool "Locate access_ok function in L1 Memory"
762 If enabled, the access_ok function is linked
763 into L1 instruction memory. (less latency)
766 bool "Locate memset function in L1 Memory"
769 If enabled, the memset function is linked
770 into L1 instruction memory. (less latency)
773 bool "Locate memcpy function in L1 Memory"
776 If enabled, the memcpy function is linked
777 into L1 instruction memory. (less latency)
779 config SYS_BFIN_SPINLOCK_L1
780 bool "Locate sys_bfin_spinlock function in L1 Memory"
783 If enabled, sys_bfin_spinlock function is linked
784 into L1 instruction memory. (less latency)
786 config IP_CHECKSUM_L1
787 bool "Locate IP Checksum function in L1 Memory"
790 If enabled, the IP Checksum function is linked
791 into L1 instruction memory. (less latency)
793 config CACHELINE_ALIGNED_L1
794 bool "Locate cacheline_aligned data to L1 Data Memory"
799 If enabled, cacheline_aligned data is linked
800 into L1 data memory. (less latency)
802 config SYSCALL_TAB_L1
803 bool "Locate Syscall Table L1 Data Memory"
807 If enabled, the Syscall LUT is linked
808 into L1 data memory. (less latency)
810 config CPLB_SWITCH_TAB_L1
811 bool "Locate CPLB Switch Tables L1 Data Memory"
815 If enabled, the CPLB Switch Tables are linked
816 into L1 data memory. (less latency)
819 bool "Support locating application stack in L1 Scratch Memory"
822 If enabled the application stack can be located in L1
823 scratch memory (less latency).
825 Currently only works with FLAT binaries.
827 config EXCEPTION_L1_SCRATCH
828 bool "Locate exception stack in L1 Scratch Memory"
830 depends on !APP_STACK_L1
832 Whenever an exception occurs, use the L1 Scratch memory for
833 stack storage. You cannot place the stacks of FLAT binaries
834 in L1 when using this option.
836 If you don't use L1 Scratch, then you should say Y here.
838 comment "Speed Optimizations"
839 config BFIN_INS_LOWOVERHEAD
840 bool "ins[bwl] low overhead, higher interrupt latency"
843 Reads on the Blackfin are speculative. In Blackfin terms, this means
844 they can be interrupted at any time (even after they have been issued
845 on to the external bus), and re-issued after the interrupt occurs.
846 For memory - this is not a big deal, since memory does not change if
849 If a FIFO is sitting on the end of the read, it will see two reads,
850 when the core only sees one since the FIFO receives both the read
851 which is cancelled (and not delivered to the core) and the one which
852 is re-issued (which is delivered to the core).
854 To solve this, interrupts are turned off before reads occur to
855 I/O space. This option controls which the overhead/latency of
856 controlling interrupts during this time
857 "n" turns interrupts off every read
858 (higher overhead, but lower interrupt latency)
859 "y" turns interrupts off every loop
860 (low overhead, but longer interrupt latency)
862 default behavior is to leave this set to on (type "Y"). If you are experiencing
863 interrupt latency issues, it is safe and OK to turn this off.
868 prompt "Kernel executes from"
870 Choose the memory type that the kernel will be running in.
875 The kernel will be resident in RAM when running.
880 The kernel will be resident in FLASH/ROM when running.
887 tristate "Enable Blackfin General Purpose Timers API"
890 Enable support for the General Purpose Timers API. If you
893 To compile this driver as a module, choose M here: the module
894 will be called gptimers.
897 prompt "Uncached DMA region"
898 default DMA_UNCACHED_1M
899 config DMA_UNCACHED_4M
900 bool "Enable 4M DMA region"
901 config DMA_UNCACHED_2M
902 bool "Enable 2M DMA region"
903 config DMA_UNCACHED_1M
904 bool "Enable 1M DMA region"
905 config DMA_UNCACHED_NONE
906 bool "Disable DMA region"
910 comment "Cache Support"
915 config BFIN_DCACHE_BANKA
916 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
917 depends on BFIN_DCACHE && !BF531
919 config BFIN_ICACHE_LOCK
920 bool "Enable Instruction Cache Locking"
923 prompt "External memory cache policy"
924 depends on BFIN_DCACHE
925 default BFIN_WB if !SMP
926 default BFIN_WT if SMP
932 Cached data will be written back to SDRAM only when needed.
933 This can give a nice increase in performance, but beware of
934 broken drivers that do not properly invalidate/flush their
937 Write Through Policy:
938 Cached data will always be written back to SDRAM when the
939 cache is updated. This is a completely safe setting, but
940 performance is worse than Write Back.
942 If you are unsure of the options and you want to be safe,
943 then go with Write Through.
949 Cached data will be written back to SDRAM only when needed.
950 This can give a nice increase in performance, but beware of
951 broken drivers that do not properly invalidate/flush their
954 Write Through Policy:
955 Cached data will always be written back to SDRAM when the
956 cache is updated. This is a completely safe setting, but
957 performance is worse than Write Back.
959 If you are unsure of the options and you want to be safe,
960 then go with Write Through.
965 prompt "L2 SRAM cache policy"
966 depends on (BF54x || BF561)
976 config BFIN_L2_NOT_CACHED
982 bool "Enable the memory protection unit (EXPERIMENTAL)"
985 Use the processor's MPU to protect applications from accessing
986 memory they do not own. This comes at a performance penalty
987 and is recommended only for debugging.
989 comment "Asynchronous Memory Configuration"
991 menu "EBIU_AMGCTL Global Control"
997 bool "DMA has priority over core for ext. accesses"
1002 bool "Bank 0 16 bit packing enable"
1007 bool "Bank 1 16 bit packing enable"
1012 bool "Bank 2 16 bit packing enable"
1017 bool "Bank 3 16 bit packing enable"
1021 prompt "Enable Asynchronous Memory Banks"
1025 bool "Disable All Banks"
1028 bool "Enable Bank 0"
1030 config C_AMBEN_B0_B1
1031 bool "Enable Bank 0 & 1"
1033 config C_AMBEN_B0_B1_B2
1034 bool "Enable Bank 0 & 1 & 2"
1037 bool "Enable All Banks"
1041 menu "EBIU_AMBCTL Control"
1043 hex "Bank 0 (AMBCTL0.L)"
1046 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1047 used to control the Asynchronous Memory Bank 0 settings.
1050 hex "Bank 1 (AMBCTL0.H)"
1052 default 0x5558 if BF54x
1054 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1055 used to control the Asynchronous Memory Bank 1 settings.
1058 hex "Bank 2 (AMBCTL1.L)"
1061 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1062 used to control the Asynchronous Memory Bank 2 settings.
1065 hex "Bank 3 (AMBCTL1.H)"
1068 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1069 used to control the Asynchronous Memory Bank 3 settings.
1073 config EBIU_MBSCTLVAL
1074 hex "EBIU Bank Select Control Register"
1079 hex "Flash Memory Mode Control Register"
1084 hex "Flash Memory Bank Control Register"
1089 #############################################################################
1090 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1096 Support for PCI bus.
1098 source "drivers/pci/Kconfig"
1101 bool "Support for hot-pluggable device"
1103 Say Y here if you want to plug devices into your computer while
1104 the system is running, and be able to use them quickly. In many
1105 cases, the devices can likewise be unplugged at any time too.
1107 One well known example of this is PCMCIA- or PC-cards, credit-card
1108 size devices such as network cards, modems or hard drives which are
1109 plugged into slots found on all modern laptop computers. Another
1110 example, used on modern desktops as well as laptops, is USB.
1112 Enable HOTPLUG and build a modular kernel. Get agent software
1113 (from <http://linux-hotplug.sourceforge.net/>) and install it.
1114 Then your kernel will automatically call out to a user mode "policy
1115 agent" (/sbin/hotplug) to load modules and set up software needed
1116 to use devices as you hotplug them.
1118 source "drivers/pcmcia/Kconfig"
1120 source "drivers/pci/hotplug/Kconfig"
1124 menu "Executable file formats"
1126 source "fs/Kconfig.binfmt"
1130 menu "Power management options"
1131 source "kernel/power/Kconfig"
1133 config ARCH_SUSPEND_POSSIBLE
1138 prompt "Standby Power Saving Mode"
1140 default PM_BFIN_SLEEP_DEEPER
1141 config PM_BFIN_SLEEP_DEEPER
1144 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1145 power dissipation by disabling the clock to the processor core (CCLK).
1146 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1147 to 0.85 V to provide the greatest power savings, while preserving the
1149 The PLL and system clock (SCLK) continue to operate at a very low
1150 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1151 the SDRAM is put into Self Refresh Mode. Typically an external event
1152 such as GPIO interrupt or RTC activity wakes up the processor.
1153 Various Peripherals such as UART, SPORT, PPI may not function as
1154 normal during Sleep Deeper, due to the reduced SCLK frequency.
1155 When in the sleep mode, system DMA access to L1 memory is not supported.
1157 If unsure, select "Sleep Deeper".
1159 config PM_BFIN_SLEEP
1162 Sleep Mode (High Power Savings) - The sleep mode reduces power
1163 dissipation by disabling the clock to the processor core (CCLK).
1164 The PLL and system clock (SCLK), however, continue to operate in
1165 this mode. Typically an external event or RTC activity will wake
1166 up the processor. When in the sleep mode, system DMA access to L1
1167 memory is not supported.
1169 If unsure, select "Sleep Deeper".
1172 config PM_WAKEUP_BY_GPIO
1173 bool "Allow Wakeup from Standby by GPIO"
1174 depends on PM && !BF54x
1176 config PM_WAKEUP_GPIO_NUMBER
1179 depends on PM_WAKEUP_BY_GPIO
1183 prompt "GPIO Polarity"
1184 depends on PM_WAKEUP_BY_GPIO
1185 default PM_WAKEUP_GPIO_POLAR_H
1186 config PM_WAKEUP_GPIO_POLAR_H
1188 config PM_WAKEUP_GPIO_POLAR_L
1190 config PM_WAKEUP_GPIO_POLAR_EDGE_F
1192 config PM_WAKEUP_GPIO_POLAR_EDGE_R
1194 config PM_WAKEUP_GPIO_POLAR_EDGE_B
1198 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1201 config PM_BFIN_WAKE_PH6
1202 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1203 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1206 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1208 config PM_BFIN_WAKE_GP
1209 bool "Allow Wake-Up from GPIOs"
1210 depends on PM && BF54x
1213 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1214 (all processors, except ADSP-BF549). This option sets
1215 the general-purpose wake-up enable (GPWE) control bit to enable
1216 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1217 On ADSP-BF549 this option enables the the same functionality on the
1218 /MRXON pin also PH7.
1222 menu "CPU Frequency scaling"
1224 source "drivers/cpufreq/Kconfig"
1226 config BFIN_CPU_FREQ
1229 select CPU_FREQ_TABLE
1233 bool "CPU Voltage scaling"
1234 depends on EXPERIMENTAL
1238 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1239 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1240 manuals. There is a theoretical risk that during VDDINT transitions
1245 source "net/Kconfig"
1247 source "drivers/Kconfig"
1251 source "arch/blackfin/Kconfig.debug"
1253 source "security/Kconfig"
1255 source "crypto/Kconfig"
1257 source "lib/Kconfig"
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