2 * linux/arch/arm/plat-mxc/dma-mx1-mx2.c
4 * i.MX DMA registration and IRQ dispatching
6 * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
7 * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
8 * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
25 #include <linux/module.h>
26 #include <linux/init.h>
27 #include <linux/kernel.h>
28 #include <linux/interrupt.h>
29 #include <linux/errno.h>
30 #include <linux/clk.h>
31 #include <linux/scatterlist.h>
34 #include <asm/system.h>
36 #include <mach/hardware.h>
38 #include <mach/dma-mx1-mx2.h>
40 #define DMA_DCR 0x00 /* Control Register */
41 #define DMA_DISR 0x04 /* Interrupt status Register */
42 #define DMA_DIMR 0x08 /* Interrupt mask Register */
43 #define DMA_DBTOSR 0x0c /* Burst timeout status Register */
44 #define DMA_DRTOSR 0x10 /* Request timeout Register */
45 #define DMA_DSESR 0x14 /* Transfer Error Status Register */
46 #define DMA_DBOSR 0x18 /* Buffer overflow status Register */
47 #define DMA_DBTOCR 0x1c /* Burst timeout control Register */
48 #define DMA_WSRA 0x40 /* W-Size Register A */
49 #define DMA_XSRA 0x44 /* X-Size Register A */
50 #define DMA_YSRA 0x48 /* Y-Size Register A */
51 #define DMA_WSRB 0x4c /* W-Size Register B */
52 #define DMA_XSRB 0x50 /* X-Size Register B */
53 #define DMA_YSRB 0x54 /* Y-Size Register B */
54 #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
55 #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
56 #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
57 #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
58 #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
59 #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
60 #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
61 #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
62 #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
64 #define DCR_DRST (1<<1)
65 #define DCR_DEN (1<<0)
66 #define DBTOCR_EN (1<<15)
67 #define DBTOCR_CNT(x) ((x) & 0x7fff)
68 #define CNTR_CNT(x) ((x) & 0xffffff)
69 #define CCR_ACRPT (1<<14)
70 #define CCR_DMOD_LINEAR (0x0 << 12)
71 #define CCR_DMOD_2D (0x1 << 12)
72 #define CCR_DMOD_FIFO (0x2 << 12)
73 #define CCR_DMOD_EOBFIFO (0x3 << 12)
74 #define CCR_SMOD_LINEAR (0x0 << 10)
75 #define CCR_SMOD_2D (0x1 << 10)
76 #define CCR_SMOD_FIFO (0x2 << 10)
77 #define CCR_SMOD_EOBFIFO (0x3 << 10)
78 #define CCR_MDIR_DEC (1<<9)
79 #define CCR_MSEL_B (1<<8)
80 #define CCR_DSIZ_32 (0x0 << 6)
81 #define CCR_DSIZ_8 (0x1 << 6)
82 #define CCR_DSIZ_16 (0x2 << 6)
83 #define CCR_SSIZ_32 (0x0 << 4)
84 #define CCR_SSIZ_8 (0x1 << 4)
85 #define CCR_SSIZ_16 (0x2 << 4)
86 #define CCR_REN (1<<3)
87 #define CCR_RPT (1<<2)
88 #define CCR_FRC (1<<1)
89 #define CCR_CEN (1<<0)
90 #define RTOR_EN (1<<15)
91 #define RTOR_CLK (1<<14)
92 #define RTOR_PSC (1<<13)
95 * struct imx_dma_channel - i.MX specific DMA extension
96 * @name: name specified by DMA client
97 * @irq_handler: client callback for end of transfer
98 * @err_handler: client callback for error condition
99 * @data: clients context data for callbacks
100 * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
101 * @sg: pointer to the actual read/written chunk for scatter-gather emulation
102 * @resbytes: total residual number of bytes to transfer
103 * (it can be lower or same as sum of SG mapped chunk sizes)
104 * @sgcount: number of chunks to be read/written
106 * Structure is used for IMX DMA processing. It would be probably good
107 * @struct dma_struct in the future for external interfacing and use
108 * @struct imx_dma_channel only as extension to it.
111 struct imx_dma_channel {
113 void (*irq_handler) (int, void *);
114 void (*err_handler) (int, void *, int errcode);
115 void (*prog_handler) (int, void *, struct scatterlist *);
118 struct scatterlist *sg;
119 unsigned int resbytes;
127 struct timer_list watchdog;
132 static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
134 static struct clk *dma_clk;
136 static int imx_dma_hw_chain(struct imx_dma_channel *imxdma)
139 return imxdma->hw_chaining;
146 * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
148 static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
150 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
154 printk(KERN_CRIT "%s: called for not allocated channel %d\n",
159 now = min(imxdma->resbytes, sg->length);
160 imxdma->resbytes -= now;
162 if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
163 __raw_writel(sg->dma_address, DMA_BASE + DMA_DAR(channel));
165 __raw_writel(sg->dma_address, DMA_BASE + DMA_SAR(channel));
167 __raw_writel(now, DMA_BASE + DMA_CNTR(channel));
169 pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
170 "size 0x%08x\n", channel,
171 __raw_readl(DMA_BASE + DMA_DAR(channel)),
172 __raw_readl(DMA_BASE + DMA_SAR(channel)),
173 __raw_readl(DMA_BASE + DMA_CNTR(channel)));
179 * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from
182 * @channel: i.MX DMA channel number
183 * @dma_address: the DMA/physical memory address of the linear data block
185 * @dma_length: length of the data block in bytes
186 * @dev_addr: physical device port address
187 * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
188 * or %DMA_MODE_WRITE from memory to the device
190 * Return value: if incorrect parameters are provided -%EINVAL.
191 * Zero indicates success.
194 imx_dma_setup_single(int channel, dma_addr_t dma_address,
195 unsigned int dma_length, unsigned int dev_addr,
198 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
201 imxdma->dma_mode = dmamode;
204 printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
210 printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
215 if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
216 pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
217 "dev_addr=0x%08x for read\n",
218 channel, __func__, (unsigned int)dma_address,
219 dma_length, dev_addr);
221 __raw_writel(dev_addr, DMA_BASE + DMA_SAR(channel));
222 __raw_writel(dma_address, DMA_BASE + DMA_DAR(channel));
223 __raw_writel(imxdma->ccr_from_device,
224 DMA_BASE + DMA_CCR(channel));
225 } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
226 pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
227 "dev_addr=0x%08x for write\n",
228 channel, __func__, (unsigned int)dma_address,
229 dma_length, dev_addr);
231 __raw_writel(dma_address, DMA_BASE + DMA_SAR(channel));
232 __raw_writel(dev_addr, DMA_BASE + DMA_DAR(channel));
233 __raw_writel(imxdma->ccr_to_device,
234 DMA_BASE + DMA_CCR(channel));
236 printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
241 __raw_writel(dma_length, DMA_BASE + DMA_CNTR(channel));
245 EXPORT_SYMBOL(imx_dma_setup_single);
248 * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
249 * @channel: i.MX DMA channel number
250 * @sg: pointer to the scatter-gather list/vector
251 * @sgcount: scatter-gather list hungs count
252 * @dma_length: total length of the transfer request in bytes
253 * @dev_addr: physical device port address
254 * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
255 * or %DMA_MODE_WRITE from memory to the device
257 * The function sets up DMA channel state and registers to be ready for
258 * transfer specified by provided parameters. The scatter-gather emulation
259 * is set up according to the parameters.
261 * The full preparation of the transfer requires setup of more register
262 * by the caller before imx_dma_enable() can be called.
264 * %BLR(channel) holds transfer burst length in bytes, 0 means 64 bytes
266 * %RSSR(channel) has to be set to the DMA request line source %DMA_REQ_xxx
268 * %CCR(channel) has to specify transfer parameters, the next settings is
269 * typical for linear or simple scatter-gather transfers if %DMA_MODE_READ is
272 * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
274 * The typical setup for %DMA_MODE_WRITE is specified by next options
277 * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
279 * Be careful here and do not mistakenly mix source and target device
280 * port sizes constants, they are really different:
281 * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
282 * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
284 * Return value: if incorrect parameters are provided -%EINVAL.
285 * Zero indicates success.
288 imx_dma_setup_sg(int channel,
289 struct scatterlist *sg, unsigned int sgcount,
290 unsigned int dma_length, unsigned int dev_addr,
293 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
299 imxdma->dma_mode = dmamode;
300 imxdma->resbytes = dma_length;
302 if (!sg || !sgcount) {
303 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg epty sg list\n",
309 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
314 if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
315 pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
316 "dev_addr=0x%08x for read\n",
317 channel, __func__, sg, sgcount, dma_length, dev_addr);
319 __raw_writel(dev_addr, DMA_BASE + DMA_SAR(channel));
320 __raw_writel(imxdma->ccr_from_device,
321 DMA_BASE + DMA_CCR(channel));
322 } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
323 pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
324 "dev_addr=0x%08x for write\n",
325 channel, __func__, sg, sgcount, dma_length, dev_addr);
327 __raw_writel(dev_addr, DMA_BASE + DMA_DAR(channel));
328 __raw_writel(imxdma->ccr_to_device,
329 DMA_BASE + DMA_CCR(channel));
331 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
336 imx_dma_sg_next(channel, sg);
340 EXPORT_SYMBOL(imx_dma_setup_sg);
343 imx_dma_config_channel(int channel, unsigned int config_port,
344 unsigned int config_mem, unsigned int dmareq, int hw_chaining)
346 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
349 imxdma->hw_chaining = 0;
352 imxdma->hw_chaining = 1;
353 if (!imx_dma_hw_chain(imxdma))
360 imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq;
361 imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq;
363 __raw_writel(dmareq, DMA_BASE + DMA_RSSR(channel));
367 EXPORT_SYMBOL(imx_dma_config_channel);
369 void imx_dma_config_burstlen(int channel, unsigned int burstlen)
371 __raw_writel(burstlen, DMA_BASE + DMA_BLR(channel));
373 EXPORT_SYMBOL(imx_dma_config_burstlen);
376 * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification
378 * @channel: i.MX DMA channel number
379 * @irq_handler: the pointer to the function called if the transfer
381 * @err_handler: the pointer to the function called if the premature
382 * end caused by error occurs
383 * @data: user specified value to be passed to the handlers
386 imx_dma_setup_handlers(int channel,
387 void (*irq_handler) (int, void *),
388 void (*err_handler) (int, void *, int),
391 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
395 printk(KERN_CRIT "%s: called for not allocated channel %d\n",
400 local_irq_save(flags);
401 __raw_writel(1 << channel, DMA_BASE + DMA_DISR);
402 imxdma->irq_handler = irq_handler;
403 imxdma->err_handler = err_handler;
405 local_irq_restore(flags);
408 EXPORT_SYMBOL(imx_dma_setup_handlers);
411 * imx_dma_setup_progression_handler - setup i.MX DMA channel progression
413 * @channel: i.MX DMA channel number
414 * @prog_handler: the pointer to the function called if the transfer progresses
417 imx_dma_setup_progression_handler(int channel,
418 void (*prog_handler) (int, void*, struct scatterlist*))
420 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
424 printk(KERN_CRIT "%s: called for not allocated channel %d\n",
429 local_irq_save(flags);
430 imxdma->prog_handler = prog_handler;
431 local_irq_restore(flags);
434 EXPORT_SYMBOL(imx_dma_setup_progression_handler);
437 * imx_dma_enable - function to start i.MX DMA channel operation
438 * @channel: i.MX DMA channel number
440 * The channel has to be allocated by driver through imx_dma_request()
441 * or imx_dma_request_by_prio() function.
442 * The transfer parameters has to be set to the channel registers through
443 * call of the imx_dma_setup_single() or imx_dma_setup_sg() function
444 * and registers %BLR(channel), %RSSR(channel) and %CCR(channel) has to
445 * be set prior this function call by the channel user.
447 void imx_dma_enable(int channel)
449 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
452 pr_debug("imxdma%d: imx_dma_enable\n", channel);
455 printk(KERN_CRIT "%s: called for not allocated channel %d\n",
463 local_irq_save(flags);
465 __raw_writel(1 << channel, DMA_BASE + DMA_DISR);
466 __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) & ~(1 << channel),
467 DMA_BASE + DMA_DIMR);
468 __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) | CCR_CEN |
470 DMA_BASE + DMA_CCR(channel));
472 #ifdef CONFIG_ARCH_MX2
473 if (imxdma->sg && imx_dma_hw_chain(imxdma)) {
474 imxdma->sg = sg_next(imxdma->sg);
477 imx_dma_sg_next(channel, imxdma->sg);
478 tmp = __raw_readl(DMA_BASE + DMA_CCR(channel));
479 __raw_writel(tmp | CCR_RPT | CCR_ACRPT,
480 DMA_BASE + DMA_CCR(channel));
486 local_irq_restore(flags);
488 EXPORT_SYMBOL(imx_dma_enable);
491 * imx_dma_disable - stop, finish i.MX DMA channel operatin
492 * @channel: i.MX DMA channel number
494 void imx_dma_disable(int channel)
496 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
499 pr_debug("imxdma%d: imx_dma_disable\n", channel);
501 if (imx_dma_hw_chain(imxdma))
502 del_timer(&imxdma->watchdog);
504 local_irq_save(flags);
505 __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) | (1 << channel),
506 DMA_BASE + DMA_DIMR);
507 __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) & ~CCR_CEN,
508 DMA_BASE + DMA_CCR(channel));
509 __raw_writel(1 << channel, DMA_BASE + DMA_DISR);
511 local_irq_restore(flags);
513 EXPORT_SYMBOL(imx_dma_disable);
515 static void imx_dma_watchdog(unsigned long chno)
517 struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
519 __raw_writel(0, DMA_BASE + DMA_CCR(chno));
523 if (imxdma->err_handler)
524 imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
527 static irqreturn_t dma_err_handler(int irq, void *dev_id)
530 struct imx_dma_channel *imxdma;
531 unsigned int err_mask;
534 disr = __raw_readl(DMA_BASE + DMA_DISR);
536 err_mask = __raw_readl(DMA_BASE + DMA_DBTOSR) |
537 __raw_readl(DMA_BASE + DMA_DRTOSR) |
538 __raw_readl(DMA_BASE + DMA_DSESR) |
539 __raw_readl(DMA_BASE + DMA_DBOSR);
544 __raw_writel(disr & err_mask, DMA_BASE + DMA_DISR);
546 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
547 if (!(err_mask & (1 << i)))
549 imxdma = &imx_dma_channels[i];
552 if (__raw_readl(DMA_BASE + DMA_DBTOSR) & (1 << i)) {
553 __raw_writel(1 << i, DMA_BASE + DMA_DBTOSR);
554 errcode |= IMX_DMA_ERR_BURST;
556 if (__raw_readl(DMA_BASE + DMA_DRTOSR) & (1 << i)) {
557 __raw_writel(1 << i, DMA_BASE + DMA_DRTOSR);
558 errcode |= IMX_DMA_ERR_REQUEST;
560 if (__raw_readl(DMA_BASE + DMA_DSESR) & (1 << i)) {
561 __raw_writel(1 << i, DMA_BASE + DMA_DSESR);
562 errcode |= IMX_DMA_ERR_TRANSFER;
564 if (__raw_readl(DMA_BASE + DMA_DBOSR) & (1 << i)) {
565 __raw_writel(1 << i, DMA_BASE + DMA_DBOSR);
566 errcode |= IMX_DMA_ERR_BUFFER;
568 if (imxdma->name && imxdma->err_handler) {
569 imxdma->err_handler(i, imxdma->data, errcode);
573 imx_dma_channels[i].sg = NULL;
576 "DMA timeout on channel %d (%s) -%s%s%s%s\n",
578 errcode & IMX_DMA_ERR_BURST ? " burst" : "",
579 errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
580 errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
581 errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
586 static void dma_irq_handle_channel(int chno)
588 struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
592 * IRQ for an unregistered DMA channel:
593 * let's clear the interrupts and disable it.
596 "spurious IRQ for DMA channel %d\n", chno);
602 struct scatterlist *current_sg = imxdma->sg;
603 imxdma->sg = sg_next(imxdma->sg);
606 imx_dma_sg_next(chno, imxdma->sg);
608 tmp = __raw_readl(DMA_BASE + DMA_CCR(chno));
610 if (imx_dma_hw_chain(imxdma)) {
611 /* FIXME: The timeout should probably be
614 mod_timer(&imxdma->watchdog,
615 jiffies + msecs_to_jiffies(500));
617 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
618 __raw_writel(tmp, DMA_BASE +
621 __raw_writel(tmp & ~CCR_CEN, DMA_BASE +
626 __raw_writel(tmp, DMA_BASE + DMA_CCR(chno));
628 if (imxdma->prog_handler)
629 imxdma->prog_handler(chno, imxdma->data,
635 if (imx_dma_hw_chain(imxdma)) {
636 del_timer(&imxdma->watchdog);
641 __raw_writel(0, DMA_BASE + DMA_CCR(chno));
643 if (imxdma->irq_handler)
644 imxdma->irq_handler(chno, imxdma->data);
647 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
651 #ifdef CONFIG_ARCH_MX2
652 dma_err_handler(irq, dev_id);
655 disr = __raw_readl(DMA_BASE + DMA_DISR);
657 pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
660 __raw_writel(disr, DMA_BASE + DMA_DISR);
661 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
663 dma_irq_handle_channel(i);
670 * imx_dma_request - request/allocate specified channel number
671 * @channel: i.MX DMA channel number
672 * @name: the driver/caller own non-%NULL identification
674 int imx_dma_request(int channel, const char *name)
676 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
680 /* basic sanity checks */
684 if (channel >= IMX_DMA_CHANNELS) {
685 printk(KERN_CRIT "%s: called for non-existed channel %d\n",
690 local_irq_save(flags);
692 local_irq_restore(flags);
696 #ifdef CONFIG_ARCH_MX2
697 ret = request_irq(MXC_INT_DMACH0 + channel, dma_irq_handler, 0, "DMA",
700 printk(KERN_CRIT "Can't register IRQ %d for DMA channel %d\n",
701 MXC_INT_DMACH0 + channel, channel);
704 init_timer(&imxdma->watchdog);
705 imxdma->watchdog.function = &imx_dma_watchdog;
706 imxdma->watchdog.data = channel;
710 imxdma->irq_handler = NULL;
711 imxdma->err_handler = NULL;
715 local_irq_restore(flags);
718 EXPORT_SYMBOL(imx_dma_request);
721 * imx_dma_free - release previously acquired channel
722 * @channel: i.MX DMA channel number
724 void imx_dma_free(int channel)
727 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
731 "%s: trying to free free channel %d\n",
736 local_irq_save(flags);
737 /* Disable interrupts */
738 __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) | (1 << channel),
739 DMA_BASE + DMA_DIMR);
740 __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) & ~CCR_CEN,
741 DMA_BASE + DMA_CCR(channel));
744 #ifdef CONFIG_ARCH_MX2
745 free_irq(MXC_INT_DMACH0 + channel, NULL);
748 local_irq_restore(flags);
750 EXPORT_SYMBOL(imx_dma_free);
753 * imx_dma_request_by_prio - find and request some of free channels best
754 * suiting requested priority
755 * @channel: i.MX DMA channel number
756 * @name: the driver/caller own non-%NULL identification
758 * This function tries to find a free channel in the specified priority group
759 * This function tries to find a free channel in the specified priority group
760 * if the priority cannot be achieved it tries to look for free channel
761 * in the higher and then even lower priority groups.
763 * Return value: If there is no free channel to allocate, -%ENODEV is returned.
764 * On successful allocation channel is returned.
766 int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio)
772 case (DMA_PRIO_HIGH):
775 case (DMA_PRIO_MEDIUM):
784 for (i = best; i < IMX_DMA_CHANNELS; i++)
785 if (!imx_dma_request(i, name))
788 for (i = best - 1; i >= 0; i--)
789 if (!imx_dma_request(i, name))
792 printk(KERN_ERR "%s: no free DMA channel found\n", __func__);
796 EXPORT_SYMBOL(imx_dma_request_by_prio);
798 static int __init imx_dma_init(void)
803 dma_clk = clk_get(NULL, "dma_clk");
806 /* reset DMA module */
807 __raw_writel(DCR_DRST, DMA_BASE + DMA_DCR);
809 #ifdef CONFIG_ARCH_MX1
810 ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL);
812 printk(KERN_CRIT "Wow! Can't register IRQ for DMA\n");
816 ret = request_irq(DMA_ERR, dma_err_handler, 0, "DMA", NULL);
818 printk(KERN_CRIT "Wow! Can't register ERRIRQ for DMA\n");
819 free_irq(DMA_INT, NULL);
823 /* enable DMA module */
824 __raw_writel(DCR_DEN, DMA_BASE + DMA_DCR);
826 /* clear all interrupts */
827 __raw_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_BASE + DMA_DISR);
829 /* disable interrupts */
830 __raw_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_BASE + DMA_DIMR);
832 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
833 imx_dma_channels[i].sg = NULL;
834 imx_dma_channels[i].dma_num = i;
840 arch_initcall(imx_dma_init);