Merge git://git.skbuff.net/gitroot/yoshfuji/linux-2.6.14+advapi-fix/
[linux-2.6] / arch / mips / mips-boards / malta / malta_setup.c
1 /*
2  * Carsten Langgaard, carstenl@mips.com
3  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
4  *
5  *  This program is free software; you can distribute it and/or modify it
6  *  under the terms of the GNU General Public License (Version 2) as
7  *  published by the Free Software Foundation.
8  *
9  *  This program is distributed in the hope it will be useful, but WITHOUT
10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12  *  for more details.
13  *
14  *  You should have received a copy of the GNU General Public License along
15  *  with this program; if not, write to the Free Software Foundation, Inc.,
16  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17  */
18 #include <linux/config.h>
19 #include <linux/init.h>
20 #include <linux/sched.h>
21 #include <linux/ioport.h>
22 #include <linux/pci.h>
23 #include <linux/tty.h>
24
25 #ifdef CONFIG_MTD
26 #include <linux/mtd/partitions.h>
27 #include <linux/mtd/physmap.h>
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/map.h>
30 #endif
31
32 #include <asm/cpu.h>
33 #include <asm/bootinfo.h>
34 #include <asm/irq.h>
35 #include <asm/mips-boards/generic.h>
36 #include <asm/mips-boards/prom.h>
37 #include <asm/mips-boards/malta.h>
38 #include <asm/mips-boards/maltaint.h>
39 #include <asm/dma.h>
40 #include <asm/time.h>
41 #include <asm/traps.h>
42 #ifdef CONFIG_VT
43 #include <linux/console.h>
44 #endif
45
46 extern void mips_reboot_setup(void);
47 extern void mips_time_init(void);
48 extern void mips_timer_setup(struct irqaction *irq);
49 extern unsigned long mips_rtc_get_time(void);
50
51 #ifdef CONFIG_KGDB
52 extern void kgdb_config(void);
53 #endif
54
55 struct resource standard_io_resources[] = {
56         { "dma1", 0x00, 0x1f, IORESOURCE_BUSY },
57         { "timer", 0x40, 0x5f, IORESOURCE_BUSY },
58         { "keyboard", 0x60, 0x6f, IORESOURCE_BUSY },
59         { "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY },
60         { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
61 };
62
63 #ifdef CONFIG_MTD
64 static struct mtd_partition malta_mtd_partitions[] = {
65         {
66                 .name =         "YAMON",
67                 .offset =       0x0,
68                 .size =         0x100000,
69                 .mask_flags =   MTD_WRITEABLE
70         },
71         {
72                 .name =         "User FS",
73                 .offset =       0x100000,
74                 .size =         0x2e0000
75         },
76         {
77                 .name =         "Board Config",
78                 .offset =       0x3e0000,
79                 .size =         0x020000,
80                 .mask_flags =   MTD_WRITEABLE
81         }
82 };
83
84 #define number_partitions       (sizeof(malta_mtd_partitions)/sizeof(struct mtd_partition))
85 #endif
86
87 const char *get_system_type(void)
88 {
89         return "MIPS Malta";
90 }
91
92 #ifdef CONFIG_BLK_DEV_FD
93 void __init fd_activate(void)
94 {
95         /*
96          * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
97          * Controller.
98          * Done by YAMON 2.00 onwards
99          */
100         /* Entering config state. */
101         SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
102
103         /* Activate floppy controller. */
104         SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
105         SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
106         SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
107         SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
108
109         /* Exit config state. */
110         SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
111 }
112 #endif
113
114 void __init plat_setup(void)
115 {
116         unsigned int i;
117
118         mips_pcibios_init();
119
120         /* Request I/O space for devices used on the Malta board. */
121         for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
122                 request_resource(&ioport_resource, standard_io_resources+i);
123
124         /*
125          * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
126          */
127         enable_dma(4);
128
129 #ifdef CONFIG_KGDB
130         kgdb_config ();
131 #endif
132
133         if ((mips_revision_corid == MIPS_REVISION_CORID_BONITO64) ||
134             (mips_revision_corid == MIPS_REVISION_CORID_CORE_20K) ||
135             (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL_BON)) {
136                 char *argptr;
137
138                 argptr = prom_getcmdline();
139                 if (strstr(argptr, "debug")) {
140                         BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
141                         printk ("Enabled Bonito debug mode\n");
142                 }
143                 else
144                         BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
145
146 #ifdef CONFIG_DMA_COHERENT
147                 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
148                         BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
149                         printk("Enabled Bonito CPU coherency\n");
150
151                         argptr = prom_getcmdline();
152                         if (strstr(argptr, "iobcuncached")) {
153                                 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
154                                 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
155                                         ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
156                                           BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
157                                 printk("Disabled Bonito IOBC coherency\n");
158                         }
159                         else {
160                                 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
161                                 BONITO_PCIMEMBASECFG |=
162                                         (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
163                                          BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
164                                 printk("Disabled Bonito IOBC coherency\n");
165                         }
166                 }
167                 else
168                         panic("Hardware DMA cache coherency not supported");
169
170 #endif
171         }
172 #ifdef CONFIG_DMA_COHERENT
173         else {
174                 panic("Hardware DMA cache coherency not supported");
175         }
176 #endif
177
178 #ifdef CONFIG_BLK_DEV_IDE
179         /* Check PCI clock */
180         {
181                 int jmpr = (*((volatile unsigned int *)ioremap(MALTA_JMPRS_REG, sizeof(unsigned int))) >> 2) & 0x07;
182                 static const int pciclocks[] __initdata = {
183                         33, 20, 25, 30, 12, 16, 37, 10
184                 };
185                 int pciclock = pciclocks[jmpr];
186                 char *argptr = prom_getcmdline();
187
188                 if (pciclock != 33 && !strstr (argptr, "idebus=")) {
189                         printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock);
190                         argptr += strlen(argptr);
191                         sprintf (argptr, " idebus=%d", pciclock);
192                         if (pciclock < 20 || pciclock > 66)
193                                 printk ("WARNING: IDE timing calculations will be incorrect\n");
194                 }
195         }
196 #endif
197 #ifdef CONFIG_BLK_DEV_FD
198         fd_activate ();
199 #endif
200 #ifdef CONFIG_VT
201 #if defined(CONFIG_VGA_CONSOLE)
202         screen_info = (struct screen_info) {
203                 0, 25,                  /* orig-x, orig-y */
204                 0,                      /* unused */
205                 0,                      /* orig-video-page */
206                 0,                      /* orig-video-mode */
207                 80,                     /* orig-video-cols */
208                 0,0,0,                  /* ega_ax, ega_bx, ega_cx */
209                 25,                     /* orig-video-lines */
210                 VIDEO_TYPE_VGAC,        /* orig-video-isVGA */
211                 16                      /* orig-video-points */
212         };
213 #endif
214 #endif
215
216 #ifdef CONFIG_MTD
217         /*
218          * Support for MTD on Malta. Use the generic physmap driver
219          */
220         physmap_configure(0x1e000000, 0x400000, 4, NULL);
221         physmap_set_partitions(malta_mtd_partitions, number_partitions);
222 #endif
223
224         mips_reboot_setup();
225
226         board_time_init = mips_time_init;
227         board_timer_setup = mips_timer_setup;
228         rtc_get_time = mips_rtc_get_time;
229 }