git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "core.h"
  21 #include "hw.h"
  22 #include "reg.h"
  23 #include "phy.h"
  24 #include "initvals.h"
  25
  26 static void ath9k_hw_iqcal_collect(struct ath_hal *ah);
  27 static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains);
  28 static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah);
  29 static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah,
  30                                            u8 numChains);
  31 static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah);
  32 static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah,
  33                                          u8 numChains);
  34
  35 static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
  36 static const int16_t NOISE_FLOOR[] = { -96, -93, -98, -96, -93, -96 };
  37
  38 static const struct hal_percal_data iq_cal_multi_sample = {
  39         IQ_MISMATCH_CAL,
  40         MAX_CAL_SAMPLES,
  41         PER_MIN_LOG_COUNT,
  42         ath9k_hw_iqcal_collect,
  43         ath9k_hw_iqcalibrate
  44 };
  45 static const struct hal_percal_data iq_cal_single_sample = {
  46         IQ_MISMATCH_CAL,
  47         MIN_CAL_SAMPLES,
  48         PER_MAX_LOG_COUNT,
  49         ath9k_hw_iqcal_collect,
  50         ath9k_hw_iqcalibrate
  51 };
  52 static const struct hal_percal_data adc_gain_cal_multi_sample = {
  53         ADC_GAIN_CAL,
  54         MAX_CAL_SAMPLES,
  55         PER_MIN_LOG_COUNT,
  56         ath9k_hw_adc_gaincal_collect,
  57         ath9k_hw_adc_gaincal_calibrate
  58 };
  59 static const struct hal_percal_data adc_gain_cal_single_sample = {
  60         ADC_GAIN_CAL,
  61         MIN_CAL_SAMPLES,
  62         PER_MAX_LOG_COUNT,
  63         ath9k_hw_adc_gaincal_collect,
  64         ath9k_hw_adc_gaincal_calibrate
  65 };
  66 static const struct hal_percal_data adc_dc_cal_multi_sample = {
  67         ADC_DC_CAL,
  68         MAX_CAL_SAMPLES,
  69         PER_MIN_LOG_COUNT,
  70         ath9k_hw_adc_dccal_collect,
  71         ath9k_hw_adc_dccal_calibrate
  72 };
  73 static const struct hal_percal_data adc_dc_cal_single_sample = {
  74         ADC_DC_CAL,
  75         MIN_CAL_SAMPLES,
  76         PER_MAX_LOG_COUNT,
  77         ath9k_hw_adc_dccal_collect,
  78         ath9k_hw_adc_dccal_calibrate
  79 };
  80 static const struct hal_percal_data adc_init_dc_cal = {
  81         ADC_DC_INIT_CAL,
  82         MIN_CAL_SAMPLES,
  83         INIT_LOG_COUNT,
  84         ath9k_hw_adc_dccal_collect,
  85         ath9k_hw_adc_dccal_calibrate
  86 };
  87
  88 static struct ath9k_rate_table ar5416_11a_table = {
  89         8,
  90         {0},
  91         {
  92                 {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
  93                 {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
  94                 {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
  95                 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
  96                 {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
  97                 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
  98                 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
  99                 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4}
 100         },
 101 };
 102
 103 static struct ath9k_rate_table ar5416_11b_table = {
 104         4,
 105         {0},
 106         {
 107                 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
 108                 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
 109                 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 1},
 110                 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 1}
 111         },
 112 };
 113
 114 static struct ath9k_rate_table ar5416_11g_table = {
 115         12,
 116         {0},
 117         {
 118                 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
 119                 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
 120                 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
 121                 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
 122
 123                 {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
 124                 {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
 125                 {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
 126                 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
 127                 {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
 128                 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
 129                 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
 130                 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8}
 131         },
 132 };
 133
 134 static struct ath9k_rate_table ar5416_11ng_table = {
 135         28,
 136         {0},
 137         {
 138                 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
 139                 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
 140                 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
 141                 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
 142
 143                 {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
 144                 {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
 145                 {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
 146                 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
 147                 {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
 148                 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
 149                 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
 150                 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8},
 151                 {true, PHY_HT, 6500, 0x80, 0x00, 0, 4},
 152                 {true, PHY_HT, 13000, 0x81, 0x00, 1, 6},
 153                 {true, PHY_HT, 19500, 0x82, 0x00, 2, 6},
 154                 {true, PHY_HT, 26000, 0x83, 0x00, 3, 8},
 155                 {true, PHY_HT, 39000, 0x84, 0x00, 4, 8},
 156                 {true, PHY_HT, 52000, 0x85, 0x00, 5, 8},
 157                 {true, PHY_HT, 58500, 0x86, 0x00, 6, 8},
 158                 {true, PHY_HT, 65000, 0x87, 0x00, 7, 8},
 159                 {true, PHY_HT, 13000, 0x88, 0x00, 8, 4},
 160                 {true, PHY_HT, 26000, 0x89, 0x00, 9, 6},
 161                 {true, PHY_HT, 39000, 0x8a, 0x00, 10, 6},
 162                 {true, PHY_HT, 52000, 0x8b, 0x00, 11, 8},
 163                 {true, PHY_HT, 78000, 0x8c, 0x00, 12, 8},
 164                 {true, PHY_HT, 104000, 0x8d, 0x00, 13, 8},
 165                 {true, PHY_HT, 117000, 0x8e, 0x00, 14, 8},
 166                 {true, PHY_HT, 130000, 0x8f, 0x00, 15, 8},
 167         },
 168 };
 169
 170 static struct ath9k_rate_table ar5416_11na_table = {
 171         24,
 172         {0},
 173         {
 174                 {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
 175                 {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
 176                 {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
 177                 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
 178                 {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
 179                 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
 180                 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
 181                 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4},
 182                 {true, PHY_HT, 6500, 0x80, 0x00, 0, 0},
 183                 {true, PHY_HT, 13000, 0x81, 0x00, 1, 2},
 184                 {true, PHY_HT, 19500, 0x82, 0x00, 2, 2},
 185                 {true, PHY_HT, 26000, 0x83, 0x00, 3, 4},
 186                 {true, PHY_HT, 39000, 0x84, 0x00, 4, 4},
 187                 {true, PHY_HT, 52000, 0x85, 0x00, 5, 4},
 188                 {true, PHY_HT, 58500, 0x86, 0x00, 6, 4},
 189                 {true, PHY_HT, 65000, 0x87, 0x00, 7, 4},
 190                 {true, PHY_HT, 13000, 0x88, 0x00, 8, 0},
 191                 {true, PHY_HT, 26000, 0x89, 0x00, 9, 2},
 192                 {true, PHY_HT, 39000, 0x8a, 0x00, 10, 2},
 193                 {true, PHY_HT, 52000, 0x8b, 0x00, 11, 4},
 194                 {true, PHY_HT, 78000, 0x8c, 0x00, 12, 4},
 195                 {true, PHY_HT, 104000, 0x8d, 0x00, 13, 4},
 196                 {true, PHY_HT, 117000, 0x8e, 0x00, 14, 4},
 197                 {true, PHY_HT, 130000, 0x8f, 0x00, 15, 4},
 198         },
 199 };
 200
 201 static enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
 202                                        const struct ath9k_channel *chan)
 203 {
 204         if (IS_CHAN_CCK(chan))
 205                 return ATH9K_MODE_11A;
 206         if (IS_CHAN_G(chan))
 207                 return ATH9K_MODE_11G;
 208         return ATH9K_MODE_11A;
 209 }
 210
 211 static bool ath9k_hw_wait(struct ath_hal *ah,
 212                           u32 reg,
 213                           u32 mask,
 214                           u32 val)
 215 {
 216         int i;
 217
 218         for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
 219                 if ((REG_READ(ah, reg) & mask) == val)
 220                         return true;
 221
 222                 udelay(AH_TIME_QUANTUM);
 223         }
 224         DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
 225                  "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 226                  __func__, reg, REG_READ(ah, reg), mask, val);
 227         return false;
 228 }
 229
 230 static bool ath9k_hw_eeprom_read(struct ath_hal *ah, u32 off,
 231                                  u16 *data)
 232 {
 233         (void) REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
 234
 235         if (!ath9k_hw_wait(ah,
 236                            AR_EEPROM_STATUS_DATA,
 237                            AR_EEPROM_STATUS_DATA_BUSY |
 238                            AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0)) {
 239                 return false;
 240         }
 241
 242         *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
 243                    AR_EEPROM_STATUS_DATA_VAL);
 244
 245         return true;
 246 }
 247
 248 static int ath9k_hw_flash_map(struct ath_hal *ah)
 249 {
 250         struct ath_hal_5416 *ahp = AH5416(ah);
 251
 252         ahp->ah_cal_mem = ioremap(AR5416_EEPROM_START_ADDR, AR5416_EEPROM_MAX);
 253
 254         if (!ahp->ah_cal_mem) {
 255                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 256                          "%s: cannot remap eeprom region \n", __func__);
 257                 return -EIO;
 258         }
 259
 260         return 0;
 261 }
 262
 263 static bool ath9k_hw_flash_read(struct ath_hal *ah, u32 off,
 264                                 u16 *data)
 265 {
 266         struct ath_hal_5416 *ahp = AH5416(ah);
 267
 268         *data = ioread16(ahp->ah_cal_mem + off);
 269         return true;
 270 }
 271
 272 static void ath9k_hw_read_revisions(struct ath_hal *ah)
 273 {
 274         u32 val;
 275
 276         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 277
 278         if (val == 0xFF) {
 279                 val = REG_READ(ah, AR_SREV);
 280
 281                 ah->ah_macVersion =
 282                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 283
 284                 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
 285                 ah->ah_isPciExpress =
 286                         (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 287
 288         } else {
 289                 if (!AR_SREV_9100(ah))
 290                         ah->ah_macVersion = MS(val, AR_SREV_VERSION);
 291
 292                 ah->ah_macRev = val & AR_SREV_REVISION;
 293
 294                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
 295                         ah->ah_isPciExpress = true;
 296         }
 297 }
 298
 299 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 300 {
 301         u32 retval;
 302         int i;
 303
 304         for (i = 0, retval = 0; i < n; i++) {
 305                 retval = (retval << 1) | (val & 1);
 306                 val >>= 1;
 307         }
 308         return retval;
 309 }
 310
 311 static void ath9k_hw_set_defaults(struct ath_hal *ah)
 312 {
 313         int i;
 314
 315         ah->ah_config.dma_beacon_response_time = 2;
 316         ah->ah_config.sw_beacon_response_time = 10;
 317         ah->ah_config.additional_swba_backoff = 0;
 318         ah->ah_config.ack_6mb = 0x0;
 319         ah->ah_config.cwm_ignore_extcca = 0;
 320         ah->ah_config.pcie_powersave_enable = 0;
 321         ah->ah_config.pcie_l1skp_enable = 0;
 322         ah->ah_config.pcie_clock_req = 0;
 323         ah->ah_config.pcie_power_reset = 0x100;
 324         ah->ah_config.pcie_restore = 0;
 325         ah->ah_config.pcie_waen = 0;
 326         ah->ah_config.analog_shiftreg = 1;
 327         ah->ah_config.ht_enable = 1;
 328         ah->ah_config.ofdm_trig_low = 200;
 329         ah->ah_config.ofdm_trig_high = 500;
 330         ah->ah_config.cck_trig_high = 200;
 331         ah->ah_config.cck_trig_low = 100;
 332         ah->ah_config.enable_ani = 0;
 333         ah->ah_config.noise_immunity_level = 4;
 334         ah->ah_config.ofdm_weaksignal_det = 1;
 335         ah->ah_config.cck_weaksignal_thr = 0;
 336         ah->ah_config.spur_immunity_level = 2;
 337         ah->ah_config.firstep_level = 0;
 338         ah->ah_config.rssi_thr_high = 40;
 339         ah->ah_config.rssi_thr_low = 7;
 340         ah->ah_config.diversity_control = 0;
 341         ah->ah_config.antenna_switch_swap = 0;
 342
 343         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 344                 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
 345                 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
 346         }
 347
 348         ah->ah_config.intr_mitigation = 0;
 349 }
 350
 351 static void ath9k_hw_override_ini(struct ath_hal *ah,
 352                                          struct ath9k_channel *chan)
 353 {
 354         if (!AR_SREV_5416_V20_OR_LATER(ah)
 355             || AR_SREV_9280_10_OR_LATER(ah))
 356                 return;
 357
 358         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
 359 }
 360
 361 static void ath9k_hw_init_bb(struct ath_hal *ah,
 362                              struct ath9k_channel *chan)
 363 {
 364         u32 synthDelay;
 365
 366         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 367         if (IS_CHAN_CCK(chan))
 368                 synthDelay = (4 * synthDelay) / 22;
 369         else
 370                 synthDelay /= 10;
 371
 372         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 373
 374         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 375 }
 376
 377 static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
 378                                           enum ath9k_opmode opmode)
 379 {
 380         struct ath_hal_5416 *ahp = AH5416(ah);
 381
 382         ahp->ah_maskReg = AR_IMR_TXERR |
 383                 AR_IMR_TXURN |
 384                 AR_IMR_RXERR |
 385                 AR_IMR_RXORN |
 386                 AR_IMR_BCNMISC;
 387
 388         if (ahp->ah_intrMitigation)
 389                 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 390         else
 391                 ahp->ah_maskReg |= AR_IMR_RXOK;
 392
 393         ahp->ah_maskReg |= AR_IMR_TXOK;
 394
 395         if (opmode == ATH9K_M_HOSTAP)
 396                 ahp->ah_maskReg |= AR_IMR_MIB;
 397
 398         REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
 399         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
 400
 401         if (!AR_SREV_9100(ah)) {
 402                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
 403                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
 404                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
 405         }
 406 }
 407
 408 static void ath9k_hw_init_qos(struct ath_hal *ah)
 409 {
 410         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 411         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 412
 413         REG_WRITE(ah, AR_QOS_NO_ACK,
 414                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 415                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 416                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 417
 418         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 419         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 420         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 421         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 422         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 423 }
 424
 425 static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah,
 426                                       u32 reg,
 427                                       u32 mask,
 428                                       u32 shift,
 429                                       u32 val)
 430 {
 431         u32 regVal;
 432
 433         regVal = REG_READ(ah, reg) & ~mask;
 434         regVal |= (val << shift) & mask;
 435
 436         REG_WRITE(ah, reg, regVal);
 437
 438         if (ah->ah_config.analog_shiftreg)
 439                 udelay(100);
 440
 441         return;
 442 }
 443
 444 static u8 ath9k_hw_get_num_ant_config(struct ath_hal_5416 *ahp,
 445                                       enum ieee80211_band freq_band)
 446 {
 447         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
 448         struct modal_eep_header *pModal =
 449                 &(eep->modalHeader[IEEE80211_BAND_5GHZ == freq_band]);
 450         struct base_eep_header *pBase = &eep->baseEepHeader;
 451         u8 num_ant_config;
 452
 453         num_ant_config = 1;
 454
 455         if (pBase->version >= 0x0E0D)
 456                 if (pModal->useAnt1)
 457                         num_ant_config += 1;
 458
 459         return num_ant_config;
 460 }
 461
 462 static int
 463 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal_5416 *ahp,
 464                                 struct ath9k_channel *chan,
 465                                 u8 index,
 466                                 u16 *config)
 467 {
 468         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
 469         struct modal_eep_header *pModal =
 470                 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
 471         struct base_eep_header *pBase = &eep->baseEepHeader;
 472
 473         switch (index) {
 474         case 0:
 475                 *config = pModal->antCtrlCommon & 0xFFFF;
 476                 return 0;
 477         case 1:
 478                 if (pBase->version >= 0x0E0D) {
 479                         if (pModal->useAnt1) {
 480                                 *config =
 481                                 ((pModal->antCtrlCommon & 0xFFFF0000) >> 16);
 482                                 return 0;
 483                         }
 484                 }
 485                 break;
 486         default:
 487                 break;
 488         }
 489
 490         return -EINVAL;
 491 }
 492
 493 static inline bool ath9k_hw_nvram_read(struct ath_hal *ah,
 494                                        u32 off,
 495                                        u16 *data)
 496 {
 497         if (ath9k_hw_use_flash(ah))
 498                 return ath9k_hw_flash_read(ah, off, data);
 499         else
 500                 return ath9k_hw_eeprom_read(ah, off, data);
 501 }
 502
 503 static bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
 504 {
 505         struct ath_hal_5416 *ahp = AH5416(ah);
 506         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
 507         u16 *eep_data;
 508         int addr, ar5416_eep_start_loc = 0;
 509
 510         if (!ath9k_hw_use_flash(ah)) {
 511                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 512                          "%s: Reading from EEPROM, not flash\n", __func__);
 513                 ar5416_eep_start_loc = 256;
 514         }
 515         if (AR_SREV_9100(ah))
 516                 ar5416_eep_start_loc = 256;
 517
 518         eep_data = (u16 *) eep;
 519         for (addr = 0;
 520              addr < sizeof(struct ar5416_eeprom) / sizeof(u16);
 521              addr++) {
 522                 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
 523                                          eep_data)) {
 524                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 525                                  "%s: Unable to read eeprom region \n",
 526                                  __func__);
 527                         return false;
 528                 }
 529                 eep_data++;
 530         }
 531         return true;
 532 }
 533
 534 /* XXX: Clean me up, make me more legible */
 535 static bool
 536 ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
 537                                  struct ath9k_channel *chan)
 538 {
 539         struct modal_eep_header *pModal;
 540         int i, regChainOffset;
 541         struct ath_hal_5416 *ahp = AH5416(ah);
 542         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
 543         u8 txRxAttenLocal;
 544         u16 ant_config;
 545
 546         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
 547
 548         txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
 549
 550         ath9k_hw_get_eeprom_antenna_cfg(ahp, chan, 1, &ant_config);
 551         REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
 552
 553         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 554                 if (AR_SREV_9280(ah)) {
 555                         if (i >= 2)
 556                                 break;
 557                 }
 558
 559                 if (AR_SREV_5416_V20_OR_LATER(ah) &&
 560                     (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5)
 561                     && (i != 0))
 562                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
 563                 else
 564                         regChainOffset = i * 0x1000;
 565
 566                 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
 567                           pModal->antCtrlChain[i]);
 568
 569                 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
 570                           (REG_READ(ah,
 571                                     AR_PHY_TIMING_CTRL4(0) +
 572                                     regChainOffset) &
 573                            ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
 574                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
 575                           SM(pModal->iqCalICh[i],
 576                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
 577                           SM(pModal->iqCalQCh[i],
 578                              AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
 579
 580                 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
 581                         if ((eep->baseEepHeader.version &
 582                              AR5416_EEP_VER_MINOR_MASK) >=
 583                             AR5416_EEP_MINOR_VER_3) {
 584                                 txRxAttenLocal = pModal->txRxAttenCh[i];
 585                                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 586                                         REG_RMW_FIELD(ah,
 587                                                 AR_PHY_GAIN_2GHZ +
 588                                                 regChainOffset,
 589                                                 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
 590                                                 pModal->
 591                                                 bswMargin[i]);
 592                                         REG_RMW_FIELD(ah,
 593                                                 AR_PHY_GAIN_2GHZ +
 594                                                 regChainOffset,
 595                                                 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
 596                                                 pModal->
 597                                                 bswAtten[i]);
 598                                         REG_RMW_FIELD(ah,
 599                                                 AR_PHY_GAIN_2GHZ +
 600                                                 regChainOffset,
 601                                                 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 602                                                 pModal->
 603                                                 xatten2Margin[i]);
 604                                         REG_RMW_FIELD(ah,
 605                                                 AR_PHY_GAIN_2GHZ +
 606                                                 regChainOffset,
 607                                                 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
 608                                                 pModal->
 609                                                 xatten2Db[i]);
 610                                 } else {
 611                                         REG_WRITE(ah,
 612                                                   AR_PHY_GAIN_2GHZ +
 613                                                   regChainOffset,
 614                                                   (REG_READ(ah,
 615                                                             AR_PHY_GAIN_2GHZ +
 616                                                             regChainOffset) &
 617                                                    ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
 618                                                   | SM(pModal->
 619                                                   bswMargin[i],
 620                                                   AR_PHY_GAIN_2GHZ_BSW_MARGIN));
 621                                         REG_WRITE(ah,
 622                                                   AR_PHY_GAIN_2GHZ +
 623                                                   regChainOffset,
 624                                                   (REG_READ(ah,
 625                                                             AR_PHY_GAIN_2GHZ +
 626                                                             regChainOffset) &
 627                                                    ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
 628                                                   | SM(pModal->bswAtten[i],
 629                                                   AR_PHY_GAIN_2GHZ_BSW_ATTEN));
 630                                 }
 631                         }
 632                         if (AR_SREV_9280_10_OR_LATER(ah)) {
 633                                 REG_RMW_FIELD(ah,
 634                                               AR_PHY_RXGAIN +
 635                                               regChainOffset,
 636                                               AR9280_PHY_RXGAIN_TXRX_ATTEN,
 637                                               txRxAttenLocal);
 638                                 REG_RMW_FIELD(ah,
 639                                               AR_PHY_RXGAIN +
 640                                               regChainOffset,
 641                                               AR9280_PHY_RXGAIN_TXRX_MARGIN,
 642                                               pModal->rxTxMarginCh[i]);
 643                         } else {
 644                                 REG_WRITE(ah,
 645                                           AR_PHY_RXGAIN + regChainOffset,
 646                                           (REG_READ(ah,
 647                                                     AR_PHY_RXGAIN +
 648                                                     regChainOffset) &
 649                                            ~AR_PHY_RXGAIN_TXRX_ATTEN) |
 650                                           SM(txRxAttenLocal,
 651                                              AR_PHY_RXGAIN_TXRX_ATTEN));
 652                                 REG_WRITE(ah,
 653                                           AR_PHY_GAIN_2GHZ +
 654                                           regChainOffset,
 655                                           (REG_READ(ah,
 656                                                     AR_PHY_GAIN_2GHZ +
 657                                                     regChainOffset) &
 658                                            ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
 659                                           SM(pModal->rxTxMarginCh[i],
 660                                              AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
 661                         }
 662                 }
 663         }
 664
 665         if (AR_SREV_9280_10_OR_LATER(ah)) {
 666                 if (IS_CHAN_2GHZ(chan)) {
 667                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
 668                                                   AR_AN_RF2G1_CH0_OB,
 669                                                   AR_AN_RF2G1_CH0_OB_S,
 670                                                   pModal->ob);
 671                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
 672                                                   AR_AN_RF2G1_CH0_DB,
 673                                                   AR_AN_RF2G1_CH0_DB_S,
 674                                                   pModal->db);
 675                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
 676                                                   AR_AN_RF2G1_CH1_OB,
 677                                                   AR_AN_RF2G1_CH1_OB_S,
 678                                                   pModal->ob_ch1);
 679                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
 680                                                   AR_AN_RF2G1_CH1_DB,
 681                                                   AR_AN_RF2G1_CH1_DB_S,
 682                                                   pModal->db_ch1);
 683                 } else {
 684                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
 685                                                   AR_AN_RF5G1_CH0_OB5,
 686                                                   AR_AN_RF5G1_CH0_OB5_S,
 687                                                   pModal->ob);
 688                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
 689                                                   AR_AN_RF5G1_CH0_DB5,
 690                                                   AR_AN_RF5G1_CH0_DB5_S,
 691                                                   pModal->db);
 692                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
 693                                                   AR_AN_RF5G1_CH1_OB5,
 694                                                   AR_AN_RF5G1_CH1_OB5_S,
 695                                                   pModal->ob_ch1);
 696                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
 697                                                   AR_AN_RF5G1_CH1_DB5,
 698                                                   AR_AN_RF5G1_CH1_DB5_S,
 699                                                   pModal->db_ch1);
 700                 }
 701                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
 702                                           AR_AN_TOP2_XPABIAS_LVL,
 703                                           AR_AN_TOP2_XPABIAS_LVL_S,
 704                                           pModal->xpaBiasLvl);
 705                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
 706                                           AR_AN_TOP2_LOCALBIAS,
 707                                           AR_AN_TOP2_LOCALBIAS_S,
 708                                           pModal->local_bias);
 709                 DPRINTF(ah->ah_sc, ATH_DBG_ANY, "ForceXPAon: %d\n",
 710                         pModal->force_xpaon);
 711                 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
 712                               pModal->force_xpaon);
 713         }
 714
 715         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
 716                       pModal->switchSettling);
 717         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
 718                       pModal->adcDesiredSize);
 719
 720         if (!AR_SREV_9280_10_OR_LATER(ah))
 721                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
 722                               AR_PHY_DESIRED_SZ_PGA,
 723                               pModal->pgaDesiredSize);
 724
 725         REG_WRITE(ah, AR_PHY_RF_CTL4,
 726                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
 727                   | SM(pModal->txEndToXpaOff,
 728                        AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
 729                   | SM(pModal->txFrameToXpaOn,
 730                        AR_PHY_RF_CTL4_FRAME_XPAA_ON)
 731                   | SM(pModal->txFrameToXpaOn,
 732                        AR_PHY_RF_CTL4_FRAME_XPAB_ON));
 733
 734         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
 735                       pModal->txEndToRxOn);
 736         if (AR_SREV_9280_10_OR_LATER(ah)) {
 737                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
 738                               pModal->thresh62);
 739                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
 740                               AR_PHY_EXT_CCA0_THRESH62,
 741                               pModal->thresh62);
 742         } else {
 743                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
 744                               pModal->thresh62);
 745                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
 746                               AR_PHY_EXT_CCA_THRESH62,
 747                               pModal->thresh62);
 748         }
 749
 750         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 751             AR5416_EEP_MINOR_VER_2) {
 752                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
 753                               AR_PHY_TX_END_DATA_START,
 754                               pModal->txFrameToDataStart);
 755                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
 756                               pModal->txFrameToPaOn);
 757         }
 758
 759         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 760             AR5416_EEP_MINOR_VER_3) {
 761                 if (IS_CHAN_HT40(chan))
 762                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
 763                                       AR_PHY_SETTLING_SWITCH,
 764                                       pModal->swSettleHt40);
 765         }
 766
 767         return true;
 768 }
 769
 770 static int ath9k_hw_check_eeprom(struct ath_hal *ah)
 771 {
 772         u32 sum = 0, el;
 773         u16 *eepdata;
 774         int i;
 775         struct ath_hal_5416 *ahp = AH5416(ah);
 776         bool need_swap = false;
 777         struct ar5416_eeprom *eep =
 778                 (struct ar5416_eeprom *) &ahp->ah_eeprom;
 779
 780         if (!ath9k_hw_use_flash(ah)) {
 781                 u16 magic, magic2;
 782                 int addr;
 783
 784                 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
 785                                         &magic)) {
 786                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 787                                  "%s: Reading Magic # failed\n", __func__);
 788                         return false;
 789                 }
 790                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "%s: Read Magic = 0x%04X\n",
 791                          __func__, magic);
 792
 793                 if (magic != AR5416_EEPROM_MAGIC) {
 794                         magic2 = swab16(magic);
 795
 796                         if (magic2 == AR5416_EEPROM_MAGIC) {
 797                                 need_swap = true;
 798                                 eepdata = (u16 *) (&ahp->ah_eeprom);
 799
 800                                 for (addr = 0;
 801                                      addr <
 802                                              sizeof(struct ar5416_eeprom) /
 803                                              sizeof(u16); addr++) {
 804                                         u16 temp;
 805
 806                                         temp = swab16(*eepdata);
 807                                         *eepdata = temp;
 808                                         eepdata++;
 809
 810                                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 811                                                  "0x%04X  ", *eepdata);
 812                                         if (((addr + 1) % 6) == 0)
 813                                                 DPRINTF(ah->ah_sc,
 814                                                          ATH_DBG_EEPROM,
 815                                                          "\n");
 816                                 }
 817                         } else {
 818                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 819                                          "Invalid EEPROM Magic. "
 820                                         "endianness missmatch.\n");
 821                                 return -EINVAL;
 822                         }
 823                 }
 824         }
 825         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
 826                  need_swap ? "True" : "False");
 827
 828         if (need_swap)
 829                 el = swab16(ahp->ah_eeprom.baseEepHeader.length);
 830         else
 831                 el = ahp->ah_eeprom.baseEepHeader.length;
 832
 833         if (el > sizeof(struct ar5416_eeprom))
 834                 el = sizeof(struct ar5416_eeprom) / sizeof(u16);
 835         else
 836                 el = el / sizeof(u16);
 837
 838         eepdata = (u16 *) (&ahp->ah_eeprom);
 839
 840         for (i = 0; i < el; i++)
 841                 sum ^= *eepdata++;
 842
 843         if (need_swap) {
 844                 u32 integer, j;
 845                 u16 word;
 846
 847                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 848                          "EEPROM Endianness is not native.. Changing \n");
 849
 850                 word = swab16(eep->baseEepHeader.length);
 851                 eep->baseEepHeader.length = word;
 852
 853                 word = swab16(eep->baseEepHeader.checksum);
 854                 eep->baseEepHeader.checksum = word;
 855
 856                 word = swab16(eep->baseEepHeader.version);
 857                 eep->baseEepHeader.version = word;
 858
 859                 word = swab16(eep->baseEepHeader.regDmn[0]);
 860                 eep->baseEepHeader.regDmn[0] = word;
 861
 862                 word = swab16(eep->baseEepHeader.regDmn[1]);
 863                 eep->baseEepHeader.regDmn[1] = word;
 864
 865                 word = swab16(eep->baseEepHeader.rfSilent);
 866                 eep->baseEepHeader.rfSilent = word;
 867
 868                 word = swab16(eep->baseEepHeader.blueToothOptions);
 869                 eep->baseEepHeader.blueToothOptions = word;
 870
 871                 word = swab16(eep->baseEepHeader.deviceCap);
 872                 eep->baseEepHeader.deviceCap = word;
 873
 874                 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
 875                         struct modal_eep_header *pModal =
 876                                 &eep->modalHeader[j];
 877                         integer = swab32(pModal->antCtrlCommon);
 878                         pModal->antCtrlCommon = integer;
 879
 880                         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 881                                 integer = swab32(pModal->antCtrlChain[i]);
 882                                 pModal->antCtrlChain[i] = integer;
 883                         }
 884
 885                         for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
 886                                 word = swab16(pModal->spurChans[i].spurChan);
 887                                 pModal->spurChans[i].spurChan = word;
 888                         }
 889                 }
 890         }
 891
 892         if (sum != 0xffff || ar5416_get_eep_ver(ahp) != AR5416_EEP_VER ||
 893             ar5416_get_eep_rev(ahp) < AR5416_EEP_NO_BACK_VER) {
 894                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 895                          "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 896                          sum, ar5416_get_eep_ver(ahp));
 897                 return -EINVAL;
 898         }
 899
 900         return 0;
 901 }
 902
 903 static bool ath9k_hw_chip_test(struct ath_hal *ah)
 904 {
 905         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 906         u32 regHold[2];
 907         u32 patternData[4] = { 0x55555555,
 908                                      0xaaaaaaaa,
 909                                      0x66666666,
 910                                      0x99999999 };
 911         int i, j;
 912
 913         for (i = 0; i < 2; i++) {
 914                 u32 addr = regAddr[i];
 915                 u32 wrData, rdData;
 916
 917                 regHold[i] = REG_READ(ah, addr);
 918                 for (j = 0; j < 0x100; j++) {
 919                         wrData = (j << 16) | j;
 920                         REG_WRITE(ah, addr, wrData);
 921                         rdData = REG_READ(ah, addr);
 922                         if (rdData != wrData) {
 923                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 924                                  "%s: address test failed "
 925                                 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 926                                  __func__, addr, wrData, rdData);
 927                                 return false;
 928                         }
 929                 }
 930                 for (j = 0; j < 4; j++) {
 931                         wrData = patternData[j];
 932                         REG_WRITE(ah, addr, wrData);
 933                         rdData = REG_READ(ah, addr);
 934                         if (wrData != rdData) {
 935                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 936                                  "%s: address test failed "
 937                                 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 938                                  __func__, addr, wrData, rdData);
 939                                 return false;
 940                         }
 941                 }
 942                 REG_WRITE(ah, regAddr[i], regHold[i]);
 943         }
 944         udelay(100);
 945         return true;
 946 }
 947
 948 u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
 949 {
 950         u32 bits = REG_READ(ah, AR_RX_FILTER);
 951         u32 phybits = REG_READ(ah, AR_PHY_ERR);
 952
 953         if (phybits & AR_PHY_ERR_RADAR)
 954                 bits |= ATH9K_RX_FILTER_PHYRADAR;
 955         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
 956                 bits |= ATH9K_RX_FILTER_PHYERR;
 957         return bits;
 958 }
 959
 960 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
 961 {
 962         u32 phybits;
 963
 964         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
 965         phybits = 0;
 966         if (bits & ATH9K_RX_FILTER_PHYRADAR)
 967                 phybits |= AR_PHY_ERR_RADAR;
 968         if (bits & ATH9K_RX_FILTER_PHYERR)
 969                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
 970         REG_WRITE(ah, AR_PHY_ERR, phybits);
 971
 972         if (phybits)
 973                 REG_WRITE(ah, AR_RXCFG,
 974                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
 975         else
 976                 REG_WRITE(ah, AR_RXCFG,
 977                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
 978 }
 979
 980 bool ath9k_hw_setcapability(struct ath_hal *ah,
 981                             enum ath9k_capability_type type,
 982                             u32 capability,
 983                             u32 setting,
 984                             int *status)
 985 {
 986         struct ath_hal_5416 *ahp = AH5416(ah);
 987         u32 v;
 988
 989         switch (type) {
 990         case ATH9K_CAP_TKIP_MIC:
 991                 if (setting)
 992                         ahp->ah_staId1Defaults |=
 993                                 AR_STA_ID1_CRPT_MIC_ENABLE;
 994                 else
 995                         ahp->ah_staId1Defaults &=
 996                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
 997                 return true;
 998         case ATH9K_CAP_DIVERSITY:
 999                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
1000                 if (setting)
1001                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1002                 else
1003                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1004                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
1005                 return true;
1006         case ATH9K_CAP_MCAST_KEYSRCH:
1007                 if (setting)
1008                         ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
1009                 else
1010                         ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
1011                 return true;
1012         case ATH9K_CAP_TSF_ADJUST:
1013                 if (setting)
1014                         ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
1015                 else
1016                         ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
1017                 return true;
1018         default:
1019                 return false;
1020         }
1021 }
1022
1023 void ath9k_hw_dmaRegDump(struct ath_hal *ah)
1024 {
1025         u32 val[ATH9K_NUM_DMA_DEBUG_REGS];
1026         int qcuOffset = 0, dcuOffset = 0;
1027         u32 *qcuBase = &val[0], *dcuBase = &val[4];
1028         int i;
1029
1030         REG_WRITE(ah, AR_MACMISC,
1031                   ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
1032                    (AR_MACMISC_MISC_OBS_BUS_1 <<
1033                     AR_MACMISC_MISC_OBS_BUS_MSB_S)));
1034
1035         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "Raw DMA Debug values:\n");
1036         for (i = 0; i < ATH9K_NUM_DMA_DEBUG_REGS; i++) {
1037                 if (i % 4 == 0)
1038                         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n");
1039
1040                 val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u32)));
1041                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "%d: %08x ", i, val[i]);
1042         }
1043
1044         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n\n");
1045         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1046                  "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n");
1047
1048         for (i = 0; i < ATH9K_NUM_QUEUES;
1049              i++, qcuOffset += 4, dcuOffset += 5) {
1050                 if (i == 8) {
1051                         qcuOffset = 0;
1052                         qcuBase++;
1053                 }
1054
1055                 if (i == 6) {
1056                         dcuOffset = 0;
1057                         dcuBase++;
1058                 }
1059
1060                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1061                          "%2d          %2x      %1x     %2x           %2x\n",
1062                          i, (*qcuBase & (0x7 << qcuOffset)) >> qcuOffset,
1063                          (*qcuBase & (0x8 << qcuOffset)) >> (qcuOffset +
1064                                                              3),
1065                          val[2] & (0x7 << (i * 3)) >> (i * 3),
1066                          (*dcuBase & (0x1f << dcuOffset)) >> dcuOffset);
1067         }
1068
1069         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n");
1070         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1071                  "qcu_stitch state:   %2x    qcu_fetch state:        %2x\n",
1072                  (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22);
1073         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1074                  "qcu_complete state: %2x    dcu_complete state:     %2x\n",
1075                  (val[3] & 0x1c000000) >> 26, (val[6] & 0x3));
1076         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1077                  "dcu_arb state:      %2x    dcu_fp state:           %2x\n",
1078                  (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27);
1079         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1080                  "chan_idle_dur:     %3d    chan_idle_dur_valid:     %1d\n",
1081                  (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10);
1082         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1083                  "txfifo_valid_0:      %1d    txfifo_valid_1:          %1d\n",
1084                  (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12);
1085         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1086                  "txfifo_dcu_num_0:   %2d    txfifo_dcu_num_1:       %2d\n",
1087                  (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
1088
1089         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "pcu observe 0x%x \n",
1090                 REG_READ(ah, AR_OBS_BUS_1));
1091         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1092                 "AR_CR 0x%x \n", REG_READ(ah, AR_CR));
1093 }
1094
1095 u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
1096                                         u32 *rxc_pcnt,
1097                                         u32 *rxf_pcnt,
1098                                         u32 *txf_pcnt)
1099 {
1100         static u32 cycles, rx_clear, rx_frame, tx_frame;
1101         u32 good = 1;
1102
1103         u32 rc = REG_READ(ah, AR_RCCNT);
1104         u32 rf = REG_READ(ah, AR_RFCNT);
1105         u32 tf = REG_READ(ah, AR_TFCNT);
1106         u32 cc = REG_READ(ah, AR_CCCNT);
1107
1108         if (cycles == 0 || cycles > cc) {
1109                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1110                          "%s: cycle counter wrap. ExtBusy = 0\n",
1111                          __func__);
1112                 good = 0;
1113         } else {
1114                 u32 cc_d = cc - cycles;
1115                 u32 rc_d = rc - rx_clear;
1116                 u32 rf_d = rf - rx_frame;
1117                 u32 tf_d = tf - tx_frame;
1118
1119                 if (cc_d != 0) {
1120                         *rxc_pcnt = rc_d * 100 / cc_d;
1121                         *rxf_pcnt = rf_d * 100 / cc_d;
1122                         *txf_pcnt = tf_d * 100 / cc_d;
1123                 } else {
1124                         good = 0;
1125                 }
1126         }
1127
1128         cycles = cc;
1129         rx_frame = rf;
1130         rx_clear = rc;
1131         tx_frame = tf;
1132
1133         return good;
1134 }
1135
1136 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
1137 {
1138         u32 macmode;
1139
1140         if (mode == ATH9K_HT_MACMODE_2040 &&
1141             !ah->ah_config.cwm_ignore_extcca)
1142                 macmode = AR_2040_JOINED_RX_CLEAR;
1143         else
1144                 macmode = 0;
1145
1146         REG_WRITE(ah, AR_2040_MODE, macmode);
1147 }
1148
1149 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1150 {
1151         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1152 }
1153
1154
1155 static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
1156                                               struct ath_softc *sc,
1157                                               void __iomem *mem,
1158                                               int *status)
1159 {
1160         static const u8 defbssidmask[ETH_ALEN] =
1161                 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1162         struct ath_hal_5416 *ahp;
1163         struct ath_hal *ah;
1164
1165         ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
1166         if (ahp == NULL) {
1167                 DPRINTF(sc, ATH_DBG_FATAL,
1168                          "%s: cannot allocate memory for state block\n",
1169                          __func__);
1170                 *status = -ENOMEM;
1171                 return NULL;
1172         }
1173
1174         ah = &ahp->ah;
1175
1176         ah->ah_sc = sc;
1177         ah->ah_sh = mem;
1178
1179         ah->ah_magic = AR5416_MAGIC;
1180         ah->ah_countryCode = CTRY_DEFAULT;
1181
1182         ah->ah_devid = devid;
1183         ah->ah_subvendorid = 0;
1184
1185         ah->ah_flags = 0;
1186         if ((devid == AR5416_AR9100_DEVID))
1187                 ah->ah_macVersion = AR_SREV_VERSION_9100;
1188         if (!AR_SREV_9100(ah))
1189                 ah->ah_flags = AH_USE_EEPROM;
1190
1191         ah->ah_powerLimit = MAX_RATE_POWER;
1192         ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
1193
1194         ahp->ah_atimWindow = 0;
1195         ahp->ah_diversityControl = ah->ah_config.diversity_control;
1196         ahp->ah_antennaSwitchSwap =
1197                 ah->ah_config.antenna_switch_swap;
1198
1199         ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
1200         ahp->ah_beaconInterval = 100;
1201         ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
1202         ahp->ah_slottime = (u32) -1;
1203         ahp->ah_acktimeout = (u32) -1;
1204         ahp->ah_ctstimeout = (u32) -1;
1205         ahp->ah_globaltxtimeout = (u32) -1;
1206         memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
1207
1208         ahp->ah_gBeaconRate = 0;
1209
1210         return ahp;
1211 }
1212
1213 static int ath9k_hw_eeprom_attach(struct ath_hal *ah)
1214 {
1215         int status;
1216
1217         if (ath9k_hw_use_flash(ah))
1218                 ath9k_hw_flash_map(ah);
1219
1220         if (!ath9k_hw_fill_eeprom(ah))
1221                 return -EIO;
1222
1223         status = ath9k_hw_check_eeprom(ah);
1224
1225         return status;
1226 }
1227
1228 u32 ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp,
1229                               enum eeprom_param param)
1230 {
1231         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
1232         struct modal_eep_header *pModal = eep->modalHeader;
1233         struct base_eep_header *pBase = &eep->baseEepHeader;
1234
1235         switch (param) {
1236         case EEP_NFTHRESH_5:
1237                 return -pModal[0].noiseFloorThreshCh[0];
1238         case EEP_NFTHRESH_2:
1239                 return -pModal[1].noiseFloorThreshCh[0];
1240         case AR_EEPROM_MAC(0):
1241                 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
1242         case AR_EEPROM_MAC(1):
1243                 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
1244         case AR_EEPROM_MAC(2):
1245                 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
1246         case EEP_REG_0:
1247                 return pBase->regDmn[0];
1248         case EEP_REG_1:
1249                 return pBase->regDmn[1];
1250         case EEP_OP_CAP:
1251                 return pBase->deviceCap;
1252         case EEP_OP_MODE:
1253                 return pBase->opCapFlags;
1254         case EEP_RF_SILENT:
1255                 return pBase->rfSilent;
1256         case EEP_OB_5:
1257                 return pModal[0].ob;
1258         case EEP_DB_5:
1259                 return pModal[0].db;
1260         case EEP_OB_2:
1261                 return pModal[1].ob;
1262         case EEP_DB_2:
1263                 return pModal[1].db;
1264         case EEP_MINOR_REV:
1265                 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
1266         case EEP_TX_MASK:
1267                 return pBase->txMask;
1268         case EEP_RX_MASK:
1269                 return pBase->rxMask;
1270         default:
1271                 return 0;
1272         }
1273 }
1274
1275 static int ath9k_hw_get_radiorev(struct ath_hal *ah)
1276 {
1277         u32 val;
1278         int i;
1279
1280         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
1281         for (i = 0; i < 8; i++)
1282                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
1283         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
1284         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
1285         return ath9k_hw_reverse_bits(val, 8);
1286 }
1287
1288 static int ath9k_hw_init_macaddr(struct ath_hal *ah)
1289 {
1290         u32 sum;
1291         int i;
1292         u16 eeval;
1293         struct ath_hal_5416 *ahp = AH5416(ah);
1294         DECLARE_MAC_BUF(mac);
1295
1296         sum = 0;
1297         for (i = 0; i < 3; i++) {
1298                 eeval = ath9k_hw_get_eeprom(ahp, AR_EEPROM_MAC(i));
1299                 sum += eeval;
1300                 ahp->ah_macaddr[2 * i] = eeval >> 8;
1301                 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
1302         }
1303         if (sum == 0 || sum == 0xffff * 3) {
1304                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1305                          "%s: mac address read failed: %s\n", __func__,
1306                          print_mac(mac, ahp->ah_macaddr));
1307                 return -EADDRNOTAVAIL;
1308         }
1309
1310         return 0;
1311 }
1312
1313 static inline int16_t ath9k_hw_interpolate(u16 target,
1314                                            u16 srcLeft,
1315                                            u16 srcRight,
1316                                            int16_t targetLeft,
1317                                            int16_t targetRight)
1318 {
1319         int16_t rv;
1320
1321         if (srcRight == srcLeft) {
1322                 rv = targetLeft;
1323         } else {
1324                 rv = (int16_t) (((target - srcLeft) * targetRight +
1325                                  (srcRight - target) * targetLeft) /
1326                                 (srcRight - srcLeft));
1327         }
1328         return rv;
1329 }
1330
1331 static inline u16 ath9k_hw_fbin2freq(u8 fbin,
1332                                            bool is2GHz)
1333 {
1334
1335         if (fbin == AR5416_BCHAN_UNUSED)
1336                 return fbin;
1337
1338         return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
1339 }
1340
1341 static u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah,
1342                                                u16 i,
1343                                                bool is2GHz)
1344 {
1345         struct ath_hal_5416 *ahp = AH5416(ah);
1346         struct ar5416_eeprom *eep =
1347                 (struct ar5416_eeprom *) &ahp->ah_eeprom;
1348         u16 spur_val = AR_NO_SPUR;
1349
1350         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1351                  "Getting spur idx %d is2Ghz. %d val %x\n",
1352                  i, is2GHz, ah->ah_config.spurchans[i][is2GHz]);
1353
1354         switch (ah->ah_config.spurmode) {
1355         case SPUR_DISABLE:
1356                 break;
1357         case SPUR_ENABLE_IOCTL:
1358                 spur_val = ah->ah_config.spurchans[i][is2GHz];
1359                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1360                          "Getting spur val from new loc. %d\n", spur_val);
1361                 break;
1362         case SPUR_ENABLE_EEPROM:
1363                 spur_val = eep->modalHeader[is2GHz].spurChans[i].spurChan;
1364                 break;
1365
1366         }
1367         return spur_val;
1368 }
1369
1370 static int ath9k_hw_rfattach(struct ath_hal *ah)
1371 {
1372         bool rfStatus = false;
1373         int ecode = 0;
1374
1375         rfStatus = ath9k_hw_init_rf(ah, &ecode);
1376         if (!rfStatus) {
1377                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1378                          "%s: RF setup failed, status %u\n", __func__,
1379                          ecode);
1380                 return ecode;
1381         }
1382
1383         return 0;
1384 }
1385
1386 static int ath9k_hw_rf_claim(struct ath_hal *ah)
1387 {
1388         u32 val;
1389
1390         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1391
1392         val = ath9k_hw_get_radiorev(ah);
1393         switch (val & AR_RADIO_SREV_MAJOR) {
1394         case 0:
1395                 val = AR_RAD5133_SREV_MAJOR;
1396                 break;
1397         case AR_RAD5133_SREV_MAJOR:
1398         case AR_RAD5122_SREV_MAJOR:
1399         case AR_RAD2133_SREV_MAJOR:
1400         case AR_RAD2122_SREV_MAJOR:
1401                 break;
1402         default:
1403                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1404                          "%s: 5G Radio Chip Rev 0x%02X is not "
1405                         "supported by this driver\n",
1406                          __func__, ah->ah_analog5GhzRev);
1407                 return -EOPNOTSUPP;
1408         }
1409
1410         ah->ah_analog5GhzRev = val;
1411
1412         return 0;
1413 }
1414
1415 static void ath9k_hw_init_pll(struct ath_hal *ah,
1416                               struct ath9k_channel *chan)
1417 {
1418         u32 pll;
1419
1420         if (AR_SREV_9100(ah)) {
1421                 if (chan && IS_CHAN_5GHZ(chan))
1422                         pll = 0x1450;
1423                 else
1424                         pll = 0x1458;
1425         } else {
1426                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1427                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1428
1429                         if (chan && IS_CHAN_HALF_RATE(chan))
1430                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1431                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1432                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1433
1434                         if (chan && IS_CHAN_5GHZ(chan)) {
1435                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1436
1437
1438                                 if (AR_SREV_9280_20(ah)) {
1439                                         if (((chan->channel % 20) == 0)
1440                                             || ((chan->channel % 10) == 0))
1441                                                 pll = 0x2850;
1442                                         else
1443                                                 pll = 0x142c;
1444                                 }
1445                         } else {
1446                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1447                         }
1448
1449                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1450
1451                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1452
1453                         if (chan && IS_CHAN_HALF_RATE(chan))
1454                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1455                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1456                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1457
1458                         if (chan && IS_CHAN_5GHZ(chan))
1459                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1460                         else
1461                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1462                 } else {
1463                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1464
1465                         if (chan && IS_CHAN_HALF_RATE(chan))
1466                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1467                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1468                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1469
1470                         if (chan && IS_CHAN_5GHZ(chan))
1471                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1472                         else
1473                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1474                 }
1475         }
1476         REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
1477
1478         udelay(RTC_PLL_SETTLE_DELAY);
1479
1480         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1481 }
1482
1483 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1484                               enum ath9k_ht_macmode macmode)
1485 {
1486         u32 phymode;
1487         struct ath_hal_5416 *ahp = AH5416(ah);
1488
1489         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1490                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
1491
1492         if (IS_CHAN_HT40(chan)) {
1493                 phymode |= AR_PHY_FC_DYN2040_EN;
1494
1495                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1496                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1497                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1498
1499                 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1500                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1501         }
1502         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1503
1504         ath9k_hw_set11nmac2040(ah, macmode);
1505
1506         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1507         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1508 }
1509
1510 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1511 {
1512         u32 val;
1513
1514         val = REG_READ(ah, AR_STA_ID1);
1515         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1516         switch (opmode) {
1517         case ATH9K_M_HOSTAP:
1518                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1519                           | AR_STA_ID1_KSRCH_MODE);
1520                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1521                 break;
1522         case ATH9K_M_IBSS:
1523                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1524                           | AR_STA_ID1_KSRCH_MODE);
1525                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1526                 break;
1527         case ATH9K_M_STA:
1528         case ATH9K_M_MONITOR:
1529                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1530                 break;
1531         }
1532 }
1533
1534 static void
1535 ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1536 {
1537         u32 rfMode = 0;
1538
1539         if (chan == NULL)
1540                 return;
1541
1542         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1543                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1544
1545         if (!AR_SREV_9280_10_OR_LATER(ah))
1546                 rfMode |= (IS_CHAN_5GHZ(chan)) ? AR_PHY_MODE_RF5GHZ :
1547                         AR_PHY_MODE_RF2GHZ;
1548
1549         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1550                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1551
1552         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1553 }
1554
1555 static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1556 {
1557         u32 rst_flags;
1558         u32 tmpReg;
1559
1560         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1561                   AR_RTC_FORCE_WAKE_ON_INT);
1562
1563         if (AR_SREV_9100(ah)) {
1564                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1565                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1566         } else {
1567                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1568                 if (tmpReg &
1569                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1570                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1571                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1572                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1573                 } else {
1574                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1575                 }
1576
1577                 rst_flags = AR_RTC_RC_MAC_WARM;
1578                 if (type == ATH9K_RESET_COLD)
1579                         rst_flags |= AR_RTC_RC_MAC_COLD;
1580         }
1581
1582         REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1583         udelay(50);
1584
1585         REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1586         if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1587                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1588                         "%s: RTC stuck in MAC reset\n",
1589                         __func__);
1590                 return false;
1591         }
1592
1593         if (!AR_SREV_9100(ah))
1594                 REG_WRITE(ah, AR_RC, 0);
1595
1596         ath9k_hw_init_pll(ah, NULL);
1597
1598         if (AR_SREV_9100(ah))
1599                 udelay(50);
1600
1601         return true;
1602 }
1603
1604 static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1605 {
1606         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1607                   AR_RTC_FORCE_WAKE_ON_INT);
1608
1609         REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1610         REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1611
1612         if (!ath9k_hw_wait(ah,
1613                            AR_RTC_STATUS,
1614                            AR_RTC_STATUS_M,
1615                            AR_RTC_STATUS_ON)) {
1616                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: RTC not waking up\n",
1617                          __func__);
1618                 return false;
1619         }
1620
1621         ath9k_hw_read_revisions(ah);
1622
1623         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1624 }
1625
1626 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah,
1627                                    u32 type)
1628 {
1629         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1630                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1631
1632         switch (type) {
1633         case ATH9K_RESET_POWER_ON:
1634                 return ath9k_hw_set_reset_power_on(ah);
1635                 break;
1636         case ATH9K_RESET_WARM:
1637         case ATH9K_RESET_COLD:
1638                 return ath9k_hw_set_reset(ah, type);
1639                 break;
1640         default:
1641                 return false;
1642         }
1643 }
1644
1645 static
1646 struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
1647                                           struct ath9k_channel *chan)
1648 {
1649         if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
1650                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1651                          "%s: invalid channel %u/0x%x; not marked as "
1652                          "2GHz or 5GHz\n", __func__, chan->channel,
1653                          chan->channelFlags);
1654                 return NULL;
1655         }
1656
1657         if (!IS_CHAN_OFDM(chan) &&
1658               !IS_CHAN_CCK(chan) &&
1659               !IS_CHAN_HT20(chan) &&
1660               !IS_CHAN_HT40(chan)) {
1661                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1662                         "%s: invalid channel %u/0x%x; not marked as "
1663                         "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1664                         __func__, chan->channel, chan->channelFlags);
1665                 return NULL;
1666         }
1667
1668         return ath9k_regd_check_channel(ah, chan);
1669 }
1670
1671 static inline bool
1672 ath9k_hw_get_lower_upper_index(u8 target,
1673                                u8 *pList,
1674                                u16 listSize,
1675                                u16 *indexL,
1676                                u16 *indexR)
1677 {
1678         u16 i;
1679
1680         if (target <= pList[0]) {
1681                 *indexL = *indexR = 0;
1682                 return true;
1683         }
1684         if (target >= pList[listSize - 1]) {
1685                 *indexL = *indexR = (u16) (listSize - 1);
1686                 return true;
1687         }
1688
1689         for (i = 0; i < listSize - 1; i++) {
1690                 if (pList[i] == target) {
1691                         *indexL = *indexR = i;
1692                         return true;
1693                 }
1694                 if (target < pList[i + 1]) {
1695                         *indexL = i;
1696                         *indexR = (u16) (i + 1);
1697                         return false;
1698                 }
1699         }
1700         return false;
1701 }
1702
1703 static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
1704 {
1705         int16_t nfval;
1706         int16_t sort[ATH9K_NF_CAL_HIST_MAX];
1707         int i, j;
1708
1709         for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
1710                 sort[i] = nfCalBuffer[i];
1711
1712         for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
1713                 for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
1714                         if (sort[j] > sort[j - 1]) {
1715                                 nfval = sort[j];
1716                                 sort[j] = sort[j - 1];
1717                                 sort[j - 1] = nfval;
1718                         }
1719                 }
1720         }
1721         nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
1722
1723         return nfval;
1724 }
1725
1726 static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
1727                                               int16_t *nfarray)
1728 {
1729         int i;
1730
1731         for (i = 0; i < NUM_NF_READINGS; i++) {
1732                 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
1733
1734                 if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
1735                         h[i].currIndex = 0;
1736
1737                 if (h[i].invalidNFcount > 0) {
1738                         if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE
1739                             || nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) {
1740                                 h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX;
1741                         } else {
1742                                 h[i].invalidNFcount--;
1743                                 h[i].privNF = nfarray[i];
1744                         }
1745                 } else {
1746                         h[i].privNF =
1747                                 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
1748                 }
1749         }
1750         return;
1751 }
1752
1753 static void ar5416GetNoiseFloor(struct ath_hal *ah,
1754                                 int16_t nfarray[NUM_NF_READINGS])
1755 {
1756         int16_t nf;
1757
1758         if (AR_SREV_9280_10_OR_LATER(ah))
1759                 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
1760         else
1761                 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
1762
1763         if (nf & 0x100)
1764                 nf = 0 - ((nf ^ 0x1ff) + 1);
1765         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1766                  "NF calibrated [ctl] [chain 0] is %d\n", nf);
1767         nfarray[0] = nf;
1768
1769         if (AR_SREV_9280_10_OR_LATER(ah))
1770                 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
1771                         AR9280_PHY_CH1_MINCCA_PWR);
1772         else
1773                 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
1774                         AR_PHY_CH1_MINCCA_PWR);
1775
1776         if (nf & 0x100)
1777                 nf = 0 - ((nf ^ 0x1ff) + 1);
1778         DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1779                  "NF calibrated [ctl] [chain 1] is %d\n", nf);
1780         nfarray[1] = nf;
1781
1782         if (!AR_SREV_9280(ah)) {
1783                 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),
1784                         AR_PHY_CH2_MINCCA_PWR);
1785                 if (nf & 0x100)
1786                         nf = 0 - ((nf ^ 0x1ff) + 1);
1787                 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1788                          "NF calibrated [ctl] [chain 2] is %d\n", nf);
1789                 nfarray[2] = nf;
1790         }
1791
1792         if (AR_SREV_9280_10_OR_LATER(ah))
1793                 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
1794                         AR9280_PHY_EXT_MINCCA_PWR);
1795         else
1796                 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
1797                         AR_PHY_EXT_MINCCA_PWR);
1798
1799         if (nf & 0x100)
1800                 nf = 0 - ((nf ^ 0x1ff) + 1);
1801         DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1802                  "NF calibrated [ext] [chain 0] is %d\n", nf);
1803         nfarray[3] = nf;
1804
1805         if (AR_SREV_9280_10_OR_LATER(ah))
1806                 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
1807                         AR9280_PHY_CH1_EXT_MINCCA_PWR);
1808         else
1809                 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
1810                         AR_PHY_CH1_EXT_MINCCA_PWR);
1811
1812         if (nf & 0x100)
1813                 nf = 0 - ((nf ^ 0x1ff) + 1);
1814         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1815                  "NF calibrated [ext] [chain 1] is %d\n", nf);
1816         nfarray[4] = nf;
1817
1818         if (!AR_SREV_9280(ah)) {
1819                 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),
1820                         AR_PHY_CH2_EXT_MINCCA_PWR);
1821                 if (nf & 0x100)
1822                         nf = 0 - ((nf ^ 0x1ff) + 1);
1823                 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1824                          "NF calibrated [ext] [chain 2] is %d\n", nf);
1825                 nfarray[5] = nf;
1826         }
1827 }
1828
1829 static bool
1830 getNoiseFloorThresh(struct ath_hal *ah,
1831                     const struct ath9k_channel *chan,
1832                     int16_t *nft)
1833 {
1834         struct ath_hal_5416 *ahp = AH5416(ah);
1835
1836         switch (chan->chanmode) {
1837         case CHANNEL_A:
1838         case CHANNEL_A_HT20:
1839         case CHANNEL_A_HT40PLUS:
1840         case CHANNEL_A_HT40MINUS:
1841                 *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_5);
1842                 break;
1843         case CHANNEL_B:
1844         case CHANNEL_G:
1845         case CHANNEL_G_HT20:
1846         case CHANNEL_G_HT40PLUS:
1847         case CHANNEL_G_HT40MINUS:
1848                 *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_2);
1849                 break;
1850         default:
1851                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1852                          "%s: invalid channel flags 0x%x\n", __func__,
1853                          chan->channelFlags);
1854                 return false;
1855         }
1856         return true;
1857 }
1858
1859 static void ath9k_hw_start_nfcal(struct ath_hal *ah)
1860 {
1861         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1862                     AR_PHY_AGC_CONTROL_ENABLE_NF);
1863         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1864                     AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1865         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1866 }
1867
1868 static void
1869 ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan)
1870 {
1871         struct ath9k_nfcal_hist *h;
1872         int i, j;
1873         int32_t val;
1874         const u32 ar5416_cca_regs[6] = {
1875                 AR_PHY_CCA,
1876                 AR_PHY_CH1_CCA,
1877                 AR_PHY_CH2_CCA,
1878                 AR_PHY_EXT_CCA,
1879                 AR_PHY_CH1_EXT_CCA,
1880                 AR_PHY_CH2_EXT_CCA
1881         };
1882         u8 chainmask;
1883
1884         if (AR_SREV_9280(ah))
1885                 chainmask = 0x1B;
1886         else
1887                 chainmask = 0x3F;
1888
1889 #ifdef ATH_NF_PER_CHAN
1890         h = chan->nfCalHist;
1891 #else
1892         h = ah->nfCalHist;
1893 #endif
1894
1895         for (i = 0; i < NUM_NF_READINGS; i++) {
1896                 if (chainmask & (1 << i)) {
1897                         val = REG_READ(ah, ar5416_cca_regs[i]);
1898                         val &= 0xFFFFFE00;
1899                         val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
1900                         REG_WRITE(ah, ar5416_cca_regs[i], val);
1901                 }
1902         }
1903
1904         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1905                     AR_PHY_AGC_CONTROL_ENABLE_NF);
1906         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1907                     AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1908         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1909
1910         for (j = 0; j < 1000; j++) {
1911                 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
1912                      AR_PHY_AGC_CONTROL_NF) == 0)
1913                         break;
1914                 udelay(10);
1915         }
1916
1917         for (i = 0; i < NUM_NF_READINGS; i++) {
1918                 if (chainmask & (1 << i)) {
1919                         val = REG_READ(ah, ar5416_cca_regs[i]);
1920                         val &= 0xFFFFFE00;
1921                         val |= (((u32) (-50) << 1) & 0x1ff);
1922                         REG_WRITE(ah, ar5416_cca_regs[i], val);
1923                 }
1924         }
1925 }
1926
1927 static int16_t ath9k_hw_getnf(struct ath_hal *ah,
1928                               struct ath9k_channel *chan)
1929 {
1930         int16_t nf, nfThresh;
1931         int16_t nfarray[NUM_NF_READINGS] = { 0 };
1932         struct ath9k_nfcal_hist *h;
1933         u8 chainmask;
1934
1935         if (AR_SREV_9280(ah))
1936                 chainmask = 0x1B;
1937         else
1938                 chainmask = 0x3F;
1939
1940         chan->channelFlags &= (~CHANNEL_CW_INT);
1941         if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
1942                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1943                          "%s: NF did not complete in calibration window\n",
1944                          __func__);
1945                 nf = 0;
1946                 chan->rawNoiseFloor = nf;
1947                 return chan->rawNoiseFloor;
1948         } else {
1949                 ar5416GetNoiseFloor(ah, nfarray);
1950                 nf = nfarray[0];
1951                 if (getNoiseFloorThresh(ah, chan, &nfThresh)
1952                     && nf > nfThresh) {
1953                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1954                                  "%s: noise floor failed detected; "
1955                                  "detected %d, threshold %d\n", __func__,
1956                                  nf, nfThresh);
1957                         chan->channelFlags |= CHANNEL_CW_INT;
1958                 }
1959         }
1960
1961 #ifdef ATH_NF_PER_CHAN
1962         h = chan->nfCalHist;
1963 #else
1964         h = ah->nfCalHist;
1965 #endif
1966
1967         ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
1968         chan->rawNoiseFloor = h[0].privNF;
1969
1970         return chan->rawNoiseFloor;
1971 }
1972
1973 static void ath9k_hw_update_mibstats(struct ath_hal *ah,
1974                               struct ath9k_mib_stats *stats)
1975 {
1976         stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
1977         stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
1978         stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
1979         stats->rts_good += REG_READ(ah, AR_RTS_OK);
1980         stats->beacons += REG_READ(ah, AR_BEACON_CNT);
1981 }
1982
1983 static void ath9k_enable_mib_counters(struct ath_hal *ah)
1984 {
1985         struct ath_hal_5416 *ahp = AH5416(ah);
1986
1987         DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable mib counters\n");
1988
1989         ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
1990
1991         REG_WRITE(ah, AR_FILT_OFDM, 0);
1992         REG_WRITE(ah, AR_FILT_CCK, 0);
1993         REG_WRITE(ah, AR_MIBC,
1994                   ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS)
1995                   & 0x0f);
1996         REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
1997         REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
1998 }
1999
2000 static void ath9k_hw_disable_mib_counters(struct ath_hal *ah)
2001 {
2002         struct ath_hal_5416 *ahp = AH5416(ah);
2003
2004         DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disabling MIB counters\n");
2005
2006         REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC);
2007
2008         ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2009
2010         REG_WRITE(ah, AR_FILT_OFDM, 0);
2011         REG_WRITE(ah, AR_FILT_CCK, 0);
2012 }
2013
2014 static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah,
2015                                         struct ath9k_channel *chan)
2016 {
2017         struct ath_hal_5416 *ahp = AH5416(ah);
2018         int i;
2019
2020         for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
2021                 if (ahp->ah_ani[i].c.channel == chan->channel)
2022                         return i;
2023                 if (ahp->ah_ani[i].c.channel == 0) {
2024                         ahp->ah_ani[i].c.channel = chan->channel;
2025                         ahp->ah_ani[i].c.channelFlags = chan->channelFlags;
2026                         return i;
2027                 }
2028         }
2029
2030         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2031                  "No more channel states left. Using channel 0\n");
2032         return 0;
2033 }
2034
2035 static void ath9k_hw_ani_attach(struct ath_hal *ah)
2036 {
2037         struct ath_hal_5416 *ahp = AH5416(ah);
2038         int i;
2039
2040         ahp->ah_hasHwPhyCounters = 1;
2041
2042         memset(ahp->ah_ani, 0, sizeof(ahp->ah_ani));
2043         for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
2044                 ahp->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH;
2045                 ahp->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW;
2046                 ahp->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH;
2047                 ahp->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW;
2048                 ahp->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
2049                 ahp->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
2050                 ahp->ah_ani[i].ofdmWeakSigDetectOff =
2051                         !ATH9K_ANI_USE_OFDM_WEAK_SIG;
2052                 ahp->ah_ani[i].cckWeakSigThreshold =
2053                         ATH9K_ANI_CCK_WEAK_SIG_THR;
2054                 ahp->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
2055                 ahp->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
2056                 if (ahp->ah_hasHwPhyCounters) {
2057                         ahp->ah_ani[i].ofdmPhyErrBase =
2058                                 AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH;
2059                         ahp->ah_ani[i].cckPhyErrBase =
2060                                 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
2061                 }
2062         }
2063         if (ahp->ah_hasHwPhyCounters) {
2064                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2065                         "Setting OfdmErrBase = 0x%08x\n",
2066                         ahp->ah_ani[0].ofdmPhyErrBase);
2067                 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
2068                         ahp->ah_ani[0].cckPhyErrBase);
2069
2070                 REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase);
2071                 REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase);
2072                 ath9k_enable_mib_counters(ah);
2073         }
2074         ahp->ah_aniPeriod = ATH9K_ANI_PERIOD;
2075         if (ah->ah_config.enable_ani)
2076                 ahp->ah_procPhyErr |= HAL_PROCESS_ANI;
2077 }
2078
2079 static void ath9k_hw_ani_setup(struct ath_hal *ah)
2080 {
2081         struct ath_hal_5416 *ahp = AH5416(ah);
2082         int i;
2083
2084         const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
2085         const int coarseHigh[] = { -14, -14, -14, -14, -12 };
2086         const int coarseLow[] = { -64, -64, -64, -64, -70 };
2087         const int firpwr[] = { -78, -78, -78, -78, -80 };
2088
2089         for (i = 0; i < 5; i++) {
2090                 ahp->ah_totalSizeDesired[i] = totalSizeDesired[i];
2091                 ahp->ah_coarseHigh[i] = coarseHigh[i];
2092                 ahp->ah_coarseLow[i] = coarseLow[i];
2093                 ahp->ah_firpwr[i] = firpwr[i];
2094         }
2095 }
2096
2097 static void ath9k_hw_ani_detach(struct ath_hal *ah)
2098 {
2099         struct ath_hal_5416 *ahp = AH5416(ah);
2100
2101         DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detaching Ani\n");
2102         if (ahp->ah_hasHwPhyCounters) {
2103                 ath9k_hw_disable_mib_counters(ah);
2104                 REG_WRITE(ah, AR_PHY_ERR_1, 0);
2105                 REG_WRITE(ah, AR_PHY_ERR_2, 0);
2106         }
2107 }
2108
2109
2110 static bool ath9k_hw_ani_control(struct ath_hal *ah,
2111                                  enum ath9k_ani_cmd cmd, int param)
2112 {
2113         struct ath_hal_5416 *ahp = AH5416(ah);
2114         struct ar5416AniState *aniState = ahp->ah_curani;
2115
2116         switch (cmd & ahp->ah_ani_function) {
2117         case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
2118                 u32 level = param;
2119
2120                 if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) {
2121                         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2122                                  "%s: level out of range (%u > %u)\n",
2123                                  __func__, level,
2124                                  (unsigned) ARRAY_SIZE(ahp->
2125                                                        ah_totalSizeDesired));
2126                         return false;
2127                 }
2128
2129                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
2130                               AR_PHY_DESIRED_SZ_TOT_DES,
2131                               ahp->ah_totalSizeDesired[level]);
2132                 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2133                               AR_PHY_AGC_CTL1_COARSE_LOW,
2134                               ahp->ah_coarseLow[level]);
2135                 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2136                               AR_PHY_AGC_CTL1_COARSE_HIGH,
2137                               ahp->ah_coarseHigh[level]);
2138                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2139                               AR_PHY_FIND_SIG_FIRPWR,
2140                               ahp->ah_firpwr[level]);
2141
2142                 if (level > aniState->noiseImmunityLevel)
2143                         ahp->ah_stats.ast_ani_niup++;
2144                 else if (level < aniState->noiseImmunityLevel)
2145                         ahp->ah_stats.ast_ani_nidown++;
2146                 aniState->noiseImmunityLevel = level;
2147                 break;
2148         }
2149         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
2150                 const int m1ThreshLow[] = { 127, 50 };
2151                 const int m2ThreshLow[] = { 127, 40 };
2152                 const int m1Thresh[] = { 127, 0x4d };
2153                 const int m2Thresh[] = { 127, 0x40 };
2154                 const int m2CountThr[] = { 31, 16 };
2155                 const int m2CountThrLow[] = { 63, 48 };
2156                 u32 on = param ? 1 : 0;
2157
2158                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2159                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
2160                               m1ThreshLow[on]);
2161                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2162                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
2163                               m2ThreshLow[on]);
2164                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2165                               AR_PHY_SFCORR_M1_THRESH,
2166                               m1Thresh[on]);
2167                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2168                               AR_PHY_SFCORR_M2_THRESH,
2169                               m2Thresh[on]);
2170                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2171                               AR_PHY_SFCORR_M2COUNT_THR,
2172                               m2CountThr[on]);
2173                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2174                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
2175                               m2CountThrLow[on]);
2176
2177                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2178                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
2179                               m1ThreshLow[on]);
2180                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2181                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
2182                               m2ThreshLow[on]);
2183                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2184                               AR_PHY_SFCORR_EXT_M1_THRESH,
2185                               m1Thresh[on]);
2186                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2187                               AR_PHY_SFCORR_EXT_M2_THRESH,
2188                               m2Thresh[on]);
2189
2190                 if (on)
2191                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
2192                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2193                 else
2194                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
2195                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2196
2197                 if (!on != aniState->ofdmWeakSigDetectOff) {
2198                         if (on)
2199                                 ahp->ah_stats.ast_ani_ofdmon++;
2200                         else
2201                                 ahp->ah_stats.ast_ani_ofdmoff++;
2202                         aniState->ofdmWeakSigDetectOff = !on;
2203                 }
2204                 break;
2205         }
2206         case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
2207                 const int weakSigThrCck[] = { 8, 6 };
2208                 u32 high = param ? 1 : 0;
2209
2210                 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
2211                               AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
2212                               weakSigThrCck[high]);
2213                 if (high != aniState->cckWeakSigThreshold) {
2214                         if (high)
2215                                 ahp->ah_stats.ast_ani_cckhigh++;
2216                         else
2217                                 ahp->ah_stats.ast_ani_ccklow++;
2218                         aniState->cckWeakSigThreshold = high;
2219                 }
2220                 break;
2221         }
2222         case ATH9K_ANI_FIRSTEP_LEVEL:{
2223                 const int firstep[] = { 0, 4, 8 };
2224                 u32 level = param;
2225
2226                 if (level >= ARRAY_SIZE(firstep)) {
2227                         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2228                                  "%s: level out of range (%u > %u)\n",
2229                                  __func__, level,
2230                                 (unsigned) ARRAY_SIZE(firstep));
2231                         return false;
2232                 }
2233                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2234                               AR_PHY_FIND_SIG_FIRSTEP,
2235                               firstep[level]);
2236                 if (level > aniState->firstepLevel)
2237                         ahp->ah_stats.ast_ani_stepup++;
2238                 else if (level < aniState->firstepLevel)
2239                         ahp->ah_stats.ast_ani_stepdown++;
2240                 aniState->firstepLevel = level;
2241                 break;
2242         }
2243         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
2244                 const int cycpwrThr1[] =
2245                         { 2, 4, 6, 8, 10, 12, 14, 16 };
2246                 u32 level = param;
2247
2248                 if (level >= ARRAY_SIZE(cycpwrThr1)) {
2249                         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2250                                  "%s: level out of range (%u > %u)\n",
2251                                  __func__, level,
2252                                  (unsigned)
2253                                 ARRAY_SIZE(cycpwrThr1));
2254                         return false;
2255                 }
2256                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
2257                               AR_PHY_TIMING5_CYCPWR_THR1,
2258                               cycpwrThr1[level]);
2259                 if (level > aniState->spurImmunityLevel)
2260                         ahp->ah_stats.ast_ani_spurup++;
2261                 else if (level < aniState->spurImmunityLevel)
2262                         ahp->ah_stats.ast_ani_spurdown++;
2263                 aniState->spurImmunityLevel = level;
2264                 break;
2265         }
2266         case ATH9K_ANI_PRESENT:
2267                 break;
2268         default:
2269                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2270                         "%s: invalid cmd %u\n", __func__, cmd);
2271                 return false;
2272         }
2273
2274         DPRINTF(ah->ah_sc, ATH_DBG_ANI, "%s: ANI parameters:\n", __func__);
2275         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2276                 "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
2277                 "ofdmWeakSigDetectOff=%d\n",
2278                  aniState->noiseImmunityLevel, aniState->spurImmunityLevel,
2279                  !aniState->ofdmWeakSigDetectOff);
2280         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2281                 "cckWeakSigThreshold=%d, "
2282                 "firstepLevel=%d, listenTime=%d\n",
2283                  aniState->cckWeakSigThreshold, aniState->firstepLevel,
2284                  aniState->listenTime);
2285         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2286                  "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
2287                  aniState->cycleCount, aniState->ofdmPhyErrCount,
2288                  aniState->cckPhyErrCount);
2289         return true;
2290 }
2291
2292 static void ath9k_ani_restart(struct ath_hal *ah)
2293 {
2294         struct ath_hal_5416 *ahp = AH5416(ah);
2295         struct ar5416AniState *aniState;
2296
2297         if (!DO_ANI(ah))
2298                 return;
2299
2300         aniState = ahp->ah_curani;
2301
2302         aniState->listenTime = 0;
2303         if (ahp->ah_hasHwPhyCounters) {
2304                 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
2305                         aniState->ofdmPhyErrBase = 0;
2306                         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2307                                  "OFDM Trigger is too high for hw counters\n");
2308                 } else {
2309                         aniState->ofdmPhyErrBase =
2310                                 AR_PHY_COUNTMAX - aniState->ofdmTrigHigh;
2311                 }
2312                 if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
2313                         aniState->cckPhyErrBase = 0;
2314                         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2315                                  "CCK Trigger is too high for hw counters\n");
2316                 } else {
2317                         aniState->cckPhyErrBase =
2318                                 AR_PHY_COUNTMAX - aniState->cckTrigHigh;
2319                 }
2320                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2321                          "%s: Writing ofdmbase=%u   cckbase=%u\n",
2322                          __func__, aniState->ofdmPhyErrBase,
2323                          aniState->cckPhyErrBase);
2324                 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
2325                 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
2326                 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2327                 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2328
2329                 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2330         }
2331         aniState->ofdmPhyErrCount = 0;
2332         aniState->cckPhyErrCount = 0;
2333 }
2334
2335 static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
2336 {
2337         struct ath_hal_5416 *ahp = AH5416(ah);
2338         struct ath9k_channel *chan = ah->ah_curchan;
2339         struct ar5416AniState *aniState;
2340         enum wireless_mode mode;
2341         int32_t rssi;
2342
2343         if (!DO_ANI(ah))
2344                 return;
2345
2346         aniState = ahp->ah_curani;
2347
2348         if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
2349                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2350                                          aniState->noiseImmunityLevel + 1)) {
2351                         return;
2352                 }
2353         }
2354
2355         if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
2356                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2357                                          aniState->spurImmunityLevel + 1)) {
2358                         return;
2359                 }
2360         }
2361
2362         if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2363                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2364                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2365                                              aniState->firstepLevel + 1);
2366                 }
2367                 return;
2368         }
2369         rssi = BEACON_RSSI(ahp);
2370         if (rssi > aniState->rssiThrHigh) {
2371                 if (!aniState->ofdmWeakSigDetectOff) {
2372                         if (ath9k_hw_ani_control(ah,
2373                                          ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2374                                          false)) {
2375                                 ath9k_hw_ani_control(ah,
2376                                         ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2377                                         0);
2378                                 return;
2379                         }
2380                 }
2381                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2382                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2383                                              aniState->firstepLevel + 1);
2384                         return;
2385                 }
2386         } else if (rssi > aniState->rssiThrLow) {
2387                 if (aniState->ofdmWeakSigDetectOff)
2388                         ath9k_hw_ani_control(ah,
2389                                      ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2390                                      true);
2391                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
2392                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2393                                              aniState->firstepLevel + 1);
2394                 return;
2395         } else {
2396                 mode = ath9k_hw_chan2wmode(ah, chan);
2397                 if (mode == ATH9K_MODE_11G || mode == ATH9K_MODE_11B) {
2398                         if (!aniState->ofdmWeakSigDetectOff)
2399                                 ath9k_hw_ani_control(ah,
2400                                      ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2401                                      false);
2402                         if (aniState->firstepLevel > 0)
2403                                 ath9k_hw_ani_control(ah,
2404                                                      ATH9K_ANI_FIRSTEP_LEVEL,
2405                                                      0);
2406                         return;
2407                 }
2408         }
2409 }
2410
2411 static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
2412 {
2413         struct ath_hal_5416 *ahp = AH5416(ah);
2414         struct ath9k_channel *chan = ah->ah_curchan;
2415         struct ar5416AniState *aniState;
2416         enum wireless_mode mode;
2417         int32_t rssi;
2418
2419         if (!DO_ANI(ah))
2420                 return;
2421
2422         aniState = ahp->ah_curani;
2423         if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
2424                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2425                                          aniState->noiseImmunityLevel + 1)) {
2426                         return;
2427                 }
2428         }
2429         if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2430                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2431                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2432                                              aniState->firstepLevel + 1);
2433                 }
2434                 return;
2435         }
2436         rssi = BEACON_RSSI(ahp);
2437         if (rssi > aniState->rssiThrLow) {
2438                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
2439                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2440                                              aniState->firstepLevel + 1);
2441         } else {
2442                 mode = ath9k_hw_chan2wmode(ah, chan);
2443                 if (mode == ATH9K_MODE_11G || mode == ATH9K_MODE_11B) {
2444                         if (aniState->firstepLevel > 0)
2445                                 ath9k_hw_ani_control(ah,
2446                                                      ATH9K_ANI_FIRSTEP_LEVEL,
2447                                                      0);
2448                 }
2449         }
2450 }
2451
2452 static void ath9k_ani_reset(struct ath_hal *ah)
2453 {
2454         struct ath_hal_5416 *ahp = AH5416(ah);
2455         struct ar5416AniState *aniState;
2456         struct ath9k_channel *chan = ah->ah_curchan;
2457         int index;
2458
2459         if (!DO_ANI(ah))
2460                 return;
2461
2462         index = ath9k_hw_get_ani_channel_idx(ah, chan);
2463         aniState = &ahp->ah_ani[index];
2464         ahp->ah_curani = aniState;
2465
2466         if (DO_ANI(ah) && ah->ah_opmode != ATH9K_M_STA
2467             && ah->ah_opmode != ATH9K_M_IBSS) {
2468                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2469                          "%s: Reset ANI state opmode %u\n", __func__,
2470                          ah->ah_opmode);
2471                 ahp->ah_stats.ast_ani_reset++;
2472                 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
2473                 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
2474                 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0);
2475                 ath9k_hw_ani_control(ah,
2476                                      ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2477                                      !ATH9K_ANI_USE_OFDM_WEAK_SIG);
2478                 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
2479                                      ATH9K_ANI_CCK_WEAK_SIG_THR);
2480                 ath9k_hw_setrxfilter(ah,
2481                                      ath9k_hw_getrxfilter(ah) |
2482                                      ATH9K_RX_FILTER_PHYERR);
2483                 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2484                         ahp->ah_curani->ofdmTrigHigh =
2485                                 ah->ah_config.ofdm_trig_high;
2486                         ahp->ah_curani->ofdmTrigLow =
2487                                 ah->ah_config.ofdm_trig_low;
2488                         ahp->ah_curani->cckTrigHigh =
2489                                 ah->ah_config.cck_trig_high;
2490                         ahp->ah_curani->cckTrigLow =
2491                                 ah->ah_config.cck_trig_low;
2492                 }
2493                 ath9k_ani_restart(ah);
2494                 return;
2495         }
2496
2497         if (aniState->noiseImmunityLevel != 0)
2498                 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2499                                      aniState->noiseImmunityLevel);
2500         if (aniState->spurImmunityLevel != 0)
2501                 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2502                                      aniState->spurImmunityLevel);
2503         if (aniState->ofdmWeakSigDetectOff)
2504                 ath9k_hw_ani_control(ah,
2505                                      ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2506                                      !aniState->ofdmWeakSigDetectOff);
2507         if (aniState->cckWeakSigThreshold)
2508                 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
2509                                      aniState->cckWeakSigThreshold);
2510         if (aniState->firstepLevel != 0)
2511                 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2512                                      aniState->firstepLevel);
2513         if (ahp->ah_hasHwPhyCounters) {
2514                 ath9k_hw_setrxfilter(ah,
2515                                      ath9k_hw_getrxfilter(ah) &
2516                                      ~ATH9K_RX_FILTER_PHYERR);
2517                 ath9k_ani_restart(ah);
2518                 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2519                 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2520
2521         } else {
2522                 ath9k_ani_restart(ah);
2523                 ath9k_hw_setrxfilter(ah,
2524                                      ath9k_hw_getrxfilter(ah) |
2525                                      ATH9K_RX_FILTER_PHYERR);
2526         }
2527 }
2528
2529 void ath9k_hw_procmibevent(struct ath_hal *ah,
2530                            const struct ath9k_node_stats *stats)
2531 {
2532         struct ath_hal_5416 *ahp = AH5416(ah);
2533         u32 phyCnt1, phyCnt2;
2534
2535         DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Processing Mib Intr\n");
2536
2537         REG_WRITE(ah, AR_FILT_OFDM, 0);
2538         REG_WRITE(ah, AR_FILT_CCK, 0);
2539         if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
2540                 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
2541
2542         ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2543         ahp->ah_stats.ast_nodestats = *stats;
2544
2545         if (!DO_ANI(ah))
2546                 return;
2547
2548         phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
2549         phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
2550         if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
2551             ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
2552                 struct ar5416AniState *aniState = ahp->ah_curani;
2553                 u32 ofdmPhyErrCnt, cckPhyErrCnt;
2554
2555                 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
2556                 ahp->ah_stats.ast_ani_ofdmerrs +=
2557                         ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
2558                 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
2559
2560                 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
2561                 ahp->ah_stats.ast_ani_cckerrs +=
2562                         cckPhyErrCnt - aniState->cckPhyErrCount;
2563                 aniState->cckPhyErrCount = cckPhyErrCnt;
2564
2565                 if (aniState->ofdmPhyErrCount > aniState->ofdmTrigHigh)
2566                         ath9k_hw_ani_ofdm_err_trigger(ah);
2567                 if (aniState->cckPhyErrCount > aniState->cckTrigHigh)
2568                         ath9k_hw_ani_cck_err_trigger(ah);
2569
2570                 ath9k_ani_restart(ah);
2571         }
2572 }
2573
2574 static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
2575 {
2576         struct ath_hal_5416 *ahp = AH5416(ah);
2577         struct ar5416AniState *aniState;
2578         int32_t rssi;
2579
2580         aniState = ahp->ah_curani;
2581
2582         if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2583                 if (aniState->firstepLevel > 0) {
2584                         if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2585                                                  aniState->firstepLevel - 1)) {
2586                                 return;
2587                         }
2588                 }
2589         } else {
2590                 rssi = BEACON_RSSI(ahp);
2591                 if (rssi > aniState->rssiThrHigh) {
2592                         /* XXX: Handle me */
2593                 } else if (rssi > aniState->rssiThrLow) {
2594                         if (aniState->ofdmWeakSigDetectOff) {
2595                                 if (ath9k_hw_ani_control(ah,
2596                                          ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2597                                          true) ==
2598                                     true) {
2599                                         return;
2600                                 }
2601                         }
2602                         if (aniState->firstepLevel > 0) {
2603                                 if (ath9k_hw_ani_control
2604                                     (ah, ATH9K_ANI_FIRSTEP_LEVEL,
2605                                      aniState->firstepLevel - 1) ==
2606                                     true) {
2607                                         return;
2608                                 }
2609                         }
2610                 } else {
2611                         if (aniState->firstepLevel > 0) {
2612                                 if (ath9k_hw_ani_control
2613                                     (ah, ATH9K_ANI_FIRSTEP_LEVEL,
2614                                      aniState->firstepLevel - 1) ==
2615                                     true) {
2616                                         return;
2617                                 }
2618                         }
2619                 }
2620         }
2621
2622         if (aniState->spurImmunityLevel > 0) {
2623                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2624                                          aniState->spurImmunityLevel - 1)) {
2625                         return;
2626                 }
2627         }
2628
2629         if (aniState->noiseImmunityLevel > 0) {
2630                 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2631                                      aniState->noiseImmunityLevel - 1);
2632                 return;
2633         }
2634 }
2635
2636 static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah)
2637 {
2638         struct ath_hal_5416 *ahp = AH5416(ah);
2639         struct ar5416AniState *aniState;
2640         u32 txFrameCount, rxFrameCount, cycleCount;
2641         int32_t listenTime;
2642
2643         txFrameCount = REG_READ(ah, AR_TFCNT);
2644         rxFrameCount = REG_READ(ah, AR_RFCNT);
2645         cycleCount = REG_READ(ah, AR_CCCNT);
2646
2647         aniState = ahp->ah_curani;
2648         if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
2649
2650                 listenTime = 0;
2651                 ahp->ah_stats.ast_ani_lzero++;
2652         } else {
2653                 int32_t ccdelta = cycleCount - aniState->cycleCount;
2654                 int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
2655                 int32_t tfdelta = txFrameCount - aniState->txFrameCount;
2656                 listenTime = (ccdelta - rfdelta - tfdelta) / 44000;
2657         }
2658         aniState->cycleCount = cycleCount;
2659         aniState->txFrameCount = txFrameCount;
2660         aniState->rxFrameCount = rxFrameCount;
2661
2662         return listenTime;
2663 }
2664
2665 void ath9k_hw_ani_monitor(struct ath_hal *ah,
2666                           const struct ath9k_node_stats *stats,
2667                           struct ath9k_channel *chan)
2668 {
2669         struct ath_hal_5416 *ahp = AH5416(ah);
2670         struct ar5416AniState *aniState;
2671         int32_t listenTime;
2672
2673         aniState = ahp->ah_curani;
2674         ahp->ah_stats.ast_nodestats = *stats;
2675
2676         listenTime = ath9k_hw_ani_get_listen_time(ah);
2677         if (listenTime < 0) {
2678                 ahp->ah_stats.ast_ani_lneg++;
2679                 ath9k_ani_restart(ah);
2680                 return;
2681         }
2682
2683         aniState->listenTime += listenTime;
2684
2685         if (ahp->ah_hasHwPhyCounters) {
2686                 u32 phyCnt1, phyCnt2;
2687                 u32 ofdmPhyErrCnt, cckPhyErrCnt;
2688
2689                 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2690
2691                 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
2692                 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
2693
2694                 if (phyCnt1 < aniState->ofdmPhyErrBase ||
2695                     phyCnt2 < aniState->cckPhyErrBase) {
2696                         if (phyCnt1 < aniState->ofdmPhyErrBase) {
2697                                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2698                                          "%s: phyCnt1 0x%x, resetting "
2699                                          "counter value to 0x%x\n",
2700                                          __func__, phyCnt1,
2701                                          aniState->ofdmPhyErrBase);
2702                                 REG_WRITE(ah, AR_PHY_ERR_1,
2703                                           aniState->ofdmPhyErrBase);
2704                                 REG_WRITE(ah, AR_PHY_ERR_MASK_1,
2705                                           AR_PHY_ERR_OFDM_TIMING);
2706                         }
2707                         if (phyCnt2 < aniState->cckPhyErrBase) {
2708                                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2709                                          "%s: phyCnt2 0x%x, resetting "
2710                                          "counter value to 0x%x\n",
2711                                          __func__, phyCnt2,
2712                                          aniState->cckPhyErrBase);
2713                                 REG_WRITE(ah, AR_PHY_ERR_2,
2714                                           aniState->cckPhyErrBase);
2715                                 REG_WRITE(ah, AR_PHY_ERR_MASK_2,
2716                                           AR_PHY_ERR_CCK_TIMING);
2717                         }
2718                         return;
2719                 }
2720
2721                 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
2722                 ahp->ah_stats.ast_ani_ofdmerrs +=
2723                         ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
2724                 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
2725
2726                 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
2727                 ahp->ah_stats.ast_ani_cckerrs +=
2728                         cckPhyErrCnt - aniState->cckPhyErrCount;
2729                 aniState->cckPhyErrCount = cckPhyErrCnt;
2730         }
2731
2732         if (!DO_ANI(ah))
2733                 return;
2734
2735         if (aniState->listenTime > 5 * ahp->ah_aniPeriod) {
2736                 if (aniState->ofdmPhyErrCount <= aniState->listenTime *
2737                     aniState->ofdmTrigLow / 1000 &&
2738                     aniState->cckPhyErrCount <= aniState->listenTime *
2739                     aniState->cckTrigLow / 1000)
2740                         ath9k_hw_ani_lower_immunity(ah);
2741                 ath9k_ani_restart(ah);
2742         } else if (aniState->listenTime > ahp->ah_aniPeriod) {
2743                 if (aniState->ofdmPhyErrCount > aniState->listenTime *
2744                     aniState->ofdmTrigHigh / 1000) {
2745                         ath9k_hw_ani_ofdm_err_trigger(ah);
2746                         ath9k_ani_restart(ah);
2747                 } else if (aniState->cckPhyErrCount >
2748                            aniState->listenTime * aniState->cckTrigHigh /
2749                            1000) {
2750                         ath9k_hw_ani_cck_err_trigger(ah);
2751                         ath9k_ani_restart(ah);
2752                 }
2753         }
2754 }
2755
2756 #ifndef ATH_NF_PER_CHAN
2757 static void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah)
2758 {
2759         int i, j;
2760
2761         for (i = 0; i < NUM_NF_READINGS; i++) {
2762                 ah->nfCalHist[i].currIndex = 0;
2763                 ah->nfCalHist[i].privNF = AR_PHY_CCA_MAX_GOOD_VALUE;
2764                 ah->nfCalHist[i].invalidNFcount =
2765                         AR_PHY_CCA_FILTERWINDOW_LENGTH;
2766                 for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
2767                         ah->nfCalHist[i].nfCalBuffer[j] =
2768                                 AR_PHY_CCA_MAX_GOOD_VALUE;
2769                 }
2770         }
2771         return;
2772 }
2773 #endif
2774
2775 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
2776                                          u32 gpio, u32 type)
2777 {
2778         int addr;
2779         u32 gpio_shift, tmp;
2780
2781         if (gpio > 11)
2782                 addr = AR_GPIO_OUTPUT_MUX3;
2783         else if (gpio > 5)
2784                 addr = AR_GPIO_OUTPUT_MUX2;
2785         else
2786                 addr = AR_GPIO_OUTPUT_MUX1;
2787
2788         gpio_shift = (gpio % 6) * 5;
2789
2790         if (AR_SREV_9280_20_OR_LATER(ah)
2791             || (addr != AR_GPIO_OUTPUT_MUX1)) {
2792                 REG_RMW(ah, addr, (type << gpio_shift),
2793                         (0x1f << gpio_shift));
2794         } else {
2795                 tmp = REG_READ(ah, addr);
2796                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2797                 tmp &= ~(0x1f << gpio_shift);
2798                 tmp |= (type << gpio_shift);
2799                 REG_WRITE(ah, addr, tmp);
2800         }
2801 }
2802
2803 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
2804                          u32 ah_signal_type)
2805 {
2806         u32 gpio_shift;
2807
2808         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2809
2810         gpio_shift = 2 * gpio;
2811
2812         REG_RMW(ah,
2813                 AR_GPIO_OE_OUT,
2814                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2815                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2816 }
2817
2818 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
2819 {
2820         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2821                 AR_GPIO_BIT(gpio));
2822 }
2823
2824 static u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
2825 {
2826         if (gpio >= ah->ah_caps.num_gpio_pins)
2827                 return 0xffffffff;
2828
2829         if (AR_SREV_9280_10_OR_LATER(ah)) {
2830                 return (MS
2831                         (REG_READ(ah, AR_GPIO_IN_OUT),
2832                          AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
2833         } else {
2834                 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
2835                         AR_GPIO_BIT(gpio)) != 0;
2836         }
2837 }
2838
2839 static int ath9k_hw_post_attach(struct ath_hal *ah)
2840 {
2841         int ecode;
2842
2843         if (!ath9k_hw_chip_test(ah)) {
2844                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
2845                          "%s: hardware self-test failed\n", __func__);
2846                 return -ENODEV;
2847         }
2848
2849         ecode = ath9k_hw_rf_claim(ah);
2850         if (ecode != 0)
2851                 return ecode;
2852
2853         ecode = ath9k_hw_eeprom_attach(ah);
2854         if (ecode != 0)
2855                 return ecode;
2856         ecode = ath9k_hw_rfattach(ah);
2857         if (ecode != 0)
2858                 return ecode;
2859
2860         if (!AR_SREV_9100(ah)) {
2861                 ath9k_hw_ani_setup(ah);
2862                 ath9k_hw_ani_attach(ah);
2863         }
2864         return 0;
2865 }
2866
2867 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
2868                                     struct ar5416_eeprom *pEepData,
2869                                     u32 reg, u32 value)
2870 {
2871         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
2872
2873         switch (ah->ah_devid) {
2874         case AR9280_DEVID_PCI:
2875                 if (reg == 0x7894) {
2876                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2877                                  "ini VAL: %x  EEPROM: %x\n", value,
2878                                  (pBase->version & 0xff));
2879
2880                         if ((pBase->version & 0xff) > 0x0a) {
2881                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2882                                          "PWDCLKIND: %d\n",
2883                                          pBase->pwdclkind);
2884                                 value &= ~AR_AN_TOP2_PWDCLKIND;
2885                                 value |= AR_AN_TOP2_PWDCLKIND & (pBase->
2886                                          pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
2887                         } else {
2888                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2889                                          "PWDCLKIND Earlier Rev\n");
2890                         }
2891
2892                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2893                                  "final ini VAL: %x\n", value);
2894                 }
2895                 break;
2896         }
2897         return value;
2898 }
2899
2900 static bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
2901 {
2902         struct ath_hal_5416 *ahp = AH5416(ah);
2903         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2904         u16 capField = 0, eeval;
2905
2906         eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_0);
2907
2908         ah->ah_currentRD = eeval;
2909
2910         eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_1);
2911         ah->ah_currentRDExt = eeval;
2912
2913         capField = ath9k_hw_get_eeprom(ahp, EEP_OP_CAP);
2914
2915         if (ah->ah_opmode != ATH9K_M_HOSTAP &&
2916             ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2917                 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
2918                         ah->ah_currentRD += 5;
2919                 else if (ah->ah_currentRD == 0x41)
2920                         ah->ah_currentRD = 0x43;
2921                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
2922                          "%s: regdomain mapped to 0x%x\n", __func__,
2923                          ah->ah_currentRD);
2924         }
2925
2926         eeval = ath9k_hw_get_eeprom(ahp, EEP_OP_MODE);
2927         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2928
2929         if (eeval & AR5416_OPFLAGS_11A) {
2930                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2931                 if (ah->ah_config.ht_enable) {
2932                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2933                                 set_bit(ATH9K_MODE_11NA_HT20,
2934                                         pCap->wireless_modes);
2935                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2936                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2937                                         pCap->wireless_modes);
2938                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2939                                         pCap->wireless_modes);
2940                         }
2941                 }
2942         }
2943
2944         if (eeval & AR5416_OPFLAGS_11G) {
2945                 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
2946                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2947                 if (ah->ah_config.ht_enable) {
2948                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2949                                 set_bit(ATH9K_MODE_11NG_HT20,
2950                                         pCap->wireless_modes);
2951                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2952                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2953                                         pCap->wireless_modes);
2954                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2955                                         pCap->wireless_modes);
2956                         }
2957                 }
2958         }
2959
2960         pCap->tx_chainmask = ath9k_hw_get_eeprom(ahp, EEP_TX_MASK);
2961         if ((ah->ah_isPciExpress)
2962             || (eeval & AR5416_OPFLAGS_11A)) {
2963                 pCap->rx_chainmask =
2964                         ath9k_hw_get_eeprom(ahp, EEP_RX_MASK);
2965         } else {
2966                 pCap->rx_chainmask =
2967                         (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
2968         }
2969
2970         if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
2971                 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
2972
2973         pCap->low_2ghz_chan = 2312;
2974         pCap->high_2ghz_chan = 2732;
2975
2976         pCap->low_5ghz_chan = 4920;
2977         pCap->high_5ghz_chan = 6100;
2978
2979         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2980         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2981         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2982
2983         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2984         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2985         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2986
2987         pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
2988
2989         if (ah->ah_config.ht_enable)
2990                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2991         else
2992                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2993
2994         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2995         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2996         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2997         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2998
2999         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3000                 pCap->total_queues =
3001                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3002         else
3003                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3004
3005         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3006                 pCap->keycache_size =
3007                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3008         else
3009                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3010
3011         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3012         pCap->num_mr_retries = 4;
3013         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3014
3015         if (AR_SREV_9280_10_OR_LATER(ah))
3016                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3017         else
3018                 pCap->num_gpio_pins = AR_NUM_GPIO;
3019
3020         if (AR_SREV_9280_10_OR_LATER(ah)) {
3021                 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3022                 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3023         } else {
3024                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3025                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3026         }
3027
3028         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3029                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3030                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3031         } else {
3032                 pCap->rts_aggr_limit = (8 * 1024);
3033         }
3034
3035         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3036
3037         ah->ah_rfsilent = ath9k_hw_get_eeprom(ahp, EEP_RF_SILENT);
3038         if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3039                 ahp->ah_gpioSelect =
3040                         MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3041                 ahp->ah_polarity =
3042                         MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3043
3044                 ath9k_hw_setcapability(ah, ATH9K_CAP_RFSILENT, 1, true,
3045                                        NULL);
3046                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3047         }
3048
3049         if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3050             (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3051             (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3052             (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3053             (ah->ah_macVersion == AR_SREV_VERSION_9280))
3054                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3055         else
3056                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3057
3058         if (AR_SREV_9280(ah))
3059                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3060         else
3061                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3062
3063         if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3064                 pCap->reg_cap =
3065                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3066                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3067                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3068                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3069         } else {
3070                 pCap->reg_cap =
3071                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3072                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3073         }
3074
3075         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3076
3077         pCap->num_antcfg_5ghz =
3078                 ath9k_hw_get_num_ant_config(ahp, IEEE80211_BAND_5GHZ);
3079         pCap->num_antcfg_2ghz =
3080                 ath9k_hw_get_num_ant_config(ahp, IEEE80211_BAND_2GHZ);
3081
3082         return true;
3083 }
3084
3085 static void ar5416DisablePciePhy(struct ath_hal *ah)
3086 {
3087         if (!AR_SREV_9100(ah))
3088                 return;
3089
3090         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3091         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3092         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
3093         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
3094         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
3095         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
3096         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3097         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3098         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
3099
3100         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3101 }
3102
3103 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
3104 {
3105         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3106         if (setChip) {
3107                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
3108                             AR_RTC_FORCE_WAKE_EN);
3109                 if (!AR_SREV_9100(ah))
3110                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
3111
3112                 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
3113                             AR_RTC_RESET_EN);
3114         }
3115 }
3116
3117 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
3118 {
3119         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3120         if (setChip) {
3121                 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3122
3123                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3124                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
3125                                   AR_RTC_FORCE_WAKE_ON_INT);
3126                 } else {
3127                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
3128                                     AR_RTC_FORCE_WAKE_EN);
3129                 }
3130         }
3131 }
3132
3133 static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
3134                                      int setChip)
3135 {
3136         u32 val;
3137         int i;
3138
3139         if (setChip) {
3140                 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
3141                     AR_RTC_STATUS_SHUTDOWN) {
3142                         if (ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)
3143                             != true) {
3144                                 return false;
3145                         }
3146                 }
3147                 if (AR_SREV_9100(ah))
3148                         REG_SET_BIT(ah, AR_RTC_RESET,
3149                                        AR_RTC_RESET_EN);
3150
3151                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
3152                             AR_RTC_FORCE_WAKE_EN);
3153                 udelay(50);
3154
3155                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
3156                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
3157                         if (val == AR_RTC_STATUS_ON)
3158                                 break;
3159                         udelay(50);
3160                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
3161                                        AR_RTC_FORCE_WAKE_EN);
3162                 }
3163                 if (i == 0) {
3164                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
3165                                  "%s: Failed to wakeup in %uus\n",
3166                                  __func__, POWER_UP_TIME / 20);
3167                         return false;
3168                 }
3169         }
3170
3171         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3172         return true;
3173 }
3174
3175 bool ath9k_hw_setpower(struct ath_hal *ah,
3176                        enum ath9k_power_mode mode)
3177 {
3178         struct ath_hal_5416 *ahp = AH5416(ah);
3179         static const char *modes[] = {
3180                 "AWAKE",
3181                 "FULL-SLEEP",
3182                 "NETWORK SLEEP",
3183                 "UNDEFINED"
3184         };
3185         int status = true, setChip = true;
3186
3187         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__,
3188                  modes[ahp->ah_powerMode], modes[mode],
3189                  setChip ? "set chip " : "");
3190
3191         switch (mode) {
3192         case ATH9K_PM_AWAKE:
3193                 status = ath9k_hw_set_power_awake(ah, setChip);
3194                 break;
3195         case ATH9K_PM_FULL_SLEEP:
3196                 ath9k_set_power_sleep(ah, setChip);
3197                 ahp->ah_chipFullSleep = true;
3198                 break;
3199         case ATH9K_PM_NETWORK_SLEEP:
3200                 ath9k_set_power_network_sleep(ah, setChip);
3201                 break;
3202         default:
3203                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
3204                          "%s: unknown power mode %u\n", __func__, mode);
3205                 return false;
3206         }
3207         ahp->ah_powerMode = mode;
3208         return status;
3209 }
3210
3211 static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3212                                           struct ath_softc *sc,
3213                                           void __iomem *mem,
3214                                           int *status)
3215 {
3216         struct ath_hal_5416 *ahp;
3217         struct ath_hal *ah;
3218         int ecode;
3219 #ifndef CONFIG_SLOW_ANT_DIV
3220         u32 i;
3221         u32 j;
3222 #endif
3223
3224         ahp = ath9k_hw_newstate(devid, sc, mem, status);
3225         if (ahp == NULL)
3226                 return NULL;
3227
3228         ah = &ahp->ah;
3229
3230         ath9k_hw_set_defaults(ah);
3231
3232         if (ah->ah_config.intr_mitigation != 0)
3233                 ahp->ah_intrMitigation = true;
3234
3235         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3236                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't reset chip\n",
3237                          __func__);
3238                 ecode = -EIO;
3239                 goto bad;
3240         }
3241
3242         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3243                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't wakeup chip\n",
3244                          __func__);
3245                 ecode = -EIO;
3246                 goto bad;
3247         }
3248
3249         if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
3250                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
3251                         ah->ah_config.serialize_regmode =
3252                                 SER_REG_MODE_ON;
3253                 } else {
3254                         ah->ah_config.serialize_regmode =
3255                                 SER_REG_MODE_OFF;
3256                 }
3257         }
3258         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3259                 "%s: serialize_regmode is %d\n",
3260                 __func__, ah->ah_config.serialize_regmode);
3261
3262         if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
3263             (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
3264             (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
3265             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) {
3266                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3267                          "%s: Mac Chip Rev 0x%02x.%x is not supported by "
3268                          "this driver\n", __func__,
3269                          ah->ah_macVersion, ah->ah_macRev);
3270                 ecode = -EOPNOTSUPP;
3271                 goto bad;
3272         }
3273
3274         if (AR_SREV_9100(ah)) {
3275                 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
3276                 ahp->ah_suppCals = IQ_MISMATCH_CAL;
3277                 ah->ah_isPciExpress = false;
3278         }
3279         ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
3280
3281         if (AR_SREV_9160_10_OR_LATER(ah)) {
3282                 if (AR_SREV_9280_10_OR_LATER(ah)) {
3283                         ahp->ah_iqCalData.calData = &iq_cal_single_sample;
3284                         ahp->ah_adcGainCalData.calData =
3285                                 &adc_gain_cal_single_sample;
3286                         ahp->ah_adcDcCalData.calData =
3287                                 &adc_dc_cal_single_sample;
3288                         ahp->ah_adcDcCalInitData.calData =
3289                                 &adc_init_dc_cal;
3290                 } else {
3291                         ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
3292                         ahp->ah_adcGainCalData.calData =
3293                                 &adc_gain_cal_multi_sample;
3294                         ahp->ah_adcDcCalData.calData =
3295                                 &adc_dc_cal_multi_sample;
3296                         ahp->ah_adcDcCalInitData.calData =
3297                                 &adc_init_dc_cal;
3298                 }
3299                 ahp->ah_suppCals =
3300                         ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
3301         }
3302
3303         if (AR_SREV_9160(ah)) {
3304                 ah->ah_config.enable_ani = 1;
3305                 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
3306                                         ATH9K_ANI_FIRSTEP_LEVEL);
3307         } else {
3308                 ahp->ah_ani_function = ATH9K_ANI_ALL;
3309                 if (AR_SREV_9280_10_OR_LATER(ah)) {
3310                         ahp->ah_ani_function &=
3311                                 ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
3312                 }
3313         }
3314
3315         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3316                  "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__,
3317                  ah->ah_macVersion, ah->ah_macRev);
3318
3319         if (AR_SREV_9280_20_OR_LATER(ah)) {
3320                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
3321                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
3322                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
3323                                ARRAY_SIZE(ar9280Common_9280_2), 2);
3324
3325                 if (ah->ah_config.pcie_clock_req) {
3326                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
3327                                        ar9280PciePhy_clkreq_off_L1_9280,
3328                                        ARRAY_SIZE
3329                                        (ar9280PciePhy_clkreq_off_L1_9280),
3330                                        2);
3331                 } else {
3332                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
3333                                        ar9280PciePhy_clkreq_always_on_L1_9280,
3334                                        ARRAY_SIZE
3335                                        (ar9280PciePhy_clkreq_always_on_L1_9280),
3336                                        2);
3337                 }
3338                 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
3339                                ar9280Modes_fast_clock_9280_2,
3340                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2),
3341                                3);
3342         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
3343                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
3344                                ARRAY_SIZE(ar9280Modes_9280), 6);
3345                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
3346                                ARRAY_SIZE(ar9280Common_9280), 2);
3347         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
3348                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
3349                                ARRAY_SIZE(ar5416Modes_9160), 6);
3350                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
3351                                ARRAY_SIZE(ar5416Common_9160), 2);
3352                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
3353                                ARRAY_SIZE(ar5416Bank0_9160), 2);
3354                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
3355                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
3356                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
3357                                ARRAY_SIZE(ar5416Bank1_9160), 2);
3358                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
3359                                ARRAY_SIZE(ar5416Bank2_9160), 2);
3360                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
3361                                ARRAY_SIZE(ar5416Bank3_9160), 3);
3362                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
3363                                ARRAY_SIZE(ar5416Bank6_9160), 3);
3364                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
3365                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
3366                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
3367                                ARRAY_SIZE(ar5416Bank7_9160), 2);
3368                 if (AR_SREV_9160_11(ah)) {
3369                         INIT_INI_ARRAY(&ahp->ah_iniAddac,
3370                                        ar5416Addac_91601_1,
3371                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
3372                 } else {
3373                         INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
3374                                        ARRAY_SIZE(ar5416Addac_9160), 2);
3375                 }
3376         } else if (AR_SREV_9100_OR_LATER(ah)) {
3377                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
3378                                ARRAY_SIZE(ar5416Modes_9100), 6);
3379                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
3380                                ARRAY_SIZE(ar5416Common_9100), 2);
3381                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
3382                                ARRAY_SIZE(ar5416Bank0_9100), 2);
3383                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
3384                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
3385                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
3386                                ARRAY_SIZE(ar5416Bank1_9100), 2);
3387                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
3388                                ARRAY_SIZE(ar5416Bank2_9100), 2);
3389                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
3390                                ARRAY_SIZE(ar5416Bank3_9100), 3);
3391                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
3392                                ARRAY_SIZE(ar5416Bank6_9100), 3);
3393                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
3394                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
3395                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
3396                                ARRAY_SIZE(ar5416Bank7_9100), 2);
3397                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
3398                                ARRAY_SIZE(ar5416Addac_9100), 2);
3399         } else {
3400                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
3401                                ARRAY_SIZE(ar5416Modes), 6);
3402                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
3403                                ARRAY_SIZE(ar5416Common), 2);
3404                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
3405                                ARRAY_SIZE(ar5416Bank0), 2);
3406                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
3407                                ARRAY_SIZE(ar5416BB_RfGain), 3);
3408                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
3409                                ARRAY_SIZE(ar5416Bank1), 2);
3410                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
3411                                ARRAY_SIZE(ar5416Bank2), 2);
3412                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
3413                                ARRAY_SIZE(ar5416Bank3), 3);
3414                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
3415                                ARRAY_SIZE(ar5416Bank6), 3);
3416                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
3417                                ARRAY_SIZE(ar5416Bank6TPC), 3);
3418                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
3419                                ARRAY_SIZE(ar5416Bank7), 2);
3420                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
3421                                ARRAY_SIZE(ar5416Addac), 2);
3422         }
3423
3424         if (ah->ah_isPciExpress)
3425                 ath9k_hw_configpcipowersave(ah, 0);
3426         else
3427                 ar5416DisablePciePhy(ah);
3428
3429         ecode = ath9k_hw_post_attach(ah);
3430         if (ecode != 0)
3431                 goto bad;
3432
3433 #ifndef CONFIG_SLOW_ANT_DIV
3434         if (ah->ah_devid == AR9280_DEVID_PCI) {
3435                 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
3436                         u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
3437
3438                         for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
3439                                 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
3440
3441                                 INI_RA(&ahp->ah_iniModes, i, j) =
3442                                         ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom,
3443                                                            reg, val);
3444                         }
3445                 }
3446         }
3447 #endif
3448
3449         if (!ath9k_hw_fill_cap_info(ah)) {
3450                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3451                          "%s:failed ath9k_hw_fill_cap_info\n", __func__);
3452                 ecode = -EINVAL;
3453                 goto bad;
3454         }
3455
3456         ecode = ath9k_hw_init_macaddr(ah);
3457         if (ecode != 0) {
3458                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3459                          "%s: failed initializing mac address\n",
3460                          __func__);
3461                 goto bad;
3462         }
3463
3464         if (AR_SREV_9285(ah))
3465                 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
3466         else
3467                 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
3468
3469 #ifndef ATH_NF_PER_CHAN
3470
3471         ath9k_init_nfcal_hist_buffer(ah);
3472 #endif
3473
3474         return ah;
3475
3476 bad:
3477         if (ahp)
3478                 ath9k_hw_detach((struct ath_hal *) ahp);
3479         if (status)
3480                 *status = ecode;
3481         return NULL;
3482 }
3483
3484 void ath9k_hw_detach(struct ath_hal *ah)
3485 {
3486         if (!AR_SREV_9100(ah))
3487                 ath9k_hw_ani_detach(ah);
3488         ath9k_hw_rfdetach(ah);
3489
3490         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3491         kfree(ah);
3492 }
3493
3494 bool ath9k_get_channel_edges(struct ath_hal *ah,
3495                              u16 flags, u16 *low,
3496                              u16 *high)
3497 {
3498         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3499
3500         if (flags & CHANNEL_5GHZ) {
3501                 *low = pCap->low_5ghz_chan;
3502                 *high = pCap->high_5ghz_chan;
3503                 return true;
3504         }
3505         if ((flags & CHANNEL_2GHZ)) {
3506                 *low = pCap->low_2ghz_chan;
3507                 *high = pCap->high_2ghz_chan;
3508
3509                 return true;
3510         }
3511         return false;
3512 }
3513
3514 static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin,
3515                                            u8 pwrMax,
3516                                            u8 *pPwrList,
3517                                            u8 *pVpdList,
3518                                            u16
3519                                            numIntercepts,
3520                                            u8 *pRetVpdList)
3521 {
3522         u16 i, k;
3523         u8 currPwr = pwrMin;
3524         u16 idxL = 0, idxR = 0;
3525
3526         for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
3527                 ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
3528                                                numIntercepts, &(idxL),
3529                                                &(idxR));
3530                 if (idxR < 1)
3531                         idxR = 1;
3532                 if (idxL == numIntercepts - 1)
3533                         idxL = (u16) (numIntercepts - 2);
3534                 if (pPwrList[idxL] == pPwrList[idxR])
3535                         k = pVpdList[idxL];
3536                 else
3537                         k = (u16) (((currPwr -
3538                                            pPwrList[idxL]) *
3539                                           pVpdList[idxR] +
3540                                           (pPwrList[idxR] -
3541                                            currPwr) * pVpdList[idxL]) /
3542                                          (pPwrList[idxR] -
3543                                           pPwrList[idxL]));
3544                 pRetVpdList[i] = (u8) k;
3545                 currPwr += 2;
3546         }
3547
3548         return true;
3549 }
3550
3551 static void
3552 ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah,
3553                                     struct ath9k_channel *chan,
3554                                     struct cal_data_per_freq *pRawDataSet,
3555                                     u8 *bChans,
3556                                     u16 availPiers,
3557                                     u16 tPdGainOverlap,
3558                                     int16_t *pMinCalPower,
3559                                     u16 *pPdGainBoundaries,
3560                                     u8 *pPDADCValues,
3561                                     u16 numXpdGains)
3562 {
3563         int i, j, k;
3564         int16_t ss;
3565         u16 idxL = 0, idxR = 0, numPiers;
3566         static u8 vpdTableL[AR5416_NUM_PD_GAINS]
3567                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3568         static u8 vpdTableR[AR5416_NUM_PD_GAINS]
3569                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3570         static u8 vpdTableI[AR5416_NUM_PD_GAINS]
3571                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3572
3573         u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
3574         u8 minPwrT4[AR5416_NUM_PD_GAINS];
3575         u8 maxPwrT4[AR5416_NUM_PD_GAINS];
3576         int16_t vpdStep;
3577         int16_t tmpVal;
3578         u16 sizeCurrVpdTable, maxIndex, tgtIndex;
3579         bool match;
3580         int16_t minDelta = 0;
3581         struct chan_centers centers;
3582
3583         ath9k_hw_get_channel_centers(ah, chan, &centers);
3584
3585         for (numPiers = 0; numPiers < availPiers; numPiers++) {
3586                 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
3587                         break;
3588         }
3589
3590         match = ath9k_hw_get_lower_upper_index((u8)
3591                                                FREQ2FBIN(centers.
3592                                                          synth_center,
3593                                                          IS_CHAN_2GHZ
3594                                                          (chan)), bChans,
3595                                                numPiers, &idxL, &idxR);
3596
3597         if (match) {
3598                 for (i = 0; i < numXpdGains; i++) {
3599                         minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
3600                         maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
3601                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3602                                                 pRawDataSet[idxL].
3603                                                 pwrPdg[i],
3604                                                 pRawDataSet[idxL].
3605                                                 vpdPdg[i],
3606                                                 AR5416_PD_GAIN_ICEPTS,
3607                                                 vpdTableI[i]);
3608                 }
3609         } else {
3610                 for (i = 0; i < numXpdGains; i++) {
3611                         pVpdL = pRawDataSet[idxL].vpdPdg[i];
3612                         pPwrL = pRawDataSet[idxL].pwrPdg[i];
3613                         pVpdR = pRawDataSet[idxR].vpdPdg[i];
3614                         pPwrR = pRawDataSet[idxR].pwrPdg[i];
3615
3616                         minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
3617
3618                         maxPwrT4[i] =
3619                                 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
3620                                     pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
3621
3622
3623                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3624                                                 pPwrL, pVpdL,
3625                                                 AR5416_PD_GAIN_ICEPTS,
3626                                                 vpdTableL[i]);
3627                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3628                                                 pPwrR, pVpdR,
3629                                                 AR5416_PD_GAIN_ICEPTS,
3630                                                 vpdTableR[i]);
3631
3632                         for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
3633                                 vpdTableI[i][j] =
3634                                         (u8) (ath9k_hw_interpolate
3635                                                     ((u16)
3636                                                      FREQ2FBIN(centers.
3637                                                                synth_center,
3638                                                                IS_CHAN_2GHZ
3639                                                                (chan)),
3640                                                      bChans[idxL],
3641                                                      bChans[idxR], vpdTableL[i]
3642                                                      [j], vpdTableR[i]
3643                                                      [j]));
3644                         }
3645                 }
3646         }
3647
3648         *pMinCalPower = (int16_t) (minPwrT4[0] / 2);
3649
3650         k = 0;
3651         for (i = 0; i < numXpdGains; i++) {
3652                 if (i == (numXpdGains - 1))
3653                         pPdGainBoundaries[i] =
3654                                 (u16) (maxPwrT4[i] / 2);
3655                 else
3656                         pPdGainBoundaries[i] =
3657                                 (u16) ((maxPwrT4[i] +
3658                                               minPwrT4[i + 1]) / 4);
3659
3660                 pPdGainBoundaries[i] =
3661                         min((u16) AR5416_MAX_RATE_POWER,
3662                             pPdGainBoundaries[i]);
3663
3664                 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) {
3665                         minDelta = pPdGainBoundaries[0] - 23;
3666                         pPdGainBoundaries[0] = 23;
3667                 } else {
3668                         minDelta = 0;
3669                 }
3670
3671                 if (i == 0) {
3672                         if (AR_SREV_9280_10_OR_LATER(ah))
3673                                 ss = (int16_t) (0 - (minPwrT4[i] / 2));
3674                         else
3675                                 ss = 0;
3676                 } else {
3677                         ss = (int16_t) ((pPdGainBoundaries[i - 1] -
3678                                          (minPwrT4[i] / 2)) -
3679                                         tPdGainOverlap + 1 + minDelta);
3680                 }
3681                 vpdStep = (int16_t) (vpdTableI[i][1] - vpdTableI[i][0]);
3682                 vpdStep = (int16_t) ((vpdStep < 1) ? 1 : vpdStep);
3683
3684                 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3685                         tmpVal = (int16_t) (vpdTableI[i][0] + ss * vpdStep);
3686                         pPDADCValues[k++] =
3687                                 (u8) ((tmpVal < 0) ? 0 : tmpVal);
3688                         ss++;
3689                 }
3690
3691                 sizeCurrVpdTable =
3692                         (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
3693                 tgtIndex = (u8) (pPdGainBoundaries[i] + tPdGainOverlap -
3694                                        (minPwrT4[i] / 2));
3695                 maxIndex = (tgtIndex <
3696                             sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
3697
3698                 while ((ss < maxIndex)
3699                        && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3700                         pPDADCValues[k++] = vpdTableI[i][ss++];
3701                 }
3702
3703                 vpdStep = (int16_t) (vpdTableI[i][sizeCurrVpdTable - 1] -
3704                                      vpdTableI[i][sizeCurrVpdTable - 2]);
3705                 vpdStep = (int16_t) ((vpdStep < 1) ? 1 : vpdStep);
3706
3707                 if (tgtIndex > maxIndex) {
3708                         while ((ss <= tgtIndex)
3709                                && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3710                                 tmpVal = (int16_t) ((vpdTableI[i]
3711                                                      [sizeCurrVpdTable -
3712                                                       1] + (ss - maxIndex +
3713                                                             1) * vpdStep));
3714                                 pPDADCValues[k++] = (u8) ((tmpVal >
3715                                                  255) ? 255 : tmpVal);
3716                                 ss++;
3717                         }
3718                 }
3719         }
3720
3721         while (i < AR5416_PD_GAINS_IN_MASK) {
3722                 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
3723                 i++;
3724         }
3725
3726         while (k < AR5416_NUM_PDADC_VALUES) {
3727                 pPDADCValues[k] = pPDADCValues[k - 1];
3728                 k++;
3729         }
3730         return;
3731 }
3732
3733 static bool
3734 ath9k_hw_set_power_cal_table(struct ath_hal *ah,
3735                              struct ar5416_eeprom *pEepData,
3736                              struct ath9k_channel *chan,
3737                              int16_t *pTxPowerIndexOffset)
3738 {
3739         struct cal_data_per_freq *pRawDataset;
3740         u8 *pCalBChans = NULL;
3741         u16 pdGainOverlap_t2;
3742         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
3743         u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
3744         u16 numPiers, i, j;
3745         int16_t tMinCalPower;
3746         u16 numXpdGain, xpdMask;
3747         u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
3748         u32 reg32, regOffset, regChainOffset;
3749         int16_t modalIdx;
3750         struct ath_hal_5416 *ahp = AH5416(ah);
3751
3752         modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
3753         xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
3754
3755         if ((pEepData->baseEepHeader.
3756              version & AR5416_EEP_VER_MINOR_MASK) >=
3757             AR5416_EEP_MINOR_VER_2) {
3758                 pdGainOverlap_t2 =
3759                         pEepData->modalHeader[modalIdx].pdGainOverlap;
3760         } else {
3761                 pdGainOverlap_t2 =
3762                         (u16) (MS
3763                                      (REG_READ(ah, AR_PHY_TPCRG5),
3764                                       AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
3765         }
3766
3767         if (IS_CHAN_2GHZ(chan)) {
3768                 pCalBChans = pEepData->calFreqPier2G;
3769                 numPiers = AR5416_NUM_2G_CAL_PIERS;
3770         } else {
3771                 pCalBChans = pEepData->calFreqPier5G;
3772                 numPiers = AR5416_NUM_5G_CAL_PIERS;
3773         }
3774
3775         numXpdGain = 0;
3776
3777         for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
3778                 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
3779                         if (numXpdGain >= AR5416_NUM_PD_GAINS)
3780                                 break;
3781                         xpdGainValues[numXpdGain] =
3782                                 (u16) (AR5416_PD_GAINS_IN_MASK - i);
3783                         numXpdGain++;
3784                 }
3785         }
3786
3787         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
3788                       (numXpdGain - 1) & 0x3);
3789         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
3790                       xpdGainValues[0]);
3791         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
3792                       xpdGainValues[1]);
3793         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
3794                       xpdGainValues[2]);
3795
3796         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3797                 if (AR_SREV_5416_V20_OR_LATER(ah) &&
3798                     (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5)
3799                     && (i != 0)) {
3800                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
3801                 } else
3802                         regChainOffset = i * 0x1000;
3803                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
3804                         if (IS_CHAN_2GHZ(chan))
3805                                 pRawDataset = pEepData->calPierData2G[i];
3806                         else
3807                                 pRawDataset = pEepData->calPierData5G[i];
3808
3809                         ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
3810                                                             pRawDataset,
3811                                                             pCalBChans,
3812                                                             numPiers,
3813                                                             pdGainOverlap_t2,
3814                                                             &tMinCalPower,
3815                                                             gainBoundaries,
3816                                                             pdadcValues,
3817                                                             numXpdGain);
3818
3819                         if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
3820
3821                                 REG_WRITE(ah,
3822                                           AR_PHY_TPCRG5 + regChainOffset,
3823                                           SM(pdGainOverlap_t2,
3824                                              AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
3825                                           | SM(gainBoundaries[0],
3826                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
3827                                           | SM(gainBoundaries[1],
3828                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
3829                                           | SM(gainBoundaries[2],
3830                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
3831                                           | SM(gainBoundaries[3],
3832                                        AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
3833                         }
3834
3835                         regOffset =
3836                                 AR_PHY_BASE + (672 << 2) + regChainOffset;
3837                         for (j = 0; j < 32; j++) {
3838                                 reg32 =
3839                                         ((pdadcValues[4 * j + 0] & 0xFF) << 0)
3840                                         | ((pdadcValues[4 * j + 1] & 0xFF) <<
3841                                            8) | ((pdadcValues[4 * j + 2] &
3842                                                   0xFF) << 16) |
3843                                         ((pdadcValues[4 * j + 3] & 0xFF) <<
3844                                          24);
3845                                 REG_WRITE(ah, regOffset, reg32);
3846
3847                                 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
3848                                          "PDADC (%d,%4x): %4.4x %8.8x\n",
3849                                          i, regChainOffset, regOffset,
3850                                          reg32);
3851                                 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
3852                                 "PDADC: Chain %d | PDADC %3d Value %3d | "
3853                                 "PDADC %3d Value %3d | PDADC %3d Value %3d | "
3854                                 "PDADC %3d Value %3d |\n",
3855                                          i, 4 * j, pdadcValues[4 * j],
3856                                          4 * j + 1, pdadcValues[4 * j + 1],
3857                                          4 * j + 2, pdadcValues[4 * j + 2],
3858                                          4 * j + 3,
3859                                          pdadcValues[4 * j + 3]);
3860
3861                                 regOffset += 4;
3862                         }
3863                 }
3864         }
3865         *pTxPowerIndexOffset = 0;
3866
3867         return true;
3868 }
3869
3870 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
3871 {
3872         struct ath_hal_5416 *ahp = AH5416(ah);
3873         u8 i;
3874
3875         if (ah->ah_isPciExpress != true)
3876                 return;
3877
3878         if (ah->ah_config.pcie_powersave_enable == 2)
3879                 return;
3880
3881         if (restore)
3882                 return;
3883
3884         if (AR_SREV_9280_20_OR_LATER(ah)) {
3885                 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
3886                         REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
3887                                   INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
3888                 }
3889                 udelay(1000);
3890         } else if (AR_SREV_9280(ah)
3891                    && (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
3892                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
3893                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3894
3895                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
3896                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
3897                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
3898
3899                 if (ah->ah_config.pcie_clock_req)
3900                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3901                 else
3902                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
3903
3904                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3905                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3906                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
3907
3908                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3909
3910                 udelay(1000);
3911         } else {
3912                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3913                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3914                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3915                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3916                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
3917                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
3918                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3919                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3920                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3921                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3922         }
3923
3924         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3925
3926         if (ah->ah_config.pcie_waen) {
3927                 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
3928         } else {
3929                 if (AR_SREV_9280(ah))
3930                         REG_WRITE(ah, AR_WA, 0x0040073f);
3931                 else
3932                         REG_WRITE(ah, AR_WA, 0x0000073f);
3933         }
3934 }
3935
3936 static void
3937 ath9k_hw_get_legacy_target_powers(struct ath_hal *ah,
3938                                   struct ath9k_channel *chan,
3939                                   struct cal_target_power_leg *powInfo,
3940                                   u16 numChannels,
3941                                   struct cal_target_power_leg *pNewPower,
3942                                   u16 numRates,
3943                                   bool isExtTarget)
3944 {
3945         u16 clo, chi;
3946         int i;
3947         int matchIndex = -1, lowIndex = -1;
3948         u16 freq;
3949         struct chan_centers centers;
3950
3951         ath9k_hw_get_channel_centers(ah, chan, &centers);
3952         freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
3953
3954         if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
3955                 IS_CHAN_2GHZ(chan))) {
3956                 matchIndex = 0;
3957         } else {
3958                 for (i = 0; (i < numChannels)
3959                      && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
3960                         if (freq ==
3961                             ath9k_hw_fbin2freq(powInfo[i].bChannel,
3962                                                IS_CHAN_2GHZ(chan))) {
3963                                 matchIndex = i;
3964                                 break;
3965                         } else if ((freq <
3966                                     ath9k_hw_fbin2freq(powInfo[i].bChannel,
3967                                                        IS_CHAN_2GHZ(chan)))
3968                                    && (freq >
3969                                        ath9k_hw_fbin2freq(powInfo[i - 1].
3970                                                           bChannel,
3971                                                           IS_CHAN_2GHZ
3972                                                           (chan)))) {
3973                                 lowIndex = i - 1;
3974                                 break;
3975                         }
3976                 }
3977                 if ((matchIndex == -1) && (lowIndex == -1))
3978                         matchIndex = i - 1;
3979         }
3980
3981         if (matchIndex != -1) {
3982                 *pNewPower = powInfo[matchIndex];
3983         } else {
3984                 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
3985                                          IS_CHAN_2GHZ(chan));
3986                 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
3987                                          IS_CHAN_2GHZ(chan));
3988
3989                 for (i = 0; i < numRates; i++) {
3990                         pNewPower->tPow2x[i] =
3991                                 (u8) ath9k_hw_interpolate(freq, clo, chi,
3992                                                                 powInfo
3993                                                                 [lowIndex].
3994                                                                 tPow2x[i],
3995                                                                 powInfo
3996                                                                 [lowIndex +
3997                                                                  1].tPow2x[i]);
3998                 }
3999         }
4000 }
4001
4002 static void
4003 ath9k_hw_get_target_powers(struct ath_hal *ah,
4004                            struct ath9k_channel *chan,
4005                            struct cal_target_power_ht *powInfo,
4006                            u16 numChannels,
4007                            struct cal_target_power_ht *pNewPower,
4008                            u16 numRates,
4009                            bool isHt40Target)
4010 {
4011         u16 clo, chi;
4012         int i;
4013         int matchIndex = -1, lowIndex = -1;
4014         u16 freq;
4015         struct chan_centers centers;
4016
4017         ath9k_hw_get_channel_centers(ah, chan, &centers);
4018         freq = isHt40Target ? centers.synth_center : centers.ctl_center;
4019
4020         if (freq <=
4021                 ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
4022                 matchIndex = 0;
4023         } else {
4024                 for (i = 0; (i < numChannels)
4025                      && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
4026                         if (freq ==
4027                             ath9k_hw_fbin2freq(powInfo[i].bChannel,
4028                                                IS_CHAN_2GHZ(chan))) {
4029                                 matchIndex = i;
4030                                 break;
4031                         } else
4032                                 if ((freq <
4033                                      ath9k_hw_fbin2freq(powInfo[i].bChannel,
4034                                                         IS_CHAN_2GHZ(chan)))
4035                                     && (freq >
4036                                         ath9k_hw_fbin2freq(powInfo[i - 1].
4037                                                            bChannel,
4038                                                            IS_CHAN_2GHZ
4039                                                            (chan)))) {
4040                                         lowIndex = i - 1;
4041                                         break;
4042                                 }
4043                 }
4044                 if ((matchIndex == -1) && (lowIndex == -1))
4045                         matchIndex = i - 1;
4046         }
4047
4048         if (matchIndex != -1) {
4049                 *pNewPower = powInfo[matchIndex];
4050         } else {
4051                 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
4052                                          IS_CHAN_2GHZ(chan));
4053                 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
4054                                          IS_CHAN_2GHZ(chan));
4055
4056                 for (i = 0; i < numRates; i++) {
4057                         pNewPower->tPow2x[i] =
4058                                 (u8) ath9k_hw_interpolate(freq, clo, chi,
4059                                                                 powInfo
4060                                                                 [lowIndex].
4061                                                                 tPow2x[i],
4062                                                                 powInfo
4063                                                                 [lowIndex +
4064                                                                  1].tPow2x[i]);
4065                 }
4066         }
4067 }
4068
4069 static u16
4070 ath9k_hw_get_max_edge_power(u16 freq,
4071                             struct cal_ctl_edges *pRdEdgesPower,
4072                             bool is2GHz)
4073 {
4074         u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4075         int i;
4076
4077         for (i = 0; (i < AR5416_NUM_BAND_EDGES)
4078              && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
4079                 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
4080                                                is2GHz)) {
4081                         twiceMaxEdgePower = pRdEdgesPower[i].tPower;
4082                         break;
4083                 } else if ((i > 0)
4084                            && (freq <
4085                                ath9k_hw_fbin2freq(pRdEdgesPower[i].
4086                                                   bChannel, is2GHz))) {
4087                         if (ath9k_hw_fbin2freq
4088                             (pRdEdgesPower[i - 1].bChannel, is2GHz) < freq
4089                             && pRdEdgesPower[i - 1].flag) {
4090                                 twiceMaxEdgePower =
4091                                         pRdEdgesPower[i - 1].tPower;
4092                         }
4093                         break;
4094                 }
4095         }
4096         return twiceMaxEdgePower;
4097 }
4098
4099 static bool
4100 ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
4101                                   struct ar5416_eeprom *pEepData,
4102                                   struct ath9k_channel *chan,
4103                                   int16_t *ratesArray,
4104                                   u16 cfgCtl,
4105                                   u8 AntennaReduction,
4106                                   u8 twiceMaxRegulatoryPower,
4107                                   u8 powerLimit)
4108 {
4109         u8 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4110         static const u16 tpScaleReductionTable[5] =
4111                 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
4112
4113         int i;
4114         int8_t twiceLargestAntenna;
4115         struct cal_ctl_data *rep;
4116         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
4117                 0, { 0, 0, 0, 0}
4118         };
4119         struct cal_target_power_leg targetPowerOfdmExt = {
4120                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
4121                 0, { 0, 0, 0, 0 }
4122         };
4123         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
4124                 0, {0, 0, 0, 0}
4125         };
4126         u8 scaledPower = 0, minCtlPower, maxRegAllowedPower;
4127         u16 ctlModesFor11a[] =
4128                 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
4129         u16 ctlModesFor11g[] =
4130                 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
4131                   CTL_2GHT40
4132                 };
4133         u16 numCtlModes, *pCtlMode, ctlMode, freq;
4134         struct chan_centers centers;
4135         int tx_chainmask;
4136         u8 twiceMinEdgePower;
4137         struct ath_hal_5416 *ahp = AH5416(ah);
4138
4139         tx_chainmask = ahp->ah_txchainmask;
4140
4141         ath9k_hw_get_channel_centers(ah, chan, &centers);
4142
4143         twiceLargestAntenna = max(
4144                 pEepData->modalHeader
4145                         [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
4146                 pEepData->modalHeader
4147                         [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
4148
4149         twiceLargestAntenna = max((u8) twiceLargestAntenna,
4150                 pEepData->modalHeader
4151                         [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
4152
4153         twiceLargestAntenna =
4154                 (int8_t) min(AntennaReduction - twiceLargestAntenna, 0);
4155
4156         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4157
4158         if (ah->ah_tpScale != ATH9K_TP_SCALE_MAX) {
4159                 maxRegAllowedPower -=
4160                         (tpScaleReductionTable[(ah->ah_tpScale)] * 2);
4161         }
4162
4163         scaledPower = min(powerLimit, maxRegAllowedPower);
4164
4165         switch (ar5416_get_ntxchains(tx_chainmask)) {
4166         case 1:
4167                 break;
4168         case 2:
4169                 scaledPower -=
4170                         pEepData->modalHeader[IS_CHAN_2GHZ(chan)].
4171                         pwrDecreaseFor2Chain;
4172                 break;
4173         case 3:
4174                 scaledPower -=
4175                         pEepData->modalHeader[IS_CHAN_2GHZ(chan)].
4176                         pwrDecreaseFor3Chain;
4177                 break;
4178         }
4179
4180         scaledPower = max(0, (int32_t) scaledPower);
4181
4182         if (IS_CHAN_2GHZ(chan)) {
4183                 numCtlModes =
4184                         ARRAY_SIZE(ctlModesFor11g) -
4185                         SUB_NUM_CTL_MODES_AT_2G_40;
4186                 pCtlMode = ctlModesFor11g;
4187
4188                 ath9k_hw_get_legacy_target_powers(ah, chan,
4189                         pEepData->
4190                         calTargetPowerCck,
4191                         AR5416_NUM_2G_CCK_TARGET_POWERS,
4192                         &targetPowerCck, 4,
4193                         false);
4194                 ath9k_hw_get_legacy_target_powers(ah, chan,
4195                         pEepData->
4196                         calTargetPower2G,
4197                         AR5416_NUM_2G_20_TARGET_POWERS,
4198                         &targetPowerOfdm, 4,
4199                         false);
4200                 ath9k_hw_get_target_powers(ah, chan,
4201                         pEepData->calTargetPower2GHT20,
4202                         AR5416_NUM_2G_20_TARGET_POWERS,
4203                         &targetPowerHt20, 8, false);
4204
4205                 if (IS_CHAN_HT40(chan)) {
4206                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4207                         ath9k_hw_get_target_powers(ah, chan,
4208                                 pEepData->
4209                                 calTargetPower2GHT40,
4210                                 AR5416_NUM_2G_40_TARGET_POWERS,
4211                                 &targetPowerHt40, 8,
4212                                 true);
4213                         ath9k_hw_get_legacy_target_powers(ah, chan,
4214                                 pEepData->
4215                                 calTargetPowerCck,
4216                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
4217                                 &targetPowerCckExt,
4218                                 4, true);
4219                         ath9k_hw_get_legacy_target_powers(ah, chan,
4220                                 pEepData->
4221                                 calTargetPower2G,
4222                                 AR5416_NUM_2G_20_TARGET_POWERS,
4223                                 &targetPowerOfdmExt,
4224                                 4, true);
4225                 }
4226         } else {
4227
4228                 numCtlModes =
4229                         ARRAY_SIZE(ctlModesFor11a) -
4230                         SUB_NUM_CTL_MODES_AT_5G_40;
4231                 pCtlMode = ctlModesFor11a;
4232
4233                 ath9k_hw_get_legacy_target_powers(ah, chan,
4234                         pEepData->
4235                         calTargetPower5G,
4236                         AR5416_NUM_5G_20_TARGET_POWERS,
4237                         &targetPowerOfdm, 4,
4238                         false);
4239                 ath9k_hw_get_target_powers(ah, chan,
4240                         pEepData->calTargetPower5GHT20,
4241                         AR5416_NUM_5G_20_TARGET_POWERS,
4242                         &targetPowerHt20, 8, false);
4243
4244                 if (IS_CHAN_HT40(chan)) {
4245                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4246                         ath9k_hw_get_target_powers(ah, chan,
4247                                 pEepData->
4248                                 calTargetPower5GHT40,
4249                                 AR5416_NUM_5G_40_TARGET_POWERS,
4250                                 &targetPowerHt40, 8,
4251                                 true);
4252                         ath9k_hw_get_legacy_target_powers(ah, chan,
4253                                 pEepData->
4254                                 calTargetPower5G,
4255                                 AR5416_NUM_5G_20_TARGET_POWERS,
4256                                 &targetPowerOfdmExt,
4257                                 4, true);
4258                 }
4259         }
4260
4261         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4262                 bool isHt40CtlMode =
4263                         (pCtlMode[ctlMode] == CTL_5GHT40)
4264                         || (pCtlMode[ctlMode] == CTL_2GHT40);
4265                 if (isHt40CtlMode)
4266                         freq = centers.synth_center;
4267                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4268                         freq = centers.ext_center;
4269                 else
4270                         freq = centers.ctl_center;
4271
4272                 if (ar5416_get_eep_ver(ahp) == 14
4273                     && ar5416_get_eep_rev(ahp) <= 2)
4274                         twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4275
4276                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4277                         "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
4278                         "EXT_ADDITIVE %d\n",
4279                          ctlMode, numCtlModes, isHt40CtlMode,
4280                          (pCtlMode[ctlMode] & EXT_ADDITIVE));
4281
4282                 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i];
4283                      i++) {
4284                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4285                                 "  LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
4286                                 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
4287                                 "chan %d\n",
4288                                 i, cfgCtl, pCtlMode[ctlMode],
4289                                 pEepData->ctlIndex[i], chan->channel);
4290
4291                         if ((((cfgCtl & ~CTL_MODE_M) |
4292                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4293                              pEepData->ctlIndex[i])
4294                             ||
4295                             (((cfgCtl & ~CTL_MODE_M) |
4296                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4297                              ((pEepData->
4298                                ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
4299                                 rep = &(pEepData->ctlData[i]);
4300
4301                                 twiceMinEdgePower =
4302                                         ath9k_hw_get_max_edge_power(freq,
4303                                                 rep->
4304                                                 ctlEdges
4305                                                 [ar5416_get_ntxchains
4306                                                 (tx_chainmask)
4307                                                 - 1],
4308                                                 IS_CHAN_2GHZ
4309                                                 (chan));
4310
4311                                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4312                                         "    MATCH-EE_IDX %d: ch %d is2 %d "
4313                                         "2xMinEdge %d chainmask %d chains %d\n",
4314                                          i, freq, IS_CHAN_2GHZ(chan),
4315                                          twiceMinEdgePower, tx_chainmask,
4316                                          ar5416_get_ntxchains
4317                                          (tx_chainmask));
4318                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
4319                                         twiceMaxEdgePower =
4320                                                 min(twiceMaxEdgePower,
4321                                                     twiceMinEdgePower);
4322                                 } else {
4323                                         twiceMaxEdgePower =
4324                                                 twiceMinEdgePower;
4325                                         break;
4326                                 }
4327                         }
4328                 }
4329
4330                 minCtlPower = min(twiceMaxEdgePower, scaledPower);
4331
4332                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4333                                 "    SEL-Min ctlMode %d pCtlMode %d "
4334                                 "2xMaxEdge %d sP %d minCtlPwr %d\n",
4335                          ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4336                          scaledPower, minCtlPower);
4337
4338                 switch (pCtlMode[ctlMode]) {
4339                 case CTL_11B:
4340                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x);
4341                              i++) {
4342                                 targetPowerCck.tPow2x[i] =
4343                                         min(targetPowerCck.tPow2x[i],
4344                                             minCtlPower);
4345                         }
4346                         break;
4347                 case CTL_11A:
4348                 case CTL_11G:
4349                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x);
4350                              i++) {
4351                                 targetPowerOfdm.tPow2x[i] =
4352                                         min(targetPowerOfdm.tPow2x[i],
4353                                             minCtlPower);
4354                         }
4355                         break;
4356                 case CTL_5GHT20:
4357                 case CTL_2GHT20:
4358                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x);
4359                              i++) {
4360                                 targetPowerHt20.tPow2x[i] =
4361                                         min(targetPowerHt20.tPow2x[i],
4362                                             minCtlPower);
4363                         }
4364                         break;
4365                 case CTL_11B_EXT:
4366                         targetPowerCckExt.tPow2x[0] =
4367                                 min(targetPowerCckExt.tPow2x[0], minCtlPower);
4368                         break;
4369                 case CTL_11A_EXT:
4370                 case CTL_11G_EXT:
4371                         targetPowerOfdmExt.tPow2x[0] =
4372                                 min(targetPowerOfdmExt.tPow2x[0], minCtlPower);
4373                         break;
4374                 case CTL_5GHT40:
4375                 case CTL_2GHT40:
4376                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x);
4377                              i++) {
4378                                 targetPowerHt40.tPow2x[i] =
4379                                         min(targetPowerHt40.tPow2x[i],
4380                                             minCtlPower);
4381                         }
4382                         break;
4383                 default:
4384                         break;
4385                 }
4386         }
4387
4388         ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
4389                 ratesArray[rate18mb] = ratesArray[rate24mb] =
4390                 targetPowerOfdm.tPow2x[0];
4391         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
4392         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
4393         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
4394         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
4395
4396         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
4397                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
4398
4399         if (IS_CHAN_2GHZ(chan)) {
4400                 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
4401                 ratesArray[rate2s] = ratesArray[rate2l] =
4402                         targetPowerCck.tPow2x[1];
4403                 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
4404                         targetPowerCck.tPow2x[2];
4405                 ;
4406                 ratesArray[rate11s] = ratesArray[rate11l] =
4407                         targetPowerCck.tPow2x[3];
4408                 ;
4409         }
4410         if (IS_CHAN_HT40(chan)) {
4411                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
4412                         ratesArray[rateHt40_0 + i] =
4413                                 targetPowerHt40.tPow2x[i];
4414                 }
4415                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
4416                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
4417                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
4418                 if (IS_CHAN_2GHZ(chan)) {
4419                         ratesArray[rateExtCck] =
4420                                 targetPowerCckExt.tPow2x[0];
4421                 }
4422         }
4423         return true;
4424 }
4425
4426 static int
4427 ath9k_hw_set_txpower(struct ath_hal *ah,
4428                      struct ar5416_eeprom *pEepData,
4429                      struct ath9k_channel *chan,
4430                      u16 cfgCtl,
4431                      u8 twiceAntennaReduction,
4432                      u8 twiceMaxRegulatoryPower,
4433                      u8 powerLimit)
4434 {
4435         struct modal_eep_header *pModal =
4436                 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
4437         int16_t ratesArray[Ar5416RateSize];
4438         int16_t txPowerIndexOffset = 0;
4439         u8 ht40PowerIncForPdadc = 2;
4440         int i;
4441
4442         memset(ratesArray, 0, sizeof(ratesArray));
4443
4444         if ((pEepData->baseEepHeader.
4445              version & AR5416_EEP_VER_MINOR_MASK) >=
4446             AR5416_EEP_MINOR_VER_2) {
4447                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
4448         }
4449
4450         if (!ath9k_hw_set_power_per_rate_table(ah, pEepData, chan,
4451                                                &ratesArray[0], cfgCtl,
4452                                                twiceAntennaReduction,
4453                                                twiceMaxRegulatoryPower,
4454                                                powerLimit)) {
4455                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
4456                         "ath9k_hw_set_txpower: unable to set "
4457                         "tx power per rate table\n");
4458                 return -EIO;
4459         }
4460
4461         if (!ath9k_hw_set_power_cal_table
4462             (ah, pEepData, chan, &txPowerIndexOffset)) {
4463                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
4464                          "ath9k_hw_set_txpower: unable to set power table\n");
4465                 return -EIO;
4466         }
4467
4468         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
4469                 ratesArray[i] =
4470                         (int16_t) (txPowerIndexOffset + ratesArray[i]);
4471                 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
4472                         ratesArray[i] = AR5416_MAX_RATE_POWER;
4473         }
4474
4475         if (AR_SREV_9280_10_OR_LATER(ah)) {
4476                 for (i = 0; i < Ar5416RateSize; i++)
4477                         ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
4478         }
4479
4480         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
4481                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
4482                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
4483                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
4484                   | ATH9K_POW_SM(ratesArray[rate6mb], 0)
4485                 );
4486         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
4487                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
4488                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
4489                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
4490                   | ATH9K_POW_SM(ratesArray[rate24mb], 0)
4491                 );
4492
4493         if (IS_CHAN_2GHZ(chan)) {
4494                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
4495                           ATH9K_POW_SM(ratesArray[rate2s], 24)
4496                           | ATH9K_POW_SM(ratesArray[rate2l], 16)
4497                           | ATH9K_POW_SM(ratesArray[rateXr], 8)
4498                           | ATH9K_POW_SM(ratesArray[rate1l], 0)
4499                         );
4500                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
4501                           ATH9K_POW_SM(ratesArray[rate11s], 24)
4502                           | ATH9K_POW_SM(ratesArray[rate11l], 16)
4503                           | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
4504                           | ATH9K_POW_SM(ratesArray[rate5_5l], 0)
4505                         );
4506         }
4507
4508         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
4509                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
4510                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
4511                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
4512                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)
4513                 );
4514         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
4515                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
4516                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
4517                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
4518                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)
4519                 );
4520
4521         if (IS_CHAN_HT40(chan)) {
4522                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
4523                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
4524                                        ht40PowerIncForPdadc, 24)
4525                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
4526                                          ht40PowerIncForPdadc, 16)
4527                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
4528                                          ht40PowerIncForPdadc, 8)
4529                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
4530                                          ht40PowerIncForPdadc, 0)
4531                         );
4532                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
4533                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
4534                                        ht40PowerIncForPdadc, 24)
4535                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
4536                                          ht40PowerIncForPdadc, 16)
4537                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
4538                                          ht40PowerIncForPdadc, 8)
4539                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
4540                                          ht40PowerIncForPdadc, 0)
4541                         );
4542
4543                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
4544                           ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
4545                           | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
4546                           | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
4547                           | ATH9K_POW_SM(ratesArray[rateDupCck], 0)
4548                         );
4549         }
4550
4551         REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
4552                   ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
4553                   | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0)
4554                 );
4555
4556         i = rate6mb;
4557         if (IS_CHAN_HT40(chan))
4558                 i = rateHt40_0;
4559         else if (IS_CHAN_HT20(chan))
4560                 i = rateHt20_0;
4561
4562         if (AR_SREV_9280_10_OR_LATER(ah))
4563                 ah->ah_maxPowerLevel =
4564                         ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
4565         else
4566                 ah->ah_maxPowerLevel = ratesArray[i];
4567
4568         return 0;
4569 }
4570
4571 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
4572                                                  u32 coef_scaled,
4573                                                  u32 *coef_mantissa,
4574                                                  u32 *coef_exponent)
4575 {
4576         u32 coef_exp, coef_man;
4577
4578         for (coef_exp = 31; coef_exp > 0; coef_exp--)
4579                 if ((coef_scaled >> coef_exp) & 0x1)
4580                         break;
4581
4582         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
4583
4584         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
4585
4586         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
4587         *coef_exponent = coef_exp - 16;
4588 }
4589
4590 static void
4591 ath9k_hw_set_delta_slope(struct ath_hal *ah,
4592                          struct ath9k_channel *chan)
4593 {
4594         u32 coef_scaled, ds_coef_exp, ds_coef_man;
4595         u32 clockMhzScaled = 0x64000000;
4596         struct chan_centers centers;
4597
4598         if (IS_CHAN_HALF_RATE(chan))
4599                 clockMhzScaled = clockMhzScaled >> 1;
4600         else if (IS_CHAN_QUARTER_RATE(chan))
4601                 clockMhzScaled = clockMhzScaled >> 2;
4602
4603         ath9k_hw_get_channel_centers(ah, chan, &centers);
4604         coef_scaled = clockMhzScaled / centers.synth_center;
4605
4606         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
4607                                       &ds_coef_exp);
4608
4609         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
4610                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
4611         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
4612                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
4613
4614         coef_scaled = (9 * coef_scaled) / 10;
4615
4616         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
4617                                       &ds_coef_exp);
4618
4619         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
4620                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
4621         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
4622                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
4623 }
4624
4625 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
4626                                         struct ath9k_channel *chan)
4627 {
4628         int bb_spur = AR_NO_SPUR;
4629         int freq;
4630         int bin, cur_bin;
4631         int bb_spur_off, spur_subchannel_sd;
4632         int spur_freq_sd;
4633         int spur_delta_phase;
4634         int denominator;
4635         int upper, lower, cur_vit_mask;
4636         int tmp, newVal;
4637         int i;
4638         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
4639                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
4640         };
4641         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
4642                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
4643         };
4644         int inc[4] = { 0, 100, 0, 0 };
4645         struct chan_centers centers;
4646
4647         int8_t mask_m[123];
4648         int8_t mask_p[123];
4649         int8_t mask_amt;
4650         int tmp_mask;
4651         int cur_bb_spur;
4652         bool is2GHz = IS_CHAN_2GHZ(chan);
4653
4654         memset(&mask_m, 0, sizeof(int8_t) * 123);
4655         memset(&mask_p, 0, sizeof(int8_t) * 123);
4656
4657         ath9k_hw_get_channel_centers(ah, chan, &centers);
4658         freq = centers.synth_center;
4659
4660         ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
4661         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
4662                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
4663
4664                 if (is2GHz)
4665                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
4666                 else
4667                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
4668
4669                 if (AR_NO_SPUR == cur_bb_spur)
4670                         break;
4671                 cur_bb_spur = cur_bb_spur - freq;
4672
4673                 if (IS_CHAN_HT40(chan)) {
4674                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
4675                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
4676                                 bb_spur = cur_bb_spur;
4677                                 break;
4678                         }
4679                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
4680                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
4681                         bb_spur = cur_bb_spur;
4682                         break;
4683                 }
4684         }
4685
4686         if (AR_NO_SPUR == bb_spur) {
4687                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
4688                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
4689                 return;
4690         } else {
4691                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
4692                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
4693         }
4694
4695         bin = bb_spur * 320;
4696
4697         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
4698
4699         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
4700                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
4701                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
4702                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
4703         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
4704
4705         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
4706                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
4707                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
4708                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
4709                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
4710         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
4711
4712         if (IS_CHAN_HT40(chan)) {
4713                 if (bb_spur < 0) {
4714                         spur_subchannel_sd = 1;
4715                         bb_spur_off = bb_spur + 10;
4716                 } else {
4717                         spur_subchannel_sd = 0;
4718                         bb_spur_off = bb_spur - 10;
4719                 }
4720         } else {
4721                 spur_subchannel_sd = 0;
4722                 bb_spur_off = bb_spur;
4723         }
4724
4725         if (IS_CHAN_HT40(chan))
4726                 spur_delta_phase =
4727                         ((bb_spur * 262144) /
4728                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
4729         else
4730                 spur_delta_phase =
4731                         ((bb_spur * 524288) /
4732                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
4733
4734         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
4735         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
4736
4737         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
4738                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
4739                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
4740         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
4741
4742         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
4743         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
4744
4745         cur_bin = -6000;
4746         upper = bin + 100;
4747         lower = bin - 100;
4748
4749         for (i = 0; i < 4; i++) {
4750                 int pilot_mask = 0;
4751                 int chan_mask = 0;
4752                 int bp = 0;
4753                 for (bp = 0; bp < 30; bp++) {
4754                         if ((cur_bin > lower) && (cur_bin < upper)) {
4755                                 pilot_mask = pilot_mask | 0x1 << bp;
4756                                 chan_mask = chan_mask | 0x1 << bp;
4757                         }
4758                         cur_bin += 100;
4759                 }
4760                 cur_bin += inc[i];
4761                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
4762                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
4763         }
4764
4765         cur_vit_mask = 6100;
4766         upper = bin + 120;
4767         lower = bin - 120;
4768
4769         for (i = 0; i < 123; i++) {
4770                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
4771
4772                         /* workaround for gcc bug #37014 */
4773                         volatile int tmp = abs(cur_vit_mask - bin);
4774
4775                         if (tmp < 75)
4776                                 mask_amt = 1;
4777                         else
4778                                 mask_amt = 0;
4779                         if (cur_vit_mask < 0)
4780                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
4781                         else
4782                                 mask_p[cur_vit_mask / 100] = mask_amt;
4783                 }
4784                 cur_vit_mask -= 100;
4785         }
4786
4787         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
4788                 | (mask_m[48] << 26) | (mask_m[49] << 24)
4789                 | (mask_m[50] << 22) | (mask_m[51] << 20)
4790                 | (mask_m[52] << 18) | (mask_m[53] << 16)
4791                 | (mask_m[54] << 14) | (mask_m[55] << 12)
4792                 | (mask_m[56] << 10) | (mask_m[57] << 8)
4793                 | (mask_m[58] << 6) | (mask_m[59] << 4)
4794                 | (mask_m[60] << 2) | (mask_m[61] << 0);
4795         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
4796         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
4797
4798         tmp_mask = (mask_m[31] << 28)
4799                 | (mask_m[32] << 26) | (mask_m[33] << 24)
4800                 | (mask_m[34] << 22) | (mask_m[35] << 20)
4801                 | (mask_m[36] << 18) | (mask_m[37] << 16)
4802                 | (mask_m[48] << 14) | (mask_m[39] << 12)
4803                 | (mask_m[40] << 10) | (mask_m[41] << 8)
4804                 | (mask_m[42] << 6) | (mask_m[43] << 4)
4805                 | (mask_m[44] << 2) | (mask_m[45] << 0);
4806         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
4807         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
4808
4809         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
4810                 | (mask_m[18] << 26) | (mask_m[18] << 24)
4811                 | (mask_m[20] << 22) | (mask_m[20] << 20)
4812                 | (mask_m[22] << 18) | (mask_m[22] << 16)
4813                 | (mask_m[24] << 14) | (mask_m[24] << 12)
4814                 | (mask_m[25] << 10) | (mask_m[26] << 8)
4815                 | (mask_m[27] << 6) | (mask_m[28] << 4)
4816                 | (mask_m[29] << 2) | (mask_m[30] << 0);
4817         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
4818         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
4819
4820         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
4821                 | (mask_m[2] << 26) | (mask_m[3] << 24)
4822                 | (mask_m[4] << 22) | (mask_m[5] << 20)
4823                 | (mask_m[6] << 18) | (mask_m[7] << 16)
4824                 | (mask_m[8] << 14) | (mask_m[9] << 12)
4825                 | (mask_m[10] << 10) | (mask_m[11] << 8)
4826                 | (mask_m[12] << 6) | (mask_m[13] << 4)
4827                 | (mask_m[14] << 2) | (mask_m[15] << 0);
4828         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
4829         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
4830
4831         tmp_mask = (mask_p[15] << 28)
4832                 | (mask_p[14] << 26) | (mask_p[13] << 24)
4833                 | (mask_p[12] << 22) | (mask_p[11] << 20)
4834                 | (mask_p[10] << 18) | (mask_p[9] << 16)
4835                 | (mask_p[8] << 14) | (mask_p[7] << 12)
4836                 | (mask_p[6] << 10) | (mask_p[5] << 8)
4837                 | (mask_p[4] << 6) | (mask_p[3] << 4)
4838                 | (mask_p[2] << 2) | (mask_p[1] << 0);
4839         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
4840         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
4841
4842         tmp_mask = (mask_p[30] << 28)
4843                 | (mask_p[29] << 26) | (mask_p[28] << 24)
4844                 | (mask_p[27] << 22) | (mask_p[26] << 20)
4845                 | (mask_p[25] << 18) | (mask_p[24] << 16)
4846                 | (mask_p[23] << 14) | (mask_p[22] << 12)
4847                 | (mask_p[21] << 10) | (mask_p[20] << 8)
4848                 | (mask_p[19] << 6) | (mask_p[18] << 4)
4849                 | (mask_p[17] << 2) | (mask_p[16] << 0);
4850         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
4851         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
4852
4853         tmp_mask = (mask_p[45] << 28)
4854                 | (mask_p[44] << 26) | (mask_p[43] << 24)
4855                 | (mask_p[42] << 22) | (mask_p[41] << 20)
4856                 | (mask_p[40] << 18) | (mask_p[39] << 16)
4857                 | (mask_p[38] << 14) | (mask_p[37] << 12)
4858                 | (mask_p[36] << 10) | (mask_p[35] << 8)
4859                 | (mask_p[34] << 6) | (mask_p[33] << 4)
4860                 | (mask_p[32] << 2) | (mask_p[31] << 0);
4861         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
4862         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
4863
4864         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
4865                 | (mask_p[59] << 26) | (mask_p[58] << 24)
4866                 | (mask_p[57] << 22) | (mask_p[56] << 20)
4867                 | (mask_p[55] << 18) | (mask_p[54] << 16)
4868                 | (mask_p[53] << 14) | (mask_p[52] << 12)
4869                 | (mask_p[51] << 10) | (mask_p[50] << 8)
4870                 | (mask_p[49] << 6) | (mask_p[48] << 4)
4871                 | (mask_p[47] << 2) | (mask_p[46] << 0);
4872         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
4873         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
4874 }
4875
4876 static void ath9k_hw_spur_mitigate(struct ath_hal *ah,
4877                                    struct ath9k_channel *chan)
4878 {
4879         int bb_spur = AR_NO_SPUR;
4880         int bin, cur_bin;
4881         int spur_freq_sd;
4882         int spur_delta_phase;
4883         int denominator;
4884         int upper, lower, cur_vit_mask;
4885         int tmp, new;
4886         int i;
4887         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
4888                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
4889         };
4890         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
4891                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
4892         };
4893         int inc[4] = { 0, 100, 0, 0 };
4894
4895         int8_t mask_m[123];
4896         int8_t mask_p[123];
4897         int8_t mask_amt;
4898         int tmp_mask;
4899         int cur_bb_spur;
4900         bool is2GHz = IS_CHAN_2GHZ(chan);
4901
4902         memset(&mask_m, 0, sizeof(int8_t) * 123);
4903         memset(&mask_p, 0, sizeof(int8_t) * 123);
4904
4905         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
4906                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
4907                 if (AR_NO_SPUR == cur_bb_spur)
4908                         break;
4909                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
4910                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
4911                         bb_spur = cur_bb_spur;
4912                         break;
4913                 }
4914         }
4915
4916         if (AR_NO_SPUR == bb_spur)
4917                 return;
4918
4919         bin = bb_spur * 32;
4920
4921         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
4922         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
4923                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
4924                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
4925                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
4926
4927         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
4928
4929         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
4930                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
4931                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
4932                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
4933                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
4934         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
4935
4936         spur_delta_phase = ((bb_spur * 524288) / 100) &
4937                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
4938
4939         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
4940         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
4941
4942         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
4943                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
4944                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
4945         REG_WRITE(ah, AR_PHY_TIMING11, new);
4946
4947         cur_bin = -6000;
4948         upper = bin + 100;
4949         lower = bin - 100;
4950
4951         for (i = 0; i < 4; i++) {
4952                 int pilot_mask = 0;
4953                 int chan_mask = 0;
4954                 int bp = 0;
4955                 for (bp = 0; bp < 30; bp++) {
4956                         if ((cur_bin > lower) && (cur_bin < upper)) {
4957                                 pilot_mask = pilot_mask | 0x1 << bp;
4958                                 chan_mask = chan_mask | 0x1 << bp;
4959                         }
4960                         cur_bin += 100;
4961                 }
4962                 cur_bin += inc[i];
4963                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
4964                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
4965         }
4966
4967         cur_vit_mask = 6100;
4968         upper = bin + 120;
4969         lower = bin - 120;
4970
4971         for (i = 0; i < 123; i++) {
4972                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
4973
4974                         /* workaround for gcc bug #37014 */
4975                         volatile int tmp = abs(cur_vit_mask - bin);
4976
4977                         if (tmp < 75)
4978                                 mask_amt = 1;
4979                         else
4980                                 mask_amt = 0;
4981                         if (cur_vit_mask < 0)
4982                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
4983                         else
4984                                 mask_p[cur_vit_mask / 100] = mask_amt;
4985                 }
4986                 cur_vit_mask -= 100;
4987         }
4988
4989         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
4990                 | (mask_m[48] << 26) | (mask_m[49] << 24)
4991                 | (mask_m[50] << 22) | (mask_m[51] << 20)
4992                 | (mask_m[52] << 18) | (mask_m[53] << 16)
4993                 | (mask_m[54] << 14) | (mask_m[55] << 12)
4994                 | (mask_m[56] << 10) | (mask_m[57] << 8)
4995                 | (mask_m[58] << 6) | (mask_m[59] << 4)
4996                 | (mask_m[60] << 2) | (mask_m[61] << 0);
4997         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
4998         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
4999
5000         tmp_mask = (mask_m[31] << 28)
5001                 | (mask_m[32] << 26) | (mask_m[33] << 24)
5002                 | (mask_m[34] << 22) | (mask_m[35] << 20)
5003                 | (mask_m[36] << 18) | (mask_m[37] << 16)
5004                 | (mask_m[48] << 14) | (mask_m[39] << 12)
5005                 | (mask_m[40] << 10) | (mask_m[41] << 8)
5006                 | (mask_m[42] << 6) | (mask_m[43] << 4)
5007                 | (mask_m[44] << 2) | (mask_m[45] << 0);
5008         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
5009         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
5010
5011         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
5012                 | (mask_m[18] << 26) | (mask_m[18] << 24)
5013                 | (mask_m[20] << 22) | (mask_m[20] << 20)
5014                 | (mask_m[22] << 18) | (mask_m[22] << 16)
5015                 | (mask_m[24] << 14) | (mask_m[24] << 12)
5016                 | (mask_m[25] << 10) | (mask_m[26] << 8)
5017                 | (mask_m[27] << 6) | (mask_m[28] << 4)
5018                 | (mask_m[29] << 2) | (mask_m[30] << 0);
5019         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
5020         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
5021
5022         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
5023                 | (mask_m[2] << 26) | (mask_m[3] << 24)
5024                 | (mask_m[4] << 22) | (mask_m[5] << 20)
5025                 | (mask_m[6] << 18) | (mask_m[7] << 16)
5026                 | (mask_m[8] << 14) | (mask_m[9] << 12)
5027                 | (mask_m[10] << 10) | (mask_m[11] << 8)
5028                 | (mask_m[12] << 6) | (mask_m[13] << 4)
5029                 | (mask_m[14] << 2) | (mask_m[15] << 0);
5030         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
5031         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
5032
5033         tmp_mask = (mask_p[15] << 28)
5034                 | (mask_p[14] << 26) | (mask_p[13] << 24)
5035                 | (mask_p[12] << 22) | (mask_p[11] << 20)
5036                 | (mask_p[10] << 18) | (mask_p[9] << 16)
5037                 | (mask_p[8] << 14) | (mask_p[7] << 12)
5038                 | (mask_p[6] << 10) | (mask_p[5] << 8)
5039                 | (mask_p[4] << 6) | (mask_p[3] << 4)
5040                 | (mask_p[2] << 2) | (mask_p[1] << 0);
5041         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
5042         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
5043
5044         tmp_mask = (mask_p[30] << 28)
5045                 | (mask_p[29] << 26) | (mask_p[28] << 24)
5046                 | (mask_p[27] << 22) | (mask_p[26] << 20)
5047                 | (mask_p[25] << 18) | (mask_p[24] << 16)
5048                 | (mask_p[23] << 14) | (mask_p[22] << 12)
5049                 | (mask_p[21] << 10) | (mask_p[20] << 8)
5050                 | (mask_p[19] << 6) | (mask_p[18] << 4)
5051                 | (mask_p[17] << 2) | (mask_p[16] << 0);
5052         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
5053         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
5054
5055         tmp_mask = (mask_p[45] << 28)
5056                 | (mask_p[44] << 26) | (mask_p[43] << 24)
5057                 | (mask_p[42] << 22) | (mask_p[41] << 20)
5058                 | (mask_p[40] << 18) | (mask_p[39] << 16)
5059                 | (mask_p[38] << 14) | (mask_p[37] << 12)
5060                 | (mask_p[36] << 10) | (mask_p[35] << 8)
5061                 | (mask_p[34] << 6) | (mask_p[33] << 4)
5062                 | (mask_p[32] << 2) | (mask_p[31] << 0);
5063         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
5064         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
5065
5066         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
5067                 | (mask_p[59] << 26) | (mask_p[58] << 24)
5068                 | (mask_p[57] << 22) | (mask_p[56] << 20)
5069                 | (mask_p[55] << 18) | (mask_p[54] << 16)
5070                 | (mask_p[53] << 14) | (mask_p[52] << 12)
5071                 | (mask_p[51] << 10) | (mask_p[50] << 8)
5072                 | (mask_p[49] << 6) | (mask_p[48] << 4)
5073                 | (mask_p[47] << 2) | (mask_p[46] << 0);
5074         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
5075         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
5076 }
5077
5078 static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
5079 {
5080         struct ath_hal_5416 *ahp = AH5416(ah);
5081         int rx_chainmask, tx_chainmask;
5082
5083         rx_chainmask = ahp->ah_rxchainmask;
5084         tx_chainmask = ahp->ah_txchainmask;
5085
5086         switch (rx_chainmask) {
5087         case 0x5:
5088                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
5089                             AR_PHY_SWAP_ALT_CHAIN);
5090         case 0x3:
5091                 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
5092                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
5093                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
5094                         break;
5095                 }
5096         case 0x1:
5097         case 0x2:
5098                 if (!AR_SREV_9280(ah))
5099                         break;
5100         case 0x7:
5101                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
5102                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
5103                 break;
5104         default:
5105                 break;
5106         }
5107
5108         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
5109         if (tx_chainmask == 0x5) {
5110                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
5111                             AR_PHY_SWAP_ALT_CHAIN);
5112         }
5113         if (AR_SREV_9100(ah))
5114                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
5115                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
5116 }
5117
5118 static void ath9k_hw_set_addac(struct ath_hal *ah,
5119                                struct ath9k_channel *chan)
5120 {
5121         struct modal_eep_header *pModal;
5122         struct ath_hal_5416 *ahp = AH5416(ah);
5123         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
5124         u8 biaslevel;
5125
5126         if (ah->ah_macVersion != AR_SREV_VERSION_9160)
5127                 return;
5128
5129         if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7)
5130                 return;
5131
5132         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
5133
5134         if (pModal->xpaBiasLvl != 0xff) {
5135                 biaslevel = pModal->xpaBiasLvl;
5136         } else {
5137
5138                 u16 resetFreqBin, freqBin, freqCount = 0;
5139                 struct chan_centers centers;
5140
5141                 ath9k_hw_get_channel_centers(ah, chan, &centers);
5142
5143                 resetFreqBin =
5144                         FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan));
5145                 freqBin = pModal->xpaBiasLvlFreq[0] & 0xff;
5146                 biaslevel = (u8) (pModal->xpaBiasLvlFreq[0] >> 14);
5147
5148                 freqCount++;
5149
5150                 while (freqCount < 3) {
5151                         if (pModal->xpaBiasLvlFreq[freqCount] == 0x0)
5152                                 break;
5153
5154                         freqBin = pModal->xpaBiasLvlFreq[freqCount] & 0xff;
5155                         if (resetFreqBin >= freqBin) {
5156                                 biaslevel =
5157                                         (u8) (pModal->
5158                                                     xpaBiasLvlFreq[freqCount]
5159                                                     >> 14);
5160                         } else {
5161                                 break;
5162                         }
5163                         freqCount++;
5164                 }
5165         }
5166
5167         if (IS_CHAN_2GHZ(chan)) {
5168                 INI_RA(&ahp->ah_iniAddac, 7, 1) =
5169                         (INI_RA(&ahp->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel
5170                         << 3;
5171         } else {
5172                 INI_RA(&ahp->ah_iniAddac, 6, 1) =
5173                         (INI_RA(&ahp->ah_iniAddac, 6, 1) & (~0xc0)) | biaslevel
5174                         << 6;
5175         }
5176 }
5177
5178 static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
5179 {
5180         if (ah->ah_curchan != NULL)
5181                 return clks /
5182                 CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)];
5183         else
5184                 return clks / CLOCK_RATE[ATH9K_MODE_11B];
5185 }
5186
5187 static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
5188 {
5189         struct ath9k_channel *chan = ah->ah_curchan;
5190
5191         if (chan && IS_CHAN_HT40(chan))
5192                 return ath9k_hw_mac_usec(ah, clks) / 2;
5193         else
5194                 return ath9k_hw_mac_usec(ah, clks);
5195 }
5196
5197 static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
5198 {
5199         if (ah->ah_curchan != NULL)
5200                 return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah,
5201                         ah->ah_curchan)];
5202         else
5203                 return usecs * CLOCK_RATE[ATH9K_MODE_11B];
5204 }
5205
5206 static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
5207 {
5208         struct ath9k_channel *chan = ah->ah_curchan;
5209
5210         if (chan && IS_CHAN_HT40(chan))
5211                 return ath9k_hw_mac_clks(ah, usecs) * 2;
5212         else
5213                 return ath9k_hw_mac_clks(ah, usecs);
5214 }
5215
5216 static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
5217 {
5218         struct ath_hal_5416 *ahp = AH5416(ah);
5219
5220         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
5221                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad ack timeout %u\n",
5222                          __func__, us);
5223                 ahp->ah_acktimeout = (u32) -1;
5224                 return false;
5225         } else {
5226                 REG_RMW_FIELD(ah, AR_TIME_OUT,
5227                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
5228                 ahp->ah_acktimeout = us;
5229                 return true;
5230         }
5231 }
5232
5233 static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
5234 {
5235         struct ath_hal_5416 *ahp = AH5416(ah);
5236
5237         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
5238                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad cts timeout %u\n",
5239                          __func__, us);
5240                 ahp->ah_ctstimeout = (u32) -1;
5241                 return false;
5242         } else {
5243                 REG_RMW_FIELD(ah, AR_TIME_OUT,
5244                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
5245                 ahp->ah_ctstimeout = us;
5246                 return true;
5247         }
5248 }
5249 static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah,
5250                                           u32 tu)
5251 {
5252         struct ath_hal_5416 *ahp = AH5416(ah);
5253
5254         if (tu > 0xFFFF) {
5255                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
5256                         "%s: bad global tx timeout %u\n", __func__, tu);
5257                 ahp->ah_globaltxtimeout = (u32) -1;
5258                 return false;
5259         } else {
5260                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
5261                 ahp->ah_globaltxtimeout = tu;
5262                 return true;
5263         }
5264 }
5265
5266 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
5267 {
5268         struct ath_hal_5416 *ahp = AH5416(ah);
5269
5270         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
5271                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad slot time %u\n",
5272                          __func__, us);
5273                 ahp->ah_slottime = (u32) -1;
5274                 return false;
5275         } else {
5276                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
5277                 ahp->ah_slottime = us;
5278                 return true;
5279         }
5280 }
5281
5282 static void ath9k_hw_init_user_settings(struct ath_hal *ah)
5283 {
5284         struct ath_hal_5416 *ahp = AH5416(ah);
5285
5286         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "--AP %s ahp->ah_miscMode 0x%x\n",
5287                  __func__, ahp->ah_miscMode);
5288         if (ahp->ah_miscMode != 0)
5289                 REG_WRITE(ah, AR_PCU_MISC,
5290                           REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
5291         if (ahp->ah_slottime != (u32) -1)
5292                 ath9k_hw_setslottime(ah, ahp->ah_slottime);
5293         if (ahp->ah_acktimeout != (u32) -1)
5294                 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
5295         if (ahp->ah_ctstimeout != (u32) -1)
5296                 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
5297         if (ahp->ah_globaltxtimeout != (u32) -1)
5298                 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
5299 }
5300
5301 static int
5302 ath9k_hw_process_ini(struct ath_hal *ah,
5303                      struct ath9k_channel *chan,
5304                      enum ath9k_ht_macmode macmode)
5305 {
5306         int i, regWrites = 0;
5307         struct ath_hal_5416 *ahp = AH5416(ah);
5308         u32 modesIndex, freqIndex;
5309         int status;
5310
5311         switch (chan->chanmode) {
5312         case CHANNEL_A:
5313         case CHANNEL_A_HT20:
5314                 modesIndex = 1;
5315                 freqIndex = 1;
5316                 break;
5317         case CHANNEL_A_HT40PLUS:
5318         case CHANNEL_A_HT40MINUS:
5319                 modesIndex = 2;
5320                 freqIndex = 1;
5321                 break;
5322         case CHANNEL_G:
5323         case CHANNEL_G_HT20:
5324         case CHANNEL_B:
5325                 modesIndex = 4;
5326                 freqIndex = 2;
5327                 break;
5328         case CHANNEL_G_HT40PLUS:
5329         case CHANNEL_G_HT40MINUS:
5330                 modesIndex = 3;
5331                 freqIndex = 2;
5332                 break;
5333
5334         default:
5335                 return -EINVAL;
5336         }
5337
5338         REG_WRITE(ah, AR_PHY(0), 0x00000007);
5339
5340         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
5341
5342         ath9k_hw_set_addac(ah, chan);
5343
5344         if (AR_SREV_5416_V22_OR_LATER(ah)) {
5345                 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
5346         } else {
5347                 struct ar5416IniArray temp;
5348                 u32 addacSize =
5349                         sizeof(u32) * ahp->ah_iniAddac.ia_rows *
5350                         ahp->ah_iniAddac.ia_columns;
5351
5352                 memcpy(ahp->ah_addac5416_21,
5353                        ahp->ah_iniAddac.ia_array, addacSize);
5354
5355                 (ahp->ah_addac5416_21)[31 *
5356                                        ahp->ah_iniAddac.ia_columns + 1] = 0;
5357
5358                 temp.ia_array = ahp->ah_addac5416_21;
5359                 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
5360                 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
5361                 REG_WRITE_ARRAY(&temp, 1, regWrites);
5362         }
5363         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
5364
5365         for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
5366                 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
5367                 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
5368
5369 #ifdef CONFIG_SLOW_ANT_DIV
5370                 if (ah->ah_devid == AR9280_DEVID_PCI)
5371                         val = ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom, reg,
5372                                                  val);
5373 #endif
5374
5375                 REG_WRITE(ah, reg, val);
5376
5377                 if (reg >= 0x7800 && reg < 0x78a0
5378                     && ah->ah_config.analog_shiftreg) {
5379                         udelay(100);
5380                 }
5381
5382                 DO_DELAY(regWrites);
5383         }
5384
5385         for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
5386                 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
5387                 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
5388
5389                 REG_WRITE(ah, reg, val);
5390
5391                 if (reg >= 0x7800 && reg < 0x78a0
5392                     && ah->ah_config.analog_shiftreg) {
5393                         udelay(100);
5394                 }
5395
5396                 DO_DELAY(regWrites);
5397         }
5398
5399         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
5400
5401         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
5402                 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
5403                                 regWrites);
5404         }
5405
5406         ath9k_hw_override_ini(ah, chan);
5407         ath9k_hw_set_regs(ah, chan, macmode);
5408         ath9k_hw_init_chain_masks(ah);
5409
5410         status = ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan,
5411                                       ath9k_regd_get_ctl(ah, chan),
5412                                       ath9k_regd_get_antenna_allowed(ah,
5413                                                                      chan),
5414                                       chan->maxRegTxPower * 2,
5415                                       min((u32) MAX_RATE_POWER,
5416                                           (u32) ah->ah_powerLimit));
5417         if (status != 0) {
5418                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
5419                          "%s: error init'ing transmit power\n", __func__);
5420                 return -EIO;
5421         }
5422
5423         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
5424                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
5425                          "%s: ar5416SetRfRegs failed\n", __func__);
5426                 return -EIO;
5427         }
5428
5429         return 0;
5430 }
5431
5432 static void ath9k_hw_setup_calibration(struct ath_hal *ah,
5433                                               struct hal_cal_list *currCal)
5434 {
5435         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
5436                       AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
5437                       currCal->calData->calCountMax);
5438
5439         switch (currCal->calData->calType) {
5440         case IQ_MISMATCH_CAL:
5441                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
5442                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5443                          "%s: starting IQ Mismatch Calibration\n",
5444                          __func__);
5445                 break;
5446         case ADC_GAIN_CAL:
5447                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
5448                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5449                          "%s: starting ADC Gain Calibration\n", __func__);
5450                 break;
5451         case ADC_DC_CAL:
5452                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
5453                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5454                          "%s: starting ADC DC Calibration\n", __func__);
5455                 break;
5456         case ADC_DC_INIT_CAL:
5457                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
5458                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5459                          "%s: starting Init ADC DC Calibration\n",
5460                          __func__);
5461                 break;
5462         }
5463
5464         REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
5465                     AR_PHY_TIMING_CTRL4_DO_CAL);
5466 }
5467
5468 static void ath9k_hw_reset_calibration(struct ath_hal *ah,
5469                                        struct hal_cal_list *currCal)
5470 {
5471         struct ath_hal_5416 *ahp = AH5416(ah);
5472         int i;
5473
5474         ath9k_hw_setup_calibration(ah, currCal);
5475
5476         currCal->calState = CAL_RUNNING;
5477
5478         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
5479                 ahp->ah_Meas0.sign[i] = 0;
5480                 ahp->ah_Meas1.sign[i] = 0;
5481                 ahp->ah_Meas2.sign[i] = 0;
5482                 ahp->ah_Meas3.sign[i] = 0;
5483         }
5484
5485         ahp->ah_CalSamples = 0;
5486 }
5487
5488 static void
5489 ath9k_hw_per_calibration(struct ath_hal *ah,
5490                          struct ath9k_channel *ichan,
5491                          u8 rxchainmask,
5492                          struct hal_cal_list *currCal,
5493                          bool *isCalDone)
5494 {
5495         struct ath_hal_5416 *ahp = AH5416(ah);
5496
5497         *isCalDone = false;
5498
5499         if (currCal->calState == CAL_RUNNING) {
5500                 if (!(REG_READ(ah,
5501                                AR_PHY_TIMING_CTRL4(0)) &
5502                       AR_PHY_TIMING_CTRL4_DO_CAL)) {
5503
5504                         currCal->calData->calCollect(ah);
5505
5506                         ahp->ah_CalSamples++;
5507
5508                         if (ahp->ah_CalSamples >=
5509                             currCal->calData->calNumSamples) {
5510                                 int i, numChains = 0;
5511                                 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
5512                                         if (rxchainmask & (1 << i))
5513                                                 numChains++;
5514                                 }
5515
5516                                 currCal->calData->calPostProc(ah,
5517                                                               numChains);
5518
5519                                 ichan->CalValid |=
5520                                         currCal->calData->calType;
5521                                 currCal->calState = CAL_DONE;
5522                                 *isCalDone = true;
5523                         } else {
5524                                 ath9k_hw_setup_calibration(ah, currCal);
5525                         }
5526                 }
5527         } else if (!(ichan->CalValid & currCal->calData->calType)) {
5528                 ath9k_hw_reset_calibration(ah, currCal);
5529         }
5530 }
5531
5532 static inline bool ath9k_hw_run_init_cals(struct ath_hal *ah,
5533                                           int init_cal_count)
5534 {
5535         struct ath_hal_5416 *ahp = AH5416(ah);
5536         struct ath9k_channel ichan;
5537         bool isCalDone;
5538         struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
5539         const struct hal_percal_data *calData = currCal->calData;
5540         int i;
5541
5542         if (currCal == NULL)
5543                 return false;
5544
5545         ichan.CalValid = 0;
5546
5547         for (i = 0; i < init_cal_count; i++) {
5548                 ath9k_hw_reset_calibration(ah, currCal);
5549
5550                 if (!ath9k_hw_wait(ah, AR_PHY_TIMING_CTRL4(0),
5551                                    AR_PHY_TIMING_CTRL4_DO_CAL, 0)) {
5552                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5553                                  "%s: Cal %d failed to complete in 100ms.\n",
5554                                  __func__, calData->calType);
5555
5556                         ahp->ah_cal_list = ahp->ah_cal_list_last =
5557                                 ahp->ah_cal_list_curr = NULL;
5558                         return false;
5559                 }
5560
5561                 ath9k_hw_per_calibration(ah, &ichan, ahp->ah_rxchainmask,
5562                                          currCal, &isCalDone);
5563                 if (!isCalDone) {
5564                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5565                                  "%s: Not able to run Init Cal %d.\n",
5566                                  __func__, calData->calType);
5567                 }
5568                 if (currCal->calNext) {
5569                         currCal = currCal->calNext;
5570                         calData = currCal->calData;
5571                 }
5572         }
5573
5574         ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = NULL;
5575         return true;
5576 }
5577
5578 static bool
5579 ath9k_hw_channel_change(struct ath_hal *ah,
5580                         struct ath9k_channel *chan,
5581                         enum ath9k_ht_macmode macmode)
5582 {
5583         u32 synthDelay, qnum;
5584         struct ath_hal_5416 *ahp = AH5416(ah);
5585
5586         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
5587                 if (ath9k_hw_numtxpending(ah, qnum)) {
5588                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
5589                                  "%s: Transmit frames pending on queue %d\n",
5590                                  __func__, qnum);
5591                         return false;
5592                 }
5593         }
5594
5595         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
5596         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
5597                            AR_PHY_RFBUS_GRANT_EN)) {
5598                 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
5599                          "%s: Could not kill baseband RX\n", __func__);
5600                 return false;
5601         }
5602
5603         ath9k_hw_set_regs(ah, chan, macmode);
5604
5605         if (AR_SREV_9280_10_OR_LATER(ah)) {
5606                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
5607                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
5608                                  "%s: failed to set channel\n", __func__);
5609                         return false;
5610                 }
5611         } else {
5612                 if (!(ath9k_hw_set_channel(ah, chan))) {
5613                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
5614                                  "%s: failed to set channel\n", __func__);
5615                         return false;
5616                 }
5617         }
5618
5619         if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan,
5620                                  ath9k_regd_get_ctl(ah, chan),
5621                                  ath9k_regd_get_antenna_allowed(ah, chan),
5622                                  chan->maxRegTxPower * 2,
5623                                  min((u32) MAX_RATE_POWER,
5624                                      (u32) ah->ah_powerLimit)) != 0) {
5625                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
5626                          "%s: error init'ing transmit power\n", __func__);
5627                 return false;
5628         }
5629
5630         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
5631         if (IS_CHAN_CCK(chan))
5632                 synthDelay = (4 * synthDelay) / 22;
5633         else
5634                 synthDelay /= 10;
5635
5636         udelay(synthDelay + BASE_ACTIVATE_DELAY);
5637
5638         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
5639
5640         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
5641                 ath9k_hw_set_delta_slope(ah, chan);
5642
5643         if (AR_SREV_9280_10_OR_LATER(ah))
5644                 ath9k_hw_9280_spur_mitigate(ah, chan);
5645         else
5646                 ath9k_hw_spur_mitigate(ah, chan);
5647
5648         if (!chan->oneTimeCalsDone)
5649                 chan->oneTimeCalsDone = true;
5650
5651         return true;
5652 }
5653
5654 static bool ath9k_hw_chip_reset(struct ath_hal *ah,
5655                                 struct ath9k_channel *chan)
5656 {
5657         struct ath_hal_5416 *ahp = AH5416(ah);
5658
5659         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
5660                 return false;
5661
5662         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
5663                 return false;
5664
5665         ahp->ah_chipFullSleep = false;
5666
5667         ath9k_hw_init_pll(ah, chan);
5668
5669         ath9k_hw_set_rfmode(ah, chan);
5670
5671         return true;
5672 }
5673
5674 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
5675 {
5676         u32 regval;
5677
5678         regval = REG_READ(ah, AR_AHB_MODE);
5679         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
5680
5681         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
5682         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
5683
5684         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
5685
5686         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
5687         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
5688
5689         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
5690
5691         if (AR_SREV_9285(ah)) {
5692                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
5693                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
5694         } else {
5695                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
5696                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
5697         }
5698 }
5699
5700 bool ath9k_hw_stopdmarecv(struct ath_hal *ah)
5701 {
5702         REG_WRITE(ah, AR_CR, AR_CR_RXD);
5703         if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) {
5704                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
5705                         "%s: dma failed to stop in 10ms\n"
5706                         "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
5707                         __func__,
5708                         REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
5709                 return false;
5710         } else {
5711                 return true;
5712         }
5713 }
5714
5715 void ath9k_hw_startpcureceive(struct ath_hal *ah)
5716 {
5717         REG_CLR_BIT(ah, AR_DIAG_SW,
5718                     (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
5719
5720         ath9k_enable_mib_counters(ah);
5721
5722         ath9k_ani_reset(ah);
5723 }
5724
5725 void ath9k_hw_stoppcurecv(struct ath_hal *ah)
5726 {
5727         REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
5728
5729         ath9k_hw_disable_mib_counters(ah);
5730 }
5731
5732 static bool ath9k_hw_iscal_supported(struct ath_hal *ah,
5733                                      struct ath9k_channel *chan,
5734                                      enum hal_cal_types calType)
5735 {
5736         struct ath_hal_5416 *ahp = AH5416(ah);
5737         bool retval = false;
5738
5739         switch (calType & ahp->ah_suppCals) {
5740         case IQ_MISMATCH_CAL:
5741                 if (!IS_CHAN_B(chan))
5742                         retval = true;
5743                 break;
5744         case ADC_GAIN_CAL:
5745         case ADC_DC_CAL:
5746                 if (!IS_CHAN_B(chan)
5747                     && !(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan)))
5748                         retval = true;
5749                 break;
5750         }
5751
5752         return retval;
5753 }
5754
5755 static bool ath9k_hw_init_cal(struct ath_hal *ah,
5756                               struct ath9k_channel *chan)
5757 {
5758         struct ath_hal_5416 *ahp = AH5416(ah);
5759         struct ath9k_channel *ichan =
5760                 ath9k_regd_check_channel(ah, chan);
5761
5762         REG_WRITE(ah, AR_PHY_AGC_CONTROL,
5763                   REG_READ(ah, AR_PHY_AGC_CONTROL) |
5764                   AR_PHY_AGC_CONTROL_CAL);
5765
5766         if (!ath9k_hw_wait
5767             (ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
5768                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5769                          "%s: offset calibration failed to complete in 1ms; "
5770                          "noisy environment?\n", __func__);
5771                 return false;
5772         }
5773
5774         REG_WRITE(ah, AR_PHY_AGC_CONTROL,
5775                   REG_READ(ah, AR_PHY_AGC_CONTROL) |
5776                   AR_PHY_AGC_CONTROL_NF);
5777
5778         ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr =
5779                 NULL;
5780
5781         if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
5782                 if (ath9k_hw_iscal_supported(ah, chan, ADC_GAIN_CAL)) {
5783                         INIT_CAL(&ahp->ah_adcGainCalData);
5784                         INSERT_CAL(ahp, &ahp->ah_adcGainCalData);
5785                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5786                                  "%s: enabling ADC Gain Calibration.\n",
5787                                  __func__);
5788                 }
5789                 if (ath9k_hw_iscal_supported(ah, chan, ADC_DC_CAL)) {
5790                         INIT_CAL(&ahp->ah_adcDcCalData);
5791                         INSERT_CAL(ahp, &ahp->ah_adcDcCalData);
5792                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5793                                  "%s: enabling ADC DC Calibration.\n",
5794                                  __func__);
5795                 }
5796                 if (ath9k_hw_iscal_supported(ah, chan, IQ_MISMATCH_CAL)) {
5797                         INIT_CAL(&ahp->ah_iqCalData);
5798                         INSERT_CAL(ahp, &ahp->ah_iqCalData);
5799                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5800                                  "%s: enabling IQ Calibration.\n",
5801                                  __func__);
5802                 }
5803
5804                 ahp->ah_cal_list_curr = ahp->ah_cal_list;
5805
5806                 if (ahp->ah_cal_list_curr)
5807                         ath9k_hw_reset_calibration(ah,
5808                                                    ahp->ah_cal_list_curr);
5809         }
5810
5811         ichan->CalValid = 0;
5812
5813         return true;
5814 }
5815
5816
5817 bool ath9k_hw_reset(struct ath_hal *ah,
5818                     struct ath9k_channel *chan,
5819                     enum ath9k_ht_macmode macmode,
5820                     u8 txchainmask, u8 rxchainmask,
5821                     enum ath9k_ht_extprotspacing extprotspacing,
5822                     bool bChannelChange,
5823                     int *status)
5824 {
5825 #define FAIL(_code)     do { ecode = _code; goto bad; } while (0)
5826         u32 saveLedState;
5827         struct ath_hal_5416 *ahp = AH5416(ah);
5828         struct ath9k_channel *curchan = ah->ah_curchan;
5829         u32 saveDefAntenna;
5830         u32 macStaId1;
5831         int ecode;
5832         int i, rx_chainmask;
5833
5834         ahp->ah_extprotspacing = extprotspacing;
5835         ahp->ah_txchainmask = txchainmask;
5836         ahp->ah_rxchainmask = rxchainmask;
5837
5838         if (AR_SREV_9280(ah)) {
5839                 ahp->ah_txchainmask &= 0x3;
5840                 ahp->ah_rxchainmask &= 0x3;
5841         }
5842
5843         if (ath9k_hw_check_chan(ah, chan) == NULL) {
5844                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
5845                          "%s: invalid channel %u/0x%x; no mapping\n",
5846                          __func__, chan->channel, chan->channelFlags);
5847                 FAIL(-EINVAL);
5848         }
5849
5850         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
5851                 return false;
5852
5853         if (curchan)
5854                 ath9k_hw_getnf(ah, curchan);
5855
5856         if (bChannelChange &&
5857             (ahp->ah_chipFullSleep != true) &&
5858             (ah->ah_curchan != NULL) &&
5859             (chan->channel != ah->ah_curchan->channel) &&
5860             ((chan->channelFlags & CHANNEL_ALL) ==
5861              (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
5862             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
5863                                    !IS_CHAN_A_5MHZ_SPACED(ah->
5864                                                           ah_curchan)))) {
5865
5866                 if (ath9k_hw_channel_change(ah, chan, macmode)) {
5867                         ath9k_hw_loadnf(ah, ah->ah_curchan);
5868                         ath9k_hw_start_nfcal(ah);
5869                         return true;
5870                 }
5871         }
5872
5873         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
5874         if (saveDefAntenna == 0)
5875                 saveDefAntenna = 1;
5876
5877         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
5878
5879         saveLedState = REG_READ(ah, AR_CFG_LED) &
5880                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
5881                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
5882
5883         ath9k_hw_mark_phy_inactive(ah);
5884
5885         if (!ath9k_hw_chip_reset(ah, chan)) {
5886                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: chip reset failed\n",
5887                          __func__);
5888                 FAIL(-EIO);
5889         }
5890
5891         if (AR_SREV_9280(ah)) {
5892                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
5893                             AR_GPIO_JTAG_DISABLE);
5894
5895                 if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) {
5896                         if (IS_CHAN_5GHZ(chan))
5897                                 ath9k_hw_set_gpio(ah, 9, 0);
5898                         else
5899                                 ath9k_hw_set_gpio(ah, 9, 1);
5900                 }
5901                 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
5902         }
5903
5904         ecode = ath9k_hw_process_ini(ah, chan, macmode);
5905         if (ecode != 0)
5906                 goto bad;
5907
5908         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
5909                 ath9k_hw_set_delta_slope(ah, chan);
5910
5911         if (AR_SREV_9280_10_OR_LATER(ah))
5912                 ath9k_hw_9280_spur_mitigate(ah, chan);
5913         else
5914                 ath9k_hw_spur_mitigate(ah, chan);
5915
5916         if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
5917                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
5918                          "%s: error setting board options\n", __func__);
5919                 FAIL(-EIO);
5920         }
5921
5922         ath9k_hw_decrease_chain_power(ah, chan);
5923
5924         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr));
5925         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4)
5926                   | macStaId1
5927                   | AR_STA_ID1_RTS_USE_DEF
5928                   | (ah->ah_config.
5929                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
5930                   | ahp->ah_staId1Defaults);
5931         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
5932
5933         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
5934         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
5935
5936         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
5937
5938         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
5939         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
5940                   ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
5941
5942         REG_WRITE(ah, AR_ISR, ~0);
5943
5944         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
5945
5946         if (AR_SREV_9280_10_OR_LATER(ah)) {
5947                 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
5948                         FAIL(-EIO);
5949         } else {
5950                 if (!(ath9k_hw_set_channel(ah, chan)))
5951                         FAIL(-EIO);
5952         }
5953
5954         for (i = 0; i < AR_NUM_DCU; i++)
5955                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
5956
5957         ahp->ah_intrTxqs = 0;
5958         for (i = 0; i < ah->ah_caps.total_queues; i++)
5959                 ath9k_hw_resettxqueue(ah, i);
5960
5961         ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
5962         ath9k_hw_init_qos(ah);
5963
5964         ath9k_hw_init_user_settings(ah);
5965
5966         REG_WRITE(ah, AR_STA_ID1,
5967                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
5968
5969         ath9k_hw_set_dma(ah);
5970
5971         REG_WRITE(ah, AR_OBS, 8);
5972
5973         if (ahp->ah_intrMitigation) {
5974
5975                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
5976                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
5977         }
5978
5979         ath9k_hw_init_bb(ah, chan);
5980
5981         if (!ath9k_hw_init_cal(ah, chan))
5982                 FAIL(-ENODEV);
5983
5984         rx_chainmask = ahp->ah_rxchainmask;
5985         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
5986                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
5987                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
5988         }
5989
5990         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
5991
5992         if (AR_SREV_9100(ah)) {
5993                 u32 mask;
5994                 mask = REG_READ(ah, AR_CFG);
5995                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
5996                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
5997                                  "%s CFG Byte Swap Set 0x%x\n", __func__,
5998                                  mask);
5999                 } else {
6000                         mask =
6001                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
6002                         REG_WRITE(ah, AR_CFG, mask);
6003                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
6004                                  "%s Setting CFG 0x%x\n", __func__,
6005                                  REG_READ(ah, AR_CFG));
6006                 }
6007         } else {
6008 #ifdef __BIG_ENDIAN
6009                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
6010 #endif
6011         }
6012
6013         return true;
6014 bad:
6015         if (status)
6016                 *status = ecode;
6017         return false;
6018 #undef FAIL
6019 }
6020
6021 bool ath9k_hw_phy_disable(struct ath_hal *ah)
6022 {
6023         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
6024 }
6025
6026 bool ath9k_hw_disable(struct ath_hal *ah)
6027 {
6028         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
6029                 return false;
6030
6031         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
6032 }
6033
6034 bool
6035 ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
6036                    u8 rxchainmask, bool longcal,
6037                    bool *isCalDone)
6038 {
6039         struct ath_hal_5416 *ahp = AH5416(ah);
6040         struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
6041         struct ath9k_channel *ichan =
6042                 ath9k_regd_check_channel(ah, chan);
6043
6044         *isCalDone = true;
6045
6046         if (ichan == NULL) {
6047                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
6048                          "%s: invalid channel %u/0x%x; no mapping\n",
6049                          __func__, chan->channel, chan->channelFlags);
6050                 return false;
6051         }
6052
6053         if (currCal &&
6054             (currCal->calState == CAL_RUNNING ||
6055              currCal->calState == CAL_WAITING)) {
6056                 ath9k_hw_per_calibration(ah, ichan, rxchainmask, currCal,
6057                                          isCalDone);
6058                 if (*isCalDone) {
6059                         ahp->ah_cal_list_curr = currCal = currCal->calNext;
6060
6061                         if (currCal->calState == CAL_WAITING) {
6062                                 *isCalDone = false;
6063                                 ath9k_hw_reset_calibration(ah, currCal);
6064                         }
6065                 }
6066         }
6067
6068         if (longcal) {
6069                 ath9k_hw_getnf(ah, ichan);
6070                 ath9k_hw_loadnf(ah, ah->ah_curchan);
6071                 ath9k_hw_start_nfcal(ah);
6072
6073                 if ((ichan->channelFlags & CHANNEL_CW_INT) != 0) {
6074
6075                         chan->channelFlags |= CHANNEL_CW_INT;
6076                         ichan->channelFlags &= ~CHANNEL_CW_INT;
6077                 }
6078         }
6079
6080         return true;
6081 }
6082
6083 static void ath9k_hw_iqcal_collect(struct ath_hal *ah)
6084 {
6085         struct ath_hal_5416 *ahp = AH5416(ah);
6086         int i;
6087
6088         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
6089                 ahp->ah_totalPowerMeasI[i] +=
6090                         REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
6091                 ahp->ah_totalPowerMeasQ[i] +=
6092                         REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
6093                 ahp->ah_totalIqCorrMeas[i] +=
6094                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6095                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6096                          "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
6097                          ahp->ah_CalSamples, i, ahp->ah_totalPowerMeasI[i],
6098                          ahp->ah_totalPowerMeasQ[i],
6099                          ahp->ah_totalIqCorrMeas[i]);
6100         }
6101 }
6102
6103 static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah)
6104 {
6105         struct ath_hal_5416 *ahp = AH5416(ah);
6106         int i;
6107
6108         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
6109                 ahp->ah_totalAdcIOddPhase[i] +=
6110                         REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
6111                 ahp->ah_totalAdcIEvenPhase[i] +=
6112                         REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
6113                 ahp->ah_totalAdcQOddPhase[i] +=
6114                         REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6115                 ahp->ah_totalAdcQEvenPhase[i] +=
6116                         REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
6117
6118                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6119                         "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
6120                         "oddq=0x%08x; evenq=0x%08x;\n",
6121                          ahp->ah_CalSamples, i,
6122                          ahp->ah_totalAdcIOddPhase[i],
6123                          ahp->ah_totalAdcIEvenPhase[i],
6124                          ahp->ah_totalAdcQOddPhase[i],
6125                          ahp->ah_totalAdcQEvenPhase[i]);
6126         }
6127 }
6128
6129 static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah)
6130 {
6131         struct ath_hal_5416 *ahp = AH5416(ah);
6132         int i;
6133
6134         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
6135                 ahp->ah_totalAdcDcOffsetIOddPhase[i] +=
6136                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
6137                 ahp->ah_totalAdcDcOffsetIEvenPhase[i] +=
6138                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
6139                 ahp->ah_totalAdcDcOffsetQOddPhase[i] +=
6140                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6141                 ahp->ah_totalAdcDcOffsetQEvenPhase[i] +=
6142                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
6143
6144                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6145                         "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
6146                         "oddq=0x%08x; evenq=0x%08x;\n",
6147                          ahp->ah_CalSamples, i,
6148                          ahp->ah_totalAdcDcOffsetIOddPhase[i],
6149                          ahp->ah_totalAdcDcOffsetIEvenPhase[i],
6150                          ahp->ah_totalAdcDcOffsetQOddPhase[i],
6151                          ahp->ah_totalAdcDcOffsetQEvenPhase[i]);
6152         }
6153 }
6154
6155 static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains)
6156 {
6157         struct ath_hal_5416 *ahp = AH5416(ah);
6158         u32 powerMeasQ, powerMeasI, iqCorrMeas;
6159         u32 qCoffDenom, iCoffDenom;
6160         int32_t qCoff, iCoff;
6161         int iqCorrNeg, i;
6162
6163         for (i = 0; i < numChains; i++) {
6164                 powerMeasI = ahp->ah_totalPowerMeasI[i];
6165                 powerMeasQ = ahp->ah_totalPowerMeasQ[i];
6166                 iqCorrMeas = ahp->ah_totalIqCorrMeas[i];
6167
6168                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6169                          "Starting IQ Cal and Correction for Chain %d\n",
6170                          i);
6171
6172                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6173                          "Orignal: Chn %diq_corr_meas = 0x%08x\n",
6174                          i, ahp->ah_totalIqCorrMeas[i]);
6175
6176                 iqCorrNeg = 0;
6177
6178
6179                 if (iqCorrMeas > 0x80000000) {
6180                         iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
6181                         iqCorrNeg = 1;
6182                 }
6183
6184                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6185                          "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
6186                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6187                          "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
6188                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
6189                          iqCorrNeg);
6190
6191                 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
6192                 qCoffDenom = powerMeasQ / 64;
6193
6194                 if (powerMeasQ != 0) {
6195
6196                         iCoff = iqCorrMeas / iCoffDenom;
6197                         qCoff = powerMeasI / qCoffDenom - 64;
6198                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6199                                  "Chn %d iCoff = 0x%08x\n", i, iCoff);
6200                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6201                                  "Chn %d qCoff = 0x%08x\n", i, qCoff);
6202
6203
6204                         iCoff = iCoff & 0x3f;
6205                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6206                                  "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
6207                         if (iqCorrNeg == 0x0)
6208                                 iCoff = 0x40 - iCoff;
6209
6210                         if (qCoff > 15)
6211                                 qCoff = 15;
6212                         else if (qCoff <= -16)
6213                                 qCoff = 16;
6214
6215                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6216                                  "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
6217                                 i, iCoff, qCoff);
6218
6219                         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
6220                                       AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
6221                                       iCoff);
6222                         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
6223                                       AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
6224                                       qCoff);
6225                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6226                                 "IQ Cal and Correction done for Chain %d\n",
6227                                 i);
6228                 }
6229         }
6230
6231         REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
6232                     AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
6233 }
6234
6235 static void
6236 ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains)
6237 {
6238         struct ath_hal_5416 *ahp = AH5416(ah);
6239         u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset,
6240                 qEvenMeasOffset;
6241         u32 qGainMismatch, iGainMismatch, val, i;
6242
6243         for (i = 0; i < numChains; i++) {
6244                 iOddMeasOffset = ahp->ah_totalAdcIOddPhase[i];
6245                 iEvenMeasOffset = ahp->ah_totalAdcIEvenPhase[i];
6246                 qOddMeasOffset = ahp->ah_totalAdcQOddPhase[i];
6247                 qEvenMeasOffset = ahp->ah_totalAdcQEvenPhase[i];
6248
6249                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6250                          "Starting ADC Gain Cal for Chain %d\n", i);
6251
6252                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6253                          "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
6254                          iOddMeasOffset);
6255                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6256                          "Chn %d pwr_meas_even_i = 0x%08x\n", i,
6257                          iEvenMeasOffset);
6258                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6259                          "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
6260                          qOddMeasOffset);
6261                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6262                          "Chn %d pwr_meas_even_q = 0x%08x\n", i,
6263                          qEvenMeasOffset);
6264
6265                 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
6266                         iGainMismatch =
6267                                 ((iEvenMeasOffset * 32) /
6268                                  iOddMeasOffset) & 0x3f;
6269                         qGainMismatch =
6270                                 ((qOddMeasOffset * 32) /
6271                                  qEvenMeasOffset) & 0x3f;
6272
6273                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6274                                  "Chn %d gain_mismatch_i = 0x%08x\n", i,
6275                                  iGainMismatch);
6276                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6277                                  "Chn %d gain_mismatch_q = 0x%08x\n", i,
6278                                  qGainMismatch);
6279
6280                         val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
6281                         val &= 0xfffff000;
6282                         val |= (qGainMismatch) | (iGainMismatch << 6);
6283                         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
6284
6285                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6286                                  "ADC Gain Cal done for Chain %d\n", i);
6287                 }
6288         }
6289
6290         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
6291                   REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
6292                   AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
6293 }
6294
6295 static void
6296 ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains)
6297 {
6298         struct ath_hal_5416 *ahp = AH5416(ah);
6299         u32 iOddMeasOffset, iEvenMeasOffset, val, i;
6300         int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
6301         const struct hal_percal_data *calData =
6302                 ahp->ah_cal_list_curr->calData;
6303         u32 numSamples =
6304                 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
6305
6306         for (i = 0; i < numChains; i++) {
6307                 iOddMeasOffset = ahp->ah_totalAdcDcOffsetIOddPhase[i];
6308                 iEvenMeasOffset = ahp->ah_totalAdcDcOffsetIEvenPhase[i];
6309                 qOddMeasOffset = ahp->ah_totalAdcDcOffsetQOddPhase[i];
6310                 qEvenMeasOffset = ahp->ah_totalAdcDcOffsetQEvenPhase[i];
6311
6312                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6313                          "Starting ADC DC Offset Cal for Chain %d\n", i);
6314
6315                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6316                          "Chn %d pwr_meas_odd_i = %d\n", i,
6317                          iOddMeasOffset);
6318                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6319                          "Chn %d pwr_meas_even_i = %d\n", i,
6320                          iEvenMeasOffset);
6321                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6322                          "Chn %d pwr_meas_odd_q = %d\n", i,
6323                          qOddMeasOffset);
6324                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6325                          "Chn %d pwr_meas_even_q = %d\n", i,
6326                          qEvenMeasOffset);
6327
6328                 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
6329                                numSamples) & 0x1ff;
6330                 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
6331                                numSamples) & 0x1ff;
6332
6333                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6334                          "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
6335                          iDcMismatch);
6336                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6337                          "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
6338                          qDcMismatch);
6339
6340                 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
6341                 val &= 0xc0000fff;
6342                 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
6343                 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
6344
6345                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6346                          "ADC DC Offset Cal done for Chain %d\n", i);
6347         }
6348
6349         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
6350                   REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
6351                   AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
6352 }
6353
6354 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
6355 {
6356         struct ath_hal_5416 *ahp = AH5416(ah);
6357         struct ath9k_channel *chan = ah->ah_curchan;
6358
6359         ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
6360
6361         if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan,
6362                                  ath9k_regd_get_ctl(ah, chan),
6363                                  ath9k_regd_get_antenna_allowed(ah,
6364                                                                 chan),
6365                                  chan->maxRegTxPower * 2,
6366                                  min((u32) MAX_RATE_POWER,
6367                                      (u32) ah->ah_powerLimit)) != 0)
6368                 return false;
6369
6370         return true;
6371 }
6372
6373 void
6374 ath9k_hw_get_channel_centers(struct ath_hal *ah,
6375                              struct ath9k_channel *chan,
6376                              struct chan_centers *centers)
6377 {
6378         int8_t extoff;
6379         struct ath_hal_5416 *ahp = AH5416(ah);
6380
6381         if (!IS_CHAN_HT40(chan)) {
6382                 centers->ctl_center = centers->ext_center =
6383                         centers->synth_center = chan->channel;
6384                 return;
6385         }
6386
6387         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
6388             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
6389                 centers->synth_center =
6390                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
6391                 extoff = 1;
6392         } else {
6393                 centers->synth_center =
6394                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
6395                 extoff = -1;
6396         }
6397
6398         centers->ctl_center = centers->synth_center - (extoff *
6399                 HT40_CHANNEL_CENTER_SHIFT);
6400         centers->ext_center = centers->synth_center + (extoff *
6401                 ((ahp->
6402                 ah_extprotspacing
6403                 ==
6404                 ATH9K_HT_EXTPROTSPACING_20)
6405                 ?
6406                 HT40_CHANNEL_CENTER_SHIFT
6407                 : 15));
6408
6409 }
6410
6411 void
6412 ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
6413                         bool *isCalDone)
6414 {
6415         struct ath_hal_5416 *ahp = AH5416(ah);
6416         struct ath9k_channel *ichan =
6417                 ath9k_regd_check_channel(ah, chan);
6418         struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
6419
6420         *isCalDone = true;
6421
6422         if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
6423                 return;
6424
6425         if (currCal == NULL)
6426                 return;
6427
6428         if (ichan == NULL) {
6429                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6430                          "%s: invalid channel %u/0x%x; no mapping\n",
6431                          __func__, chan->channel, chan->channelFlags);
6432                 return;
6433         }
6434
6435
6436         if (currCal->calState != CAL_DONE) {
6437                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6438                          "%s: Calibration state incorrect, %d\n",
6439                          __func__, currCal->calState);
6440                 return;
6441         }
6442
6443
6444         if (!ath9k_hw_iscal_supported(ah, chan, currCal->calData->calType))
6445                 return;
6446
6447         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6448                  "%s: Resetting Cal %d state for channel %u/0x%x\n",
6449                  __func__, currCal->calData->calType, chan->channel,
6450                  chan->channelFlags);
6451
6452         ichan->CalValid &= ~currCal->calData->calType;
6453         currCal->calState = CAL_WAITING;
6454
6455         *isCalDone = false;
6456 }
6457
6458 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
6459 {
6460         struct ath_hal_5416 *ahp = AH5416(ah);
6461
6462         memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
6463 }
6464
6465 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
6466 {
6467         struct ath_hal_5416 *ahp = AH5416(ah);
6468
6469         memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
6470         return true;
6471 }
6472
6473 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
6474 {
6475         struct ath_hal_5416 *ahp = AH5416(ah);
6476
6477         memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
6478 }
6479
6480 bool
6481 ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
6482 {
6483         struct ath_hal_5416 *ahp = AH5416(ah);
6484
6485         memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
6486
6487         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
6488         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
6489
6490         return true;
6491 }
6492
6493 #ifdef CONFIG_ATH9K_RFKILL
6494 static void ath9k_enable_rfkill(struct ath_hal *ah)
6495 {
6496         struct ath_hal_5416 *ahp = AH5416(ah);
6497
6498         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
6499                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
6500
6501         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
6502                     AR_GPIO_INPUT_MUX2_RFSILENT);
6503
6504         ath9k_hw_cfg_gpio_input(ah, ahp->ah_gpioSelect);
6505         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
6506
6507         if (ahp->ah_gpioBit == ath9k_hw_gpio_get(ah, ahp->ah_gpioSelect)) {
6508
6509                 ath9k_hw_set_gpio_intr(ah, ahp->ah_gpioSelect,
6510                                        !ahp->ah_gpioBit);
6511         } else {
6512                 ath9k_hw_set_gpio_intr(ah, ahp->ah_gpioSelect,
6513                                        ahp->ah_gpioBit);
6514         }
6515 }
6516 #endif
6517
6518 void
6519 ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
6520                        u16 assocId)
6521 {
6522         struct ath_hal_5416 *ahp = AH5416(ah);
6523
6524         memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
6525         ahp->ah_assocId = assocId;
6526
6527         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
6528         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
6529                   ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
6530 }
6531
6532 u64 ath9k_hw_gettsf64(struct ath_hal *ah)
6533 {
6534         u64 tsf;
6535
6536         tsf = REG_READ(ah, AR_TSF_U32);
6537         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
6538         return tsf;
6539 }
6540
6541 void ath9k_hw_reset_tsf(struct ath_hal *ah)
6542 {
6543         int count;
6544
6545         count = 0;
6546         while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
6547                 count++;
6548                 if (count > 10) {
6549                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
6550                          "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n",
6551                                  __func__);
6552                         break;
6553                 }
6554                 udelay(10);
6555         }
6556         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
6557 }
6558
6559 u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
6560 {
6561         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
6562 }
6563
6564 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
6565 {
6566         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
6567 }
6568
6569 bool
6570 ath9k_hw_setantennaswitch(struct ath_hal *ah,
6571                           enum ath9k_ant_setting settings,
6572                           struct ath9k_channel *chan,
6573                           u8 *tx_chainmask,
6574                           u8 *rx_chainmask,
6575                           u8 *antenna_cfgd)
6576 {
6577         struct ath_hal_5416 *ahp = AH5416(ah);
6578         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
6579
6580         if (AR_SREV_9280(ah)) {
6581                 if (!tx_chainmask_cfg) {
6582
6583                         tx_chainmask_cfg = *tx_chainmask;
6584                         rx_chainmask_cfg = *rx_chainmask;
6585                 }
6586
6587                 switch (settings) {
6588                 case ATH9K_ANT_FIXED_A:
6589                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
6590                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
6591                         *antenna_cfgd = true;
6592                         break;
6593                 case ATH9K_ANT_FIXED_B:
6594                         if (ah->ah_caps.tx_chainmask >
6595                             ATH9K_ANTENNA1_CHAINMASK) {
6596                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
6597                         }
6598                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
6599                         *antenna_cfgd = true;
6600                         break;
6601                 case ATH9K_ANT_VARIABLE:
6602                         *tx_chainmask = tx_chainmask_cfg;
6603                         *rx_chainmask = rx_chainmask_cfg;
6604                         *antenna_cfgd = true;
6605                         break;
6606                 default:
6607                         break;
6608                 }
6609         } else {
6610                 ahp->ah_diversityControl = settings;
6611         }
6612
6613         return true;
6614 }
6615
6616 void ath9k_hw_setopmode(struct ath_hal *ah)
6617 {
6618         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
6619 }
6620
6621 bool
6622 ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
6623                        u32 capability, u32 *result)
6624 {
6625         struct ath_hal_5416 *ahp = AH5416(ah);
6626         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6627
6628         switch (type) {
6629         case ATH9K_CAP_CIPHER:
6630                 switch (capability) {
6631                 case ATH9K_CIPHER_AES_CCM:
6632                 case ATH9K_CIPHER_AES_OCB:
6633                 case ATH9K_CIPHER_TKIP:
6634                 case ATH9K_CIPHER_WEP:
6635                 case ATH9K_CIPHER_MIC:
6636                 case ATH9K_CIPHER_CLR:
6637                         return true;
6638                 default:
6639                         return false;
6640                 }
6641         case ATH9K_CAP_TKIP_MIC:
6642                 switch (capability) {
6643                 case 0:
6644                         return true;
6645                 case 1:
6646                         return (ahp->ah_staId1Defaults &
6647                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
6648                         false;
6649                 }
6650         case ATH9K_CAP_TKIP_SPLIT:
6651                 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
6652                         false : true;
6653         case ATH9K_CAP_WME_TKIPMIC:
6654                 return 0;
6655         case ATH9K_CAP_PHYCOUNTERS:
6656                 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
6657         case ATH9K_CAP_DIVERSITY:
6658                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
6659                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
6660                         true : false;
6661         case ATH9K_CAP_PHYDIAG:
6662                 return true;
6663         case ATH9K_CAP_MCAST_KEYSRCH:
6664                 switch (capability) {
6665                 case 0:
6666                         return true;
6667                 case 1:
6668                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
6669                                 return false;
6670                         } else {
6671                                 return (ahp->ah_staId1Defaults &
6672                                         AR_STA_ID1_MCAST_KSRCH) ? true :
6673                                         false;
6674                         }
6675                 }
6676                 return false;
6677         case ATH9K_CAP_TSF_ADJUST:
6678                 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
6679                         true : false;
6680         case ATH9K_CAP_RFSILENT:
6681                 if (capability == 3)
6682                         return false;
6683         case ATH9K_CAP_ANT_CFG_2GHZ:
6684                 *result = pCap->num_antcfg_2ghz;
6685                 return true;
6686         case ATH9K_CAP_ANT_CFG_5GHZ:
6687                 *result = pCap->num_antcfg_5ghz;
6688                 return true;
6689         case ATH9K_CAP_TXPOW:
6690                 switch (capability) {
6691                 case 0:
6692                         return 0;
6693                 case 1:
6694                         *result = ah->ah_powerLimit;
6695                         return 0;
6696                 case 2:
6697                         *result = ah->ah_maxPowerLevel;
6698                         return 0;
6699                 case 3:
6700                         *result = ah->ah_tpScale;
6701                         return 0;
6702                 }
6703                 return false;
6704         default:
6705                 return false;
6706         }
6707 }
6708
6709 int
6710 ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
6711 {
6712         struct ath_hal_5416 *ahp = AH5416(ah);
6713         struct ath9k_channel *chan = ah->ah_curchan;
6714         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6715         u16 ant_config;
6716         u32 halNumAntConfig;
6717
6718         halNumAntConfig =
6719                 IS_CHAN_2GHZ(chan) ? pCap->num_antcfg_2ghz : pCap->
6720                 num_antcfg_5ghz;
6721
6722         if (cfg < halNumAntConfig) {
6723                 if (!ath9k_hw_get_eeprom_antenna_cfg(ahp, chan,
6724                                                      cfg, &ant_config)) {
6725                         REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
6726                         return 0;
6727                 }
6728         }
6729
6730         return -EINVAL;
6731 }
6732
6733 bool ath9k_hw_intrpend(struct ath_hal *ah)
6734 {
6735         u32 host_isr;
6736
6737         if (AR_SREV_9100(ah))
6738                 return true;
6739
6740         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
6741         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
6742                 return true;
6743
6744         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
6745         if ((host_isr & AR_INTR_SYNC_DEFAULT)
6746             && (host_isr != AR_INTR_SPURIOUS))
6747                 return true;
6748
6749         return false;
6750 }
6751
6752 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
6753 {
6754         u32 isr = 0;
6755         u32 mask2 = 0;
6756         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6757         u32 sync_cause = 0;
6758         bool fatal_int = false;
6759
6760         if (!AR_SREV_9100(ah)) {
6761                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
6762                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
6763                             == AR_RTC_STATUS_ON) {
6764                                 isr = REG_READ(ah, AR_ISR);
6765                         }
6766                 }
6767
6768                 sync_cause =
6769                         REG_READ(ah,
6770                                  AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
6771
6772                 *masked = 0;
6773
6774                 if (!isr && !sync_cause)
6775                         return false;
6776         } else {
6777                 *masked = 0;
6778                 isr = REG_READ(ah, AR_ISR);
6779         }
6780
6781         if (isr) {
6782                 struct ath_hal_5416 *ahp = AH5416(ah);
6783
6784                 if (isr & AR_ISR_BCNMISC) {
6785                         u32 isr2;
6786                         isr2 = REG_READ(ah, AR_ISR_S2);
6787                         if (isr2 & AR_ISR_S2_TIM)
6788                                 mask2 |= ATH9K_INT_TIM;
6789                         if (isr2 & AR_ISR_S2_DTIM)
6790                                 mask2 |= ATH9K_INT_DTIM;
6791                         if (isr2 & AR_ISR_S2_DTIMSYNC)
6792                                 mask2 |= ATH9K_INT_DTIMSYNC;
6793                         if (isr2 & (AR_ISR_S2_CABEND))
6794                                 mask2 |= ATH9K_INT_CABEND;
6795                         if (isr2 & AR_ISR_S2_GTT)
6796                                 mask2 |= ATH9K_INT_GTT;
6797                         if (isr2 & AR_ISR_S2_CST)
6798                                 mask2 |= ATH9K_INT_CST;
6799                 }
6800
6801                 isr = REG_READ(ah, AR_ISR_RAC);
6802                 if (isr == 0xffffffff) {
6803                         *masked = 0;
6804                         return false;
6805                 }
6806
6807                 *masked = isr & ATH9K_INT_COMMON;
6808
6809                 if (ahp->ah_intrMitigation) {
6810
6811                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
6812                                 *masked |= ATH9K_INT_RX;
6813                 }
6814
6815                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
6816                         *masked |= ATH9K_INT_RX;
6817                 if (isr &
6818                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
6819                      AR_ISR_TXEOL)) {
6820                         u32 s0_s, s1_s;
6821
6822                         *masked |= ATH9K_INT_TX;
6823
6824                         s0_s = REG_READ(ah, AR_ISR_S0_S);
6825                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
6826                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
6827
6828                         s1_s = REG_READ(ah, AR_ISR_S1_S);
6829                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
6830                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
6831                 }
6832
6833                 if (isr & AR_ISR_RXORN) {
6834                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
6835                                  "%s: receive FIFO overrun interrupt\n",
6836                                  __func__);
6837                 }
6838
6839                 if (!AR_SREV_9100(ah)) {
6840                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
6841                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
6842                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
6843                                         *masked |= ATH9K_INT_TIM_TIMER;
6844                         }
6845                 }
6846
6847                 *masked |= mask2;
6848         }
6849         if (AR_SREV_9100(ah))
6850                 return true;
6851         if (sync_cause) {
6852                 fatal_int =
6853                         (sync_cause &
6854                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
6855                         ? true : false;
6856
6857                 if (fatal_int) {
6858                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
6859                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
6860                                          "%s: received PCI FATAL interrupt\n",
6861                                          __func__);
6862                         }
6863                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
6864                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
6865                                          "%s: received PCI PERR interrupt\n",
6866                                          __func__);
6867                         }
6868                 }
6869                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
6870                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
6871                                  "%s: AR_INTR_SYNC_RADM_CPL_TIMEOUT\n",
6872                                  __func__);
6873                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
6874                         REG_WRITE(ah, AR_RC, 0);
6875                         *masked |= ATH9K_INT_FATAL;
6876                 }
6877                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
6878                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
6879                                  "%s: AR_INTR_SYNC_LOCAL_TIMEOUT\n",
6880                                  __func__);
6881                 }
6882
6883                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
6884                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
6885         }
6886         return true;
6887 }
6888
6889 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
6890 {
6891         return AH5416(ah)->ah_maskReg;
6892 }
6893
6894 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
6895 {
6896         struct ath_hal_5416 *ahp = AH5416(ah);
6897         u32 omask = ahp->ah_maskReg;
6898         u32 mask, mask2;
6899         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6900
6901         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: 0x%x => 0x%x\n", __func__,
6902                  omask, ints);
6903
6904         if (omask & ATH9K_INT_GLOBAL) {
6905                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: disable IER\n",
6906                          __func__);
6907                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
6908                 (void) REG_READ(ah, AR_IER);
6909                 if (!AR_SREV_9100(ah)) {
6910                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
6911                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
6912
6913                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
6914                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
6915                 }
6916         }
6917
6918         mask = ints & ATH9K_INT_COMMON;
6919         mask2 = 0;
6920
6921         if (ints & ATH9K_INT_TX) {
6922                 if (ahp->ah_txOkInterruptMask)
6923                         mask |= AR_IMR_TXOK;
6924                 if (ahp->ah_txDescInterruptMask)
6925                         mask |= AR_IMR_TXDESC;
6926                 if (ahp->ah_txErrInterruptMask)
6927                         mask |= AR_IMR_TXERR;
6928                 if (ahp->ah_txEolInterruptMask)
6929                         mask |= AR_IMR_TXEOL;
6930         }
6931         if (ints & ATH9K_INT_RX) {
6932                 mask |= AR_IMR_RXERR;
6933                 if (ahp->ah_intrMitigation)
6934                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
6935                 else
6936                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
6937                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
6938                         mask |= AR_IMR_GENTMR;
6939         }
6940
6941         if (ints & (ATH9K_INT_BMISC)) {
6942                 mask |= AR_IMR_BCNMISC;
6943                 if (ints & ATH9K_INT_TIM)
6944                         mask2 |= AR_IMR_S2_TIM;
6945                 if (ints & ATH9K_INT_DTIM)
6946                         mask2 |= AR_IMR_S2_DTIM;
6947                 if (ints & ATH9K_INT_DTIMSYNC)
6948                         mask2 |= AR_IMR_S2_DTIMSYNC;
6949                 if (ints & ATH9K_INT_CABEND)
6950                         mask2 |= (AR_IMR_S2_CABEND);
6951         }
6952
6953         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
6954                 mask |= AR_IMR_BCNMISC;
6955                 if (ints & ATH9K_INT_GTT)
6956                         mask2 |= AR_IMR_S2_GTT;
6957                 if (ints & ATH9K_INT_CST)
6958                         mask2 |= AR_IMR_S2_CST;
6959         }
6960
6961         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: new IMR 0x%x\n", __func__,
6962                  mask);
6963         REG_WRITE(ah, AR_IMR, mask);
6964         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
6965                                            AR_IMR_S2_DTIM |
6966                                            AR_IMR_S2_DTIMSYNC |
6967                                            AR_IMR_S2_CABEND |
6968                                            AR_IMR_S2_CABTO |
6969                                            AR_IMR_S2_TSFOOR |
6970                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
6971         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
6972         ahp->ah_maskReg = ints;
6973
6974         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
6975                 if (ints & ATH9K_INT_TIM_TIMER)
6976                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
6977                 else
6978                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
6979         }
6980
6981         if (ints & ATH9K_INT_GLOBAL) {
6982                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: enable IER\n",
6983                          __func__);
6984                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
6985                 if (!AR_SREV_9100(ah)) {
6986                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
6987                                   AR_INTR_MAC_IRQ);
6988                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
6989
6990
6991                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
6992                                   AR_INTR_SYNC_DEFAULT);
6993                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
6994                                   AR_INTR_SYNC_DEFAULT);
6995                 }
6996                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
6997                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
6998         }
6999
7000         return omask;
7001 }
7002
7003 void
7004 ath9k_hw_beaconinit(struct ath_hal *ah,
7005                     u32 next_beacon, u32 beacon_period)
7006 {
7007         struct ath_hal_5416 *ahp = AH5416(ah);
7008         int flags = 0;
7009
7010         ahp->ah_beaconInterval = beacon_period;
7011
7012         switch (ah->ah_opmode) {
7013         case ATH9K_M_STA:
7014         case ATH9K_M_MONITOR:
7015                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
7016                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
7017                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
7018                 flags |= AR_TBTT_TIMER_EN;
7019                 break;
7020         case ATH9K_M_IBSS:
7021                 REG_SET_BIT(ah, AR_TXCFG,
7022                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
7023                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
7024                           TU_TO_USEC(next_beacon +
7025                                      (ahp->ah_atimWindow ? ahp->
7026                                       ah_atimWindow : 1)));
7027                 flags |= AR_NDP_TIMER_EN;
7028         case ATH9K_M_HOSTAP:
7029                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
7030                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
7031                           TU_TO_USEC(next_beacon -
7032                                      ah->ah_config.
7033                                      dma_beacon_response_time));
7034                 REG_WRITE(ah, AR_NEXT_SWBA,
7035                           TU_TO_USEC(next_beacon -
7036                                      ah->ah_config.
7037                                      sw_beacon_response_time));
7038                 flags |=
7039                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
7040                 break;
7041         }
7042
7043         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
7044         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
7045         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
7046         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
7047
7048         beacon_period &= ~ATH9K_BEACON_ENA;
7049         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
7050                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
7051                 ath9k_hw_reset_tsf(ah);
7052         }
7053
7054         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
7055 }
7056
7057 void
7058 ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
7059                                const struct ath9k_beacon_state *bs)
7060 {
7061         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
7062         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7063
7064         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
7065
7066         REG_WRITE(ah, AR_BEACON_PERIOD,
7067                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
7068         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
7069                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
7070
7071         REG_RMW_FIELD(ah, AR_RSSI_THR,
7072                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
7073
7074         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
7075
7076         if (bs->bs_sleepduration > beaconintval)
7077                 beaconintval = bs->bs_sleepduration;
7078
7079         dtimperiod = bs->bs_dtimperiod;
7080         if (bs->bs_sleepduration > dtimperiod)
7081                 dtimperiod = bs->bs_sleepduration;
7082
7083         if (beaconintval == dtimperiod)
7084                 nextTbtt = bs->bs_nextdtim;
7085         else
7086                 nextTbtt = bs->bs_nexttbtt;
7087
7088         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next DTIM %d\n", __func__,
7089                  bs->bs_nextdtim);
7090         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next beacon %d\n", __func__,
7091                  nextTbtt);
7092         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: beacon period %d\n", __func__,
7093                  beaconintval);
7094         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: DTIM period %d\n", __func__,
7095                  dtimperiod);
7096
7097         REG_WRITE(ah, AR_NEXT_DTIM,
7098                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
7099         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
7100
7101         REG_WRITE(ah, AR_SLEEP1,
7102                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
7103                   | AR_SLEEP1_ASSUME_DTIM);
7104
7105         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
7106                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
7107         else
7108                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
7109
7110         REG_WRITE(ah, AR_SLEEP2,
7111                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
7112
7113         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
7114         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
7115
7116         REG_SET_BIT(ah, AR_TIMER_MODE,
7117                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
7118                     AR_DTIM_TIMER_EN);
7119
7120 }
7121
7122 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
7123 {
7124         if (entry < ah->ah_caps.keycache_size) {
7125                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
7126                 if (val & AR_KEYTABLE_VALID)
7127                         return true;
7128         }
7129         return false;
7130 }
7131
7132 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
7133 {
7134         u32 keyType;
7135
7136         if (entry >= ah->ah_caps.keycache_size) {
7137                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7138                          "%s: entry %u out of range\n", __func__, entry);
7139                 return false;
7140         }
7141         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
7142
7143         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
7144         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
7145         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
7146         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
7147         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
7148         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
7149         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
7150         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
7151
7152         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
7153                 u16 micentry = entry + 64;
7154
7155                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
7156                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
7157                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
7158                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
7159
7160         }
7161
7162         if (ah->ah_curchan == NULL)
7163                 return true;
7164
7165         return true;
7166 }
7167
7168 bool
7169 ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry,
7170                    const u8 *mac)
7171 {
7172         u32 macHi, macLo;
7173
7174         if (entry >= ah->ah_caps.keycache_size) {
7175                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7176                          "%s: entry %u out of range\n", __func__, entry);
7177                 return false;
7178         }
7179
7180         if (mac != NULL) {
7181                 macHi = (mac[5] << 8) | mac[4];
7182                 macLo = (mac[3] << 24) | (mac[2] << 16)
7183                         | (mac[1] << 8) | mac[0];
7184                 macLo >>= 1;
7185                 macLo |= (macHi & 1) << 31;
7186                 macHi >>= 1;
7187         } else {
7188                 macLo = macHi = 0;
7189         }
7190         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
7191         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
7192
7193         return true;
7194 }
7195
7196 bool
7197 ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
7198                             const struct ath9k_keyval *k,
7199                             const u8 *mac, int xorKey)
7200 {
7201         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7202         u32 key0, key1, key2, key3, key4;
7203         u32 keyType;
7204         u32 xorMask = xorKey ?
7205                 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
7206                  | ATH9K_KEY_XOR) : 0;
7207         struct ath_hal_5416 *ahp = AH5416(ah);
7208
7209         if (entry >= pCap->keycache_size) {
7210                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7211                          "%s: entry %u out of range\n", __func__, entry);
7212                 return false;
7213         }
7214         switch (k->kv_type) {
7215         case ATH9K_CIPHER_AES_OCB:
7216                 keyType = AR_KEYTABLE_TYPE_AES;
7217                 break;
7218         case ATH9K_CIPHER_AES_CCM:
7219                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
7220                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7221                                  "%s: AES-CCM not supported by "
7222                                  "mac rev 0x%x\n", __func__,
7223                                  ah->ah_macRev);
7224                         return false;
7225                 }
7226                 keyType = AR_KEYTABLE_TYPE_CCM;
7227                 break;
7228         case ATH9K_CIPHER_TKIP:
7229                 keyType = AR_KEYTABLE_TYPE_TKIP;
7230                 if (ATH9K_IS_MIC_ENABLED(ah)
7231                     && entry + 64 >= pCap->keycache_size) {
7232                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7233                                  "%s: entry %u inappropriate for TKIP\n",
7234                                  __func__, entry);
7235                         return false;
7236                 }
7237                 break;
7238         case ATH9K_CIPHER_WEP:
7239                 if (k->kv_len < LEN_WEP40) {
7240                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7241                                  "%s: WEP key length %u too small\n",
7242                                  __func__, k->kv_len);
7243                         return false;
7244                 }
7245                 if (k->kv_len <= LEN_WEP40)
7246                         keyType = AR_KEYTABLE_TYPE_40;
7247                 else if (k->kv_len <= LEN_WEP104)
7248                         keyType = AR_KEYTABLE_TYPE_104;
7249                 else
7250                         keyType = AR_KEYTABLE_TYPE_128;
7251                 break;
7252         case ATH9K_CIPHER_CLR:
7253                 keyType = AR_KEYTABLE_TYPE_CLR;
7254                 break;
7255         default:
7256                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7257                          "%s: cipher %u not supported\n", __func__,
7258                          k->kv_type);
7259                 return false;
7260         }
7261
7262         key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
7263         key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
7264         key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
7265         key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
7266         key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
7267         if (k->kv_len <= LEN_WEP104)
7268                 key4 &= 0xff;
7269
7270         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
7271                 u16 micentry = entry + 64;
7272
7273                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
7274                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
7275                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
7276                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
7277                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
7278                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
7279                 (void) ath9k_hw_keysetmac(ah, entry, mac);
7280
7281                 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
7282                         u32 mic0, mic1, mic2, mic3, mic4;
7283
7284                         mic0 = get_unaligned_le32(k->kv_mic + 0);
7285                         mic2 = get_unaligned_le32(k->kv_mic + 4);
7286                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
7287                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
7288                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
7289                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
7290                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
7291                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
7292                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
7293                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
7294                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
7295                                   AR_KEYTABLE_TYPE_CLR);
7296
7297                 } else {
7298                         u32 mic0, mic2;
7299
7300                         mic0 = get_unaligned_le32(k->kv_mic + 0);
7301                         mic2 = get_unaligned_le32(k->kv_mic + 4);
7302                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
7303                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
7304                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
7305                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
7306                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
7307                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
7308                                   AR_KEYTABLE_TYPE_CLR);
7309                 }
7310                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
7311                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
7312                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
7313                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
7314         } else {
7315                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
7316                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
7317                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
7318                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
7319                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
7320                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
7321
7322                 (void) ath9k_hw_keysetmac(ah, entry, mac);
7323         }
7324
7325         if (ah->ah_curchan == NULL)
7326                 return true;
7327
7328         return true;
7329 }
7330
7331 bool
7332 ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel)
7333 {
7334         struct ath_hal_5416 *ahp = AH5416(ah);
7335         u32 txcfg, curLevel, newLevel;
7336         enum ath9k_int omask;
7337
7338         if (ah->ah_txTrigLevel >= MAX_TX_FIFO_THRESHOLD)
7339                 return false;
7340
7341         omask = ath9k_hw_set_interrupts(ah,
7342                                         ahp->ah_maskReg & ~ATH9K_INT_GLOBAL);
7343
7344         txcfg = REG_READ(ah, AR_TXCFG);
7345         curLevel = MS(txcfg, AR_FTRIG);
7346         newLevel = curLevel;
7347         if (bIncTrigLevel) {
7348                 if (curLevel < MAX_TX_FIFO_THRESHOLD)
7349                         newLevel++;
7350         } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
7351                 newLevel--;
7352         if (newLevel != curLevel)
7353                 REG_WRITE(ah, AR_TXCFG,
7354                           (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
7355
7356         ath9k_hw_set_interrupts(ah, omask);
7357
7358         ah->ah_txTrigLevel = newLevel;
7359
7360         return newLevel != curLevel;
7361 }
7362
7363 bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
7364                             const struct ath9k_tx_queue_info *qinfo)
7365 {
7366         u32 cw;
7367         struct ath_hal_5416 *ahp = AH5416(ah);
7368         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7369         struct ath9k_tx_queue_info *qi;
7370
7371         if (q >= pCap->total_queues) {
7372                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
7373                          __func__, q);
7374                 return false;
7375         }
7376
7377         qi = &ahp->ah_txq[q];
7378         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
7379                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n",
7380                          __func__);
7381                 return false;
7382         }
7383
7384         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %p\n", __func__, qi);
7385
7386         qi->tqi_ver = qinfo->tqi_ver;
7387         qi->tqi_subtype = qinfo->tqi_subtype;
7388         qi->tqi_qflags = qinfo->tqi_qflags;
7389         qi->tqi_priority = qinfo->tqi_priority;
7390         if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
7391                 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
7392         else
7393                 qi->tqi_aifs = INIT_AIFS;
7394         if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
7395                 cw = min(qinfo->tqi_cwmin, 1024U);
7396                 qi->tqi_cwmin = 1;
7397                 while (qi->tqi_cwmin < cw)
7398                         qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
7399         } else
7400                 qi->tqi_cwmin = qinfo->tqi_cwmin;
7401         if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
7402                 cw = min(qinfo->tqi_cwmax, 1024U);
7403                 qi->tqi_cwmax = 1;
7404                 while (qi->tqi_cwmax < cw)
7405                         qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
7406         } else
7407                 qi->tqi_cwmax = INIT_CWMAX;
7408
7409         if (qinfo->tqi_shretry != 0)
7410                 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
7411         else
7412                 qi->tqi_shretry = INIT_SH_RETRY;
7413         if (qinfo->tqi_lgretry != 0)
7414                 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
7415         else
7416                 qi->tqi_lgretry = INIT_LG_RETRY;
7417         qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
7418         qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
7419         qi->tqi_burstTime = qinfo->tqi_burstTime;
7420         qi->tqi_readyTime = qinfo->tqi_readyTime;
7421
7422         switch (qinfo->tqi_subtype) {
7423         case ATH9K_WME_UPSD:
7424                 if (qi->tqi_type == ATH9K_TX_QUEUE_DATA)
7425                         qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS;
7426                 break;
7427         default:
7428                 break;
7429         }
7430         return true;
7431 }
7432
7433 bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
7434                             struct ath9k_tx_queue_info *qinfo)
7435 {
7436         struct ath_hal_5416 *ahp = AH5416(ah);
7437         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7438         struct ath9k_tx_queue_info *qi;
7439
7440         if (q >= pCap->total_queues) {
7441                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
7442                          __func__, q);
7443                 return false;
7444         }
7445
7446         qi = &ahp->ah_txq[q];
7447         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
7448                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n",
7449                          __func__);
7450                 return false;
7451         }
7452
7453         qinfo->tqi_qflags = qi->tqi_qflags;
7454         qinfo->tqi_ver = qi->tqi_ver;
7455         qinfo->tqi_subtype = qi->tqi_subtype;
7456         qinfo->tqi_qflags = qi->tqi_qflags;
7457         qinfo->tqi_priority = qi->tqi_priority;
7458         qinfo->tqi_aifs = qi->tqi_aifs;
7459         qinfo->tqi_cwmin = qi->tqi_cwmin;
7460         qinfo->tqi_cwmax = qi->tqi_cwmax;
7461         qinfo->tqi_shretry = qi->tqi_shretry;
7462         qinfo->tqi_lgretry = qi->tqi_lgretry;
7463         qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
7464         qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
7465         qinfo->tqi_burstTime = qi->tqi_burstTime;
7466         qinfo->tqi_readyTime = qi->tqi_readyTime;
7467
7468         return true;
7469 }
7470
7471 int
7472 ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
7473                       const struct ath9k_tx_queue_info *qinfo)
7474 {
7475         struct ath_hal_5416 *ahp = AH5416(ah);
7476         struct ath9k_tx_queue_info *qi;
7477         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7478         int q;
7479
7480         switch (type) {
7481         case ATH9K_TX_QUEUE_BEACON:
7482                 q = pCap->total_queues - 1;
7483                 break;
7484         case ATH9K_TX_QUEUE_CAB:
7485                 q = pCap->total_queues - 2;
7486                 break;
7487         case ATH9K_TX_QUEUE_PSPOLL:
7488                 q = 1;
7489                 break;
7490         case ATH9K_TX_QUEUE_UAPSD:
7491                 q = pCap->total_queues - 3;
7492                 break;
7493         case ATH9K_TX_QUEUE_DATA:
7494                 for (q = 0; q < pCap->total_queues; q++)
7495                         if (ahp->ah_txq[q].tqi_type ==
7496                             ATH9K_TX_QUEUE_INACTIVE)
7497                                 break;
7498                 if (q == pCap->total_queues) {
7499                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
7500                                  "%s: no available tx queue\n", __func__);
7501                         return -1;
7502                 }
7503                 break;
7504         default:
7505                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: bad tx queue type %u\n",
7506                          __func__, type);
7507                 return -1;
7508         }
7509
7510         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q);
7511
7512         qi = &ahp->ah_txq[q];
7513         if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
7514                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
7515                          "%s: tx queue %u already active\n", __func__, q);
7516                 return -1;
7517         }
7518         memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
7519         qi->tqi_type = type;
7520         if (qinfo == NULL) {
7521                 qi->tqi_qflags =
7522                         TXQ_FLAG_TXOKINT_ENABLE
7523                         | TXQ_FLAG_TXERRINT_ENABLE
7524                         | TXQ_FLAG_TXDESCINT_ENABLE | TXQ_FLAG_TXURNINT_ENABLE;
7525                 qi->tqi_aifs = INIT_AIFS;
7526                 qi->tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
7527                 qi->tqi_cwmax = INIT_CWMAX;
7528                 qi->tqi_shretry = INIT_SH_RETRY;
7529                 qi->tqi_lgretry = INIT_LG_RETRY;
7530                 qi->tqi_physCompBuf = 0;
7531         } else {
7532                 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
7533                 (void) ath9k_hw_set_txq_props(ah, q, qinfo);
7534         }
7535
7536         return q;
7537 }
7538
7539 static void
7540 ath9k_hw_set_txq_interrupts(struct ath_hal *ah,
7541                             struct ath9k_tx_queue_info *qi)
7542 {
7543         struct ath_hal_5416 *ahp = AH5416(ah);
7544
7545         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
7546                  "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
7547                  __func__, ahp->ah_txOkInterruptMask,
7548                  ahp->ah_txErrInterruptMask, ahp->ah_txDescInterruptMask,
7549                  ahp->ah_txEolInterruptMask, ahp->ah_txUrnInterruptMask);
7550
7551         REG_WRITE(ah, AR_IMR_S0,
7552                   SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK)
7553                   | SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC));
7554         REG_WRITE(ah, AR_IMR_S1,
7555                   SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR)
7556                   | SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL));
7557         REG_RMW_FIELD(ah, AR_IMR_S2,
7558                       AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask);
7559 }
7560
7561 bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q)
7562 {
7563         struct ath_hal_5416 *ahp = AH5416(ah);
7564         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7565         struct ath9k_tx_queue_info *qi;
7566
7567         if (q >= pCap->total_queues) {
7568                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
7569                          __func__, q);
7570                 return false;
7571         }
7572         qi = &ahp->ah_txq[q];
7573         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
7574                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n",
7575                          __func__, q);
7576                 return false;
7577         }
7578
7579         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: release queue %u\n",
7580                 __func__, q);
7581
7582         qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
7583         ahp->ah_txOkInterruptMask &= ~(1 << q);
7584         ahp->ah_txErrInterruptMask &= ~(1 << q);
7585         ahp->ah_txDescInterruptMask &= ~(1 << q);
7586         ahp->ah_txEolInterruptMask &= ~(1 << q);
7587         ahp->ah_txUrnInterruptMask &= ~(1 << q);
7588         ath9k_hw_set_txq_interrupts(ah, qi);
7589
7590         return true;
7591 }
7592
7593 bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q)
7594 {
7595         struct ath_hal_5416 *ahp = AH5416(ah);
7596         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7597         struct ath9k_channel *chan = ah->ah_curchan;
7598         struct ath9k_tx_queue_info *qi;
7599         u32 cwMin, chanCwMin, value;
7600
7601         if (q >= pCap->total_queues) {
7602                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
7603                          __func__, q);
7604                 return false;
7605         }
7606         qi = &ahp->ah_txq[q];
7607         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
7608                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n",
7609                          __func__, q);
7610                 return true;
7611         }
7612
7613         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: reset queue %u\n", __func__, q);
7614
7615         if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
7616                 if (chan && IS_CHAN_B(chan))
7617                         chanCwMin = INIT_CWMIN_11B;
7618                 else
7619                         chanCwMin = INIT_CWMIN;
7620
7621                 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
7622         } else
7623                 cwMin = qi->tqi_cwmin;
7624
7625         REG_WRITE(ah, AR_DLCL_IFS(q), SM(cwMin, AR_D_LCL_IFS_CWMIN)
7626                   | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
7627                   | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
7628
7629         REG_WRITE(ah, AR_DRETRY_LIMIT(q),
7630                   SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH)
7631                   | SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG)
7632                   | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
7633
7634         REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
7635         REG_WRITE(ah, AR_DMISC(q),
7636                   AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
7637
7638         if (qi->tqi_cbrPeriod) {
7639                 REG_WRITE(ah, AR_QCBRCFG(q),
7640                           SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL)
7641                           | SM(qi->tqi_cbrOverflowLimit,
7642                                AR_Q_CBRCFG_OVF_THRESH));
7643                 REG_WRITE(ah, AR_QMISC(q),
7644                           REG_READ(ah,
7645                                    AR_QMISC(q)) | AR_Q_MISC_FSP_CBR | (qi->
7646                                         tqi_cbrOverflowLimit
7647                                         ?
7648                                         AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN
7649                                         :
7650                                         0));
7651         }
7652         if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
7653                 REG_WRITE(ah, AR_QRDYTIMECFG(q),
7654                           SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
7655                           AR_Q_RDYTIMECFG_EN);
7656         }
7657
7658         REG_WRITE(ah, AR_DCHNTIME(q),
7659                   SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
7660                   (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
7661
7662         if (qi->tqi_burstTime
7663             && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) {
7664                 REG_WRITE(ah, AR_QMISC(q),
7665                           REG_READ(ah,
7666                                    AR_QMISC(q)) |
7667                           AR_Q_MISC_RDYTIME_EXP_POLICY);
7668
7669         }
7670
7671         if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) {
7672                 REG_WRITE(ah, AR_DMISC(q),
7673                           REG_READ(ah, AR_DMISC(q)) |
7674                           AR_D_MISC_POST_FR_BKOFF_DIS);
7675         }
7676         if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
7677                 REG_WRITE(ah, AR_DMISC(q),
7678                           REG_READ(ah, AR_DMISC(q)) |
7679                           AR_D_MISC_FRAG_BKOFF_EN);
7680         }
7681         switch (qi->tqi_type) {
7682         case ATH9K_TX_QUEUE_BEACON:
7683                 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
7684                           | AR_Q_MISC_FSP_DBA_GATED
7685                           | AR_Q_MISC_BEACON_USE
7686                           | AR_Q_MISC_CBR_INCR_DIS1);
7687
7688                 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7689                           | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
7690                              AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
7691                           | AR_D_MISC_BEACON_USE
7692                           | AR_D_MISC_POST_FR_BKOFF_DIS);
7693                 break;
7694         case ATH9K_TX_QUEUE_CAB:
7695                 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
7696                           | AR_Q_MISC_FSP_DBA_GATED
7697                           | AR_Q_MISC_CBR_INCR_DIS1
7698                           | AR_Q_MISC_CBR_INCR_DIS0);
7699                 value = (qi->tqi_readyTime
7700                          - (ah->ah_config.sw_beacon_response_time -
7701                             ah->ah_config.dma_beacon_response_time)
7702                          -
7703                          ah->ah_config.additional_swba_backoff) *
7704                         1024;
7705                 REG_WRITE(ah, AR_QRDYTIMECFG(q),
7706                           value | AR_Q_RDYTIMECFG_EN);
7707                 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7708                           | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
7709                              AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
7710                 break;
7711         case ATH9K_TX_QUEUE_PSPOLL:
7712                 REG_WRITE(ah, AR_QMISC(q),
7713                           REG_READ(ah,
7714                                    AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
7715                 break;
7716         case ATH9K_TX_QUEUE_UAPSD:
7717                 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7718                           | AR_D_MISC_POST_FR_BKOFF_DIS);
7719                 break;
7720         default:
7721                 break;
7722         }
7723
7724         if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
7725                 REG_WRITE(ah, AR_DMISC(q),
7726                           REG_READ(ah, AR_DMISC(q)) |
7727                           SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
7728                              AR_D_MISC_ARB_LOCKOUT_CNTRL) |
7729                           AR_D_MISC_POST_FR_BKOFF_DIS);
7730         }
7731
7732         if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
7733                 ahp->ah_txOkInterruptMask |= 1 << q;
7734         else
7735                 ahp->ah_txOkInterruptMask &= ~(1 << q);
7736         if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
7737                 ahp->ah_txErrInterruptMask |= 1 << q;
7738         else
7739                 ahp->ah_txErrInterruptMask &= ~(1 << q);
7740         if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
7741                 ahp->ah_txDescInterruptMask |= 1 << q;
7742         else
7743                 ahp->ah_txDescInterruptMask &= ~(1 << q);
7744         if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
7745                 ahp->ah_txEolInterruptMask |= 1 << q;
7746         else
7747                 ahp->ah_txEolInterruptMask &= ~(1 << q);
7748         if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
7749                 ahp->ah_txUrnInterruptMask |= 1 << q;
7750         else
7751                 ahp->ah_txUrnInterruptMask &= ~(1 << q);
7752         ath9k_hw_set_txq_interrupts(ah, qi);
7753
7754         return true;
7755 }
7756
7757 void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs)
7758 {
7759         struct ath_hal_5416 *ahp = AH5416(ah);
7760         *txqs &= ahp->ah_intrTxqs;
7761         ahp->ah_intrTxqs &= ~(*txqs);
7762 }
7763
7764 bool
7765 ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
7766                     u32 segLen, bool firstSeg,
7767                     bool lastSeg, const struct ath_desc *ds0)
7768 {
7769         struct ar5416_desc *ads = AR5416DESC(ds);
7770
7771         if (firstSeg) {
7772                 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
7773         } else if (lastSeg) {
7774                 ads->ds_ctl0 = 0;
7775                 ads->ds_ctl1 = segLen;
7776                 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
7777                 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
7778         } else {
7779                 ads->ds_ctl0 = 0;
7780                 ads->ds_ctl1 = segLen | AR_TxMore;
7781                 ads->ds_ctl2 = 0;
7782                 ads->ds_ctl3 = 0;
7783         }
7784         ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
7785         ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
7786         ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
7787         ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
7788         ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
7789         return true;
7790 }
7791
7792 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds)
7793 {
7794         struct ar5416_desc *ads = AR5416DESC(ds);
7795
7796         ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
7797         ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
7798         ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
7799         ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
7800         ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
7801 }
7802
7803 int
7804 ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds)
7805 {
7806         struct ar5416_desc *ads = AR5416DESC(ds);
7807
7808         if ((ads->ds_txstatus9 & AR_TxDone) == 0)
7809                 return -EINPROGRESS;
7810
7811         ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
7812         ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
7813         ds->ds_txstat.ts_status = 0;
7814         ds->ds_txstat.ts_flags = 0;
7815
7816         if (ads->ds_txstatus1 & AR_ExcessiveRetries)
7817                 ds->ds_txstat.ts_status |= ATH9K_TXERR_XRETRY;
7818         if (ads->ds_txstatus1 & AR_Filtered)
7819                 ds->ds_txstat.ts_status |= ATH9K_TXERR_FILT;
7820         if (ads->ds_txstatus1 & AR_FIFOUnderrun)
7821                 ds->ds_txstat.ts_status |= ATH9K_TXERR_FIFO;
7822         if (ads->ds_txstatus9 & AR_TxOpExceeded)
7823                 ds->ds_txstat.ts_status |= ATH9K_TXERR_XTXOP;
7824         if (ads->ds_txstatus1 & AR_TxTimerExpired)
7825                 ds->ds_txstat.ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
7826
7827         if (ads->ds_txstatus1 & AR_DescCfgErr)
7828                 ds->ds_txstat.ts_flags |= ATH9K_TX_DESC_CFG_ERR;
7829         if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
7830                 ds->ds_txstat.ts_flags |= ATH9K_TX_DATA_UNDERRUN;
7831                 ath9k_hw_updatetxtriglevel(ah, true);
7832         }
7833         if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
7834                 ds->ds_txstat.ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
7835                 ath9k_hw_updatetxtriglevel(ah, true);
7836         }
7837         if (ads->ds_txstatus0 & AR_TxBaStatus) {
7838                 ds->ds_txstat.ts_flags |= ATH9K_TX_BA;
7839                 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
7840                 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
7841         }
7842
7843         ds->ds_txstat.ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
7844         switch (ds->ds_txstat.ts_rateindex) {
7845         case 0:
7846                 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
7847                 break;
7848         case 1:
7849                 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
7850                 break;
7851         case 2:
7852                 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
7853                 break;
7854         case 3:
7855                 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
7856                 break;
7857         }
7858
7859         ds->ds_txstat.ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
7860         ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
7861         ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
7862         ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
7863         ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
7864         ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
7865         ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
7866         ds->ds_txstat.evm0 = ads->AR_TxEVM0;
7867         ds->ds_txstat.evm1 = ads->AR_TxEVM1;
7868         ds->ds_txstat.evm2 = ads->AR_TxEVM2;
7869         ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
7870         ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
7871         ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
7872         ds->ds_txstat.ts_antenna = 1;
7873
7874         return 0;
7875 }
7876
7877 void
7878 ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
7879                        u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
7880                        u32 keyIx, enum ath9k_key_type keyType, u32 flags)
7881 {
7882         struct ar5416_desc *ads = AR5416DESC(ds);
7883         struct ath_hal_5416 *ahp = AH5416(ah);
7884
7885         txPower += ahp->ah_txPowerIndexOffset;
7886         if (txPower > 63)
7887                 txPower = 63;
7888
7889         ads->ds_ctl0 = (pktLen & AR_FrameLen)
7890                 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
7891                 | SM(txPower, AR_XmitPower)
7892                 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
7893                 | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
7894                 | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
7895                 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
7896
7897         ads->ds_ctl1 =
7898                 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
7899                 | SM(type, AR_FrameType)
7900                 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
7901                 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
7902                 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
7903
7904         ads->ds_ctl6 = SM(keyType, AR_EncrType);
7905
7906         if (AR_SREV_9285(ah)) {
7907
7908                 ads->ds_ctl8 = 0;
7909                 ads->ds_ctl9 = 0;
7910                 ads->ds_ctl10 = 0;
7911                 ads->ds_ctl11 = 0;
7912         }
7913 }
7914
7915 void
7916 ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
7917                              struct ath_desc *lastds,
7918                              u32 durUpdateEn, u32 rtsctsRate,
7919                              u32 rtsctsDuration,
7920                              struct ath9k_11n_rate_series series[],
7921                              u32 nseries, u32 flags)
7922 {
7923         struct ar5416_desc *ads = AR5416DESC(ds);
7924         struct ar5416_desc *last_ads = AR5416DESC(lastds);
7925         u32 ds_ctl0;
7926
7927         (void) nseries;
7928         (void) rtsctsDuration;
7929
7930         if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
7931                 ds_ctl0 = ads->ds_ctl0;
7932
7933                 if (flags & ATH9K_TXDESC_RTSENA) {
7934                         ds_ctl0 &= ~AR_CTSEnable;
7935                         ds_ctl0 |= AR_RTSEnable;
7936                 } else {
7937                         ds_ctl0 &= ~AR_RTSEnable;
7938                         ds_ctl0 |= AR_CTSEnable;
7939                 }
7940
7941                 ads->ds_ctl0 = ds_ctl0;
7942         } else {
7943                 ads->ds_ctl0 =
7944                         (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
7945         }
7946
7947         ads->ds_ctl2 = set11nTries(series, 0)
7948                 | set11nTries(series, 1)
7949                 | set11nTries(series, 2)
7950                 | set11nTries(series, 3)
7951                 | (durUpdateEn ? AR_DurUpdateEna : 0)
7952                 | SM(0, AR_BurstDur);
7953
7954         ads->ds_ctl3 = set11nRate(series, 0)
7955                 | set11nRate(series, 1)
7956                 | set11nRate(series, 2)
7957                 | set11nRate(series, 3);
7958
7959         ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
7960                 | set11nPktDurRTSCTS(series, 1);
7961
7962         ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
7963                 | set11nPktDurRTSCTS(series, 3);
7964
7965         ads->ds_ctl7 = set11nRateFlags(series, 0)
7966                 | set11nRateFlags(series, 1)
7967                 | set11nRateFlags(series, 2)
7968                 | set11nRateFlags(series, 3)
7969                 | SM(rtsctsRate, AR_RTSCTSRate);
7970         last_ads->ds_ctl2 = ads->ds_ctl2;
7971         last_ads->ds_ctl3 = ads->ds_ctl3;
7972 }
7973
7974 void
7975 ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
7976                            u32 aggrLen)
7977 {
7978         struct ar5416_desc *ads = AR5416DESC(ds);
7979
7980         ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
7981
7982         ads->ds_ctl6 &= ~AR_AggrLen;
7983         ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
7984 }
7985
7986 void
7987 ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
7988                             u32 numDelims)
7989 {
7990         struct ar5416_desc *ads = AR5416DESC(ds);
7991         unsigned int ctl6;
7992
7993         ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
7994
7995         ctl6 = ads->ds_ctl6;
7996         ctl6 &= ~AR_PadDelim;
7997         ctl6 |= SM(numDelims, AR_PadDelim);
7998         ads->ds_ctl6 = ctl6;
7999 }
8000
8001 void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds)
8002 {
8003         struct ar5416_desc *ads = AR5416DESC(ds);
8004
8005         ads->ds_ctl1 |= AR_IsAggr;
8006         ads->ds_ctl1 &= ~AR_MoreAggr;
8007         ads->ds_ctl6 &= ~AR_PadDelim;
8008 }
8009
8010 void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds)
8011 {
8012         struct ar5416_desc *ads = AR5416DESC(ds);
8013
8014         ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
8015 }
8016
8017 void
8018 ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,
8019                               u32 burstDuration)
8020 {
8021         struct ar5416_desc *ads = AR5416DESC(ds);
8022
8023         ads->ds_ctl2 &= ~AR_BurstDur;
8024         ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
8025 }
8026
8027 void
8028 ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds,
8029                                 u32 vmf)
8030 {
8031         struct ar5416_desc *ads = AR5416DESC(ds);
8032
8033         if (vmf)
8034                 ads->ds_ctl0 |= AR_VirtMoreFrag;
8035         else
8036                 ads->ds_ctl0 &= ~AR_VirtMoreFrag;
8037 }
8038
8039 void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp)
8040 {
8041         REG_WRITE(ah, AR_RXDP, rxdp);
8042 }
8043
8044 void ath9k_hw_rxena(struct ath_hal *ah)
8045 {
8046         REG_WRITE(ah, AR_CR, AR_CR_RXE);
8047 }
8048
8049 bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set)
8050 {
8051         if (set) {
8052
8053                 REG_SET_BIT(ah, AR_DIAG_SW,
8054                             (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
8055
8056                 if (!ath9k_hw_wait
8057                     (ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 0)) {
8058                         u32 reg;
8059
8060                         REG_CLR_BIT(ah, AR_DIAG_SW,
8061                                     (AR_DIAG_RX_DIS |
8062                                      AR_DIAG_RX_ABORT));
8063
8064                         reg = REG_READ(ah, AR_OBS_BUS_1);
8065                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
8066                                 "%s: rx failed to go idle in 10 ms RXSM=0x%x\n",
8067                                 __func__, reg);
8068
8069                         return false;
8070                 }
8071         } else {
8072                 REG_CLR_BIT(ah, AR_DIAG_SW,
8073                             (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
8074         }
8075
8076         return true;
8077 }
8078
8079 void
8080 ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0,
8081                         u32 filter1)
8082 {
8083         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
8084         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
8085 }
8086
8087 bool
8088 ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
8089                      u32 size, u32 flags)
8090 {
8091         struct ar5416_desc *ads = AR5416DESC(ds);
8092         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
8093
8094         ads->ds_ctl1 = size & AR_BufLen;
8095         if (flags & ATH9K_RXDESC_INTREQ)
8096                 ads->ds_ctl1 |= AR_RxIntrReq;
8097
8098         ads->ds_rxstatus8 &= ~AR_RxDone;
8099         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
8100                 memset(&(ads->u), 0, sizeof(ads->u));
8101         return true;
8102 }
8103
8104 int
8105 ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
8106                     u32 pa, struct ath_desc *nds, u64 tsf)
8107 {
8108         struct ar5416_desc ads;
8109         struct ar5416_desc *adsp = AR5416DESC(ds);
8110
8111         if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
8112                 return -EINPROGRESS;
8113
8114         ads.u.rx = adsp->u.rx;
8115
8116         ds->ds_rxstat.rs_status = 0;
8117         ds->ds_rxstat.rs_flags = 0;
8118
8119         ds->ds_rxstat.rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
8120         ds->ds_rxstat.rs_tstamp = ads.AR_RcvTimestamp;
8121
8122         ds->ds_rxstat.rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
8123         ds->ds_rxstat.rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00);
8124         ds->ds_rxstat.rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01);
8125         ds->ds_rxstat.rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02);
8126         ds->ds_rxstat.rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10);
8127         ds->ds_rxstat.rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11);
8128         ds->ds_rxstat.rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12);
8129         if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
8130                 ds->ds_rxstat.rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
8131         else
8132                 ds->ds_rxstat.rs_keyix = ATH9K_RXKEYIX_INVALID;
8133
8134         ds->ds_rxstat.rs_rate = RXSTATUS_RATE(ah, (&ads));
8135         ds->ds_rxstat.rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
8136
8137         ds->ds_rxstat.rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
8138         ds->ds_rxstat.rs_moreaggr =
8139                 (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
8140         ds->ds_rxstat.rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
8141         ds->ds_rxstat.rs_flags =
8142                 (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
8143         ds->ds_rxstat.rs_flags |=
8144                 (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;
8145
8146         if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
8147                 ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
8148         if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
8149                 ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_POST;
8150         if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
8151                 ds->ds_rxstat.rs_flags |= ATH9K_RX_DECRYPT_BUSY;
8152
8153         if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
8154
8155                 if (ads.ds_rxstatus8 & AR_CRCErr)
8156                         ds->ds_rxstat.rs_status |= ATH9K_RXERR_CRC;
8157                 else if (ads.ds_rxstatus8 & AR_PHYErr) {
8158                         u32 phyerr;
8159
8160                         ds->ds_rxstat.rs_status |= ATH9K_RXERR_PHY;
8161                         phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
8162                         ds->ds_rxstat.rs_phyerr = phyerr;
8163                 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
8164                         ds->ds_rxstat.rs_status |= ATH9K_RXERR_DECRYPT;
8165                 else if (ads.ds_rxstatus8 & AR_MichaelErr)
8166                         ds->ds_rxstat.rs_status |= ATH9K_RXERR_MIC;
8167         }
8168
8169         return 0;
8170 }
8171
8172 static void ath9k_hw_setup_rate_table(struct ath_hal *ah,
8173                                       struct ath9k_rate_table *rt)
8174 {
8175         int i;
8176
8177         if (rt->rateCodeToIndex[0] != 0)
8178                 return;
8179         for (i = 0; i < 256; i++)
8180                 rt->rateCodeToIndex[i] = (u8) -1;
8181         for (i = 0; i < rt->rateCount; i++) {
8182                 u8 code = rt->info[i].rateCode;
8183                 u8 cix = rt->info[i].controlRate;
8184
8185                 rt->rateCodeToIndex[code] = i;
8186                 rt->rateCodeToIndex[code | rt->info[i].shortPreamble] = i;
8187
8188                 rt->info[i].lpAckDuration =
8189                         ath9k_hw_computetxtime(ah, rt,
8190                                                WLAN_CTRL_FRAME_SIZE,
8191                                                cix,
8192                                                false);
8193                 rt->info[i].spAckDuration =
8194                         ath9k_hw_computetxtime(ah, rt,
8195                                                WLAN_CTRL_FRAME_SIZE,
8196                                                cix,
8197                                                true);
8198         }
8199 }
8200
8201 const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
8202                                                    u32 mode)
8203 {
8204         struct ath9k_rate_table *rt;
8205         switch (mode) {
8206         case ATH9K_MODE_11A:
8207                 rt = &ar5416_11a_table;
8208                 break;
8209         case ATH9K_MODE_11B:
8210                 rt = &ar5416_11b_table;
8211                 break;
8212         case ATH9K_MODE_11G:
8213                 rt = &ar5416_11g_table;
8214                 break;
8215         case ATH9K_MODE_11NG_HT20:
8216         case ATH9K_MODE_11NG_HT40PLUS:
8217         case ATH9K_MODE_11NG_HT40MINUS:
8218                 rt = &ar5416_11ng_table;
8219                 break;
8220         case ATH9K_MODE_11NA_HT20:
8221         case ATH9K_MODE_11NA_HT40PLUS:
8222         case ATH9K_MODE_11NA_HT40MINUS:
8223                 rt = &ar5416_11na_table;
8224                 break;
8225         default:
8226                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, "%s: invalid mode 0x%x\n",
8227                          __func__, mode);
8228                 return NULL;
8229         }
8230         ath9k_hw_setup_rate_table(ah, rt);
8231         return rt;
8232 }
8233
8234 static const char *ath9k_hw_devname(u16 devid)
8235 {
8236         switch (devid) {
8237         case AR5416_DEVID_PCI:
8238         case AR5416_DEVID_PCIE:
8239                 return "Atheros 5416";
8240         case AR9160_DEVID_PCI:
8241                 return "Atheros 9160";
8242         case AR9280_DEVID_PCI:
8243         case AR9280_DEVID_PCIE:
8244                 return "Atheros 9280";
8245         }
8246         return NULL;
8247 }
8248
8249 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
8250 {
8251         return vendorid == ATHEROS_VENDOR_ID ?
8252                 ath9k_hw_devname(devid) : NULL;
8253 }
8254
8255 struct ath_hal *ath9k_hw_attach(u16 devid,
8256                                 struct ath_softc *sc,
8257                                 void __iomem *mem,
8258                                 int *error)
8259 {
8260         struct ath_hal *ah = NULL;
8261
8262         switch (devid) {
8263         case AR5416_DEVID_PCI:
8264         case AR5416_DEVID_PCIE:
8265         case AR9160_DEVID_PCI:
8266         case AR9280_DEVID_PCI:
8267         case AR9280_DEVID_PCIE:
8268                 ah = ath9k_hw_do_attach(devid, sc, mem, error);
8269                 break;
8270         default:
8271                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
8272                          "devid=0x%x not supported.\n", devid);
8273                 ah = NULL;
8274                 *error = -ENXIO;
8275                 break;
8276         }
8277
8278         return ah;
8279 }
8280
8281 u16
8282 ath9k_hw_computetxtime(struct ath_hal *ah,
8283                        const struct ath9k_rate_table *rates,
8284                        u32 frameLen, u16 rateix,
8285                        bool shortPreamble)
8286 {
8287         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
8288         u32 kbps;
8289
8290         kbps = rates->info[rateix].rateKbps;
8291
8292         if (kbps == 0)
8293                 return 0;
8294         switch (rates->info[rateix].phy) {
8295
8296         case PHY_CCK:
8297                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
8298                 if (shortPreamble && rates->info[rateix].shortPreamble)
8299                         phyTime >>= 1;
8300                 numBits = frameLen << 3;
8301                 txTime = CCK_SIFS_TIME + phyTime
8302                         + ((numBits * 1000) / kbps);
8303                 break;
8304         case PHY_OFDM:
8305                 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
8306                         bitsPerSymbol =
8307                                 (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
8308
8309                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
8310                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
8311                         txTime = OFDM_SIFS_TIME_QUARTER
8312                                 + OFDM_PREAMBLE_TIME_QUARTER
8313                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
8314                 } else if (ah->ah_curchan &&
8315                            IS_CHAN_HALF_RATE(ah->ah_curchan)) {
8316                         bitsPerSymbol =
8317                                 (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
8318
8319                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
8320                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
8321                         txTime = OFDM_SIFS_TIME_HALF +
8322                                 OFDM_PREAMBLE_TIME_HALF
8323                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
8324                 } else {
8325                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
8326
8327                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
8328                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
8329                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
8330                                 + (numSymbols * OFDM_SYMBOL_TIME);
8331                 }
8332                 break;
8333
8334         default:
8335                 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
8336                          "%s: unknown phy %u (rate ix %u)\n", __func__,
8337                          rates->info[rateix].phy, rateix);
8338                 txTime = 0;
8339                 break;
8340         }
8341         return txTime;
8342 }
8343
8344 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
8345 {
8346         if (flags & CHANNEL_2GHZ) {
8347                 if (freq == 2484)
8348                         return 14;
8349                 if (freq < 2484)
8350                         return (freq - 2407) / 5;
8351                 else
8352                         return 15 + ((freq - 2512) / 20);
8353         } else if (flags & CHANNEL_5GHZ) {
8354                 if (ath9k_regd_is_public_safety_sku(ah) &&
8355                     IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
8356                         return ((freq * 10) +
8357                                 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
8358                 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
8359                         return (freq - 4000) / 5;
8360                 } else {
8361                         return (freq - 5000) / 5;
8362                 }
8363         } else {
8364                 if (freq == 2484)
8365                         return 14;
8366                 if (freq < 2484)
8367                         return (freq - 2407) / 5;
8368                 if (freq < 5000) {
8369                         if (ath9k_regd_is_public_safety_sku(ah)
8370                             && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
8371                                 return ((freq * 10) +
8372                                         (((freq % 5) ==
8373                                           2) ? 5 : 0) - 49400) / 5;
8374                         } else if (freq > 4900) {
8375                                 return (freq - 4000) / 5;
8376                         } else {
8377                                 return 15 + ((freq - 2512) / 20);
8378                         }
8379                 }
8380                 return (freq - 5000) / 5;
8381         }
8382 }
8383
8384 int16_t
8385 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan)
8386 {
8387         struct ath9k_channel *ichan;
8388
8389         ichan = ath9k_regd_check_channel(ah, chan);
8390         if (ichan == NULL) {
8391                 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
8392                          "%s: invalid channel %u/0x%x; no mapping\n",
8393                          __func__, chan->channel, chan->channelFlags);
8394                 return 0;
8395         }
8396         if (ichan->rawNoiseFloor == 0) {
8397                 enum wireless_mode mode = ath9k_hw_chan2wmode(ah, chan);
8398                 return NOISE_FLOOR[mode];
8399         } else
8400                 return ichan->rawNoiseFloor;
8401 }
8402
8403 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
8404 {
8405         struct ath_hal_5416 *ahp = AH5416(ah);
8406
8407         if (setting)
8408                 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
8409         else
8410                 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
8411         return true;
8412 }
8413
8414 bool ath9k_hw_phycounters(struct ath_hal *ah)
8415 {
8416         struct ath_hal_5416 *ahp = AH5416(ah);
8417
8418         return ahp->ah_hasHwPhyCounters ? true : false;
8419 }
8420
8421 u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q)
8422 {
8423         return REG_READ(ah, AR_QTXDP(q));
8424 }
8425
8426 bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q,
8427                        u32 txdp)
8428 {
8429         REG_WRITE(ah, AR_QTXDP(q), txdp);
8430
8431         return true;
8432 }
8433
8434 bool ath9k_hw_txstart(struct ath_hal *ah, u32 q)
8435 {
8436         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q);
8437
8438         REG_WRITE(ah, AR_Q_TXE, 1 << q);
8439
8440         return true;
8441 }
8442
8443 u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q)
8444 {
8445         u32 npend;
8446
8447         npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
8448         if (npend == 0) {
8449
8450                 if (REG_READ(ah, AR_Q_TXE) & (1 << q))
8451                         npend = 1;
8452         }
8453         return npend;
8454 }
8455
8456 bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q)
8457 {
8458         u32 wait;
8459
8460         REG_WRITE(ah, AR_Q_TXD, 1 << q);
8461
8462         for (wait = 1000; wait != 0; wait--) {
8463                 if (ath9k_hw_numtxpending(ah, q) == 0)
8464                         break;
8465                 udelay(100);
8466         }
8467
8468         if (ath9k_hw_numtxpending(ah, q)) {
8469                 u32 tsfLow, j;
8470
8471                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
8472                          "%s: Num of pending TX Frames %d on Q %d\n",
8473                          __func__, ath9k_hw_numtxpending(ah, q), q);
8474
8475                 for (j = 0; j < 2; j++) {
8476                         tsfLow = REG_READ(ah, AR_TSF_L32);
8477                         REG_WRITE(ah, AR_QUIET2,
8478                                   SM(10, AR_QUIET2_QUIET_DUR));
8479                         REG_WRITE(ah, AR_QUIET_PERIOD, 100);
8480                         REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
8481                         REG_SET_BIT(ah, AR_TIMER_MODE,
8482                                        AR_QUIET_TIMER_EN);
8483
8484                         if ((REG_READ(ah, AR_TSF_L32) >> 10) ==
8485                             (tsfLow >> 10)) {
8486                                 break;
8487                         }
8488                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
8489                                 "%s: TSF have moved while trying to set "
8490                                 "quiet time TSF: 0x%08x\n",
8491                                 __func__, tsfLow);
8492                 }
8493
8494                 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
8495
8496                 udelay(200);
8497                 REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
8498
8499                 wait = 1000;
8500
8501                 while (ath9k_hw_numtxpending(ah, q)) {
8502                         if ((--wait) == 0) {
8503                                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
8504                                         "%s: Failed to stop Tx DMA in 100 "
8505                                         "msec after killing last frame\n",
8506                                         __func__);
8507                                 break;
8508                         }
8509                         udelay(100);
8510                 }
8511
8512                 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
8513         }
8514
8515         REG_WRITE(ah, AR_Q_TXD, 0);
8516         return wait != 0;
8517 }