drm/i915 more registers for S3 (DSPCLK_GATE_D, CACHE_MODE_0, MI_ARB_STATE)
[linux-2.6] / drivers / char / drm / i915_drv.c
1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2  */
3 /*
4  *
5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the
10  * "Software"), to deal in the Software without restriction, including
11  * without limitation the rights to use, copy, modify, merge, publish,
12  * distribute, sub license, and/or sell copies of the Software, and to
13  * permit persons to whom the Software is furnished to do so, subject to
14  * the following conditions:
15  *
16  * The above copyright notice and this permission notice (including the
17  * next paragraph) shall be included in all copies or substantial portions
18  * of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27  *
28  */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drm.h"
33 #include "i915_drv.h"
34
35 #include "drm_pciids.h"
36
37 static struct pci_device_id pciidlist[] = {
38         i915_PCI_IDS
39 };
40
41 enum pipe {
42     PIPE_A = 0,
43     PIPE_B,
44 };
45
46 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
47 {
48         struct drm_i915_private *dev_priv = dev->dev_private;
49
50         if (pipe == PIPE_A)
51                 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
52         else
53                 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
54 }
55
56 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
57 {
58         struct drm_i915_private *dev_priv = dev->dev_private;
59         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
60         u32 *array;
61         int i;
62
63         if (!i915_pipe_enabled(dev, pipe))
64                 return;
65
66         if (pipe == PIPE_A)
67                 array = dev_priv->save_palette_a;
68         else
69                 array = dev_priv->save_palette_b;
70
71         for(i = 0; i < 256; i++)
72                 array[i] = I915_READ(reg + (i << 2));
73 }
74
75 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
76 {
77         struct drm_i915_private *dev_priv = dev->dev_private;
78         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
79         u32 *array;
80         int i;
81
82         if (!i915_pipe_enabled(dev, pipe))
83                 return;
84
85         if (pipe == PIPE_A)
86                 array = dev_priv->save_palette_a;
87         else
88                 array = dev_priv->save_palette_b;
89
90         for(i = 0; i < 256; i++)
91                 I915_WRITE(reg + (i << 2), array[i]);
92 }
93
94 static u8 i915_read_indexed(u16 index_port, u16 data_port, u8 reg)
95 {
96         outb(reg, index_port);
97         return inb(data_port);
98 }
99
100 static u8 i915_read_ar(u16 st01, u8 reg, u16 palette_enable)
101 {
102         inb(st01);
103         outb(palette_enable | reg, VGA_AR_INDEX);
104         return inb(VGA_AR_DATA_READ);
105 }
106
107 static void i915_write_ar(u8 st01, u8 reg, u8 val, u16 palette_enable)
108 {
109         inb(st01);
110         outb(palette_enable | reg, VGA_AR_INDEX);
111         outb(val, VGA_AR_DATA_WRITE);
112 }
113
114 static void i915_write_indexed(u16 index_port, u16 data_port, u8 reg, u8 val)
115 {
116         outb(reg, index_port);
117         outb(val, data_port);
118 }
119
120 static void i915_save_vga(struct drm_device *dev)
121 {
122         struct drm_i915_private *dev_priv = dev->dev_private;
123         int i;
124         u16 cr_index, cr_data, st01;
125
126         /* VGA color palette registers */
127         dev_priv->saveDACMASK = inb(VGA_DACMASK);
128         /* DACCRX automatically increments during read */
129         outb(0, VGA_DACRX);
130         /* Read 3 bytes of color data from each index */
131         for (i = 0; i < 256 * 3; i++)
132                 dev_priv->saveDACDATA[i] = inb(VGA_DACDATA);
133
134         /* MSR bits */
135         dev_priv->saveMSR = inb(VGA_MSR_READ);
136         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
137                 cr_index = VGA_CR_INDEX_CGA;
138                 cr_data = VGA_CR_DATA_CGA;
139                 st01 = VGA_ST01_CGA;
140         } else {
141                 cr_index = VGA_CR_INDEX_MDA;
142                 cr_data = VGA_CR_DATA_MDA;
143                 st01 = VGA_ST01_MDA;
144         }
145
146         /* CRT controller regs */
147         i915_write_indexed(cr_index, cr_data, 0x11,
148                            i915_read_indexed(cr_index, cr_data, 0x11) &
149                            (~0x80));
150         for (i = 0; i < 0x24; i++)
151                 dev_priv->saveCR[i] =
152                         i915_read_indexed(cr_index, cr_data, i);
153         /* Make sure we don't turn off CR group 0 writes */
154         dev_priv->saveCR[0x11] &= ~0x80;
155
156         /* Attribute controller registers */
157         inb(st01);
158         dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX);
159         for (i = 0; i < 20; i++)
160                 dev_priv->saveAR[i] = i915_read_ar(st01, i, 0);
161         inb(st01);
162         outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX);
163
164         /* Graphics controller registers */
165         for (i = 0; i < 9; i++)
166                 dev_priv->saveGR[i] =
167                         i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, i);
168
169         dev_priv->saveGR[0x10] =
170                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10);
171         dev_priv->saveGR[0x11] =
172                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11);
173         dev_priv->saveGR[0x18] =
174                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18);
175
176         /* Sequencer registers */
177         for (i = 0; i < 8; i++)
178                 dev_priv->saveSR[i] =
179                         i915_read_indexed(VGA_SR_INDEX, VGA_SR_DATA, i);
180 }
181
182 static void i915_restore_vga(struct drm_device *dev)
183 {
184         struct drm_i915_private *dev_priv = dev->dev_private;
185         int i;
186         u16 cr_index, cr_data, st01;
187
188         /* MSR bits */
189         outb(dev_priv->saveMSR, VGA_MSR_WRITE);
190         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
191                 cr_index = VGA_CR_INDEX_CGA;
192                 cr_data = VGA_CR_DATA_CGA;
193                 st01 = VGA_ST01_CGA;
194         } else {
195                 cr_index = VGA_CR_INDEX_MDA;
196                 cr_data = VGA_CR_DATA_MDA;
197                 st01 = VGA_ST01_MDA;
198         }
199
200         /* Sequencer registers, don't write SR07 */
201         for (i = 0; i < 7; i++)
202                 i915_write_indexed(VGA_SR_INDEX, VGA_SR_DATA, i,
203                                    dev_priv->saveSR[i]);
204
205         /* CRT controller regs */
206         /* Enable CR group 0 writes */
207         i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
208         for (i = 0; i < 0x24; i++)
209                 i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]);
210
211         /* Graphics controller regs */
212         for (i = 0; i < 9; i++)
213                 i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, i,
214                                    dev_priv->saveGR[i]);
215
216         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10,
217                            dev_priv->saveGR[0x10]);
218         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11,
219                            dev_priv->saveGR[0x11]);
220         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18,
221                            dev_priv->saveGR[0x18]);
222
223         /* Attribute controller registers */
224         for (i = 0; i < 20; i++)
225                 i915_write_ar(st01, i, dev_priv->saveAR[i], 0);
226         inb(st01); /* switch back to index mode */
227         outb(dev_priv->saveAR_INDEX | 0x20, VGA_AR_INDEX);
228
229         /* VGA color palette registers */
230         outb(dev_priv->saveDACMASK, VGA_DACMASK);
231         /* DACCRX automatically increments during read */
232         outb(0, VGA_DACWX);
233         /* Read 3 bytes of color data from each index */
234         for (i = 0; i < 256 * 3; i++)
235                 outb(dev_priv->saveDACDATA[i], VGA_DACDATA);
236
237 }
238
239 static int i915_suspend(struct drm_device *dev)
240 {
241         struct drm_i915_private *dev_priv = dev->dev_private;
242         int i;
243
244         if (!dev || !dev_priv) {
245                 printk(KERN_ERR "dev: %p, dev_priv: %p\n", dev, dev_priv);
246                 printk(KERN_ERR "DRM not initialized, aborting suspend.\n");
247                 return -ENODEV;
248         }
249
250         pci_save_state(dev->pdev);
251         pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
252
253         /* Pipe & plane A info */
254         dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
255         dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
256         dev_priv->saveFPA0 = I915_READ(FPA0);
257         dev_priv->saveFPA1 = I915_READ(FPA1);
258         dev_priv->saveDPLL_A = I915_READ(DPLL_A);
259         if (IS_I965G(dev))
260                 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
261         dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
262         dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
263         dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
264         dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
265         dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
266         dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
267         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
268
269         dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
270         dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
271         dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
272         dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
273         dev_priv->saveDSPABASE = I915_READ(DSPABASE);
274         if (IS_I965G(dev)) {
275                 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
276                 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
277         }
278         i915_save_palette(dev, PIPE_A);
279         dev_priv->savePIPEASTAT = I915_READ(I915REG_PIPEASTAT);
280
281         /* Pipe & plane B info */
282         dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
283         dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
284         dev_priv->saveFPB0 = I915_READ(FPB0);
285         dev_priv->saveFPB1 = I915_READ(FPB1);
286         dev_priv->saveDPLL_B = I915_READ(DPLL_B);
287         if (IS_I965G(dev))
288                 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
289         dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
290         dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
291         dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
292         dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
293         dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
294         dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
295         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
296
297         dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
298         dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
299         dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
300         dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
301         dev_priv->saveDSPBBASE = I915_READ(DSPBBASE);
302         if (IS_I965GM(dev) || IS_IGD_GM(dev)) {
303                 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
304                 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
305         }
306         i915_save_palette(dev, PIPE_B);
307         dev_priv->savePIPEBSTAT = I915_READ(I915REG_PIPEBSTAT);
308
309         /* CRT state */
310         dev_priv->saveADPA = I915_READ(ADPA);
311
312         /* LVDS state */
313         dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
314         dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
315         dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
316         if (IS_I965G(dev))
317                 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
318         if (IS_MOBILE(dev) && !IS_I830(dev))
319                 dev_priv->saveLVDS = I915_READ(LVDS);
320         if (!IS_I830(dev) && !IS_845G(dev))
321                 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
322         dev_priv->saveLVDSPP_ON = I915_READ(LVDSPP_ON);
323         dev_priv->saveLVDSPP_OFF = I915_READ(LVDSPP_OFF);
324         dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE);
325
326         /* FIXME: save TV & SDVO state */
327
328         /* FBC state */
329         dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
330         dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
331         dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
332         dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
333
334         /* Interrupt state */
335         dev_priv->saveIIR = I915_READ(I915REG_INT_IDENTITY_R);
336         dev_priv->saveIER = I915_READ(I915REG_INT_ENABLE_R);
337         dev_priv->saveIMR = I915_READ(I915REG_INT_MASK_R);
338
339         /* VGA state */
340         dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
341         dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
342         dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV);
343         dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
344
345         /* Clock gating state */
346         dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
347
348         /* Cache mode state */
349         dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
350
351         /* Memory Arbitration state */
352         dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
353
354         /* Scratch space */
355         for (i = 0; i < 16; i++) {
356                 dev_priv->saveSWF0[i] = I915_READ(SWF0 + (i << 2));
357                 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
358         }
359         for (i = 0; i < 3; i++)
360                 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
361
362         i915_save_vga(dev);
363
364         /* Shut down the device */
365         pci_disable_device(dev->pdev);
366         pci_set_power_state(dev->pdev, PCI_D3hot);
367
368         return 0;
369 }
370
371 static int i915_resume(struct drm_device *dev)
372 {
373         struct drm_i915_private *dev_priv = dev->dev_private;
374         int i;
375
376         pci_set_power_state(dev->pdev, PCI_D0);
377         pci_restore_state(dev->pdev);
378         if (pci_enable_device(dev->pdev))
379                 return -1;
380
381         pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
382
383         /* Pipe & plane A info */
384         /* Prime the clock */
385         if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
386                 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
387                            ~DPLL_VCO_ENABLE);
388                 udelay(150);
389         }
390         I915_WRITE(FPA0, dev_priv->saveFPA0);
391         I915_WRITE(FPA1, dev_priv->saveFPA1);
392         /* Actually enable it */
393         I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
394         udelay(150);
395         if (IS_I965G(dev))
396                 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
397         udelay(150);
398
399         /* Restore mode */
400         I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
401         I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
402         I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
403         I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
404         I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
405         I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
406         I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
407
408         /* Restore plane info */
409         I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
410         I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
411         I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
412         I915_WRITE(DSPABASE, dev_priv->saveDSPABASE);
413         I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
414         if (IS_I965G(dev)) {
415                 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
416                 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
417         }
418
419         I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
420
421         i915_restore_palette(dev, PIPE_A);
422         /* Enable the plane */
423         I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
424         I915_WRITE(DSPABASE, I915_READ(DSPABASE));
425
426         /* Pipe & plane B info */
427         if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
428                 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
429                            ~DPLL_VCO_ENABLE);
430                 udelay(150);
431         }
432         I915_WRITE(FPB0, dev_priv->saveFPB0);
433         I915_WRITE(FPB1, dev_priv->saveFPB1);
434         /* Actually enable it */
435         I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
436         udelay(150);
437         if (IS_I965G(dev))
438                 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
439         udelay(150);
440
441         /* Restore mode */
442         I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
443         I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
444         I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
445         I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
446         I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
447         I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
448         I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
449
450         /* Restore plane info */
451         I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
452         I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
453         I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
454         I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE);
455         I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
456         if (IS_I965G(dev)) {
457                 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
458                 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
459         }
460
461         I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
462
463         i915_restore_palette(dev, PIPE_B);
464         /* Enable the plane */
465         I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
466         I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));
467
468         /* CRT state */
469         I915_WRITE(ADPA, dev_priv->saveADPA);
470
471         /* LVDS state */
472         if (IS_I965G(dev))
473                 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
474         if (IS_MOBILE(dev) && !IS_I830(dev))
475                 I915_WRITE(LVDS, dev_priv->saveLVDS);
476         if (!IS_I830(dev) && !IS_845G(dev))
477                 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
478
479         I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
480         I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
481         I915_WRITE(LVDSPP_ON, dev_priv->saveLVDSPP_ON);
482         I915_WRITE(LVDSPP_OFF, dev_priv->saveLVDSPP_OFF);
483         I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE);
484         I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
485
486         /* FIXME: restore TV & SDVO state */
487
488         /* FBC info */
489         I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
490         I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
491         I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
492         I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
493
494         /* VGA state */
495         I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
496         I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0);
497         I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1);
498         I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV);
499         udelay(150);
500
501         /* Clock gating state */
502         I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
503
504         /* Cache mode state */
505         I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
506
507         /* Memory arbitration state */
508         I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
509
510         for (i = 0; i < 16; i++) {
511                 I915_WRITE(SWF0 + (i << 2), dev_priv->saveSWF0[i]);
512                 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
513         }
514         for (i = 0; i < 3; i++)
515                 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
516
517         i915_restore_vga(dev);
518
519         return 0;
520 }
521
522 static struct drm_driver driver = {
523         /* don't use mtrr's here, the Xserver or user space app should
524          * deal with them for intel hardware.
525          */
526         .driver_features =
527             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
528             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL |
529             DRIVER_IRQ_VBL2,
530         .load = i915_driver_load,
531         .unload = i915_driver_unload,
532         .lastclose = i915_driver_lastclose,
533         .preclose = i915_driver_preclose,
534         .suspend = i915_suspend,
535         .resume = i915_resume,
536         .device_is_agp = i915_driver_device_is_agp,
537         .vblank_wait = i915_driver_vblank_wait,
538         .vblank_wait2 = i915_driver_vblank_wait2,
539         .irq_preinstall = i915_driver_irq_preinstall,
540         .irq_postinstall = i915_driver_irq_postinstall,
541         .irq_uninstall = i915_driver_irq_uninstall,
542         .irq_handler = i915_driver_irq_handler,
543         .reclaim_buffers = drm_core_reclaim_buffers,
544         .get_map_ofs = drm_core_get_map_ofs,
545         .get_reg_ofs = drm_core_get_reg_ofs,
546         .ioctls = i915_ioctls,
547         .fops = {
548                  .owner = THIS_MODULE,
549                  .open = drm_open,
550                  .release = drm_release,
551                  .ioctl = drm_ioctl,
552                  .mmap = drm_mmap,
553                  .poll = drm_poll,
554                  .fasync = drm_fasync,
555 #ifdef CONFIG_COMPAT
556                  .compat_ioctl = i915_compat_ioctl,
557 #endif
558         },
559
560         .pci_driver = {
561                  .name = DRIVER_NAME,
562                  .id_table = pciidlist,
563         },
564
565         .name = DRIVER_NAME,
566         .desc = DRIVER_DESC,
567         .date = DRIVER_DATE,
568         .major = DRIVER_MAJOR,
569         .minor = DRIVER_MINOR,
570         .patchlevel = DRIVER_PATCHLEVEL,
571 };
572
573 static int __init i915_init(void)
574 {
575         driver.num_ioctls = i915_max_ioctl;
576         return drm_init(&driver);
577 }
578
579 static void __exit i915_exit(void)
580 {
581         drm_exit(&driver);
582 }
583
584 module_init(i915_init);
585 module_exit(i915_exit);
586
587 MODULE_AUTHOR(DRIVER_AUTHOR);
588 MODULE_DESCRIPTION(DRIVER_DESC);
589 MODULE_LICENSE("GPL and additional rights");