git.oblomov.eu Git - linux-2.6/blob - drivers/char/synclink_gt.c

   1 /*
   2  * $Id: synclink_gt.c,v 4.36 2006/08/28 20:47:14 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink GT serial adapters.
   5  *
   6  * written by Paul Fulghum for Microgate Corporation
   7  * paulkf@microgate.com
   8  *
   9  * Microgate and SyncLink are trademarks of Microgate Corporation
  10  *
  11  * This code is released under the GNU General Public License (GPL)
  12  *
  13  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  14  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  16  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  17  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  18  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  19  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  21  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  23  * OF THE POSSIBILITY OF SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * DEBUG OUTPUT DEFINITIONS
  28  *
  29  * uncomment lines below to enable specific types of debug output
  30  *
  31  * DBGINFO   information - most verbose output
  32  * DBGERR    serious errors
  33  * DBGBH     bottom half service routine debugging
  34  * DBGISR    interrupt service routine debugging
  35  * DBGDATA   output receive and transmit data
  36  * DBGTBUF   output transmit DMA buffers and registers
  37  * DBGRBUF   output receive DMA buffers and registers
  38  */
  39
  40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  45 //#define DBGTBUF(info) dump_tbufs(info)
  46 //#define DBGRBUF(info) dump_rbufs(info)
  47
  48
  49 #include <linux/module.h>
  50 #include <linux/version.h>
  51 #include <linux/errno.h>
  52 #include <linux/signal.h>
  53 #include <linux/sched.h>
  54 #include <linux/timer.h>
  55 #include <linux/interrupt.h>
  56 #include <linux/pci.h>
  57 #include <linux/tty.h>
  58 #include <linux/tty_flip.h>
  59 #include <linux/serial.h>
  60 #include <linux/major.h>
  61 #include <linux/string.h>
  62 #include <linux/fcntl.h>
  63 #include <linux/ptrace.h>
  64 #include <linux/ioport.h>
  65 #include <linux/mm.h>
  66 #include <linux/slab.h>
  67 #include <linux/netdevice.h>
  68 #include <linux/vmalloc.h>
  69 #include <linux/init.h>
  70 #include <linux/delay.h>
  71 #include <linux/ioctl.h>
  72 #include <linux/termios.h>
  73 #include <linux/bitops.h>
  74 #include <linux/workqueue.h>
  75 #include <linux/hdlc.h>
  76
  77 #include <asm/system.h>
  78 #include <asm/io.h>
  79 #include <asm/irq.h>
  80 #include <asm/dma.h>
  81 #include <asm/types.h>
  82 #include <asm/uaccess.h>
  83
  84 #include "linux/synclink.h"
  85
  86 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  87 #define SYNCLINK_GENERIC_HDLC 1
  88 #else
  89 #define SYNCLINK_GENERIC_HDLC 0
  90 #endif
  91
  92 /*
  93  * module identification
  94  */
  95 static char *driver_name     = "SyncLink GT";
  96 static char *driver_version  = "$Revision: 4.36 $";
  97 static char *tty_driver_name = "synclink_gt";
  98 static char *tty_dev_prefix  = "ttySLG";
  99 MODULE_LICENSE("GPL");
 100 #define MGSL_MAGIC 0x5401
 101 #define MAX_DEVICES 32
 102
 103 static struct pci_device_id pci_table[] = {
 104         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 105         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 106         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 107         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 108         {0,}, /* terminate list */
 109 };
 110 MODULE_DEVICE_TABLE(pci, pci_table);
 111
 112 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 113 static void remove_one(struct pci_dev *dev);
 114 static struct pci_driver pci_driver = {
 115         .name           = "synclink_gt",
 116         .id_table       = pci_table,
 117         .probe          = init_one,
 118         .remove         = __devexit_p(remove_one),
 119 };
 120
 121 static int pci_registered;
 122
 123 /*
 124  * module configuration and status
 125  */
 126 static struct slgt_info *slgt_device_list;
 127 static int slgt_device_count;
 128
 129 static int ttymajor;
 130 static int debug_level;
 131 static int maxframe[MAX_DEVICES];
 132 static int dosyncppp[MAX_DEVICES];
 133
 134 module_param(ttymajor, int, 0);
 135 module_param(debug_level, int, 0);
 136 module_param_array(maxframe, int, NULL, 0);
 137 module_param_array(dosyncppp, int, NULL, 0);
 138
 139 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 140 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 141 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 142 MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
 143
 144 /*
 145  * tty support and callbacks
 146  */
 147 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
 148
 149 static struct tty_driver *serial_driver;
 150
 151 static int  open(struct tty_struct *tty, struct file * filp);
 152 static void close(struct tty_struct *tty, struct file * filp);
 153 static void hangup(struct tty_struct *tty);
 154 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 155
 156 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 157 static void put_char(struct tty_struct *tty, unsigned char ch);
 158 static void send_xchar(struct tty_struct *tty, char ch);
 159 static void wait_until_sent(struct tty_struct *tty, int timeout);
 160 static int  write_room(struct tty_struct *tty);
 161 static void flush_chars(struct tty_struct *tty);
 162 static void flush_buffer(struct tty_struct *tty);
 163 static void tx_hold(struct tty_struct *tty);
 164 static void tx_release(struct tty_struct *tty);
 165
 166 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 167 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 168 static int  chars_in_buffer(struct tty_struct *tty);
 169 static void throttle(struct tty_struct * tty);
 170 static void unthrottle(struct tty_struct * tty);
 171 static void set_break(struct tty_struct *tty, int break_state);
 172
 173 /*
 174  * generic HDLC support and callbacks
 175  */
 176 #if SYNCLINK_GENERIC_HDLC
 177 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 178 static void hdlcdev_tx_done(struct slgt_info *info);
 179 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 180 static int  hdlcdev_init(struct slgt_info *info);
 181 static void hdlcdev_exit(struct slgt_info *info);
 182 #endif
 183
 184
 185 /*
 186  * device specific structures, macros and functions
 187  */
 188
 189 #define SLGT_MAX_PORTS 4
 190 #define SLGT_REG_SIZE  256
 191
 192 /*
 193  * conditional wait facility
 194  */
 195 struct cond_wait {
 196         struct cond_wait *next;
 197         wait_queue_head_t q;
 198         wait_queue_t wait;
 199         unsigned int data;
 200 };
 201 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 202 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 203 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 204 static void flush_cond_wait(struct cond_wait **head);
 205
 206 /*
 207  * DMA buffer descriptor and access macros
 208  */
 209 struct slgt_desc
 210 {
 211         unsigned short count;
 212         unsigned short status;
 213         unsigned int pbuf;  /* physical address of data buffer */
 214         unsigned int next;  /* physical address of next descriptor */
 215
 216         /* driver book keeping */
 217         char *buf;          /* virtual  address of data buffer */
 218         unsigned int pdesc; /* physical address of this descriptor */
 219         dma_addr_t buf_dma_addr;
 220 };
 221
 222 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 223 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 224 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 225 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 226 #define desc_count(a)      (le16_to_cpu((a).count))
 227 #define desc_status(a)     (le16_to_cpu((a).status))
 228 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 229 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 230 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 231 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 232 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 233
 234 struct _input_signal_events {
 235         int ri_up;
 236         int ri_down;
 237         int dsr_up;
 238         int dsr_down;
 239         int dcd_up;
 240         int dcd_down;
 241         int cts_up;
 242         int cts_down;
 243 };
 244
 245 /*
 246  * device instance data structure
 247  */
 248 struct slgt_info {
 249         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 250
 251         struct slgt_info *next_device;  /* device list link */
 252
 253         int magic;
 254         int flags;
 255
 256         char device_name[25];
 257         struct pci_dev *pdev;
 258
 259         int port_count;  /* count of ports on adapter */
 260         int adapter_num; /* adapter instance number */
 261         int port_num;    /* port instance number */
 262
 263         /* array of pointers to port contexts on this adapter */
 264         struct slgt_info *port_array[SLGT_MAX_PORTS];
 265
 266         int                     count;          /* count of opens */
 267         int                     line;           /* tty line instance number */
 268         unsigned short          close_delay;
 269         unsigned short          closing_wait;   /* time to wait before closing */
 270
 271         struct mgsl_icount      icount;
 272
 273         struct tty_struct       *tty;
 274         int                     timeout;
 275         int                     x_char;         /* xon/xoff character */
 276         int                     blocked_open;   /* # of blocked opens */
 277         unsigned int            read_status_mask;
 278         unsigned int            ignore_status_mask;
 279
 280         wait_queue_head_t       open_wait;
 281         wait_queue_head_t       close_wait;
 282
 283         wait_queue_head_t       status_event_wait_q;
 284         wait_queue_head_t       event_wait_q;
 285         struct timer_list       tx_timer;
 286         struct timer_list       rx_timer;
 287
 288         unsigned int            gpio_present;
 289         struct cond_wait        *gpio_wait_q;
 290
 291         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 292
 293         struct work_struct task;
 294         u32 pending_bh;
 295         int bh_requested;
 296         int bh_running;
 297
 298         int isr_overflow;
 299         int irq_requested;      /* nonzero if IRQ requested */
 300         int irq_occurred;       /* for diagnostics use */
 301
 302         /* device configuration */
 303
 304         unsigned int bus_type;
 305         unsigned int irq_level;
 306         unsigned long irq_flags;
 307
 308         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 309         u32 phys_reg_addr;
 310         int reg_addr_requested;
 311
 312         MGSL_PARAMS params;       /* communications parameters */
 313         u32 idle_mode;
 314         u32 max_frame_size;       /* as set by device config */
 315
 316         unsigned int raw_rx_size;
 317         unsigned int if_mode;
 318
 319         /* device status */
 320
 321         int rx_enabled;
 322         int rx_restart;
 323
 324         int tx_enabled;
 325         int tx_active;
 326
 327         unsigned char signals;    /* serial signal states */
 328         int init_error;  /* initialization error */
 329
 330         unsigned char *tx_buf;
 331         int tx_count;
 332
 333         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 334         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 335         BOOLEAN drop_rts_on_tx_done;
 336         struct  _input_signal_events    input_signal_events;
 337
 338         int dcd_chkcount;       /* check counts to prevent */
 339         int cts_chkcount;       /* too many IRQs if a signal */
 340         int dsr_chkcount;       /* is floating */
 341         int ri_chkcount;
 342
 343         char *bufs;             /* virtual address of DMA buffer lists */
 344         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 345
 346         unsigned int rbuf_count;
 347         struct slgt_desc *rbufs;
 348         unsigned int rbuf_current;
 349         unsigned int rbuf_index;
 350
 351         unsigned int tbuf_count;
 352         struct slgt_desc *tbufs;
 353         unsigned int tbuf_current;
 354         unsigned int tbuf_start;
 355
 356         unsigned char *tmp_rbuf;
 357         unsigned int tmp_rbuf_count;
 358
 359         /* SPPP/Cisco HDLC device parts */
 360
 361         int netcount;
 362         int dosyncppp;
 363         spinlock_t netlock;
 364 #if SYNCLINK_GENERIC_HDLC
 365         struct net_device *netdev;
 366 #endif
 367
 368 };
 369
 370 static MGSL_PARAMS default_params = {
 371         .mode            = MGSL_MODE_HDLC,
 372         .loopback        = 0,
 373         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 374         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 375         .clock_speed     = 0,
 376         .addr_filter     = 0xff,
 377         .crc_type        = HDLC_CRC_16_CCITT,
 378         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 379         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 380         .data_rate       = 9600,
 381         .data_bits       = 8,
 382         .stop_bits       = 1,
 383         .parity          = ASYNC_PARITY_NONE
 384 };
 385
 386
 387 #define BH_RECEIVE  1
 388 #define BH_TRANSMIT 2
 389 #define BH_STATUS   4
 390 #define IO_PIN_SHUTDOWN_LIMIT 100
 391
 392 #define DMABUFSIZE 256
 393 #define DESC_LIST_SIZE 4096
 394
 395 #define MASK_PARITY  BIT1
 396 #define MASK_FRAMING BIT0
 397 #define MASK_BREAK   BIT14
 398 #define MASK_OVERRUN BIT4
 399
 400 #define GSR   0x00 /* global status */
 401 #define JCR   0x04 /* JTAG control */
 402 #define IODR  0x08 /* GPIO direction */
 403 #define IOER  0x0c /* GPIO interrupt enable */
 404 #define IOVR  0x10 /* GPIO value */
 405 #define IOSR  0x14 /* GPIO interrupt status */
 406 #define TDR   0x80 /* tx data */
 407 #define RDR   0x80 /* rx data */
 408 #define TCR   0x82 /* tx control */
 409 #define TIR   0x84 /* tx idle */
 410 #define TPR   0x85 /* tx preamble */
 411 #define RCR   0x86 /* rx control */
 412 #define VCR   0x88 /* V.24 control */
 413 #define CCR   0x89 /* clock control */
 414 #define BDR   0x8a /* baud divisor */
 415 #define SCR   0x8c /* serial control */
 416 #define SSR   0x8e /* serial status */
 417 #define RDCSR 0x90 /* rx DMA control/status */
 418 #define TDCSR 0x94 /* tx DMA control/status */
 419 #define RDDAR 0x98 /* rx DMA descriptor address */
 420 #define TDDAR 0x9c /* tx DMA descriptor address */
 421
 422 #define RXIDLE      BIT14
 423 #define RXBREAK     BIT14
 424 #define IRQ_TXDATA  BIT13
 425 #define IRQ_TXIDLE  BIT12
 426 #define IRQ_TXUNDER BIT11 /* HDLC */
 427 #define IRQ_RXDATA  BIT10
 428 #define IRQ_RXIDLE  BIT9  /* HDLC */
 429 #define IRQ_RXBREAK BIT9  /* async */
 430 #define IRQ_RXOVER  BIT8
 431 #define IRQ_DSR     BIT7
 432 #define IRQ_CTS     BIT6
 433 #define IRQ_DCD     BIT5
 434 #define IRQ_RI      BIT4
 435 #define IRQ_ALL     0x3ff0
 436 #define IRQ_MASTER  BIT0
 437
 438 #define slgt_irq_on(info, mask) \
 439         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 440 #define slgt_irq_off(info, mask) \
 441         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 442
 443 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 444 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 445 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 446 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 447 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 448 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 449
 450 static void  msc_set_vcr(struct slgt_info *info);
 451
 452 static int  startup(struct slgt_info *info);
 453 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 454 static void shutdown(struct slgt_info *info);
 455 static void program_hw(struct slgt_info *info);
 456 static void change_params(struct slgt_info *info);
 457
 458 static int  register_test(struct slgt_info *info);
 459 static int  irq_test(struct slgt_info *info);
 460 static int  loopback_test(struct slgt_info *info);
 461 static int  adapter_test(struct slgt_info *info);
 462
 463 static void reset_adapter(struct slgt_info *info);
 464 static void reset_port(struct slgt_info *info);
 465 static void async_mode(struct slgt_info *info);
 466 static void sync_mode(struct slgt_info *info);
 467
 468 static void rx_stop(struct slgt_info *info);
 469 static void rx_start(struct slgt_info *info);
 470 static void reset_rbufs(struct slgt_info *info);
 471 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 472 static void rdma_reset(struct slgt_info *info);
 473 static int  rx_get_frame(struct slgt_info *info);
 474 static int  rx_get_buf(struct slgt_info *info);
 475
 476 static void tx_start(struct slgt_info *info);
 477 static void tx_stop(struct slgt_info *info);
 478 static void tx_set_idle(struct slgt_info *info);
 479 static unsigned int free_tbuf_count(struct slgt_info *info);
 480 static void reset_tbufs(struct slgt_info *info);
 481 static void tdma_reset(struct slgt_info *info);
 482 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 483
 484 static void get_signals(struct slgt_info *info);
 485 static void set_signals(struct slgt_info *info);
 486 static void enable_loopback(struct slgt_info *info);
 487 static void set_rate(struct slgt_info *info, u32 data_rate);
 488
 489 static int  bh_action(struct slgt_info *info);
 490 static void bh_handler(struct work_struct *work);
 491 static void bh_transmit(struct slgt_info *info);
 492 static void isr_serial(struct slgt_info *info);
 493 static void isr_rdma(struct slgt_info *info);
 494 static void isr_txeom(struct slgt_info *info, unsigned short status);
 495 static void isr_tdma(struct slgt_info *info);
 496 static irqreturn_t slgt_interrupt(int irq, void *dev_id);
 497
 498 static int  alloc_dma_bufs(struct slgt_info *info);
 499 static void free_dma_bufs(struct slgt_info *info);
 500 static int  alloc_desc(struct slgt_info *info);
 501 static void free_desc(struct slgt_info *info);
 502 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 503 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 504
 505 static int  alloc_tmp_rbuf(struct slgt_info *info);
 506 static void free_tmp_rbuf(struct slgt_info *info);
 507
 508 static void tx_timeout(unsigned long context);
 509 static void rx_timeout(unsigned long context);
 510
 511 /*
 512  * ioctl handlers
 513  */
 514 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 515 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 516 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 517 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 518 static int  set_txidle(struct slgt_info *info, int idle_mode);
 519 static int  tx_enable(struct slgt_info *info, int enable);
 520 static int  tx_abort(struct slgt_info *info);
 521 static int  rx_enable(struct slgt_info *info, int enable);
 522 static int  modem_input_wait(struct slgt_info *info,int arg);
 523 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 524 static int  tiocmget(struct tty_struct *tty, struct file *file);
 525 static int  tiocmset(struct tty_struct *tty, struct file *file,
 526                      unsigned int set, unsigned int clear);
 527 static void set_break(struct tty_struct *tty, int break_state);
 528 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 529 static int  set_interface(struct slgt_info *info, int if_mode);
 530 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 531 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 532 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 533
 534 /*
 535  * driver functions
 536  */
 537 static void add_device(struct slgt_info *info);
 538 static void device_init(int adapter_num, struct pci_dev *pdev);
 539 static int  claim_resources(struct slgt_info *info);
 540 static void release_resources(struct slgt_info *info);
 541
 542 /*
 543  * DEBUG OUTPUT CODE
 544  */
 545 #ifndef DBGINFO
 546 #define DBGINFO(fmt)
 547 #endif
 548 #ifndef DBGERR
 549 #define DBGERR(fmt)
 550 #endif
 551 #ifndef DBGBH
 552 #define DBGBH(fmt)
 553 #endif
 554 #ifndef DBGISR
 555 #define DBGISR(fmt)
 556 #endif
 557
 558 #ifdef DBGDATA
 559 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 560 {
 561         int i;
 562         int linecount;
 563         printk("%s %s data:\n",info->device_name, label);
 564         while(count) {
 565                 linecount = (count > 16) ? 16 : count;
 566                 for(i=0; i < linecount; i++)
 567                         printk("%02X ",(unsigned char)data[i]);
 568                 for(;i<17;i++)
 569                         printk("   ");
 570                 for(i=0;i<linecount;i++) {
 571                         if (data[i]>=040 && data[i]<=0176)
 572                                 printk("%c",data[i]);
 573                         else
 574                                 printk(".");
 575                 }
 576                 printk("\n");
 577                 data  += linecount;
 578                 count -= linecount;
 579         }
 580 }
 581 #else
 582 #define DBGDATA(info, buf, size, label)
 583 #endif
 584
 585 #ifdef DBGTBUF
 586 static void dump_tbufs(struct slgt_info *info)
 587 {
 588         int i;
 589         printk("tbuf_current=%d\n", info->tbuf_current);
 590         for (i=0 ; i < info->tbuf_count ; i++) {
 591                 printk("%d: count=%04X status=%04X\n",
 592                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 593         }
 594 }
 595 #else
 596 #define DBGTBUF(info)
 597 #endif
 598
 599 #ifdef DBGRBUF
 600 static void dump_rbufs(struct slgt_info *info)
 601 {
 602         int i;
 603         printk("rbuf_current=%d\n", info->rbuf_current);
 604         for (i=0 ; i < info->rbuf_count ; i++) {
 605                 printk("%d: count=%04X status=%04X\n",
 606                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 607         }
 608 }
 609 #else
 610 #define DBGRBUF(info)
 611 #endif
 612
 613 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 614 {
 615 #ifdef SANITY_CHECK
 616         if (!info) {
 617                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 618                 return 1;
 619         }
 620         if (info->magic != MGSL_MAGIC) {
 621                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 622                 return 1;
 623         }
 624 #else
 625         if (!info)
 626                 return 1;
 627 #endif
 628         return 0;
 629 }
 630
 631 /**
 632  * line discipline callback wrappers
 633  *
 634  * The wrappers maintain line discipline references
 635  * while calling into the line discipline.
 636  *
 637  * ldisc_receive_buf  - pass receive data to line discipline
 638  */
 639 static void ldisc_receive_buf(struct tty_struct *tty,
 640                               const __u8 *data, char *flags, int count)
 641 {
 642         struct tty_ldisc *ld;
 643         if (!tty)
 644                 return;
 645         ld = tty_ldisc_ref(tty);
 646         if (ld) {
 647                 if (ld->receive_buf)
 648                         ld->receive_buf(tty, data, flags, count);
 649                 tty_ldisc_deref(ld);
 650         }
 651 }
 652
 653 /* tty callbacks */
 654
 655 static int open(struct tty_struct *tty, struct file *filp)
 656 {
 657         struct slgt_info *info;
 658         int retval, line;
 659         unsigned long flags;
 660
 661         line = tty->index;
 662         if ((line < 0) || (line >= slgt_device_count)) {
 663                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 664                 return -ENODEV;
 665         }
 666
 667         info = slgt_device_list;
 668         while(info && info->line != line)
 669                 info = info->next_device;
 670         if (sanity_check(info, tty->name, "open"))
 671                 return -ENODEV;
 672         if (info->init_error) {
 673                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 674                 return -ENODEV;
 675         }
 676
 677         tty->driver_data = info;
 678         info->tty = tty;
 679
 680         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->count));
 681
 682         /* If port is closing, signal caller to try again */
 683         if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
 684                 if (info->flags & ASYNC_CLOSING)
 685                         interruptible_sleep_on(&info->close_wait);
 686                 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
 687                         -EAGAIN : -ERESTARTSYS);
 688                 goto cleanup;
 689         }
 690
 691         info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 692
 693         spin_lock_irqsave(&info->netlock, flags);
 694         if (info->netcount) {
 695                 retval = -EBUSY;
 696                 spin_unlock_irqrestore(&info->netlock, flags);
 697                 goto cleanup;
 698         }
 699         info->count++;
 700         spin_unlock_irqrestore(&info->netlock, flags);
 701
 702         if (info->count == 1) {
 703                 /* 1st open on this device, init hardware */
 704                 retval = startup(info);
 705                 if (retval < 0)
 706                         goto cleanup;
 707         }
 708
 709         retval = block_til_ready(tty, filp, info);
 710         if (retval) {
 711                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 712                 goto cleanup;
 713         }
 714
 715         retval = 0;
 716
 717 cleanup:
 718         if (retval) {
 719                 if (tty->count == 1)
 720                         info->tty = NULL; /* tty layer will release tty struct */
 721                 if(info->count)
 722                         info->count--;
 723         }
 724
 725         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 726         return retval;
 727 }
 728
 729 static void close(struct tty_struct *tty, struct file *filp)
 730 {
 731         struct slgt_info *info = tty->driver_data;
 732
 733         if (sanity_check(info, tty->name, "close"))
 734                 return;
 735         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->count));
 736
 737         if (!info->count)
 738                 return;
 739
 740         if (tty_hung_up_p(filp))
 741                 goto cleanup;
 742
 743         if ((tty->count == 1) && (info->count != 1)) {
 744                 /*
 745                  * tty->count is 1 and the tty structure will be freed.
 746                  * info->count should be one in this case.
 747                  * if it's not, correct it so that the port is shutdown.
 748                  */
 749                 DBGERR(("%s close: bad refcount; tty->count=1, "
 750                        "info->count=%d\n", info->device_name, info->count));
 751                 info->count = 1;
 752         }
 753
 754         info->count--;
 755
 756         /* if at least one open remaining, leave hardware active */
 757         if (info->count)
 758                 goto cleanup;
 759
 760         info->flags |= ASYNC_CLOSING;
 761
 762         /* set tty->closing to notify line discipline to
 763          * only process XON/XOFF characters. Only the N_TTY
 764          * discipline appears to use this (ppp does not).
 765          */
 766         tty->closing = 1;
 767
 768         /* wait for transmit data to clear all layers */
 769
 770         if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 771                 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
 772                 tty_wait_until_sent(tty, info->closing_wait);
 773         }
 774
 775         if (info->flags & ASYNC_INITIALIZED)
 776                 wait_until_sent(tty, info->timeout);
 777         if (tty->driver->flush_buffer)
 778                 tty->driver->flush_buffer(tty);
 779         tty_ldisc_flush(tty);
 780
 781         shutdown(info);
 782
 783         tty->closing = 0;
 784         info->tty = NULL;
 785
 786         if (info->blocked_open) {
 787                 if (info->close_delay) {
 788                         msleep_interruptible(jiffies_to_msecs(info->close_delay));
 789                 }
 790                 wake_up_interruptible(&info->open_wait);
 791         }
 792
 793         info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 794
 795         wake_up_interruptible(&info->close_wait);
 796
 797 cleanup:
 798         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->count));
 799 }
 800
 801 static void hangup(struct tty_struct *tty)
 802 {
 803         struct slgt_info *info = tty->driver_data;
 804
 805         if (sanity_check(info, tty->name, "hangup"))
 806                 return;
 807         DBGINFO(("%s hangup\n", info->device_name));
 808
 809         flush_buffer(tty);
 810         shutdown(info);
 811
 812         info->count = 0;
 813         info->flags &= ~ASYNC_NORMAL_ACTIVE;
 814         info->tty = NULL;
 815
 816         wake_up_interruptible(&info->open_wait);
 817 }
 818
 819 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 820 {
 821         struct slgt_info *info = tty->driver_data;
 822         unsigned long flags;
 823
 824         DBGINFO(("%s set_termios\n", tty->driver->name));
 825
 826         /* just return if nothing has changed */
 827         if ((tty->termios->c_cflag == old_termios->c_cflag)
 828             && (RELEVANT_IFLAG(tty->termios->c_iflag)
 829                 == RELEVANT_IFLAG(old_termios->c_iflag)))
 830                 return;
 831
 832         change_params(info);
 833
 834         /* Handle transition to B0 status */
 835         if (old_termios->c_cflag & CBAUD &&
 836             !(tty->termios->c_cflag & CBAUD)) {
 837                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 838                 spin_lock_irqsave(&info->lock,flags);
 839                 set_signals(info);
 840                 spin_unlock_irqrestore(&info->lock,flags);
 841         }
 842
 843         /* Handle transition away from B0 status */
 844         if (!(old_termios->c_cflag & CBAUD) &&
 845             tty->termios->c_cflag & CBAUD) {
 846                 info->signals |= SerialSignal_DTR;
 847                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 848                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 849                         info->signals |= SerialSignal_RTS;
 850                 }
 851                 spin_lock_irqsave(&info->lock,flags);
 852                 set_signals(info);
 853                 spin_unlock_irqrestore(&info->lock,flags);
 854         }
 855
 856         /* Handle turning off CRTSCTS */
 857         if (old_termios->c_cflag & CRTSCTS &&
 858             !(tty->termios->c_cflag & CRTSCTS)) {
 859                 tty->hw_stopped = 0;
 860                 tx_release(tty);
 861         }
 862 }
 863
 864 static int write(struct tty_struct *tty,
 865                  const unsigned char *buf, int count)
 866 {
 867         int ret = 0;
 868         struct slgt_info *info = tty->driver_data;
 869         unsigned long flags;
 870
 871         if (sanity_check(info, tty->name, "write"))
 872                 goto cleanup;
 873         DBGINFO(("%s write count=%d\n", info->device_name, count));
 874
 875         if (!info->tx_buf)
 876                 goto cleanup;
 877
 878         if (count > info->max_frame_size) {
 879                 ret = -EIO;
 880                 goto cleanup;
 881         }
 882
 883         if (!count)
 884                 goto cleanup;
 885
 886         if (info->params.mode == MGSL_MODE_RAW ||
 887             info->params.mode == MGSL_MODE_MONOSYNC ||
 888             info->params.mode == MGSL_MODE_BISYNC) {
 889                 unsigned int bufs_needed = (count/DMABUFSIZE);
 890                 unsigned int bufs_free = free_tbuf_count(info);
 891                 if (count % DMABUFSIZE)
 892                         ++bufs_needed;
 893                 if (bufs_needed > bufs_free)
 894                         goto cleanup;
 895         } else {
 896                 if (info->tx_active)
 897                         goto cleanup;
 898                 if (info->tx_count) {
 899                         /* send accumulated data from send_char() calls */
 900                         /* as frame and wait before accepting more data. */
 901                         tx_load(info, info->tx_buf, info->tx_count);
 902                         goto start;
 903                 }
 904         }
 905
 906         ret = info->tx_count = count;
 907         tx_load(info, buf, count);
 908         goto start;
 909
 910 start:
 911         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 912                 spin_lock_irqsave(&info->lock,flags);
 913                 if (!info->tx_active)
 914                         tx_start(info);
 915                 spin_unlock_irqrestore(&info->lock,flags);
 916         }
 917
 918 cleanup:
 919         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 920         return ret;
 921 }
 922
 923 static void put_char(struct tty_struct *tty, unsigned char ch)
 924 {
 925         struct slgt_info *info = tty->driver_data;
 926         unsigned long flags;
 927
 928         if (sanity_check(info, tty->name, "put_char"))
 929                 return;
 930         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 931         if (!info->tx_buf)
 932                 return;
 933         spin_lock_irqsave(&info->lock,flags);
 934         if (!info->tx_active && (info->tx_count < info->max_frame_size))
 935                 info->tx_buf[info->tx_count++] = ch;
 936         spin_unlock_irqrestore(&info->lock,flags);
 937 }
 938
 939 static void send_xchar(struct tty_struct *tty, char ch)
 940 {
 941         struct slgt_info *info = tty->driver_data;
 942         unsigned long flags;
 943
 944         if (sanity_check(info, tty->name, "send_xchar"))
 945                 return;
 946         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 947         info->x_char = ch;
 948         if (ch) {
 949                 spin_lock_irqsave(&info->lock,flags);
 950                 if (!info->tx_enabled)
 951                         tx_start(info);
 952                 spin_unlock_irqrestore(&info->lock,flags);
 953         }
 954 }
 955
 956 static void wait_until_sent(struct tty_struct *tty, int timeout)
 957 {
 958         struct slgt_info *info = tty->driver_data;
 959         unsigned long orig_jiffies, char_time;
 960
 961         if (!info )
 962                 return;
 963         if (sanity_check(info, tty->name, "wait_until_sent"))
 964                 return;
 965         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 966         if (!(info->flags & ASYNC_INITIALIZED))
 967                 goto exit;
 968
 969         orig_jiffies = jiffies;
 970
 971         /* Set check interval to 1/5 of estimated time to
 972          * send a character, and make it at least 1. The check
 973          * interval should also be less than the timeout.
 974          * Note: use tight timings here to satisfy the NIST-PCTS.
 975          */
 976
 977         if (info->params.data_rate) {
 978                 char_time = info->timeout/(32 * 5);
 979                 if (!char_time)
 980                         char_time++;
 981         } else
 982                 char_time = 1;
 983
 984         if (timeout)
 985                 char_time = min_t(unsigned long, char_time, timeout);
 986
 987         while (info->tx_active) {
 988                 msleep_interruptible(jiffies_to_msecs(char_time));
 989                 if (signal_pending(current))
 990                         break;
 991                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 992                         break;
 993         }
 994
 995 exit:
 996         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 997 }
 998
 999 static int write_room(struct tty_struct *tty)
1000 {
1001         struct slgt_info *info = tty->driver_data;
1002         int ret;
1003
1004         if (sanity_check(info, tty->name, "write_room"))
1005                 return 0;
1006         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1007         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
1008         return ret;
1009 }
1010
1011 static void flush_chars(struct tty_struct *tty)
1012 {
1013         struct slgt_info *info = tty->driver_data;
1014         unsigned long flags;
1015
1016         if (sanity_check(info, tty->name, "flush_chars"))
1017                 return;
1018         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
1019
1020         if (info->tx_count <= 0 || tty->stopped ||
1021             tty->hw_stopped || !info->tx_buf)
1022                 return;
1023
1024         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1025
1026         spin_lock_irqsave(&info->lock,flags);
1027         if (!info->tx_active && info->tx_count) {
1028                 tx_load(info, info->tx_buf,info->tx_count);
1029                 tx_start(info);
1030         }
1031         spin_unlock_irqrestore(&info->lock,flags);
1032 }
1033
1034 static void flush_buffer(struct tty_struct *tty)
1035 {
1036         struct slgt_info *info = tty->driver_data;
1037         unsigned long flags;
1038
1039         if (sanity_check(info, tty->name, "flush_buffer"))
1040                 return;
1041         DBGINFO(("%s flush_buffer\n", info->device_name));
1042
1043         spin_lock_irqsave(&info->lock,flags);
1044         if (!info->tx_active)
1045                 info->tx_count = 0;
1046         spin_unlock_irqrestore(&info->lock,flags);
1047
1048         tty_wakeup(tty);
1049 }
1050
1051 /*
1052  * throttle (stop) transmitter
1053  */
1054 static void tx_hold(struct tty_struct *tty)
1055 {
1056         struct slgt_info *info = tty->driver_data;
1057         unsigned long flags;
1058
1059         if (sanity_check(info, tty->name, "tx_hold"))
1060                 return;
1061         DBGINFO(("%s tx_hold\n", info->device_name));
1062         spin_lock_irqsave(&info->lock,flags);
1063         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1064                 tx_stop(info);
1065         spin_unlock_irqrestore(&info->lock,flags);
1066 }
1067
1068 /*
1069  * release (start) transmitter
1070  */
1071 static void tx_release(struct tty_struct *tty)
1072 {
1073         struct slgt_info *info = tty->driver_data;
1074         unsigned long flags;
1075
1076         if (sanity_check(info, tty->name, "tx_release"))
1077                 return;
1078         DBGINFO(("%s tx_release\n", info->device_name));
1079         spin_lock_irqsave(&info->lock,flags);
1080         if (!info->tx_active && info->tx_count) {
1081                 tx_load(info, info->tx_buf, info->tx_count);
1082                 tx_start(info);
1083         }
1084         spin_unlock_irqrestore(&info->lock,flags);
1085 }
1086
1087 /*
1088  * Service an IOCTL request
1089  *
1090  * Arguments
1091  *
1092  *      tty     pointer to tty instance data
1093  *      file    pointer to associated file object for device
1094  *      cmd     IOCTL command code
1095  *      arg     command argument/context
1096  *
1097  * Return 0 if success, otherwise error code
1098  */
1099 static int ioctl(struct tty_struct *tty, struct file *file,
1100                  unsigned int cmd, unsigned long arg)
1101 {
1102         struct slgt_info *info = tty->driver_data;
1103         struct mgsl_icount cnow;        /* kernel counter temps */
1104         struct serial_icounter_struct __user *p_cuser;  /* user space */
1105         unsigned long flags;
1106         void __user *argp = (void __user *)arg;
1107
1108         if (sanity_check(info, tty->name, "ioctl"))
1109                 return -ENODEV;
1110         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1111
1112         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1113             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1114                 if (tty->flags & (1 << TTY_IO_ERROR))
1115                     return -EIO;
1116         }
1117
1118         switch (cmd) {
1119         case MGSL_IOCGPARAMS:
1120                 return get_params(info, argp);
1121         case MGSL_IOCSPARAMS:
1122                 return set_params(info, argp);
1123         case MGSL_IOCGTXIDLE:
1124                 return get_txidle(info, argp);
1125         case MGSL_IOCSTXIDLE:
1126                 return set_txidle(info, (int)arg);
1127         case MGSL_IOCTXENABLE:
1128                 return tx_enable(info, (int)arg);
1129         case MGSL_IOCRXENABLE:
1130                 return rx_enable(info, (int)arg);
1131         case MGSL_IOCTXABORT:
1132                 return tx_abort(info);
1133         case MGSL_IOCGSTATS:
1134                 return get_stats(info, argp);
1135         case MGSL_IOCWAITEVENT:
1136                 return wait_mgsl_event(info, argp);
1137         case TIOCMIWAIT:
1138                 return modem_input_wait(info,(int)arg);
1139         case MGSL_IOCGIF:
1140                 return get_interface(info, argp);
1141         case MGSL_IOCSIF:
1142                 return set_interface(info,(int)arg);
1143         case MGSL_IOCSGPIO:
1144                 return set_gpio(info, argp);
1145         case MGSL_IOCGGPIO:
1146                 return get_gpio(info, argp);
1147         case MGSL_IOCWAITGPIO:
1148                 return wait_gpio(info, argp);
1149         case TIOCGICOUNT:
1150                 spin_lock_irqsave(&info->lock,flags);
1151                 cnow = info->icount;
1152                 spin_unlock_irqrestore(&info->lock,flags);
1153                 p_cuser = argp;
1154                 if (put_user(cnow.cts, &p_cuser->cts) ||
1155                     put_user(cnow.dsr, &p_cuser->dsr) ||
1156                     put_user(cnow.rng, &p_cuser->rng) ||
1157                     put_user(cnow.dcd, &p_cuser->dcd) ||
1158                     put_user(cnow.rx, &p_cuser->rx) ||
1159                     put_user(cnow.tx, &p_cuser->tx) ||
1160                     put_user(cnow.frame, &p_cuser->frame) ||
1161                     put_user(cnow.overrun, &p_cuser->overrun) ||
1162                     put_user(cnow.parity, &p_cuser->parity) ||
1163                     put_user(cnow.brk, &p_cuser->brk) ||
1164                     put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1165                         return -EFAULT;
1166                 return 0;
1167         default:
1168                 return -ENOIOCTLCMD;
1169         }
1170         return 0;
1171 }
1172
1173 /*
1174  * support for 32 bit ioctl calls on 64 bit systems
1175  */
1176 #ifdef CONFIG_COMPAT
1177 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1178 {
1179         struct MGSL_PARAMS32 tmp_params;
1180
1181         DBGINFO(("%s get_params32\n", info->device_name));
1182         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1183         tmp_params.loopback        = info->params.loopback;
1184         tmp_params.flags           = info->params.flags;
1185         tmp_params.encoding        = info->params.encoding;
1186         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1187         tmp_params.addr_filter     = info->params.addr_filter;
1188         tmp_params.crc_type        = info->params.crc_type;
1189         tmp_params.preamble_length = info->params.preamble_length;
1190         tmp_params.preamble        = info->params.preamble;
1191         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1192         tmp_params.data_bits       = info->params.data_bits;
1193         tmp_params.stop_bits       = info->params.stop_bits;
1194         tmp_params.parity          = info->params.parity;
1195         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1196                 return -EFAULT;
1197         return 0;
1198 }
1199
1200 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1201 {
1202         struct MGSL_PARAMS32 tmp_params;
1203
1204         DBGINFO(("%s set_params32\n", info->device_name));
1205         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1206                 return -EFAULT;
1207
1208         spin_lock(&info->lock);
1209         info->params.mode            = tmp_params.mode;
1210         info->params.loopback        = tmp_params.loopback;
1211         info->params.flags           = tmp_params.flags;
1212         info->params.encoding        = tmp_params.encoding;
1213         info->params.clock_speed     = tmp_params.clock_speed;
1214         info->params.addr_filter     = tmp_params.addr_filter;
1215         info->params.crc_type        = tmp_params.crc_type;
1216         info->params.preamble_length = tmp_params.preamble_length;
1217         info->params.preamble        = tmp_params.preamble;
1218         info->params.data_rate       = tmp_params.data_rate;
1219         info->params.data_bits       = tmp_params.data_bits;
1220         info->params.stop_bits       = tmp_params.stop_bits;
1221         info->params.parity          = tmp_params.parity;
1222         spin_unlock(&info->lock);
1223
1224         change_params(info);
1225
1226         return 0;
1227 }
1228
1229 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1230                          unsigned int cmd, unsigned long arg)
1231 {
1232         struct slgt_info *info = tty->driver_data;
1233         int rc = -ENOIOCTLCMD;
1234
1235         if (sanity_check(info, tty->name, "compat_ioctl"))
1236                 return -ENODEV;
1237         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1238
1239         switch (cmd) {
1240
1241         case MGSL_IOCSPARAMS32:
1242                 rc = set_params32(info, compat_ptr(arg));
1243                 break;
1244
1245         case MGSL_IOCGPARAMS32:
1246                 rc = get_params32(info, compat_ptr(arg));
1247                 break;
1248
1249         case MGSL_IOCGPARAMS:
1250         case MGSL_IOCSPARAMS:
1251         case MGSL_IOCGTXIDLE:
1252         case MGSL_IOCGSTATS:
1253         case MGSL_IOCWAITEVENT:
1254         case MGSL_IOCGIF:
1255         case MGSL_IOCSGPIO:
1256         case MGSL_IOCGGPIO:
1257         case MGSL_IOCWAITGPIO:
1258         case TIOCGICOUNT:
1259                 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1260                 break;
1261
1262         case MGSL_IOCSTXIDLE:
1263         case MGSL_IOCTXENABLE:
1264         case MGSL_IOCRXENABLE:
1265         case MGSL_IOCTXABORT:
1266         case TIOCMIWAIT:
1267         case MGSL_IOCSIF:
1268                 rc = ioctl(tty, file, cmd, arg);
1269                 break;
1270         }
1271
1272         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1273         return rc;
1274 }
1275 #else
1276 #define slgt_compat_ioctl NULL
1277 #endif /* ifdef CONFIG_COMPAT */
1278
1279 /*
1280  * proc fs support
1281  */
1282 static inline int line_info(char *buf, struct slgt_info *info)
1283 {
1284         char stat_buf[30];
1285         int ret;
1286         unsigned long flags;
1287
1288         ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1289                       info->device_name, info->phys_reg_addr,
1290                       info->irq_level, info->max_frame_size);
1291
1292         /* output current serial signal states */
1293         spin_lock_irqsave(&info->lock,flags);
1294         get_signals(info);
1295         spin_unlock_irqrestore(&info->lock,flags);
1296
1297         stat_buf[0] = 0;
1298         stat_buf[1] = 0;
1299         if (info->signals & SerialSignal_RTS)
1300                 strcat(stat_buf, "|RTS");
1301         if (info->signals & SerialSignal_CTS)
1302                 strcat(stat_buf, "|CTS");
1303         if (info->signals & SerialSignal_DTR)
1304                 strcat(stat_buf, "|DTR");
1305         if (info->signals & SerialSignal_DSR)
1306                 strcat(stat_buf, "|DSR");
1307         if (info->signals & SerialSignal_DCD)
1308                 strcat(stat_buf, "|CD");
1309         if (info->signals & SerialSignal_RI)
1310                 strcat(stat_buf, "|RI");
1311
1312         if (info->params.mode != MGSL_MODE_ASYNC) {
1313                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1314                                info->icount.txok, info->icount.rxok);
1315                 if (info->icount.txunder)
1316                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1317                 if (info->icount.txabort)
1318                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1319                 if (info->icount.rxshort)
1320                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1321                 if (info->icount.rxlong)
1322                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1323                 if (info->icount.rxover)
1324                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1325                 if (info->icount.rxcrc)
1326                         ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1327         } else {
1328                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1329                                info->icount.tx, info->icount.rx);
1330                 if (info->icount.frame)
1331                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1332                 if (info->icount.parity)
1333                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1334                 if (info->icount.brk)
1335                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1336                 if (info->icount.overrun)
1337                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1338         }
1339
1340         /* Append serial signal status to end */
1341         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1342
1343         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1344                        info->tx_active,info->bh_requested,info->bh_running,
1345                        info->pending_bh);
1346
1347         return ret;
1348 }
1349
1350 /* Called to print information about devices
1351  */
1352 static int read_proc(char *page, char **start, off_t off, int count,
1353                      int *eof, void *data)
1354 {
1355         int len = 0, l;
1356         off_t   begin = 0;
1357         struct slgt_info *info;
1358
1359         len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1360
1361         info = slgt_device_list;
1362         while( info ) {
1363                 l = line_info(page + len, info);
1364                 len += l;
1365                 if (len+begin > off+count)
1366                         goto done;
1367                 if (len+begin < off) {
1368                         begin += len;
1369                         len = 0;
1370                 }
1371                 info = info->next_device;
1372         }
1373
1374         *eof = 1;
1375 done:
1376         if (off >= len+begin)
1377                 return 0;
1378         *start = page + (off-begin);
1379         return ((count < begin+len-off) ? count : begin+len-off);
1380 }
1381
1382 /*
1383  * return count of bytes in transmit buffer
1384  */
1385 static int chars_in_buffer(struct tty_struct *tty)
1386 {
1387         struct slgt_info *info = tty->driver_data;
1388         if (sanity_check(info, tty->name, "chars_in_buffer"))
1389                 return 0;
1390         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1391         return info->tx_count;
1392 }
1393
1394 /*
1395  * signal remote device to throttle send data (our receive data)
1396  */
1397 static void throttle(struct tty_struct * tty)
1398 {
1399         struct slgt_info *info = tty->driver_data;
1400         unsigned long flags;
1401
1402         if (sanity_check(info, tty->name, "throttle"))
1403                 return;
1404         DBGINFO(("%s throttle\n", info->device_name));
1405         if (I_IXOFF(tty))
1406                 send_xchar(tty, STOP_CHAR(tty));
1407         if (tty->termios->c_cflag & CRTSCTS) {
1408                 spin_lock_irqsave(&info->lock,flags);
1409                 info->signals &= ~SerialSignal_RTS;
1410                 set_signals(info);
1411                 spin_unlock_irqrestore(&info->lock,flags);
1412         }
1413 }
1414
1415 /*
1416  * signal remote device to stop throttling send data (our receive data)
1417  */
1418 static void unthrottle(struct tty_struct * tty)
1419 {
1420         struct slgt_info *info = tty->driver_data;
1421         unsigned long flags;
1422
1423         if (sanity_check(info, tty->name, "unthrottle"))
1424                 return;
1425         DBGINFO(("%s unthrottle\n", info->device_name));
1426         if (I_IXOFF(tty)) {
1427                 if (info->x_char)
1428                         info->x_char = 0;
1429                 else
1430                         send_xchar(tty, START_CHAR(tty));
1431         }
1432         if (tty->termios->c_cflag & CRTSCTS) {
1433                 spin_lock_irqsave(&info->lock,flags);
1434                 info->signals |= SerialSignal_RTS;
1435                 set_signals(info);
1436                 spin_unlock_irqrestore(&info->lock,flags);
1437         }
1438 }
1439
1440 /*
1441  * set or clear transmit break condition
1442  * break_state  -1=set break condition, 0=clear
1443  */
1444 static void set_break(struct tty_struct *tty, int break_state)
1445 {
1446         struct slgt_info *info = tty->driver_data;
1447         unsigned short value;
1448         unsigned long flags;
1449
1450         if (sanity_check(info, tty->name, "set_break"))
1451                 return;
1452         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1453
1454         spin_lock_irqsave(&info->lock,flags);
1455         value = rd_reg16(info, TCR);
1456         if (break_state == -1)
1457                 value |= BIT6;
1458         else
1459                 value &= ~BIT6;
1460         wr_reg16(info, TCR, value);
1461         spin_unlock_irqrestore(&info->lock,flags);
1462 }
1463
1464 #if SYNCLINK_GENERIC_HDLC
1465
1466 /**
1467  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1468  * set encoding and frame check sequence (FCS) options
1469  *
1470  * dev       pointer to network device structure
1471  * encoding  serial encoding setting
1472  * parity    FCS setting
1473  *
1474  * returns 0 if success, otherwise error code
1475  */
1476 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1477                           unsigned short parity)
1478 {
1479         struct slgt_info *info = dev_to_port(dev);
1480         unsigned char  new_encoding;
1481         unsigned short new_crctype;
1482
1483         /* return error if TTY interface open */
1484         if (info->count)
1485                 return -EBUSY;
1486
1487         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1488
1489         switch (encoding)
1490         {
1491         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1492         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1493         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1494         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1495         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1496         default: return -EINVAL;
1497         }
1498
1499         switch (parity)
1500         {
1501         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1502         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1503         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1504         default: return -EINVAL;
1505         }
1506
1507         info->params.encoding = new_encoding;
1508         info->params.crc_type = new_crctype;
1509
1510         /* if network interface up, reprogram hardware */
1511         if (info->netcount)
1512                 program_hw(info);
1513
1514         return 0;
1515 }
1516
1517 /**
1518  * called by generic HDLC layer to send frame
1519  *
1520  * skb  socket buffer containing HDLC frame
1521  * dev  pointer to network device structure
1522  *
1523  * returns 0 if success, otherwise error code
1524  */
1525 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1526 {
1527         struct slgt_info *info = dev_to_port(dev);
1528         struct net_device_stats *stats = hdlc_stats(dev);
1529         unsigned long flags;
1530
1531         DBGINFO(("%s hdlc_xmit\n", dev->name));
1532
1533         /* stop sending until this frame completes */
1534         netif_stop_queue(dev);
1535
1536         /* copy data to device buffers */
1537         info->tx_count = skb->len;
1538         tx_load(info, skb->data, skb->len);
1539
1540         /* update network statistics */
1541         stats->tx_packets++;
1542         stats->tx_bytes += skb->len;
1543
1544         /* done with socket buffer, so free it */
1545         dev_kfree_skb(skb);
1546
1547         /* save start time for transmit timeout detection */
1548         dev->trans_start = jiffies;
1549
1550         /* start hardware transmitter if necessary */
1551         spin_lock_irqsave(&info->lock,flags);
1552         if (!info->tx_active)
1553                 tx_start(info);
1554         spin_unlock_irqrestore(&info->lock,flags);
1555
1556         return 0;
1557 }
1558
1559 /**
1560  * called by network layer when interface enabled
1561  * claim resources and initialize hardware
1562  *
1563  * dev  pointer to network device structure
1564  *
1565  * returns 0 if success, otherwise error code
1566  */
1567 static int hdlcdev_open(struct net_device *dev)
1568 {
1569         struct slgt_info *info = dev_to_port(dev);
1570         int rc;
1571         unsigned long flags;
1572
1573         DBGINFO(("%s hdlcdev_open\n", dev->name));
1574
1575         /* generic HDLC layer open processing */
1576         if ((rc = hdlc_open(dev)))
1577                 return rc;
1578
1579         /* arbitrate between network and tty opens */
1580         spin_lock_irqsave(&info->netlock, flags);
1581         if (info->count != 0 || info->netcount != 0) {
1582                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1583                 spin_unlock_irqrestore(&info->netlock, flags);
1584                 return -EBUSY;
1585         }
1586         info->netcount=1;
1587         spin_unlock_irqrestore(&info->netlock, flags);
1588
1589         /* claim resources and init adapter */
1590         if ((rc = startup(info)) != 0) {
1591                 spin_lock_irqsave(&info->netlock, flags);
1592                 info->netcount=0;
1593                 spin_unlock_irqrestore(&info->netlock, flags);
1594                 return rc;
1595         }
1596
1597         /* assert DTR and RTS, apply hardware settings */
1598         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1599         program_hw(info);
1600
1601         /* enable network layer transmit */
1602         dev->trans_start = jiffies;
1603         netif_start_queue(dev);
1604
1605         /* inform generic HDLC layer of current DCD status */
1606         spin_lock_irqsave(&info->lock, flags);
1607         get_signals(info);
1608         spin_unlock_irqrestore(&info->lock, flags);
1609         if (info->signals & SerialSignal_DCD)
1610                 netif_carrier_on(dev);
1611         else
1612                 netif_carrier_off(dev);
1613         return 0;
1614 }
1615
1616 /**
1617  * called by network layer when interface is disabled
1618  * shutdown hardware and release resources
1619  *
1620  * dev  pointer to network device structure
1621  *
1622  * returns 0 if success, otherwise error code
1623  */
1624 static int hdlcdev_close(struct net_device *dev)
1625 {
1626         struct slgt_info *info = dev_to_port(dev);
1627         unsigned long flags;
1628
1629         DBGINFO(("%s hdlcdev_close\n", dev->name));
1630
1631         netif_stop_queue(dev);
1632
1633         /* shutdown adapter and release resources */
1634         shutdown(info);
1635
1636         hdlc_close(dev);
1637
1638         spin_lock_irqsave(&info->netlock, flags);
1639         info->netcount=0;
1640         spin_unlock_irqrestore(&info->netlock, flags);
1641
1642         return 0;
1643 }
1644
1645 /**
1646  * called by network layer to process IOCTL call to network device
1647  *
1648  * dev  pointer to network device structure
1649  * ifr  pointer to network interface request structure
1650  * cmd  IOCTL command code
1651  *
1652  * returns 0 if success, otherwise error code
1653  */
1654 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1655 {
1656         const size_t size = sizeof(sync_serial_settings);
1657         sync_serial_settings new_line;
1658         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1659         struct slgt_info *info = dev_to_port(dev);
1660         unsigned int flags;
1661
1662         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1663
1664         /* return error if TTY interface open */
1665         if (info->count)
1666                 return -EBUSY;
1667
1668         if (cmd != SIOCWANDEV)
1669                 return hdlc_ioctl(dev, ifr, cmd);
1670
1671         switch(ifr->ifr_settings.type) {
1672         case IF_GET_IFACE: /* return current sync_serial_settings */
1673
1674                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1675                 if (ifr->ifr_settings.size < size) {
1676                         ifr->ifr_settings.size = size; /* data size wanted */
1677                         return -ENOBUFS;
1678                 }
1679
1680                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1681                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1682                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1683                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1684
1685                 switch (flags){
1686                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1687                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1688                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1689                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1690                 default: new_line.clock_type = CLOCK_DEFAULT;
1691                 }
1692
1693                 new_line.clock_rate = info->params.clock_speed;
1694                 new_line.loopback   = info->params.loopback ? 1:0;
1695
1696                 if (copy_to_user(line, &new_line, size))
1697                         return -EFAULT;
1698                 return 0;
1699
1700         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1701
1702                 if(!capable(CAP_NET_ADMIN))
1703                         return -EPERM;
1704                 if (copy_from_user(&new_line, line, size))
1705                         return -EFAULT;
1706
1707                 switch (new_line.clock_type)
1708                 {
1709                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1710                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1711                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1712                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1713                 case CLOCK_DEFAULT:  flags = info->params.flags &
1714                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1715                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1716                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1717                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1718                 default: return -EINVAL;
1719                 }
1720
1721                 if (new_line.loopback != 0 && new_line.loopback != 1)
1722                         return -EINVAL;
1723
1724                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1725                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1726                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1727                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1728                 info->params.flags |= flags;
1729
1730                 info->params.loopback = new_line.loopback;
1731
1732                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1733                         info->params.clock_speed = new_line.clock_rate;
1734                 else
1735                         info->params.clock_speed = 0;
1736
1737                 /* if network interface up, reprogram hardware */
1738                 if (info->netcount)
1739                         program_hw(info);
1740                 return 0;
1741
1742         default:
1743                 return hdlc_ioctl(dev, ifr, cmd);
1744         }
1745 }
1746
1747 /**
1748  * called by network layer when transmit timeout is detected
1749  *
1750  * dev  pointer to network device structure
1751  */
1752 static void hdlcdev_tx_timeout(struct net_device *dev)
1753 {
1754         struct slgt_info *info = dev_to_port(dev);
1755         struct net_device_stats *stats = hdlc_stats(dev);
1756         unsigned long flags;
1757
1758         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1759
1760         stats->tx_errors++;
1761         stats->tx_aborted_errors++;
1762
1763         spin_lock_irqsave(&info->lock,flags);
1764         tx_stop(info);
1765         spin_unlock_irqrestore(&info->lock,flags);
1766
1767         netif_wake_queue(dev);
1768 }
1769
1770 /**
1771  * called by device driver when transmit completes
1772  * reenable network layer transmit if stopped
1773  *
1774  * info  pointer to device instance information
1775  */
1776 static void hdlcdev_tx_done(struct slgt_info *info)
1777 {
1778         if (netif_queue_stopped(info->netdev))
1779                 netif_wake_queue(info->netdev);
1780 }
1781
1782 /**
1783  * called by device driver when frame received
1784  * pass frame to network layer
1785  *
1786  * info  pointer to device instance information
1787  * buf   pointer to buffer contianing frame data
1788  * size  count of data bytes in buf
1789  */
1790 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1791 {
1792         struct sk_buff *skb = dev_alloc_skb(size);
1793         struct net_device *dev = info->netdev;
1794         struct net_device_stats *stats = hdlc_stats(dev);
1795
1796         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1797
1798         if (skb == NULL) {
1799                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1800                 stats->rx_dropped++;
1801                 return;
1802         }
1803
1804         memcpy(skb_put(skb, size),buf,size);
1805
1806         skb->protocol = hdlc_type_trans(skb, info->netdev);
1807
1808         stats->rx_packets++;
1809         stats->rx_bytes += size;
1810
1811         netif_rx(skb);
1812
1813         info->netdev->last_rx = jiffies;
1814 }
1815
1816 /**
1817  * called by device driver when adding device instance
1818  * do generic HDLC initialization
1819  *
1820  * info  pointer to device instance information
1821  *
1822  * returns 0 if success, otherwise error code
1823  */
1824 static int hdlcdev_init(struct slgt_info *info)
1825 {
1826         int rc;
1827         struct net_device *dev;
1828         hdlc_device *hdlc;
1829
1830         /* allocate and initialize network and HDLC layer objects */
1831
1832         if (!(dev = alloc_hdlcdev(info))) {
1833                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1834                 return -ENOMEM;
1835         }
1836
1837         /* for network layer reporting purposes only */
1838         dev->mem_start = info->phys_reg_addr;
1839         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1840         dev->irq       = info->irq_level;
1841
1842         /* network layer callbacks and settings */
1843         dev->do_ioctl       = hdlcdev_ioctl;
1844         dev->open           = hdlcdev_open;
1845         dev->stop           = hdlcdev_close;
1846         dev->tx_timeout     = hdlcdev_tx_timeout;
1847         dev->watchdog_timeo = 10*HZ;
1848         dev->tx_queue_len   = 50;
1849
1850         /* generic HDLC layer callbacks and settings */
1851         hdlc         = dev_to_hdlc(dev);
1852         hdlc->attach = hdlcdev_attach;
1853         hdlc->xmit   = hdlcdev_xmit;
1854
1855         /* register objects with HDLC layer */
1856         if ((rc = register_hdlc_device(dev))) {
1857                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1858                 free_netdev(dev);
1859                 return rc;
1860         }
1861
1862         info->netdev = dev;
1863         return 0;
1864 }
1865
1866 /**
1867  * called by device driver when removing device instance
1868  * do generic HDLC cleanup
1869  *
1870  * info  pointer to device instance information
1871  */
1872 static void hdlcdev_exit(struct slgt_info *info)
1873 {
1874         unregister_hdlc_device(info->netdev);
1875         free_netdev(info->netdev);
1876         info->netdev = NULL;
1877 }
1878
1879 #endif /* ifdef CONFIG_HDLC */
1880
1881 /*
1882  * get async data from rx DMA buffers
1883  */
1884 static void rx_async(struct slgt_info *info)
1885 {
1886         struct tty_struct *tty = info->tty;
1887         struct mgsl_icount *icount = &info->icount;
1888         unsigned int start, end;
1889         unsigned char *p;
1890         unsigned char status;
1891         struct slgt_desc *bufs = info->rbufs;
1892         int i, count;
1893         int chars = 0;
1894         int stat;
1895         unsigned char ch;
1896
1897         start = end = info->rbuf_current;
1898
1899         while(desc_complete(bufs[end])) {
1900                 count = desc_count(bufs[end]) - info->rbuf_index;
1901                 p     = bufs[end].buf + info->rbuf_index;
1902
1903                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1904                 DBGDATA(info, p, count, "rx");
1905
1906                 for(i=0 ; i < count; i+=2, p+=2) {
1907                         ch = *p;
1908                         icount->rx++;
1909
1910                         stat = 0;
1911
1912                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1913                                 if (status & BIT1)
1914                                         icount->parity++;
1915                                 else if (status & BIT0)
1916                                         icount->frame++;
1917                                 /* discard char if tty control flags say so */
1918                                 if (status & info->ignore_status_mask)
1919                                         continue;
1920                                 if (status & BIT1)
1921                                         stat = TTY_PARITY;
1922                                 else if (status & BIT0)
1923                                         stat = TTY_FRAME;
1924                         }
1925                         if (tty) {
1926                                 tty_insert_flip_char(tty, ch, stat);
1927                                 chars++;
1928                         }
1929                 }
1930
1931                 if (i < count) {
1932                         /* receive buffer not completed */
1933                         info->rbuf_index += i;
1934                         mod_timer(&info->rx_timer, jiffies + 1);
1935                         break;
1936                 }
1937
1938                 info->rbuf_index = 0;
1939                 free_rbufs(info, end, end);
1940
1941                 if (++end == info->rbuf_count)
1942                         end = 0;
1943
1944                 /* if entire list searched then no frame available */
1945                 if (end == start)
1946                         break;
1947         }
1948
1949         if (tty && chars)
1950                 tty_flip_buffer_push(tty);
1951 }
1952
1953 /*
1954  * return next bottom half action to perform
1955  */
1956 static int bh_action(struct slgt_info *info)
1957 {
1958         unsigned long flags;
1959         int rc;
1960
1961         spin_lock_irqsave(&info->lock,flags);
1962
1963         if (info->pending_bh & BH_RECEIVE) {
1964                 info->pending_bh &= ~BH_RECEIVE;
1965                 rc = BH_RECEIVE;
1966         } else if (info->pending_bh & BH_TRANSMIT) {
1967                 info->pending_bh &= ~BH_TRANSMIT;
1968                 rc = BH_TRANSMIT;
1969         } else if (info->pending_bh & BH_STATUS) {
1970                 info->pending_bh &= ~BH_STATUS;
1971                 rc = BH_STATUS;
1972         } else {
1973                 /* Mark BH routine as complete */
1974                 info->bh_running   = 0;
1975                 info->bh_requested = 0;
1976                 rc = 0;
1977         }
1978
1979         spin_unlock_irqrestore(&info->lock,flags);
1980
1981         return rc;
1982 }
1983
1984 /*
1985  * perform bottom half processing
1986  */
1987 static void bh_handler(struct work_struct *work)
1988 {
1989         struct slgt_info *info = container_of(work, struct slgt_info, task);
1990         int action;
1991
1992         if (!info)
1993                 return;
1994         info->bh_running = 1;
1995
1996         while((action = bh_action(info))) {
1997                 switch (action) {
1998                 case BH_RECEIVE:
1999                         DBGBH(("%s bh receive\n", info->device_name));
2000                         switch(info->params.mode) {
2001                         case MGSL_MODE_ASYNC:
2002                                 rx_async(info);
2003                                 break;
2004                         case MGSL_MODE_HDLC:
2005                                 while(rx_get_frame(info));
2006                                 break;
2007                         case MGSL_MODE_RAW:
2008                         case MGSL_MODE_MONOSYNC:
2009                         case MGSL_MODE_BISYNC:
2010                                 while(rx_get_buf(info));
2011                                 break;
2012                         }
2013                         /* restart receiver if rx DMA buffers exhausted */
2014                         if (info->rx_restart)
2015                                 rx_start(info);
2016                         break;
2017                 case BH_TRANSMIT:
2018                         bh_transmit(info);
2019                         break;
2020                 case BH_STATUS:
2021                         DBGBH(("%s bh status\n", info->device_name));
2022                         info->ri_chkcount = 0;
2023                         info->dsr_chkcount = 0;
2024                         info->dcd_chkcount = 0;
2025                         info->cts_chkcount = 0;
2026                         break;
2027                 default:
2028                         DBGBH(("%s unknown action\n", info->device_name));
2029                         break;
2030                 }
2031         }
2032         DBGBH(("%s bh_handler exit\n", info->device_name));
2033 }
2034
2035 static void bh_transmit(struct slgt_info *info)
2036 {
2037         struct tty_struct *tty = info->tty;
2038
2039         DBGBH(("%s bh_transmit\n", info->device_name));
2040         if (tty)
2041                 tty_wakeup(tty);
2042 }
2043
2044 static void dsr_change(struct slgt_info *info)
2045 {
2046         get_signals(info);
2047         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2048         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2049                 slgt_irq_off(info, IRQ_DSR);
2050                 return;
2051         }
2052         info->icount.dsr++;
2053         if (info->signals & SerialSignal_DSR)
2054                 info->input_signal_events.dsr_up++;
2055         else
2056                 info->input_signal_events.dsr_down++;
2057         wake_up_interruptible(&info->status_event_wait_q);
2058         wake_up_interruptible(&info->event_wait_q);
2059         info->pending_bh |= BH_STATUS;
2060 }
2061
2062 static void cts_change(struct slgt_info *info)
2063 {
2064         get_signals(info);
2065         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2066         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2067                 slgt_irq_off(info, IRQ_CTS);
2068                 return;
2069         }
2070         info->icount.cts++;
2071         if (info->signals & SerialSignal_CTS)
2072                 info->input_signal_events.cts_up++;
2073         else
2074                 info->input_signal_events.cts_down++;
2075         wake_up_interruptible(&info->status_event_wait_q);
2076         wake_up_interruptible(&info->event_wait_q);
2077         info->pending_bh |= BH_STATUS;
2078
2079         if (info->flags & ASYNC_CTS_FLOW) {
2080                 if (info->tty) {
2081                         if (info->tty->hw_stopped) {
2082                                 if (info->signals & SerialSignal_CTS) {
2083                                         info->tty->hw_stopped = 0;
2084                                         info->pending_bh |= BH_TRANSMIT;
2085                                         return;
2086                                 }
2087                         } else {
2088                                 if (!(info->signals & SerialSignal_CTS))
2089                                         info->tty->hw_stopped = 1;
2090                         }
2091                 }
2092         }
2093 }
2094
2095 static void dcd_change(struct slgt_info *info)
2096 {
2097         get_signals(info);
2098         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2099         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2100                 slgt_irq_off(info, IRQ_DCD);
2101                 return;
2102         }
2103         info->icount.dcd++;
2104         if (info->signals & SerialSignal_DCD) {
2105                 info->input_signal_events.dcd_up++;
2106         } else {
2107                 info->input_signal_events.dcd_down++;
2108         }
2109 #if SYNCLINK_GENERIC_HDLC
2110         if (info->netcount) {
2111                 if (info->signals & SerialSignal_DCD)
2112                         netif_carrier_on(info->netdev);
2113                 else
2114                         netif_carrier_off(info->netdev);
2115         }
2116 #endif
2117         wake_up_interruptible(&info->status_event_wait_q);
2118         wake_up_interruptible(&info->event_wait_q);
2119         info->pending_bh |= BH_STATUS;
2120
2121         if (info->flags & ASYNC_CHECK_CD) {
2122                 if (info->signals & SerialSignal_DCD)
2123                         wake_up_interruptible(&info->open_wait);
2124                 else {
2125                         if (info->tty)
2126                                 tty_hangup(info->tty);
2127                 }
2128         }
2129 }
2130
2131 static void ri_change(struct slgt_info *info)
2132 {
2133         get_signals(info);
2134         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2135         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2136                 slgt_irq_off(info, IRQ_RI);
2137                 return;
2138         }
2139         info->icount.dcd++;
2140         if (info->signals & SerialSignal_RI) {
2141                 info->input_signal_events.ri_up++;
2142         } else {
2143                 info->input_signal_events.ri_down++;
2144         }
2145         wake_up_interruptible(&info->status_event_wait_q);
2146         wake_up_interruptible(&info->event_wait_q);
2147         info->pending_bh |= BH_STATUS;
2148 }
2149
2150 static void isr_serial(struct slgt_info *info)
2151 {
2152         unsigned short status = rd_reg16(info, SSR);
2153
2154         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2155
2156         wr_reg16(info, SSR, status); /* clear pending */
2157
2158         info->irq_occurred = 1;
2159
2160         if (info->params.mode == MGSL_MODE_ASYNC) {
2161                 if (status & IRQ_TXIDLE) {
2162                         if (info->tx_count)
2163                                 isr_txeom(info, status);
2164                 }
2165                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2166                         info->icount.brk++;
2167                         /* process break detection if tty control allows */
2168                         if (info->tty) {
2169                                 if (!(status & info->ignore_status_mask)) {
2170                                         if (info->read_status_mask & MASK_BREAK) {
2171                                                 tty_insert_flip_char(info->tty, 0, TTY_BREAK);
2172                                                 if (info->flags & ASYNC_SAK)
2173                                                         do_SAK(info->tty);
2174                                         }
2175                                 }
2176                         }
2177                 }
2178         } else {
2179                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2180                         isr_txeom(info, status);
2181
2182                 if (status & IRQ_RXIDLE) {
2183                         if (status & RXIDLE)
2184                                 info->icount.rxidle++;
2185                         else
2186                                 info->icount.exithunt++;
2187                         wake_up_interruptible(&info->event_wait_q);
2188                 }
2189
2190                 if (status & IRQ_RXOVER)
2191                         rx_start(info);
2192         }
2193
2194         if (status & IRQ_DSR)
2195                 dsr_change(info);
2196         if (status & IRQ_CTS)
2197                 cts_change(info);
2198         if (status & IRQ_DCD)
2199                 dcd_change(info);
2200         if (status & IRQ_RI)
2201                 ri_change(info);
2202 }
2203
2204 static void isr_rdma(struct slgt_info *info)
2205 {
2206         unsigned int status = rd_reg32(info, RDCSR);
2207
2208         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2209
2210         /* RDCSR (rx DMA control/status)
2211          *
2212          * 31..07  reserved
2213          * 06      save status byte to DMA buffer
2214          * 05      error
2215          * 04      eol (end of list)
2216          * 03      eob (end of buffer)
2217          * 02      IRQ enable
2218          * 01      reset
2219          * 00      enable
2220          */
2221         wr_reg32(info, RDCSR, status);  /* clear pending */
2222
2223         if (status & (BIT5 + BIT4)) {
2224                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2225                 info->rx_restart = 1;
2226         }
2227         info->pending_bh |= BH_RECEIVE;
2228 }
2229
2230 static void isr_tdma(struct slgt_info *info)
2231 {
2232         unsigned int status = rd_reg32(info, TDCSR);
2233
2234         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2235
2236         /* TDCSR (tx DMA control/status)
2237          *
2238          * 31..06  reserved
2239          * 05      error
2240          * 04      eol (end of list)
2241          * 03      eob (end of buffer)
2242          * 02      IRQ enable
2243          * 01      reset
2244          * 00      enable
2245          */
2246         wr_reg32(info, TDCSR, status);  /* clear pending */
2247
2248         if (status & (BIT5 + BIT4 + BIT3)) {
2249                 // another transmit buffer has completed
2250                 // run bottom half to get more send data from user
2251                 info->pending_bh |= BH_TRANSMIT;
2252         }
2253 }
2254
2255 static void isr_txeom(struct slgt_info *info, unsigned short status)
2256 {
2257         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2258
2259         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2260         tdma_reset(info);
2261         reset_tbufs(info);
2262         if (status & IRQ_TXUNDER) {
2263                 unsigned short val = rd_reg16(info, TCR);
2264                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2265                 wr_reg16(info, TCR, val); /* clear reset bit */
2266         }
2267
2268         if (info->tx_active) {
2269                 if (info->params.mode != MGSL_MODE_ASYNC) {
2270                         if (status & IRQ_TXUNDER)
2271                                 info->icount.txunder++;
2272                         else if (status & IRQ_TXIDLE)
2273                                 info->icount.txok++;
2274                 }
2275
2276                 info->tx_active = 0;
2277                 info->tx_count = 0;
2278
2279                 del_timer(&info->tx_timer);
2280
2281                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2282                         info->signals &= ~SerialSignal_RTS;
2283                         info->drop_rts_on_tx_done = 0;
2284                         set_signals(info);
2285                 }
2286
2287 #if SYNCLINK_GENERIC_HDLC
2288                 if (info->netcount)
2289                         hdlcdev_tx_done(info);
2290                 else
2291 #endif
2292                 {
2293                         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2294                                 tx_stop(info);
2295                                 return;
2296                         }
2297                         info->pending_bh |= BH_TRANSMIT;
2298                 }
2299         }
2300 }
2301
2302 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2303 {
2304         struct cond_wait *w, *prev;
2305
2306         /* wake processes waiting for specific transitions */
2307         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2308                 if (w->data & changed) {
2309                         w->data = state;
2310                         wake_up_interruptible(&w->q);
2311                         if (prev != NULL)
2312                                 prev->next = w->next;
2313                         else
2314                                 info->gpio_wait_q = w->next;
2315                 } else
2316                         prev = w;
2317         }
2318 }
2319
2320 /* interrupt service routine
2321  *
2322  *      irq     interrupt number
2323  *      dev_id  device ID supplied during interrupt registration
2324  */
2325 static irqreturn_t slgt_interrupt(int irq, void *dev_id)
2326 {
2327         struct slgt_info *info;
2328         unsigned int gsr;
2329         unsigned int i;
2330
2331         DBGISR(("slgt_interrupt irq=%d entry\n", irq));
2332
2333         info = dev_id;
2334         if (!info)
2335                 return IRQ_NONE;
2336
2337         spin_lock(&info->lock);
2338
2339         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2340                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2341                 info->irq_occurred = 1;
2342                 for(i=0; i < info->port_count ; i++) {
2343                         if (info->port_array[i] == NULL)
2344                                 continue;
2345                         if (gsr & (BIT8 << i))
2346                                 isr_serial(info->port_array[i]);
2347                         if (gsr & (BIT16 << (i*2)))
2348                                 isr_rdma(info->port_array[i]);
2349                         if (gsr & (BIT17 << (i*2)))
2350                                 isr_tdma(info->port_array[i]);
2351                 }
2352         }
2353
2354         if (info->gpio_present) {
2355                 unsigned int state;
2356                 unsigned int changed;
2357                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2358                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2359                         /* read latched state of GPIO signals */
2360                         state = rd_reg32(info, IOVR);
2361                         /* clear pending GPIO interrupt bits */
2362                         wr_reg32(info, IOSR, changed);
2363                         for (i=0 ; i < info->port_count ; i++) {
2364                                 if (info->port_array[i] != NULL)
2365                                         isr_gpio(info->port_array[i], changed, state);
2366                         }
2367                 }
2368         }
2369
2370         for(i=0; i < info->port_count ; i++) {
2371                 struct slgt_info *port = info->port_array[i];
2372
2373                 if (port && (port->count || port->netcount) &&
2374                     port->pending_bh && !port->bh_running &&
2375                     !port->bh_requested) {
2376                         DBGISR(("%s bh queued\n", port->device_name));
2377                         schedule_work(&port->task);
2378                         port->bh_requested = 1;
2379                 }
2380         }
2381
2382         spin_unlock(&info->lock);
2383
2384         DBGISR(("slgt_interrupt irq=%d exit\n", irq));
2385         return IRQ_HANDLED;
2386 }
2387
2388 static int startup(struct slgt_info *info)
2389 {
2390         DBGINFO(("%s startup\n", info->device_name));
2391
2392         if (info->flags & ASYNC_INITIALIZED)
2393                 return 0;
2394
2395         if (!info->tx_buf) {
2396                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2397                 if (!info->tx_buf) {
2398                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2399                         return -ENOMEM;
2400                 }
2401         }
2402
2403         info->pending_bh = 0;
2404
2405         memset(&info->icount, 0, sizeof(info->icount));
2406
2407         /* program hardware for current parameters */
2408         change_params(info);
2409
2410         if (info->tty)
2411                 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2412
2413         info->flags |= ASYNC_INITIALIZED;
2414
2415         return 0;
2416 }
2417
2418 /*
2419  *  called by close() and hangup() to shutdown hardware
2420  */
2421 static void shutdown(struct slgt_info *info)
2422 {
2423         unsigned long flags;
2424
2425         if (!(info->flags & ASYNC_INITIALIZED))
2426                 return;
2427
2428         DBGINFO(("%s shutdown\n", info->device_name));
2429
2430         /* clear status wait queue because status changes */
2431         /* can't happen after shutting down the hardware */
2432         wake_up_interruptible(&info->status_event_wait_q);
2433         wake_up_interruptible(&info->event_wait_q);
2434
2435         del_timer_sync(&info->tx_timer);
2436         del_timer_sync(&info->rx_timer);
2437
2438         kfree(info->tx_buf);
2439         info->tx_buf = NULL;
2440
2441         spin_lock_irqsave(&info->lock,flags);
2442
2443         tx_stop(info);
2444         rx_stop(info);
2445
2446         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2447
2448         if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2449                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2450                 set_signals(info);
2451         }
2452
2453         flush_cond_wait(&info->gpio_wait_q);
2454
2455         spin_unlock_irqrestore(&info->lock,flags);
2456
2457         if (info->tty)
2458                 set_bit(TTY_IO_ERROR, &info->tty->flags);
2459
2460         info->flags &= ~ASYNC_INITIALIZED;
2461 }
2462
2463 static void program_hw(struct slgt_info *info)
2464 {
2465         unsigned long flags;
2466
2467         spin_lock_irqsave(&info->lock,flags);
2468
2469         rx_stop(info);
2470         tx_stop(info);
2471
2472         if (info->params.mode != MGSL_MODE_ASYNC ||
2473             info->netcount)
2474                 sync_mode(info);
2475         else
2476                 async_mode(info);
2477
2478         set_signals(info);
2479
2480         info->dcd_chkcount = 0;
2481         info->cts_chkcount = 0;
2482         info->ri_chkcount = 0;
2483         info->dsr_chkcount = 0;
2484
2485         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2486         get_signals(info);
2487
2488         if (info->netcount ||
2489             (info->tty && info->tty->termios->c_cflag & CREAD))
2490                 rx_start(info);
2491
2492         spin_unlock_irqrestore(&info->lock,flags);
2493 }
2494
2495 /*
2496  * reconfigure adapter based on new parameters
2497  */
2498 static void change_params(struct slgt_info *info)
2499 {
2500         unsigned cflag;
2501         int bits_per_char;
2502
2503         if (!info->tty || !info->tty->termios)
2504                 return;
2505         DBGINFO(("%s change_params\n", info->device_name));
2506
2507         cflag = info->tty->termios->c_cflag;
2508
2509         /* if B0 rate (hangup) specified then negate DTR and RTS */
2510         /* otherwise assert DTR and RTS */
2511         if (cflag & CBAUD)
2512                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2513         else
2514                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2515
2516         /* byte size and parity */
2517
2518         switch (cflag & CSIZE) {
2519         case CS5: info->params.data_bits = 5; break;
2520         case CS6: info->params.data_bits = 6; break;
2521         case CS7: info->params.data_bits = 7; break;
2522         case CS8: info->params.data_bits = 8; break;
2523         default:  info->params.data_bits = 7; break;
2524         }
2525
2526         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2527
2528         if (cflag & PARENB)
2529                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2530         else
2531                 info->params.parity = ASYNC_PARITY_NONE;
2532
2533         /* calculate number of jiffies to transmit a full
2534          * FIFO (32 bytes) at specified data rate
2535          */
2536         bits_per_char = info->params.data_bits +
2537                         info->params.stop_bits + 1;
2538
2539         info->params.data_rate = tty_get_baud_rate(info->tty);
2540
2541         if (info->params.data_rate) {
2542                 info->timeout = (32*HZ*bits_per_char) /
2543                                 info->params.data_rate;
2544         }
2545         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2546
2547         if (cflag & CRTSCTS)
2548                 info->flags |= ASYNC_CTS_FLOW;
2549         else
2550                 info->flags &= ~ASYNC_CTS_FLOW;
2551
2552         if (cflag & CLOCAL)
2553                 info->flags &= ~ASYNC_CHECK_CD;
2554         else
2555                 info->flags |= ASYNC_CHECK_CD;
2556
2557         /* process tty input control flags */
2558
2559         info->read_status_mask = IRQ_RXOVER;
2560         if (I_INPCK(info->tty))
2561                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2562         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2563                 info->read_status_mask |= MASK_BREAK;
2564         if (I_IGNPAR(info->tty))
2565                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2566         if (I_IGNBRK(info->tty)) {
2567                 info->ignore_status_mask |= MASK_BREAK;
2568                 /* If ignoring parity and break indicators, ignore
2569                  * overruns too.  (For real raw support).
2570                  */
2571                 if (I_IGNPAR(info->tty))
2572                         info->ignore_status_mask |= MASK_OVERRUN;
2573         }
2574
2575         program_hw(info);
2576 }
2577
2578 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2579 {
2580         DBGINFO(("%s get_stats\n",  info->device_name));
2581         if (!user_icount) {
2582                 memset(&info->icount, 0, sizeof(info->icount));
2583         } else {
2584                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2585                         return -EFAULT;
2586         }
2587         return 0;
2588 }
2589
2590 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2591 {
2592         DBGINFO(("%s get_params\n", info->device_name));
2593         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2594                 return -EFAULT;
2595         return 0;
2596 }
2597
2598 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2599 {
2600         unsigned long flags;
2601         MGSL_PARAMS tmp_params;
2602
2603         DBGINFO(("%s set_params\n", info->device_name));
2604         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2605                 return -EFAULT;
2606
2607         spin_lock_irqsave(&info->lock, flags);
2608         memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2609         spin_unlock_irqrestore(&info->lock, flags);
2610
2611         change_params(info);
2612
2613         return 0;
2614 }
2615
2616 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2617 {
2618         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2619         if (put_user(info->idle_mode, idle_mode))
2620                 return -EFAULT;
2621         return 0;
2622 }
2623
2624 static int set_txidle(struct slgt_info *info, int idle_mode)
2625 {
2626         unsigned long flags;
2627         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2628         spin_lock_irqsave(&info->lock,flags);
2629         info->idle_mode = idle_mode;
2630         if (info->params.mode != MGSL_MODE_ASYNC)
2631                 tx_set_idle(info);
2632         spin_unlock_irqrestore(&info->lock,flags);
2633         return 0;
2634 }
2635
2636 static int tx_enable(struct slgt_info *info, int enable)
2637 {
2638         unsigned long flags;
2639         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2640         spin_lock_irqsave(&info->lock,flags);
2641         if (enable) {
2642                 if (!info->tx_enabled)
2643                         tx_start(info);
2644         } else {
2645                 if (info->tx_enabled)
2646                         tx_stop(info);
2647         }
2648         spin_unlock_irqrestore(&info->lock,flags);
2649         return 0;
2650 }
2651
2652 /*
2653  * abort transmit HDLC frame
2654  */
2655 static int tx_abort(struct slgt_info *info)
2656 {
2657         unsigned long flags;
2658         DBGINFO(("%s tx_abort\n", info->device_name));
2659         spin_lock_irqsave(&info->lock,flags);
2660         tdma_reset(info);
2661         spin_unlock_irqrestore(&info->lock,flags);
2662         return 0;
2663 }
2664
2665 static int rx_enable(struct slgt_info *info, int enable)
2666 {
2667         unsigned long flags;
2668         DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2669         spin_lock_irqsave(&info->lock,flags);
2670         if (enable) {
2671                 if (!info->rx_enabled)
2672                         rx_start(info);
2673                 else if (enable == 2) {
2674                         /* force hunt mode (write 1 to RCR[3]) */
2675                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2676                 }
2677         } else {
2678                 if (info->rx_enabled)
2679                         rx_stop(info);
2680         }
2681         spin_unlock_irqrestore(&info->lock,flags);
2682         return 0;
2683 }
2684
2685 /*
2686  *  wait for specified event to occur
2687  */
2688 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2689 {
2690         unsigned long flags;
2691         int s;
2692         int rc=0;
2693         struct mgsl_icount cprev, cnow;
2694         int events;
2695         int mask;
2696         struct  _input_signal_events oldsigs, newsigs;
2697         DECLARE_WAITQUEUE(wait, current);
2698
2699         if (get_user(mask, mask_ptr))
2700                 return -EFAULT;
2701
2702         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2703
2704         spin_lock_irqsave(&info->lock,flags);
2705
2706         /* return immediately if state matches requested events */
2707         get_signals(info);
2708         s = info->signals;
2709
2710         events = mask &
2711                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2712                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2713                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2714                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2715         if (events) {
2716                 spin_unlock_irqrestore(&info->lock,flags);
2717                 goto exit;
2718         }
2719
2720         /* save current irq counts */
2721         cprev = info->icount;
2722         oldsigs = info->input_signal_events;
2723
2724         /* enable hunt and idle irqs if needed */
2725         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2726                 unsigned short val = rd_reg16(info, SCR);
2727                 if (!(val & IRQ_RXIDLE))
2728                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2729         }
2730
2731         set_current_state(TASK_INTERRUPTIBLE);
2732         add_wait_queue(&info->event_wait_q, &wait);
2733
2734         spin_unlock_irqrestore(&info->lock,flags);
2735
2736         for(;;) {
2737                 schedule();
2738                 if (signal_pending(current)) {
2739                         rc = -ERESTARTSYS;
2740                         break;
2741                 }
2742
2743                 /* get current irq counts */
2744                 spin_lock_irqsave(&info->lock,flags);
2745                 cnow = info->icount;
2746                 newsigs = info->input_signal_events;
2747                 set_current_state(TASK_INTERRUPTIBLE);
2748                 spin_unlock_irqrestore(&info->lock,flags);
2749
2750                 /* if no change, wait aborted for some reason */
2751                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2752                     newsigs.dsr_down == oldsigs.dsr_down &&
2753                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2754                     newsigs.dcd_down == oldsigs.dcd_down &&
2755                     newsigs.cts_up   == oldsigs.cts_up   &&
2756                     newsigs.cts_down == oldsigs.cts_down &&
2757                     newsigs.ri_up    == oldsigs.ri_up    &&
2758                     newsigs.ri_down  == oldsigs.ri_down  &&
2759                     cnow.exithunt    == cprev.exithunt   &&
2760                     cnow.rxidle      == cprev.rxidle) {
2761                         rc = -EIO;
2762                         break;
2763                 }
2764
2765                 events = mask &
2766                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2767                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2768                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2769                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2770                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2771                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2772                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2773                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2774                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2775                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2776                 if (events)
2777                         break;
2778
2779                 cprev = cnow;
2780                 oldsigs = newsigs;
2781         }
2782
2783         remove_wait_queue(&info->event_wait_q, &wait);
2784         set_current_state(TASK_RUNNING);
2785
2786
2787         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2788                 spin_lock_irqsave(&info->lock,flags);
2789                 if (!waitqueue_active(&info->event_wait_q)) {
2790                         /* disable enable exit hunt mode/idle rcvd IRQs */
2791                         wr_reg16(info, SCR,
2792                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2793                 }
2794                 spin_unlock_irqrestore(&info->lock,flags);
2795         }
2796 exit:
2797         if (rc == 0)
2798                 rc = put_user(events, mask_ptr);
2799         return rc;
2800 }
2801
2802 static int get_interface(struct slgt_info *info, int __user *if_mode)
2803 {
2804         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2805         if (put_user(info->if_mode, if_mode))
2806                 return -EFAULT;
2807         return 0;
2808 }
2809
2810 static int set_interface(struct slgt_info *info, int if_mode)
2811 {
2812         unsigned long flags;
2813         unsigned short val;
2814
2815         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2816         spin_lock_irqsave(&info->lock,flags);
2817         info->if_mode = if_mode;
2818
2819         msc_set_vcr(info);
2820
2821         /* TCR (tx control) 07  1=RTS driver control */
2822         val = rd_reg16(info, TCR);
2823         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2824                 val |= BIT7;
2825         else
2826                 val &= ~BIT7;
2827         wr_reg16(info, TCR, val);
2828
2829         spin_unlock_irqrestore(&info->lock,flags);
2830         return 0;
2831 }
2832
2833 /*
2834  * set general purpose IO pin state and direction
2835  *
2836  * user_gpio fields:
2837  * state   each bit indicates a pin state
2838  * smask   set bit indicates pin state to set
2839  * dir     each bit indicates a pin direction (0=input, 1=output)
2840  * dmask   set bit indicates pin direction to set
2841  */
2842 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2843 {
2844         unsigned long flags;
2845         struct gpio_desc gpio;
2846         __u32 data;
2847
2848         if (!info->gpio_present)
2849                 return -EINVAL;
2850         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2851                 return -EFAULT;
2852         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2853                  info->device_name, gpio.state, gpio.smask,
2854                  gpio.dir, gpio.dmask));
2855
2856         spin_lock_irqsave(&info->lock,flags);
2857         if (gpio.dmask) {
2858                 data = rd_reg32(info, IODR);
2859                 data |= gpio.dmask & gpio.dir;
2860                 data &= ~(gpio.dmask & ~gpio.dir);
2861                 wr_reg32(info, IODR, data);
2862         }
2863         if (gpio.smask) {
2864                 data = rd_reg32(info, IOVR);
2865                 data |= gpio.smask & gpio.state;
2866                 data &= ~(gpio.smask & ~gpio.state);
2867                 wr_reg32(info, IOVR, data);
2868         }
2869         spin_unlock_irqrestore(&info->lock,flags);
2870
2871         return 0;
2872 }
2873
2874 /*
2875  * get general purpose IO pin state and direction
2876  */
2877 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2878 {
2879         struct gpio_desc gpio;
2880         if (!info->gpio_present)
2881                 return -EINVAL;
2882         gpio.state = rd_reg32(info, IOVR);
2883         gpio.smask = 0xffffffff;
2884         gpio.dir   = rd_reg32(info, IODR);
2885         gpio.dmask = 0xffffffff;
2886         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2887                 return -EFAULT;
2888         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2889                  info->device_name, gpio.state, gpio.dir));
2890         return 0;
2891 }
2892
2893 /*
2894  * conditional wait facility
2895  */
2896 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2897 {
2898         init_waitqueue_head(&w->q);
2899         init_waitqueue_entry(&w->wait, current);
2900         w->data = data;
2901 }
2902
2903 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2904 {
2905         set_current_state(TASK_INTERRUPTIBLE);
2906         add_wait_queue(&w->q, &w->wait);
2907         w->next = *head;
2908         *head = w;
2909 }
2910
2911 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2912 {
2913         struct cond_wait *w, *prev;
2914         remove_wait_queue(&cw->q, &cw->wait);
2915         set_current_state(TASK_RUNNING);
2916         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2917                 if (w == cw) {
2918                         if (prev != NULL)
2919                                 prev->next = w->next;
2920                         else
2921                                 *head = w->next;
2922                         break;
2923                 }
2924         }
2925 }
2926
2927 static void flush_cond_wait(struct cond_wait **head)
2928 {
2929         while (*head != NULL) {
2930                 wake_up_interruptible(&(*head)->q);
2931                 *head = (*head)->next;
2932         }
2933 }
2934
2935 /*
2936  * wait for general purpose I/O pin(s) to enter specified state
2937  *
2938  * user_gpio fields:
2939  * state - bit indicates target pin state
2940  * smask - set bit indicates watched pin
2941  *
2942  * The wait ends when at least one watched pin enters the specified
2943  * state. When 0 (no error) is returned, user_gpio->state is set to the
2944  * state of all GPIO pins when the wait ends.
2945  *
2946  * Note: Each pin may be a dedicated input, dedicated output, or
2947  * configurable input/output. The number and configuration of pins
2948  * varies with the specific adapter model. Only input pins (dedicated
2949  * or configured) can be monitored with this function.
2950  */
2951 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2952 {
2953         unsigned long flags;
2954         int rc = 0;
2955         struct gpio_desc gpio;
2956         struct cond_wait wait;
2957         u32 state;
2958
2959         if (!info->gpio_present)
2960                 return -EINVAL;
2961         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2962                 return -EFAULT;
2963         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2964                  info->device_name, gpio.state, gpio.smask));
2965         /* ignore output pins identified by set IODR bit */
2966         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2967                 return -EINVAL;
2968         init_cond_wait(&wait, gpio.smask);
2969
2970         spin_lock_irqsave(&info->lock, flags);
2971         /* enable interrupts for watched pins */
2972         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2973         /* get current pin states */
2974         state = rd_reg32(info, IOVR);
2975
2976         if (gpio.smask & ~(state ^ gpio.state)) {
2977                 /* already in target state */
2978                 gpio.state = state;
2979         } else {
2980                 /* wait for target state */
2981                 add_cond_wait(&info->gpio_wait_q, &wait);
2982                 spin_unlock_irqrestore(&info->lock, flags);
2983                 schedule();
2984                 if (signal_pending(current))
2985                         rc = -ERESTARTSYS;
2986                 else
2987                         gpio.state = wait.data;
2988                 spin_lock_irqsave(&info->lock, flags);
2989                 remove_cond_wait(&info->gpio_wait_q, &wait);
2990         }
2991
2992         /* disable all GPIO interrupts if no waiting processes */
2993         if (info->gpio_wait_q == NULL)
2994                 wr_reg32(info, IOER, 0);
2995         spin_unlock_irqrestore(&info->lock,flags);
2996
2997         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2998                 rc = -EFAULT;
2999         return rc;
3000 }
3001
3002 static int modem_input_wait(struct slgt_info *info,int arg)
3003 {
3004         unsigned long flags;
3005         int rc;
3006         struct mgsl_icount cprev, cnow;
3007         DECLARE_WAITQUEUE(wait, current);
3008
3009         /* save current irq counts */
3010         spin_lock_irqsave(&info->lock,flags);
3011         cprev = info->icount;
3012         add_wait_queue(&info->status_event_wait_q, &wait);
3013         set_current_state(TASK_INTERRUPTIBLE);
3014         spin_unlock_irqrestore(&info->lock,flags);
3015
3016         for(;;) {
3017                 schedule();
3018                 if (signal_pending(current)) {
3019                         rc = -ERESTARTSYS;
3020                         break;
3021                 }
3022
3023                 /* get new irq counts */
3024                 spin_lock_irqsave(&info->lock,flags);
3025                 cnow = info->icount;
3026                 set_current_state(TASK_INTERRUPTIBLE);
3027                 spin_unlock_irqrestore(&info->lock,flags);
3028
3029                 /* if no change, wait aborted for some reason */
3030                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3031                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3032                         rc = -EIO;
3033                         break;
3034                 }
3035
3036                 /* check for change in caller specified modem input */
3037                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3038                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3039                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3040                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3041                         rc = 0;
3042                         break;
3043                 }
3044
3045                 cprev = cnow;
3046         }
3047         remove_wait_queue(&info->status_event_wait_q, &wait);
3048         set_current_state(TASK_RUNNING);
3049         return rc;
3050 }
3051
3052 /*
3053  *  return state of serial control and status signals
3054  */
3055 static int tiocmget(struct tty_struct *tty, struct file *file)
3056 {
3057         struct slgt_info *info = tty->driver_data;
3058         unsigned int result;
3059         unsigned long flags;
3060
3061         spin_lock_irqsave(&info->lock,flags);
3062         get_signals(info);
3063         spin_unlock_irqrestore(&info->lock,flags);
3064
3065         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3066                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3067                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3068                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3069                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3070                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3071
3072         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3073         return result;
3074 }
3075
3076 /*
3077  * set modem control signals (DTR/RTS)
3078  *
3079  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3080  *              TIOCMSET = set/clear signal values
3081  *      value   bit mask for command
3082  */
3083 static int tiocmset(struct tty_struct *tty, struct file *file,
3084                     unsigned int set, unsigned int clear)
3085 {
3086         struct slgt_info *info = tty->driver_data;
3087         unsigned long flags;
3088
3089         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3090
3091         if (set & TIOCM_RTS)
3092                 info->signals |= SerialSignal_RTS;
3093         if (set & TIOCM_DTR)
3094                 info->signals |= SerialSignal_DTR;
3095         if (clear & TIOCM_RTS)
3096                 info->signals &= ~SerialSignal_RTS;
3097         if (clear & TIOCM_DTR)
3098                 info->signals &= ~SerialSignal_DTR;
3099
3100         spin_lock_irqsave(&info->lock,flags);
3101         set_signals(info);
3102         spin_unlock_irqrestore(&info->lock,flags);
3103         return 0;
3104 }
3105
3106 /*
3107  *  block current process until the device is ready to open
3108  */
3109 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3110                            struct slgt_info *info)
3111 {
3112         DECLARE_WAITQUEUE(wait, current);
3113         int             retval;
3114         int             do_clocal = 0, extra_count = 0;
3115         unsigned long   flags;
3116
3117         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3118
3119         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3120                 /* nonblock mode is set or port is not enabled */
3121                 info->flags |= ASYNC_NORMAL_ACTIVE;
3122                 return 0;
3123         }
3124
3125         if (tty->termios->c_cflag & CLOCAL)
3126                 do_clocal = 1;
3127
3128         /* Wait for carrier detect and the line to become
3129          * free (i.e., not in use by the callout).  While we are in
3130          * this loop, info->count is dropped by one, so that
3131          * close() knows when to free things.  We restore it upon
3132          * exit, either normal or abnormal.
3133          */
3134
3135         retval = 0;
3136         add_wait_queue(&info->open_wait, &wait);
3137
3138         spin_lock_irqsave(&info->lock, flags);
3139         if (!tty_hung_up_p(filp)) {
3140                 extra_count = 1;
3141                 info->count--;
3142         }
3143         spin_unlock_irqrestore(&info->lock, flags);
3144         info->blocked_open++;
3145
3146         while (1) {
3147                 if ((tty->termios->c_cflag & CBAUD)) {
3148                         spin_lock_irqsave(&info->lock,flags);
3149                         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3150                         set_signals(info);
3151                         spin_unlock_irqrestore(&info->lock,flags);
3152                 }
3153
3154                 set_current_state(TASK_INTERRUPTIBLE);
3155
3156                 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3157                         retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3158                                         -EAGAIN : -ERESTARTSYS;
3159                         break;
3160                 }
3161
3162                 spin_lock_irqsave(&info->lock,flags);
3163                 get_signals(info);
3164                 spin_unlock_irqrestore(&info->lock,flags);
3165
3166                 if (!(info->flags & ASYNC_CLOSING) &&
3167                     (do_clocal || (info->signals & SerialSignal_DCD)) ) {
3168                         break;
3169                 }
3170
3171                 if (signal_pending(current)) {
3172                         retval = -ERESTARTSYS;
3173                         break;
3174                 }
3175
3176                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3177                 schedule();
3178         }
3179
3180         set_current_state(TASK_RUNNING);
3181         remove_wait_queue(&info->open_wait, &wait);
3182
3183         if (extra_count)
3184                 info->count++;
3185         info->blocked_open--;
3186
3187         if (!retval)
3188                 info->flags |= ASYNC_NORMAL_ACTIVE;
3189
3190         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3191         return retval;
3192 }
3193
3194 static int alloc_tmp_rbuf(struct slgt_info *info)
3195 {
3196         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3197         if (info->tmp_rbuf == NULL)
3198                 return -ENOMEM;
3199         return 0;
3200 }
3201
3202 static void free_tmp_rbuf(struct slgt_info *info)
3203 {
3204         kfree(info->tmp_rbuf);
3205         info->tmp_rbuf = NULL;
3206 }
3207
3208 /*
3209  * allocate DMA descriptor lists.
3210  */
3211 static int alloc_desc(struct slgt_info *info)
3212 {
3213         unsigned int i;
3214         unsigned int pbufs;
3215
3216         /* allocate memory to hold descriptor lists */
3217         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3218         if (info->bufs == NULL)
3219                 return -ENOMEM;
3220
3221         memset(info->bufs, 0, DESC_LIST_SIZE);
3222
3223         info->rbufs = (struct slgt_desc*)info->bufs;
3224         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3225
3226         pbufs = (unsigned int)info->bufs_dma_addr;
3227
3228         /*
3229          * Build circular lists of descriptors
3230          */
3231
3232         for (i=0; i < info->rbuf_count; i++) {
3233                 /* physical address of this descriptor */
3234                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3235
3236                 /* physical address of next descriptor */
3237                 if (i == info->rbuf_count - 1)
3238                         info->rbufs[i].next = cpu_to_le32(pbufs);
3239                 else
3240                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3241                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3242         }
3243
3244         for (i=0; i < info->tbuf_count; i++) {
3245                 /* physical address of this descriptor */
3246                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3247
3248                 /* physical address of next descriptor */
3249                 if (i == info->tbuf_count - 1)
3250                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3251                 else
3252                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3253         }
3254
3255         return 0;
3256 }
3257
3258 static void free_desc(struct slgt_info *info)
3259 {
3260         if (info->bufs != NULL) {
3261                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3262                 info->bufs  = NULL;
3263                 info->rbufs = NULL;
3264                 info->tbufs = NULL;
3265         }
3266 }
3267
3268 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3269 {
3270         int i;
3271         for (i=0; i < count; i++) {
3272                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3273                         return -ENOMEM;
3274                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3275         }
3276         return 0;
3277 }
3278
3279 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3280 {
3281         int i;
3282         for (i=0; i < count; i++) {
3283                 if (bufs[i].buf == NULL)
3284                         continue;
3285                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3286                 bufs[i].buf = NULL;
3287         }
3288 }
3289
3290 static int alloc_dma_bufs(struct slgt_info *info)
3291 {
3292         info->rbuf_count = 32;
3293         info->tbuf_count = 32;
3294
3295         if (alloc_desc(info) < 0 ||
3296             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3297             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3298             alloc_tmp_rbuf(info) < 0) {
3299                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3300                 return -ENOMEM;
3301         }
3302         reset_rbufs(info);
3303         return 0;
3304 }
3305
3306 static void free_dma_bufs(struct slgt_info *info)
3307 {
3308         if (info->bufs) {
3309                 free_bufs(info, info->rbufs, info->rbuf_count);
3310                 free_bufs(info, info->tbufs, info->tbuf_count);
3311                 free_desc(info);
3312         }
3313         free_tmp_rbuf(info);
3314 }
3315
3316 static int claim_resources(struct slgt_info *info)
3317 {
3318         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3319                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3320                         info->device_name, info->phys_reg_addr));
3321                 info->init_error = DiagStatus_AddressConflict;
3322                 goto errout;
3323         }
3324         else
3325                 info->reg_addr_requested = 1;
3326
3327         info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3328         if (!info->reg_addr) {
3329                 DBGERR(("%s cant map device registers, addr=%08X\n",
3330                         info->device_name, info->phys_reg_addr));
3331                 info->init_error = DiagStatus_CantAssignPciResources;
3332                 goto errout;
3333         }
3334         return 0;
3335
3336 errout:
3337         release_resources(info);
3338         return -ENODEV;
3339 }
3340
3341 static void release_resources(struct slgt_info *info)
3342 {
3343         if (info->irq_requested) {
3344                 free_irq(info->irq_level, info);
3345                 info->irq_requested = 0;
3346         }
3347
3348         if (info->reg_addr_requested) {
3349                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3350                 info->reg_addr_requested = 0;
3351         }
3352
3353         if (info->reg_addr) {
3354                 iounmap(info->reg_addr);
3355                 info->reg_addr = NULL;
3356         }
3357 }
3358
3359 /* Add the specified device instance data structure to the
3360  * global linked list of devices and increment the device count.
3361  */
3362 static void add_device(struct slgt_info *info)
3363 {
3364         char *devstr;
3365
3366         info->next_device = NULL;
3367         info->line = slgt_device_count;
3368         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3369
3370         if (info->line < MAX_DEVICES) {
3371                 if (maxframe[info->line])
3372                         info->max_frame_size = maxframe[info->line];
3373                 info->dosyncppp = dosyncppp[info->line];
3374         }
3375
3376         slgt_device_count++;
3377
3378         if (!slgt_device_list)
3379                 slgt_device_list = info;
3380         else {
3381                 struct slgt_info *current_dev = slgt_device_list;
3382                 while(current_dev->next_device)
3383                         current_dev = current_dev->next_device;
3384                 current_dev->next_device = info;
3385         }
3386
3387         if (info->max_frame_size < 4096)
3388                 info->max_frame_size = 4096;
3389         else if (info->max_frame_size > 65535)
3390                 info->max_frame_size = 65535;
3391
3392         switch(info->pdev->device) {
3393         case SYNCLINK_GT_DEVICE_ID:
3394                 devstr = "GT";
3395                 break;
3396         case SYNCLINK_GT2_DEVICE_ID:
3397                 devstr = "GT2";
3398                 break;
3399         case SYNCLINK_GT4_DEVICE_ID:
3400                 devstr = "GT4";
3401                 break;
3402         case SYNCLINK_AC_DEVICE_ID:
3403                 devstr = "AC";
3404                 info->params.mode = MGSL_MODE_ASYNC;
3405                 break;
3406         default:
3407                 devstr = "(unknown model)";
3408         }
3409         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3410                 devstr, info->device_name, info->phys_reg_addr,
3411                 info->irq_level, info->max_frame_size);
3412
3413 #if SYNCLINK_GENERIC_HDLC
3414         hdlcdev_init(info);
3415 #endif
3416 }
3417
3418 /*
3419  *  allocate device instance structure, return NULL on failure
3420  */
3421 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3422 {
3423         struct slgt_info *info;
3424
3425         info = kmalloc(sizeof(struct slgt_info), GFP_KERNEL);
3426
3427         if (!info) {
3428                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3429                         driver_name, adapter_num, port_num));
3430         } else {
3431                 memset(info, 0, sizeof(struct slgt_info));
3432                 info->magic = MGSL_MAGIC;
3433                 INIT_WORK(&info->task, bh_handler);
3434                 info->max_frame_size = 4096;
3435                 info->raw_rx_size = DMABUFSIZE;
3436                 info->close_delay = 5*HZ/10;
3437                 info->closing_wait = 30*HZ;
3438                 init_waitqueue_head(&info->open_wait);
3439                 init_waitqueue_head(&info->close_wait);
3440                 init_waitqueue_head(&info->status_event_wait_q);
3441                 init_waitqueue_head(&info->event_wait_q);
3442                 spin_lock_init(&info->netlock);
3443                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3444                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3445                 info->adapter_num = adapter_num;
3446                 info->port_num = port_num;
3447
3448                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3449                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3450
3451                 /* Copy configuration info to device instance data */
3452                 info->pdev = pdev;
3453                 info->irq_level = pdev->irq;
3454                 info->phys_reg_addr = pci_resource_start(pdev,0);
3455
3456                 info->bus_type = MGSL_BUS_TYPE_PCI;
3457                 info->irq_flags = IRQF_SHARED;
3458
3459                 info->init_error = -1; /* assume error, set to 0 on successful init */
3460         }
3461
3462         return info;
3463 }
3464
3465 static void device_init(int adapter_num, struct pci_dev *pdev)
3466 {
3467         struct slgt_info *port_array[SLGT_MAX_PORTS];
3468         int i;
3469         int port_count = 1;
3470
3471         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3472                 port_count = 2;
3473         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3474                 port_count = 4;
3475
3476         /* allocate device instances for all ports */
3477         for (i=0; i < port_count; ++i) {
3478                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3479                 if (port_array[i] == NULL) {
3480                         for (--i; i >= 0; --i)
3481                                 kfree(port_array[i]);
3482                         return;
3483                 }
3484         }
3485
3486         /* give copy of port_array to all ports and add to device list  */
3487         for (i=0; i < port_count; ++i) {
3488                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3489                 add_device(port_array[i]);
3490                 port_array[i]->port_count = port_count;
3491                 spin_lock_init(&port_array[i]->lock);
3492         }
3493
3494         /* Allocate and claim adapter resources */
3495         if (!claim_resources(port_array[0])) {
3496
3497                 alloc_dma_bufs(port_array[0]);
3498
3499                 /* copy resource information from first port to others */
3500                 for (i = 1; i < port_count; ++i) {
3501                         port_array[i]->lock      = port_array[0]->lock;
3502                         port_array[i]->irq_level = port_array[0]->irq_level;
3503                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3504                         alloc_dma_bufs(port_array[i]);
3505                 }
3506
3507                 if (request_irq(port_array[0]->irq_level,
3508                                         slgt_interrupt,
3509                                         port_array[0]->irq_flags,
3510                                         port_array[0]->device_name,
3511                                         port_array[0]) < 0) {
3512                         DBGERR(("%s request_irq failed IRQ=%d\n",
3513                                 port_array[0]->device_name,
3514                                 port_array[0]->irq_level));
3515                 } else {
3516                         port_array[0]->irq_requested = 1;
3517                         adapter_test(port_array[0]);
3518                         for (i=1 ; i < port_count ; i++) {
3519                                 port_array[i]->init_error = port_array[0]->init_error;
3520                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3521                         }
3522                 }
3523         }
3524
3525         for (i=0; i < port_count; ++i)
3526                 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3527 }
3528
3529 static int __devinit init_one(struct pci_dev *dev,
3530                               const struct pci_device_id *ent)
3531 {
3532         if (pci_enable_device(dev)) {
3533                 printk("error enabling pci device %p\n", dev);
3534                 return -EIO;
3535         }
3536         pci_set_master(dev);
3537         device_init(slgt_device_count, dev);
3538         return 0;
3539 }
3540
3541 static void __devexit remove_one(struct pci_dev *dev)
3542 {
3543 }
3544
3545 static const struct tty_operations ops = {
3546         .open = open,
3547         .close = close,
3548         .write = write,
3549         .put_char = put_char,
3550         .flush_chars = flush_chars,
3551         .write_room = write_room,
3552         .chars_in_buffer = chars_in_buffer,
3553         .flush_buffer = flush_buffer,
3554         .ioctl = ioctl,
3555         .compat_ioctl = slgt_compat_ioctl,
3556         .throttle = throttle,
3557         .unthrottle = unthrottle,
3558         .send_xchar = send_xchar,
3559         .break_ctl = set_break,
3560         .wait_until_sent = wait_until_sent,
3561         .read_proc = read_proc,
3562         .set_termios = set_termios,
3563         .stop = tx_hold,
3564         .start = tx_release,
3565         .hangup = hangup,
3566         .tiocmget = tiocmget,
3567         .tiocmset = tiocmset,
3568 };
3569
3570 static void slgt_cleanup(void)
3571 {
3572         int rc;
3573         struct slgt_info *info;
3574         struct slgt_info *tmp;
3575
3576         printk("unload %s %s\n", driver_name, driver_version);
3577
3578         if (serial_driver) {
3579                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3580                         tty_unregister_device(serial_driver, info->line);
3581                 if ((rc = tty_unregister_driver(serial_driver)))
3582                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3583                 put_tty_driver(serial_driver);
3584         }
3585
3586         /* reset devices */
3587         info = slgt_device_list;
3588         while(info) {
3589                 reset_port(info);
3590                 info = info->next_device;
3591         }
3592
3593         /* release devices */
3594         info = slgt_device_list;
3595         while(info) {
3596 #if SYNCLINK_GENERIC_HDLC
3597                 hdlcdev_exit(info);
3598 #endif
3599                 free_dma_bufs(info);
3600                 free_tmp_rbuf(info);
3601                 if (info->port_num == 0)
3602                         release_resources(info);
3603                 tmp = info;
3604                 info = info->next_device;
3605                 kfree(tmp);
3606         }
3607
3608         if (pci_registered)
3609                 pci_unregister_driver(&pci_driver);
3610 }
3611
3612 /*
3613  *  Driver initialization entry point.
3614  */
3615 static int __init slgt_init(void)
3616 {
3617         int rc;
3618
3619         printk("%s %s\n", driver_name, driver_version);
3620
3621         serial_driver = alloc_tty_driver(MAX_DEVICES);
3622         if (!serial_driver) {
3623                 printk("%s can't allocate tty driver\n", driver_name);
3624                 return -ENOMEM;
3625         }
3626
3627         /* Initialize the tty_driver structure */
3628
3629         serial_driver->owner = THIS_MODULE;
3630         serial_driver->driver_name = tty_driver_name;
3631         serial_driver->name = tty_dev_prefix;
3632         serial_driver->major = ttymajor;
3633         serial_driver->minor_start = 64;
3634         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3635         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3636         serial_driver->init_termios = tty_std_termios;
3637         serial_driver->init_termios.c_cflag =
3638                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3639         serial_driver->init_termios.c_ispeed = 9600;
3640         serial_driver->init_termios.c_ospeed = 9600;
3641         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3642         tty_set_operations(serial_driver, &ops);
3643         if ((rc = tty_register_driver(serial_driver)) < 0) {
3644                 DBGERR(("%s can't register serial driver\n", driver_name));
3645                 put_tty_driver(serial_driver);
3646                 serial_driver = NULL;
3647                 goto error;
3648         }
3649
3650         printk("%s %s, tty major#%d\n",
3651                 driver_name, driver_version,
3652                 serial_driver->major);
3653
3654         slgt_device_count = 0;
3655         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3656                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3657                 goto error;
3658         }
3659         pci_registered = 1;
3660
3661         if (!slgt_device_list)
3662                 printk("%s no devices found\n",driver_name);
3663
3664         return 0;
3665
3666 error:
3667         slgt_cleanup();
3668         return rc;
3669 }
3670
3671 static void __exit slgt_exit(void)
3672 {
3673         slgt_cleanup();
3674 }
3675
3676 module_init(slgt_init);
3677 module_exit(slgt_exit);
3678
3679 /*
3680  * register access routines
3681  */
3682
3683 #define CALC_REGADDR() \
3684         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3685         if (addr >= 0x80) \
3686                 reg_addr += (info->port_num) * 32;
3687
3688 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3689 {
3690         CALC_REGADDR();
3691         return readb((void __iomem *)reg_addr);
3692 }
3693
3694 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3695 {
3696         CALC_REGADDR();
3697         writeb(value, (void __iomem *)reg_addr);
3698 }
3699
3700 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3701 {
3702         CALC_REGADDR();
3703         return readw((void __iomem *)reg_addr);
3704 }
3705
3706 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3707 {
3708         CALC_REGADDR();
3709         writew(value, (void __iomem *)reg_addr);
3710 }
3711
3712 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3713 {
3714         CALC_REGADDR();
3715         return readl((void __iomem *)reg_addr);
3716 }
3717
3718 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3719 {
3720         CALC_REGADDR();
3721         writel(value, (void __iomem *)reg_addr);
3722 }
3723
3724 static void rdma_reset(struct slgt_info *info)
3725 {
3726         unsigned int i;
3727
3728         /* set reset bit */
3729         wr_reg32(info, RDCSR, BIT1);
3730
3731         /* wait for enable bit cleared */
3732         for(i=0 ; i < 1000 ; i++)
3733                 if (!(rd_reg32(info, RDCSR) & BIT0))
3734                         break;
3735 }
3736
3737 static void tdma_reset(struct slgt_info *info)
3738 {
3739         unsigned int i;
3740
3741         /* set reset bit */
3742         wr_reg32(info, TDCSR, BIT1);
3743
3744         /* wait for enable bit cleared */
3745         for(i=0 ; i < 1000 ; i++)
3746                 if (!(rd_reg32(info, TDCSR) & BIT0))
3747                         break;
3748 }
3749
3750 /*
3751  * enable internal loopback
3752  * TxCLK and RxCLK are generated from BRG
3753  * and TxD is looped back to RxD internally.
3754  */
3755 static void enable_loopback(struct slgt_info *info)
3756 {
3757         /* SCR (serial control) BIT2=looopback enable */
3758         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3759
3760         if (info->params.mode != MGSL_MODE_ASYNC) {
3761                 /* CCR (clock control)
3762                  * 07..05  tx clock source (010 = BRG)
3763                  * 04..02  rx clock source (010 = BRG)
3764                  * 01      auxclk enable   (0 = disable)
3765                  * 00      BRG enable      (1 = enable)
3766                  *
3767                  * 0100 1001
3768                  */
3769                 wr_reg8(info, CCR, 0x49);
3770
3771                 /* set speed if available, otherwise use default */
3772                 if (info->params.clock_speed)
3773                         set_rate(info, info->params.clock_speed);
3774                 else
3775                         set_rate(info, 3686400);
3776         }
3777 }
3778
3779 /*
3780  *  set baud rate generator to specified rate
3781  */
3782 static void set_rate(struct slgt_info *info, u32 rate)
3783 {
3784         unsigned int div;
3785         static unsigned int osc = 14745600;
3786
3787         /* div = osc/rate - 1
3788          *
3789          * Round div up if osc/rate is not integer to
3790          * force to next slowest rate.
3791          */
3792
3793         if (rate) {
3794                 div = osc/rate;
3795                 if (!(osc % rate) && div)
3796                         div--;
3797                 wr_reg16(info, BDR, (unsigned short)div);
3798         }
3799 }
3800
3801 static void rx_stop(struct slgt_info *info)
3802 {
3803         unsigned short val;
3804
3805         /* disable and reset receiver */
3806         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3807         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3808         wr_reg16(info, RCR, val);                  /* clear reset bit */
3809
3810         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3811
3812         /* clear pending rx interrupts */
3813         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3814
3815         rdma_reset(info);
3816
3817         info->rx_enabled = 0;
3818         info->rx_restart = 0;
3819 }
3820
3821 static void rx_start(struct slgt_info *info)
3822 {
3823         unsigned short val;
3824
3825         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3826
3827         /* clear pending rx overrun IRQ */
3828         wr_reg16(info, SSR, IRQ_RXOVER);
3829
3830         /* reset and disable receiver */
3831         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3832         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3833         wr_reg16(info, RCR, val);                  /* clear reset bit */
3834
3835         rdma_reset(info);
3836         reset_rbufs(info);
3837
3838         /* set 1st descriptor address */
3839         wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3840
3841         if (info->params.mode != MGSL_MODE_ASYNC) {
3842                 /* enable rx DMA and DMA interrupt */
3843                 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3844         } else {
3845                 /* enable saving of rx status, rx DMA and DMA interrupt */
3846                 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3847         }
3848
3849         slgt_irq_on(info, IRQ_RXOVER);
3850
3851         /* enable receiver */
3852         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3853
3854         info->rx_restart = 0;
3855         info->rx_enabled = 1;
3856 }
3857
3858 static void tx_start(struct slgt_info *info)
3859 {
3860         if (!info->tx_enabled) {
3861                 wr_reg16(info, TCR,
3862                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3863                 info->tx_enabled = TRUE;
3864         }
3865
3866         if (info->tx_count) {
3867                 info->drop_rts_on_tx_done = 0;
3868
3869                 if (info->params.mode != MGSL_MODE_ASYNC) {
3870                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3871                                 get_signals(info);
3872                                 if (!(info->signals & SerialSignal_RTS)) {
3873                                         info->signals |= SerialSignal_RTS;
3874                                         set_signals(info);
3875                                         info->drop_rts_on_tx_done = 1;
3876                                 }
3877                         }
3878
3879                         slgt_irq_off(info, IRQ_TXDATA);
3880                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3881                         /* clear tx idle and underrun status bits */
3882                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3883
3884                         if (!(rd_reg32(info, TDCSR) & BIT0)) {
3885                                 /* tx DMA stopped, restart tx DMA */
3886                                 tdma_reset(info);
3887                                 /* set 1st descriptor address */
3888                                 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3889                                 switch(info->params.mode) {
3890                                 case MGSL_MODE_RAW:
3891                                 case MGSL_MODE_MONOSYNC:
3892                                 case MGSL_MODE_BISYNC:
3893                                         wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3894                                         break;
3895                                 default:
3896                                         wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3897                                 }
3898                         }
3899
3900                         if (info->params.mode == MGSL_MODE_HDLC)
3901                                 mod_timer(&info->tx_timer, jiffies +
3902                                                 msecs_to_jiffies(5000));
3903                 } else {
3904                         tdma_reset(info);
3905                         /* set 1st descriptor address */
3906                         wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3907
3908                         slgt_irq_off(info, IRQ_TXDATA);
3909                         slgt_irq_on(info, IRQ_TXIDLE);
3910                         /* clear tx idle status bit */
3911                         wr_reg16(info, SSR, IRQ_TXIDLE);
3912
3913                         /* enable tx DMA */
3914                         wr_reg32(info, TDCSR, BIT0);
3915                 }
3916
3917                 info->tx_active = 1;
3918         }
3919 }
3920
3921 static void tx_stop(struct slgt_info *info)
3922 {
3923         unsigned short val;
3924
3925         del_timer(&info->tx_timer);
3926
3927         tdma_reset(info);
3928
3929         /* reset and disable transmitter */
3930         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
3931         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3932
3933         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3934
3935         /* clear tx idle and underrun status bit */
3936         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3937
3938         reset_tbufs(info);
3939
3940         info->tx_enabled = 0;
3941         info->tx_active  = 0;
3942 }
3943
3944 static void reset_port(struct slgt_info *info)
3945 {
3946         if (!info->reg_addr)
3947                 return;
3948
3949         tx_stop(info);
3950         rx_stop(info);
3951
3952         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3953         set_signals(info);
3954
3955         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3956 }
3957
3958 static void reset_adapter(struct slgt_info *info)
3959 {
3960         int i;
3961         for (i=0; i < info->port_count; ++i) {
3962                 if (info->port_array[i])
3963                         reset_port(info->port_array[i]);
3964         }
3965 }
3966
3967 static void async_mode(struct slgt_info *info)
3968 {
3969         unsigned short val;
3970
3971         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3972         tx_stop(info);
3973         rx_stop(info);
3974
3975         /* TCR (tx control)
3976          *
3977          * 15..13  mode, 010=async
3978          * 12..10  encoding, 000=NRZ
3979          * 09      parity enable
3980          * 08      1=odd parity, 0=even parity
3981          * 07      1=RTS driver control
3982          * 06      1=break enable
3983          * 05..04  character length
3984          *         00=5 bits
3985          *         01=6 bits
3986          *         10=7 bits
3987          *         11=8 bits
3988          * 03      0=1 stop bit, 1=2 stop bits
3989          * 02      reset
3990          * 01      enable
3991          * 00      auto-CTS enable
3992          */
3993         val = 0x4000;
3994
3995         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
3996                 val |= BIT7;
3997
3998         if (info->params.parity != ASYNC_PARITY_NONE) {
3999                 val |= BIT9;
4000                 if (info->params.parity == ASYNC_PARITY_ODD)
4001                         val |= BIT8;
4002         }
4003
4004         switch (info->params.data_bits)
4005         {
4006         case 6: val |= BIT4; break;
4007         case 7: val |= BIT5; break;
4008         case 8: val |= BIT5 + BIT4; break;
4009         }
4010
4011         if (info->params.stop_bits != 1)
4012                 val |= BIT3;
4013
4014         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4015                 val |= BIT0;
4016
4017         wr_reg16(info, TCR, val);
4018
4019         /* RCR (rx control)
4020          *
4021          * 15..13  mode, 010=async
4022          * 12..10  encoding, 000=NRZ
4023          * 09      parity enable
4024          * 08      1=odd parity, 0=even parity
4025          * 07..06  reserved, must be 0
4026          * 05..04  character length
4027          *         00=5 bits
4028          *         01=6 bits
4029          *         10=7 bits
4030          *         11=8 bits
4031          * 03      reserved, must be zero
4032          * 02      reset
4033          * 01      enable
4034          * 00      auto-DCD enable
4035          */
4036         val = 0x4000;
4037
4038         if (info->params.parity != ASYNC_PARITY_NONE) {
4039                 val |= BIT9;
4040                 if (info->params.parity == ASYNC_PARITY_ODD)
4041                         val |= BIT8;
4042         }
4043
4044         switch (info->params.data_bits)
4045         {
4046         case 6: val |= BIT4; break;
4047         case 7: val |= BIT5; break;
4048         case 8: val |= BIT5 + BIT4; break;
4049         }
4050
4051         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4052                 val |= BIT0;
4053
4054         wr_reg16(info, RCR, val);
4055
4056         /* CCR (clock control)
4057          *
4058          * 07..05  011 = tx clock source is BRG/16
4059          * 04..02  010 = rx clock source is BRG
4060          * 01      0 = auxclk disabled
4061          * 00      1 = BRG enabled
4062          *
4063          * 0110 1001
4064          */
4065         wr_reg8(info, CCR, 0x69);
4066
4067         msc_set_vcr(info);
4068
4069         /* SCR (serial control)
4070          *
4071          * 15  1=tx req on FIFO half empty
4072          * 14  1=rx req on FIFO half full
4073          * 13  tx data  IRQ enable
4074          * 12  tx idle  IRQ enable
4075          * 11  rx break on IRQ enable
4076          * 10  rx data  IRQ enable
4077          * 09  rx break off IRQ enable
4078          * 08  overrun  IRQ enable
4079          * 07  DSR      IRQ enable
4080          * 06  CTS      IRQ enable
4081          * 05  DCD      IRQ enable
4082          * 04  RI       IRQ enable
4083          * 03  reserved, must be zero
4084          * 02  1=txd->rxd internal loopback enable
4085          * 01  reserved, must be zero
4086          * 00  1=master IRQ enable
4087          */
4088         val = BIT15 + BIT14 + BIT0;
4089         wr_reg16(info, SCR, val);
4090
4091         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4092
4093         set_rate(info, info->params.data_rate * 16);
4094
4095         if (info->params.loopback)
4096                 enable_loopback(info);
4097 }
4098
4099 static void sync_mode(struct slgt_info *info)
4100 {
4101         unsigned short val;
4102
4103         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4104         tx_stop(info);
4105         rx_stop(info);
4106
4107         /* TCR (tx control)
4108          *
4109          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4110          * 12..10  encoding
4111          * 09      CRC enable
4112          * 08      CRC32
4113          * 07      1=RTS driver control
4114          * 06      preamble enable
4115          * 05..04  preamble length
4116          * 03      share open/close flag
4117          * 02      reset
4118          * 01      enable
4119          * 00      auto-CTS enable
4120          */
4121         val = 0;
4122
4123         switch(info->params.mode) {
4124         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4125         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4126         case MGSL_MODE_RAW:      val |= BIT13; break;
4127         }
4128         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4129                 val |= BIT7;
4130
4131         switch(info->params.encoding)
4132         {
4133         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4134         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4135         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4136         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4137         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4138         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4139         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4140         }
4141
4142         switch (info->params.crc_type & HDLC_CRC_MASK)
4143         {
4144         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4145         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4146         }
4147
4148         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4149                 val |= BIT6;
4150
4151         switch (info->params.preamble_length)
4152         {
4153         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4154         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4155         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4156         }
4157
4158         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4159                 val |= BIT0;
4160
4161         wr_reg16(info, TCR, val);
4162
4163         /* TPR (transmit preamble) */
4164
4165         switch (info->params.preamble)
4166         {
4167         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4168         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4169         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4170         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4171         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4172         default:                          val = 0x7e; break;
4173         }
4174         wr_reg8(info, TPR, (unsigned char)val);
4175
4176         /* RCR (rx control)
4177          *
4178          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4179          * 12..10  encoding
4180          * 09      CRC enable
4181          * 08      CRC32
4182          * 07..03  reserved, must be 0
4183          * 02      reset
4184          * 01      enable
4185          * 00      auto-DCD enable
4186          */
4187         val = 0;
4188
4189         switch(info->params.mode) {
4190         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4191         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4192         case MGSL_MODE_RAW:      val |= BIT13; break;
4193         }
4194
4195         switch(info->params.encoding)
4196         {
4197         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4198         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4199         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4200         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4201         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4202         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4203         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4204         }
4205
4206         switch (info->params.crc_type & HDLC_CRC_MASK)
4207         {
4208         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4209         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4210         }
4211
4212         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4213                 val |= BIT0;
4214
4215         wr_reg16(info, RCR, val);
4216
4217         /* CCR (clock control)
4218          *
4219          * 07..05  tx clock source
4220          * 04..02  rx clock source
4221          * 01      auxclk enable
4222          * 00      BRG enable
4223          */
4224         val = 0;
4225
4226         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4227         {
4228                 // when RxC source is DPLL, BRG generates 16X DPLL
4229                 // reference clock, so take TxC from BRG/16 to get
4230                 // transmit clock at actual data rate
4231                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4232                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4233                 else
4234                         val |= BIT6;    /* 010, txclk = BRG */
4235         }
4236         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4237                 val |= BIT7;    /* 100, txclk = DPLL Input */
4238         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4239                 val |= BIT5;    /* 001, txclk = RXC Input */
4240
4241         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4242                 val |= BIT3;    /* 010, rxclk = BRG */
4243         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4244                 val |= BIT4;    /* 100, rxclk = DPLL */
4245         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4246                 val |= BIT2;    /* 001, rxclk = TXC Input */
4247
4248         if (info->params.clock_speed)
4249                 val |= BIT1 + BIT0;
4250
4251         wr_reg8(info, CCR, (unsigned char)val);
4252
4253         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4254         {
4255                 // program DPLL mode
4256                 switch(info->params.encoding)
4257                 {
4258                 case HDLC_ENCODING_BIPHASE_MARK:
4259                 case HDLC_ENCODING_BIPHASE_SPACE:
4260                         val = BIT7; break;
4261                 case HDLC_ENCODING_BIPHASE_LEVEL:
4262                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4263                         val = BIT7 + BIT6; break;
4264                 default: val = BIT6;    // NRZ encodings
4265                 }
4266                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4267
4268                 // DPLL requires a 16X reference clock from BRG
4269                 set_rate(info, info->params.clock_speed * 16);
4270         }
4271         else
4272                 set_rate(info, info->params.clock_speed);
4273
4274         tx_set_idle(info);
4275
4276         msc_set_vcr(info);
4277
4278         /* SCR (serial control)
4279          *
4280          * 15  1=tx req on FIFO half empty
4281          * 14  1=rx req on FIFO half full
4282          * 13  tx data  IRQ enable
4283          * 12  tx idle  IRQ enable
4284          * 11  underrun IRQ enable
4285          * 10  rx data  IRQ enable
4286          * 09  rx idle  IRQ enable
4287          * 08  overrun  IRQ enable
4288          * 07  DSR      IRQ enable
4289          * 06  CTS      IRQ enable
4290          * 05  DCD      IRQ enable
4291          * 04  RI       IRQ enable
4292          * 03  reserved, must be zero
4293          * 02  1=txd->rxd internal loopback enable
4294          * 01  reserved, must be zero
4295          * 00  1=master IRQ enable
4296          */
4297         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4298
4299         if (info->params.loopback)
4300                 enable_loopback(info);
4301 }
4302
4303 /*
4304  *  set transmit idle mode
4305  */
4306 static void tx_set_idle(struct slgt_info *info)
4307 {
4308         unsigned char val;
4309         unsigned short tcr;
4310
4311         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4312          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4313          */
4314         tcr = rd_reg16(info, TCR);
4315         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4316                 /* disable preamble, set idle size to 16 bits */
4317                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4318                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4319                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4320         } else if (!(tcr & BIT6)) {
4321                 /* preamble is disabled, set idle size to 8 bits */
4322                 tcr &= ~(BIT5 + BIT4);
4323         }
4324         wr_reg16(info, TCR, tcr);
4325
4326         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4327                 /* LSB of custom tx idle specified in tx idle register */
4328                 val = (unsigned char)(info->idle_mode & 0xff);
4329         } else {
4330                 /* standard 8 bit idle patterns */
4331                 switch(info->idle_mode)
4332                 {
4333                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4334                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4335                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4336                 case HDLC_TXIDLE_ZEROS:
4337                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4338                 default:                         val = 0xff;
4339                 }
4340         }
4341
4342         wr_reg8(info, TIR, val);
4343 }
4344
4345 /*
4346  * get state of V24 status (input) signals
4347  */
4348 static void get_signals(struct slgt_info *info)
4349 {
4350         unsigned short status = rd_reg16(info, SSR);
4351
4352         /* clear all serial signals except DTR and RTS */
4353         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4354
4355         if (status & BIT3)
4356                 info->signals |= SerialSignal_DSR;
4357         if (status & BIT2)
4358                 info->signals |= SerialSignal_CTS;
4359         if (status & BIT1)
4360                 info->signals |= SerialSignal_DCD;
4361         if (status & BIT0)
4362                 info->signals |= SerialSignal_RI;
4363 }
4364
4365 /*
4366  * set V.24 Control Register based on current configuration
4367  */
4368 static void msc_set_vcr(struct slgt_info *info)
4369 {
4370         unsigned char val = 0;
4371
4372         /* VCR (V.24 control)
4373          *
4374          * 07..04  serial IF select
4375          * 03      DTR
4376          * 02      RTS
4377          * 01      LL
4378          * 00      RL
4379          */
4380
4381         switch(info->if_mode & MGSL_INTERFACE_MASK)
4382         {
4383         case MGSL_INTERFACE_RS232:
4384                 val |= BIT5; /* 0010 */
4385                 break;
4386         case MGSL_INTERFACE_V35:
4387                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4388                 break;
4389         case MGSL_INTERFACE_RS422:
4390                 val |= BIT6; /* 0100 */
4391                 break;
4392         }
4393
4394         if (info->signals & SerialSignal_DTR)
4395                 val |= BIT3;
4396         if (info->signals & SerialSignal_RTS)
4397                 val |= BIT2;
4398         if (info->if_mode & MGSL_INTERFACE_LL)
4399                 val |= BIT1;
4400         if (info->if_mode & MGSL_INTERFACE_RL)
4401                 val |= BIT0;
4402         wr_reg8(info, VCR, val);
4403 }
4404
4405 /*
4406  * set state of V24 control (output) signals
4407  */
4408 static void set_signals(struct slgt_info *info)
4409 {
4410         unsigned char val = rd_reg8(info, VCR);
4411         if (info->signals & SerialSignal_DTR)
4412                 val |= BIT3;
4413         else
4414                 val &= ~BIT3;
4415         if (info->signals & SerialSignal_RTS)
4416                 val |= BIT2;
4417         else
4418                 val &= ~BIT2;
4419         wr_reg8(info, VCR, val);
4420 }
4421
4422 /*
4423  * free range of receive DMA buffers (i to last)
4424  */
4425 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4426 {
4427         int done = 0;
4428
4429         while(!done) {
4430                 /* reset current buffer for reuse */
4431                 info->rbufs[i].status = 0;
4432                 switch(info->params.mode) {
4433                 case MGSL_MODE_RAW:
4434                 case MGSL_MODE_MONOSYNC:
4435                 case MGSL_MODE_BISYNC:
4436                         set_desc_count(info->rbufs[i], info->raw_rx_size);
4437                         break;
4438                 default:
4439                         set_desc_count(info->rbufs[i], DMABUFSIZE);
4440                 }
4441
4442                 if (i == last)
4443                         done = 1;
4444                 if (++i == info->rbuf_count)
4445                         i = 0;
4446         }
4447         info->rbuf_current = i;
4448 }
4449
4450 /*
4451  * mark all receive DMA buffers as free
4452  */
4453 static void reset_rbufs(struct slgt_info *info)
4454 {
4455         free_rbufs(info, 0, info->rbuf_count - 1);
4456 }
4457
4458 /*
4459  * pass receive HDLC frame to upper layer
4460  *
4461  * return 1 if frame available, otherwise 0
4462  */
4463 static int rx_get_frame(struct slgt_info *info)
4464 {
4465         unsigned int start, end;
4466         unsigned short status;
4467         unsigned int framesize = 0;
4468         int rc = 0;
4469         unsigned long flags;
4470         struct tty_struct *tty = info->tty;
4471         unsigned char addr_field = 0xff;
4472         unsigned int crc_size = 0;
4473
4474         switch (info->params.crc_type & HDLC_CRC_MASK) {
4475         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4476         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4477         }
4478
4479 check_again:
4480
4481         framesize = 0;
4482         addr_field = 0xff;
4483         start = end = info->rbuf_current;
4484
4485         for (;;) {
4486                 if (!desc_complete(info->rbufs[end]))
4487                         goto cleanup;
4488
4489                 if (framesize == 0 && info->params.addr_filter != 0xff)
4490                         addr_field = info->rbufs[end].buf[0];
4491
4492                 framesize += desc_count(info->rbufs[end]);
4493
4494                 if (desc_eof(info->rbufs[end]))
4495                         break;
4496
4497                 if (++end == info->rbuf_count)
4498                         end = 0;
4499
4500                 if (end == info->rbuf_current) {
4501                         if (info->rx_enabled){
4502                                 spin_lock_irqsave(&info->lock,flags);
4503                                 rx_start(info);
4504                                 spin_unlock_irqrestore(&info->lock,flags);
4505                         }
4506                         goto cleanup;
4507                 }
4508         }
4509
4510         /* status
4511          *
4512          * 15      buffer complete
4513          * 14..06  reserved
4514          * 05..04  residue
4515          * 02      eof (end of frame)
4516          * 01      CRC error
4517          * 00      abort
4518          */
4519         status = desc_status(info->rbufs[end]);
4520
4521         /* ignore CRC bit if not using CRC (bit is undefined) */
4522         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4523                 status &= ~BIT1;
4524
4525         if (framesize == 0 ||
4526                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4527                 free_rbufs(info, start, end);
4528                 goto check_again;
4529         }
4530
4531         if (framesize < (2 + crc_size) || status & BIT0) {
4532                 info->icount.rxshort++;
4533                 framesize = 0;
4534         } else if (status & BIT1) {
4535                 info->icount.rxcrc++;
4536                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4537                         framesize = 0;
4538         }
4539
4540 #if SYNCLINK_GENERIC_HDLC
4541         if (framesize == 0) {
4542                 struct net_device_stats *stats = hdlc_stats(info->netdev);
4543                 stats->rx_errors++;
4544                 stats->rx_frame_errors++;
4545         }
4546 #endif
4547
4548         DBGBH(("%s rx frame status=%04X size=%d\n",
4549                 info->device_name, status, framesize));
4550         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4551
4552         if (framesize) {
4553                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4554                         framesize -= crc_size;
4555                         crc_size = 0;
4556                 }
4557
4558                 if (framesize > info->max_frame_size + crc_size)
4559                         info->icount.rxlong++;
4560                 else {
4561                         /* copy dma buffer(s) to contiguous temp buffer */
4562                         int copy_count = framesize;
4563                         int i = start;
4564                         unsigned char *p = info->tmp_rbuf;
4565                         info->tmp_rbuf_count = framesize;
4566
4567                         info->icount.rxok++;
4568
4569                         while(copy_count) {
4570                                 int partial_count = min(copy_count, DMABUFSIZE);
4571                                 memcpy(p, info->rbufs[i].buf, partial_count);
4572                                 p += partial_count;
4573                                 copy_count -= partial_count;
4574                                 if (++i == info->rbuf_count)
4575                                         i = 0;
4576                         }
4577
4578                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4579                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4580                                 framesize++;
4581                         }
4582
4583 #if SYNCLINK_GENERIC_HDLC
4584                         if (info->netcount)
4585                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4586                         else
4587 #endif
4588                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4589                 }
4590         }
4591         free_rbufs(info, start, end);
4592         rc = 1;
4593
4594 cleanup:
4595         return rc;
4596 }
4597
4598 /*
4599  * pass receive buffer (RAW synchronous mode) to tty layer
4600  * return 1 if buffer available, otherwise 0
4601  */
4602 static int rx_get_buf(struct slgt_info *info)
4603 {
4604         unsigned int i = info->rbuf_current;
4605         unsigned int count;
4606
4607         if (!desc_complete(info->rbufs[i]))
4608                 return 0;
4609         count = desc_count(info->rbufs[i]);
4610         switch(info->params.mode) {
4611         case MGSL_MODE_MONOSYNC:
4612         case MGSL_MODE_BISYNC:
4613                 /* ignore residue in byte synchronous modes */
4614                 if (desc_residue(info->rbufs[i]))
4615                         count--;
4616                 break;
4617         }
4618         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4619         DBGINFO(("rx_get_buf size=%d\n", count));
4620         if (count)
4621                 ldisc_receive_buf(info->tty, info->rbufs[i].buf,
4622                                   info->flag_buf, count);
4623         free_rbufs(info, i, i);
4624         return 1;
4625 }
4626
4627 static void reset_tbufs(struct slgt_info *info)
4628 {
4629         unsigned int i;
4630         info->tbuf_current = 0;
4631         for (i=0 ; i < info->tbuf_count ; i++) {
4632                 info->tbufs[i].status = 0;
4633                 info->tbufs[i].count  = 0;
4634         }
4635 }
4636
4637 /*
4638  * return number of free transmit DMA buffers
4639  */
4640 static unsigned int free_tbuf_count(struct slgt_info *info)
4641 {
4642         unsigned int count = 0;
4643         unsigned int i = info->tbuf_current;
4644
4645         do
4646         {
4647                 if (desc_count(info->tbufs[i]))
4648                         break; /* buffer in use */
4649                 ++count;
4650                 if (++i == info->tbuf_count)
4651                         i=0;
4652         } while (i != info->tbuf_current);
4653
4654         /* last buffer with zero count may be in use, assume it is */
4655         if (count)
4656                 --count;
4657
4658         return count;
4659 }
4660
4661 /*
4662  * load transmit DMA buffer(s) with data
4663  */
4664 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4665 {
4666         unsigned short count;
4667         unsigned int i;
4668         struct slgt_desc *d;
4669
4670         if (size == 0)
4671                 return;
4672
4673         DBGDATA(info, buf, size, "tx");
4674
4675         info->tbuf_start = i = info->tbuf_current;
4676
4677         while (size) {
4678                 d = &info->tbufs[i];
4679                 if (++i == info->tbuf_count)
4680                         i = 0;
4681
4682                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4683                 memcpy(d->buf, buf, count);
4684
4685                 size -= count;
4686                 buf  += count;
4687
4688                 /*
4689                  * set EOF bit for last buffer of HDLC frame or
4690                  * for every buffer in raw mode
4691                  */
4692                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4693                     info->params.mode == MGSL_MODE_RAW)
4694                         set_desc_eof(*d, 1);
4695                 else
4696                         set_desc_eof(*d, 0);
4697
4698                 set_desc_count(*d, count);
4699         }
4700
4701         info->tbuf_current = i;
4702 }
4703
4704 static int register_test(struct slgt_info *info)
4705 {
4706         static unsigned short patterns[] =
4707                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4708         static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4709         unsigned int i;
4710         int rc = 0;
4711
4712         for (i=0 ; i < count ; i++) {
4713                 wr_reg16(info, TIR, patterns[i]);
4714                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4715                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4716                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4717                         rc = -ENODEV;
4718                         break;
4719                 }
4720         }
4721         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4722         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4723         return rc;
4724 }
4725
4726 static int irq_test(struct slgt_info *info)
4727 {
4728         unsigned long timeout;
4729         unsigned long flags;
4730         struct tty_struct *oldtty = info->tty;
4731         u32 speed = info->params.data_rate;
4732
4733         info->params.data_rate = 921600;
4734         info->tty = NULL;
4735
4736         spin_lock_irqsave(&info->lock, flags);
4737         async_mode(info);
4738         slgt_irq_on(info, IRQ_TXIDLE);
4739
4740         /* enable transmitter */
4741         wr_reg16(info, TCR,
4742                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4743
4744         /* write one byte and wait for tx idle */
4745         wr_reg16(info, TDR, 0);
4746
4747         /* assume failure */
4748         info->init_error = DiagStatus_IrqFailure;
4749         info->irq_occurred = FALSE;
4750
4751         spin_unlock_irqrestore(&info->lock, flags);
4752
4753         timeout=100;
4754         while(timeout-- && !info->irq_occurred)
4755                 msleep_interruptible(10);
4756
4757         spin_lock_irqsave(&info->lock,flags);
4758         reset_port(info);
4759         spin_unlock_irqrestore(&info->lock,flags);
4760
4761         info->params.data_rate = speed;
4762         info->tty = oldtty;
4763
4764         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4765         return info->irq_occurred ? 0 : -ENODEV;
4766 }
4767
4768 static int loopback_test_rx(struct slgt_info *info)
4769 {
4770         unsigned char *src, *dest;
4771         int count;
4772
4773         if (desc_complete(info->rbufs[0])) {
4774                 count = desc_count(info->rbufs[0]);
4775                 src   = info->rbufs[0].buf;
4776                 dest  = info->tmp_rbuf;
4777
4778                 for( ; count ; count-=2, src+=2) {
4779                         /* src=data byte (src+1)=status byte */
4780                         if (!(*(src+1) & (BIT9 + BIT8))) {
4781                                 *dest = *src;
4782                                 dest++;
4783                                 info->tmp_rbuf_count++;
4784                         }
4785                 }
4786                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4787                 return 1;
4788         }
4789         return 0;
4790 }
4791
4792 static int loopback_test(struct slgt_info *info)
4793 {
4794 #define TESTFRAMESIZE 20
4795
4796         unsigned long timeout;
4797         u16 count = TESTFRAMESIZE;
4798         unsigned char buf[TESTFRAMESIZE];
4799         int rc = -ENODEV;
4800         unsigned long flags;
4801
4802         struct tty_struct *oldtty = info->tty;
4803         MGSL_PARAMS params;
4804
4805         memcpy(&params, &info->params, sizeof(params));
4806
4807         info->params.mode = MGSL_MODE_ASYNC;
4808         info->params.data_rate = 921600;
4809         info->params.loopback = 1;
4810         info->tty = NULL;
4811
4812         /* build and send transmit frame */
4813         for (count = 0; count < TESTFRAMESIZE; ++count)
4814                 buf[count] = (unsigned char)count;
4815
4816         info->tmp_rbuf_count = 0;
4817         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4818
4819         /* program hardware for HDLC and enabled receiver */
4820         spin_lock_irqsave(&info->lock,flags);
4821         async_mode(info);
4822         rx_start(info);
4823         info->tx_count = count;
4824         tx_load(info, buf, count);
4825         tx_start(info);
4826         spin_unlock_irqrestore(&info->lock, flags);
4827
4828         /* wait for receive complete */
4829         for (timeout = 100; timeout; --timeout) {
4830                 msleep_interruptible(10);
4831                 if (loopback_test_rx(info)) {
4832                         rc = 0;
4833                         break;
4834                 }
4835         }
4836
4837         /* verify received frame length and contents */
4838         if (!rc && (info->tmp_rbuf_count != count ||
4839                   memcmp(buf, info->tmp_rbuf, count))) {
4840                 rc = -ENODEV;
4841         }
4842
4843         spin_lock_irqsave(&info->lock,flags);
4844         reset_adapter(info);
4845         spin_unlock_irqrestore(&info->lock,flags);
4846
4847         memcpy(&info->params, &params, sizeof(info->params));
4848         info->tty = oldtty;
4849
4850         info->init_error = rc ? DiagStatus_DmaFailure : 0;
4851         return rc;
4852 }
4853
4854 static int adapter_test(struct slgt_info *info)
4855 {
4856         DBGINFO(("testing %s\n", info->device_name));
4857         if (register_test(info) < 0) {
4858                 printk("register test failure %s addr=%08X\n",
4859                         info->device_name, info->phys_reg_addr);
4860         } else if (irq_test(info) < 0) {
4861                 printk("IRQ test failure %s IRQ=%d\n",
4862                         info->device_name, info->irq_level);
4863         } else if (loopback_test(info) < 0) {
4864                 printk("loopback test failure %s\n", info->device_name);
4865         }
4866         return info->init_error;
4867 }
4868
4869 /*
4870  * transmit timeout handler
4871  */
4872 static void tx_timeout(unsigned long context)
4873 {
4874         struct slgt_info *info = (struct slgt_info*)context;
4875         unsigned long flags;
4876
4877         DBGINFO(("%s tx_timeout\n", info->device_name));
4878         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4879                 info->icount.txtimeout++;
4880         }
4881         spin_lock_irqsave(&info->lock,flags);
4882         info->tx_active = 0;
4883         info->tx_count = 0;
4884         spin_unlock_irqrestore(&info->lock,flags);
4885
4886 #if SYNCLINK_GENERIC_HDLC
4887         if (info->netcount)
4888                 hdlcdev_tx_done(info);
4889         else
4890 #endif
4891                 bh_transmit(info);
4892 }
4893
4894 /*
4895  * receive buffer polling timer
4896  */
4897 static void rx_timeout(unsigned long context)
4898 {
4899         struct slgt_info *info = (struct slgt_info*)context;
4900         unsigned long flags;
4901
4902         DBGINFO(("%s rx_timeout\n", info->device_name));
4903         spin_lock_irqsave(&info->lock, flags);
4904         info->pending_bh |= BH_RECEIVE;
4905         spin_unlock_irqrestore(&info->lock, flags);
4906         bh_handler(&info->task);
4907 }
4908