2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
4 * Copyright 2005 Tejun Heo
6 * Based on preview driver from Silicon Image.
8 * NOTE: No NCQ/ATAPI support yet. The preview driver didn't support
9 * NCQ nor ATAPI, and, unfortunately, I couldn't find out how to make
10 * those work. Enabling those shouldn't be difficult. Basic
11 * structure is all there (in libata-dev tree). If you have any
12 * information about this hardware, please contact me or linux-ide.
13 * Info is needed on...
15 * - How to issue tagged commands and turn on sactive on issue accordingly.
16 * - Where to put an ATAPI command and how to tell the device to send it.
17 * - How to enable/use 64bit.
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2, or (at your option) any
24 * This program is distributed in the hope that it will be useful, but
25 * WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
27 * General Public License for more details.
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/blkdev.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/device.h>
39 #include <scsi/scsi_host.h>
40 #include <scsi/scsi_cmnd.h>
41 #include <linux/libata.h>
44 #define DRV_NAME "sata_sil24"
45 #define DRV_VERSION "0.22" /* Silicon Image's preview driver was 0.10 */
48 * Port request block (PRB) 32 bytes
58 * Scatter gather entry (SGE) 16 bytes
69 struct sil24_port_multiplier {
76 * Global controller registers (128 bytes @ BAR0)
79 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
83 HOST_BIST_CTRL = 0x50,
84 HOST_BIST_PTRN = 0x54,
85 HOST_BIST_STAT = 0x58,
86 HOST_MEM_BIST_STAT = 0x5c,
87 HOST_FLASH_CMD = 0x70,
89 HOST_FLASH_DATA = 0x74,
90 HOST_TRANSITION_DETECT = 0x75,
91 HOST_GPIO_CTRL = 0x76,
92 HOST_I2C_ADDR = 0x78, /* 32 bit */
94 HOST_I2C_XFER_CNT = 0x7e,
97 /* HOST_SLOT_STAT bits */
98 HOST_SSTAT_ATTN = (1 << 31),
102 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
104 PORT_REGS_SIZE = 0x2000,
105 PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */
107 PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
109 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
110 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
111 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
112 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
113 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
114 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
115 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
116 PORT_CMD_ERR = 0x1024, /* command error number */
117 PORT_FIS_CFG = 0x1028,
118 PORT_FIFO_THRES = 0x102c,
120 PORT_DECODE_ERR_CNT = 0x1040,
121 PORT_DECODE_ERR_THRESH = 0x1042,
122 PORT_CRC_ERR_CNT = 0x1044,
123 PORT_CRC_ERR_THRESH = 0x1046,
124 PORT_HSHK_ERR_CNT = 0x1048,
125 PORT_HSHK_ERR_THRESH = 0x104a,
127 PORT_PHY_CFG = 0x1050,
128 PORT_SLOT_STAT = 0x1800,
129 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
130 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
131 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
132 PORT_SCONTROL = 0x1f00,
133 PORT_SSTATUS = 0x1f04,
134 PORT_SERROR = 0x1f08,
135 PORT_SACTIVE = 0x1f0c,
137 /* PORT_CTRL_STAT bits */
138 PORT_CS_PORT_RST = (1 << 0), /* port reset */
139 PORT_CS_DEV_RST = (1 << 1), /* device reset */
140 PORT_CS_INIT = (1 << 2), /* port initialize */
141 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
142 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
143 PORT_CS_RESUME = (1 << 6), /* port resume */
144 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
145 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */
146 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
148 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
149 /* bits[11:0] are masked */
150 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
151 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
152 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
153 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
154 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
155 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
156 PORT_IRQ_UNK_FIS = (1 << 6), /* Unknown FIS received */
157 PORT_IRQ_SDB_FIS = (1 << 11), /* SDB FIS received */
159 /* bits[27:16] are unmasked (raw) */
160 PORT_IRQ_RAW_SHIFT = 16,
161 PORT_IRQ_MASKED_MASK = 0x7ff,
162 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
164 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
165 PORT_IRQ_STEER_SHIFT = 30,
166 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
168 /* PORT_CMD_ERR constants */
169 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
170 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
171 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
172 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
173 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
174 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
175 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
176 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
177 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
178 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
179 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
180 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
181 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
182 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
183 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
184 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
185 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
186 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
187 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
188 PORT_CERR_XFR_MSGABRT = 34, /* PSD ecode 10 - master abort */
189 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
190 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
192 /* bits of PRB control field */
193 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
194 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
195 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
196 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
197 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
199 /* PRB protocol field */
200 PRB_PROT_PACKET = (1 << 0),
201 PRB_PROT_TCQ = (1 << 1),
202 PRB_PROT_NCQ = (1 << 2),
203 PRB_PROT_READ = (1 << 3),
204 PRB_PROT_WRITE = (1 << 4),
205 PRB_PROT_TRANSPARENT = (1 << 5),
210 SGE_TRM = (1 << 31), /* Last SGE in chain */
211 SGE_LNK = (1 << 30), /* linked list
212 Points to SGT, not SGE */
213 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
214 data address ignored */
221 IRQ_STAT_4PORTS = 0xf,
224 struct sil24_cmd_block {
225 struct sil24_prb prb;
226 struct sil24_sge sge[LIBATA_MAX_PRD];
232 * The preview driver always returned 0 for status. We emulate it
233 * here from the previous interrupt.
235 struct sil24_port_priv {
236 struct sil24_cmd_block *cmd_block; /* 32 cmd blocks */
237 dma_addr_t cmd_block_dma; /* DMA base addr for them */
238 struct ata_taskfile tf; /* Cached taskfile registers */
241 /* ap->host_set->private_data */
242 struct sil24_host_priv {
243 void __iomem *host_base; /* global controller control (128 bytes @BAR0) */
244 void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */
247 static u8 sil24_check_status(struct ata_port *ap);
248 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
249 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
250 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
251 static void sil24_phy_reset(struct ata_port *ap);
252 static void sil24_qc_prep(struct ata_queued_cmd *qc);
253 static int sil24_qc_issue(struct ata_queued_cmd *qc);
254 static void sil24_irq_clear(struct ata_port *ap);
255 static void sil24_eng_timeout(struct ata_port *ap);
256 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
257 static int sil24_port_start(struct ata_port *ap);
258 static void sil24_port_stop(struct ata_port *ap);
259 static void sil24_host_stop(struct ata_host_set *host_set);
260 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
262 static const struct pci_device_id sil24_pci_tbl[] = {
263 { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
264 { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 },
265 { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
266 { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
267 { } /* terminate list */
270 static struct pci_driver sil24_pci_driver = {
272 .id_table = sil24_pci_tbl,
273 .probe = sil24_init_one,
274 .remove = ata_pci_remove_one, /* safe? */
277 static struct scsi_host_template sil24_sht = {
278 .module = THIS_MODULE,
280 .ioctl = ata_scsi_ioctl,
281 .queuecommand = ata_scsi_queuecmd,
282 .eh_strategy_handler = ata_scsi_error,
283 .can_queue = ATA_DEF_QUEUE,
284 .this_id = ATA_SHT_THIS_ID,
285 .sg_tablesize = LIBATA_MAX_PRD,
286 .max_sectors = ATA_MAX_SECTORS,
287 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
288 .emulated = ATA_SHT_EMULATED,
289 .use_clustering = ATA_SHT_USE_CLUSTERING,
290 .proc_name = DRV_NAME,
291 .dma_boundary = ATA_DMA_BOUNDARY,
292 .slave_configure = ata_scsi_slave_config,
293 .bios_param = ata_std_bios_param,
294 .ordered_flush = 1, /* NCQ not supported yet */
297 static const struct ata_port_operations sil24_ops = {
298 .port_disable = ata_port_disable,
300 .check_status = sil24_check_status,
301 .check_altstatus = sil24_check_status,
302 .dev_select = ata_noop_dev_select,
304 .tf_read = sil24_tf_read,
306 .phy_reset = sil24_phy_reset,
308 .qc_prep = sil24_qc_prep,
309 .qc_issue = sil24_qc_issue,
311 .eng_timeout = sil24_eng_timeout,
313 .irq_handler = sil24_interrupt,
314 .irq_clear = sil24_irq_clear,
316 .scr_read = sil24_scr_read,
317 .scr_write = sil24_scr_write,
319 .port_start = sil24_port_start,
320 .port_stop = sil24_port_stop,
321 .host_stop = sil24_host_stop,
325 * Use bits 30-31 of host_flags to encode available port numbers.
326 * Current maxium is 4.
328 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
329 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
331 static struct ata_port_info sil24_port_info[] = {
335 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
336 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
337 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(4),
338 .pio_mask = 0x1f, /* pio0-4 */
339 .mwdma_mask = 0x07, /* mwdma0-2 */
340 .udma_mask = 0x3f, /* udma0-5 */
341 .port_ops = &sil24_ops,
346 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
347 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
348 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(2),
349 .pio_mask = 0x1f, /* pio0-4 */
350 .mwdma_mask = 0x07, /* mwdma0-2 */
351 .udma_mask = 0x3f, /* udma0-5 */
352 .port_ops = &sil24_ops,
354 /* sil_3131/sil_3531 */
357 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
358 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
359 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(1),
360 .pio_mask = 0x1f, /* pio0-4 */
361 .mwdma_mask = 0x07, /* mwdma0-2 */
362 .udma_mask = 0x3f, /* udma0-5 */
363 .port_ops = &sil24_ops,
367 static inline void sil24_update_tf(struct ata_port *ap)
369 struct sil24_port_priv *pp = ap->private_data;
370 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
371 struct sil24_prb __iomem *prb = port;
374 memcpy_fromio(fis, prb->fis, 6 * 4);
375 ata_tf_from_fis(fis, &pp->tf);
378 static u8 sil24_check_status(struct ata_port *ap)
380 struct sil24_port_priv *pp = ap->private_data;
381 return pp->tf.command;
384 static int sil24_scr_map[] = {
391 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
393 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
394 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
396 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
397 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
402 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
404 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
405 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
407 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
408 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
412 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
414 struct sil24_port_priv *pp = ap->private_data;
418 static void sil24_phy_reset(struct ata_port *ap)
420 __sata_phy_reset(ap);
422 * No ATAPI yet. Just unconditionally indicate ATA device.
423 * If ATAPI device is attached, it will fail ATA_CMD_ID_ATA
424 * and libata core will ignore the device.
426 if (!(ap->flags & ATA_FLAG_PORT_DISABLED))
427 ap->device[0].class = ATA_DEV_ATA;
430 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
431 struct sil24_cmd_block *cb)
433 struct sil24_sge *sge = cb->sge;
434 struct scatterlist *sg;
435 unsigned int idx = 0;
437 ata_for_each_sg(sg, qc) {
438 sge->addr = cpu_to_le64(sg_dma_address(sg));
439 sge->cnt = cpu_to_le32(sg_dma_len(sg));
440 if (ata_sg_is_last(sg, qc))
441 sge->flags = cpu_to_le32(SGE_TRM);
450 static void sil24_qc_prep(struct ata_queued_cmd *qc)
452 struct ata_port *ap = qc->ap;
453 struct sil24_port_priv *pp = ap->private_data;
454 struct sil24_cmd_block *cb = pp->cmd_block + qc->tag;
455 struct sil24_prb *prb = &cb->prb;
457 switch (qc->tf.protocol) {
460 case ATA_PROT_NODATA:
463 /* ATAPI isn't supported yet */
467 ata_tf_to_fis(&qc->tf, prb->fis, 0);
469 if (qc->flags & ATA_QCFLAG_DMAMAP)
470 sil24_fill_sg(qc, cb);
473 static int sil24_qc_issue(struct ata_queued_cmd *qc)
475 struct ata_port *ap = qc->ap;
476 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
477 struct sil24_port_priv *pp = ap->private_data;
478 dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block);
480 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
484 static void sil24_irq_clear(struct ata_port *ap)
489 static int __sil24_reset_controller(void __iomem *port)
494 /* Reset controller state. Is this correct? */
495 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
496 readl(port + PORT_CTRL_STAT); /* sync */
499 for (cnt = 0; cnt < 1000; cnt++) {
501 tmp = readl(port + PORT_CTRL_STAT);
502 if (!(tmp & PORT_CS_DEV_RST))
506 if (tmp & PORT_CS_DEV_RST)
511 static void sil24_reset_controller(struct ata_port *ap)
513 printk(KERN_NOTICE DRV_NAME
514 " ata%u: resetting controller...\n", ap->id);
515 if (__sil24_reset_controller((void __iomem *)ap->ioaddr.cmd_addr))
516 printk(KERN_ERR DRV_NAME
517 " ata%u: failed to reset controller\n", ap->id);
520 static void sil24_eng_timeout(struct ata_port *ap)
522 struct ata_queued_cmd *qc;
524 qc = ata_qc_from_tag(ap, ap->active_tag);
526 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
532 * hack alert! We cannot use the supplied completion
533 * function from inside the ->eh_strategy_handler() thread.
534 * libata is the only user of ->eh_strategy_handler() in
535 * any kernel, so the default scsi_done() assumes it is
536 * not being called from the SCSI EH.
538 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
539 qc->scsidone = scsi_finish_command;
540 ata_qc_complete(qc, AC_ERR_OTHER);
542 sil24_reset_controller(ap);
545 static void sil24_error_intr(struct ata_port *ap, u32 slot_stat)
547 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
548 struct sil24_port_priv *pp = ap->private_data;
549 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
550 u32 irq_stat, cmd_err, sstatus, serror;
551 unsigned int err_mask;
553 irq_stat = readl(port + PORT_IRQ_STAT);
554 writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */
556 if (!(irq_stat & PORT_IRQ_ERROR)) {
557 /* ignore non-completion, non-error irqs for now */
558 printk(KERN_WARNING DRV_NAME
559 "ata%u: non-error exception irq (irq_stat %x)\n",
564 cmd_err = readl(port + PORT_CMD_ERR);
565 sstatus = readl(port + PORT_SSTATUS);
566 serror = readl(port + PORT_SERROR);
568 writel(serror, port + PORT_SERROR);
570 printk(KERN_ERR DRV_NAME " ata%u: error interrupt on port%d\n"
571 " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n",
572 ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror);
574 if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) {
576 * Device is reporting error, tf registers are valid.
579 err_mask = ac_err_mask(pp->tf.command);
582 * Other errors. libata currently doesn't have any
583 * mechanism to report these errors. Just turn on
586 err_mask = AC_ERR_OTHER;
590 ata_qc_complete(qc, err_mask);
592 sil24_reset_controller(ap);
595 static inline void sil24_host_intr(struct ata_port *ap)
597 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
598 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
601 slot_stat = readl(port + PORT_SLOT_STAT);
602 if (!(slot_stat & HOST_SSTAT_ATTN)) {
603 struct sil24_port_priv *pp = ap->private_data;
605 * !HOST_SSAT_ATTN guarantees successful completion,
606 * so reading back tf registers is unnecessary for
607 * most commands. TODO: read tf registers for
608 * commands which require these values on successful
609 * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER,
610 * DEVICE RESET and READ PORT MULTIPLIER (any more?).
615 ata_qc_complete(qc, ac_err_mask(pp->tf.command));
617 sil24_error_intr(ap, slot_stat);
620 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
622 struct ata_host_set *host_set = dev_instance;
623 struct sil24_host_priv *hpriv = host_set->private_data;
624 unsigned handled = 0;
628 status = readl(hpriv->host_base + HOST_IRQ_STAT);
630 if (status == 0xffffffff) {
631 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
632 "PCI fault or device removal?\n");
636 if (!(status & IRQ_STAT_4PORTS))
639 spin_lock(&host_set->lock);
641 for (i = 0; i < host_set->n_ports; i++)
642 if (status & (1 << i)) {
643 struct ata_port *ap = host_set->ports[i];
644 if (ap && !(ap->flags & ATA_FLAG_PORT_DISABLED)) {
645 sil24_host_intr(host_set->ports[i]);
648 printk(KERN_ERR DRV_NAME
649 ": interrupt from disabled port %d\n", i);
652 spin_unlock(&host_set->lock);
654 return IRQ_RETVAL(handled);
657 static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev)
659 const size_t cb_size = sizeof(*pp->cmd_block);
661 dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
664 static int sil24_port_start(struct ata_port *ap)
666 struct device *dev = ap->host_set->dev;
667 struct sil24_port_priv *pp;
668 struct sil24_cmd_block *cb;
669 size_t cb_size = sizeof(*cb);
673 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
677 pp->tf.command = ATA_DRDY;
679 cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
682 memset(cb, 0, cb_size);
684 rc = ata_pad_alloc(ap, dev);
689 pp->cmd_block_dma = cb_dma;
691 ap->private_data = pp;
696 sil24_cblk_free(pp, dev);
703 static void sil24_port_stop(struct ata_port *ap)
705 struct device *dev = ap->host_set->dev;
706 struct sil24_port_priv *pp = ap->private_data;
708 sil24_cblk_free(pp, dev);
709 ata_pad_free(ap, dev);
713 static void sil24_host_stop(struct ata_host_set *host_set)
715 struct sil24_host_priv *hpriv = host_set->private_data;
717 iounmap(hpriv->host_base);
718 iounmap(hpriv->port_base);
722 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
724 static int printed_version = 0;
725 unsigned int board_id = (unsigned int)ent->driver_data;
726 struct ata_port_info *pinfo = &sil24_port_info[board_id];
727 struct ata_probe_ent *probe_ent = NULL;
728 struct sil24_host_priv *hpriv = NULL;
729 void __iomem *host_base = NULL;
730 void __iomem *port_base = NULL;
733 if (!printed_version++)
734 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
736 rc = pci_enable_device(pdev);
740 rc = pci_request_regions(pdev, DRV_NAME);
745 /* ioremap mmio registers */
746 host_base = ioremap(pci_resource_start(pdev, 0),
747 pci_resource_len(pdev, 0));
750 port_base = ioremap(pci_resource_start(pdev, 2),
751 pci_resource_len(pdev, 2));
755 /* allocate & init probe_ent and hpriv */
756 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
760 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
764 memset(probe_ent, 0, sizeof(*probe_ent));
765 probe_ent->dev = pci_dev_to_dev(pdev);
766 INIT_LIST_HEAD(&probe_ent->node);
768 probe_ent->sht = pinfo->sht;
769 probe_ent->host_flags = pinfo->host_flags;
770 probe_ent->pio_mask = pinfo->pio_mask;
771 probe_ent->udma_mask = pinfo->udma_mask;
772 probe_ent->port_ops = pinfo->port_ops;
773 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags);
775 probe_ent->irq = pdev->irq;
776 probe_ent->irq_flags = SA_SHIRQ;
777 probe_ent->mmio_base = port_base;
778 probe_ent->private_data = hpriv;
780 memset(hpriv, 0, sizeof(*hpriv));
781 hpriv->host_base = host_base;
782 hpriv->port_base = port_base;
785 * Configure the device
788 * FIXME: This device is certainly 64-bit capable. We just
789 * don't know how to use it. After fixing 32bit activation in
790 * this function, enable 64bit masks here.
792 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
794 dev_printk(KERN_ERR, &pdev->dev,
795 "32-bit DMA enable failed\n");
798 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
800 dev_printk(KERN_ERR, &pdev->dev,
801 "32-bit consistent DMA enable failed\n");
806 writel(0, host_base + HOST_FLASH_CMD);
808 /* Mask interrupts during initialization */
809 writel(0, host_base + HOST_CTRL);
811 for (i = 0; i < probe_ent->n_ports; i++) {
812 void __iomem *port = port_base + i * PORT_REGS_SIZE;
813 unsigned long portu = (unsigned long)port;
817 probe_ent->port[i].cmd_addr = portu + PORT_PRB;
818 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
820 ata_std_ports(&probe_ent->port[i]);
822 /* Initial PHY setting */
823 writel(0x20c, port + PORT_PHY_CFG);
826 tmp = readl(port + PORT_CTRL_STAT);
827 if (tmp & PORT_CS_PORT_RST) {
828 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
829 readl(port + PORT_CTRL_STAT); /* sync */
830 for (cnt = 0; cnt < 10; cnt++) {
832 tmp = readl(port + PORT_CTRL_STAT);
833 if (!(tmp & PORT_CS_PORT_RST))
836 if (tmp & PORT_CS_PORT_RST)
837 dev_printk(KERN_ERR, &pdev->dev,
838 "failed to clear port RST\n");
841 /* Zero error counters. */
842 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
843 writel(0x8000, port + PORT_CRC_ERR_THRESH);
844 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
845 writel(0x0000, port + PORT_DECODE_ERR_CNT);
846 writel(0x0000, port + PORT_CRC_ERR_CNT);
847 writel(0x0000, port + PORT_HSHK_ERR_CNT);
849 /* FIXME: 32bit activation? */
850 writel(0, port + PORT_ACTIVATE_UPPER_ADDR);
851 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT);
853 /* Configure interrupts */
854 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
855 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | PORT_IRQ_SDB_FIS,
856 port + PORT_IRQ_ENABLE_SET);
858 /* Clear interrupts */
859 writel(0x0fff0fff, port + PORT_IRQ_STAT);
860 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
862 /* Clear port multiplier enable and resume bits */
863 writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
866 if (__sil24_reset_controller(port))
867 dev_printk(KERN_ERR, &pdev->dev,
868 "failed to reset controller\n");
871 /* Turn on interrupts */
872 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
874 pci_set_master(pdev);
876 /* FIXME: check ata_device_add return value */
877 ata_device_add(probe_ent);
889 pci_release_regions(pdev);
891 pci_disable_device(pdev);
895 static int __init sil24_init(void)
897 return pci_module_init(&sil24_pci_driver);
900 static void __exit sil24_exit(void)
902 pci_unregister_driver(&sil24_pci_driver);
905 MODULE_AUTHOR("Tejun Heo");
906 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
907 MODULE_LICENSE("GPL");
908 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
910 module_init(sil24_init);
911 module_exit(sil24_exit);