2 * Intel AGPGART routines.
5 #include <linux/module.h>
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/pagemap.h>
10 #include <linux/agp_backend.h>
13 #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
14 #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
15 #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
16 #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
17 #define PCI_DEVICE_ID_INTEL_82965G_1_HB 0x2980
18 #define PCI_DEVICE_ID_INTEL_82965G_1_IG 0x2982
19 #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
20 #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
21 #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
22 #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
23 #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
24 #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
25 #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
26 #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
27 #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
28 #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
29 #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
30 #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
31 #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
32 #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
33 #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
34 #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
36 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
37 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
38 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
39 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
40 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
41 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
43 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
44 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
45 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
47 extern int agp_memory_reserved;
50 /* Intel 815 register */
51 #define INTEL_815_APCONT 0x51
52 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
54 /* Intel i820 registers */
55 #define INTEL_I820_RDCR 0x51
56 #define INTEL_I820_ERRSTS 0xc8
58 /* Intel i840 registers */
59 #define INTEL_I840_MCHCFG 0x50
60 #define INTEL_I840_ERRSTS 0xc8
62 /* Intel i850 registers */
63 #define INTEL_I850_MCHCFG 0x50
64 #define INTEL_I850_ERRSTS 0xc8
66 /* intel 915G registers */
67 #define I915_GMADDR 0x18
68 #define I915_MMADDR 0x10
69 #define I915_PTEADDR 0x1C
70 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
71 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
72 #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
73 #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
74 #define I915_IFPADDR 0x60
76 /* Intel 965G registers */
77 #define I965_MSAC 0x62
78 #define I965_IFPADDR 0x70
80 /* Intel 7505 registers */
81 #define INTEL_I7505_APSIZE 0x74
82 #define INTEL_I7505_NCAPID 0x60
83 #define INTEL_I7505_NISTAT 0x6c
84 #define INTEL_I7505_ATTBASE 0x78
85 #define INTEL_I7505_ERRSTS 0x42
86 #define INTEL_I7505_AGPCTRL 0x70
87 #define INTEL_I7505_MCHCFG 0x50
89 static const struct aper_size_info_fixed intel_i810_sizes[] =
92 /* The 32M mode still requires a 64k gatt */
96 #define AGP_DCACHE_MEMORY 1
97 #define AGP_PHYS_MEMORY 2
98 #define INTEL_AGP_CACHED_MEMORY 3
100 static struct gatt_mask intel_i810_masks[] =
102 {.mask = I810_PTE_VALID, .type = 0},
103 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
104 {.mask = I810_PTE_VALID, .type = 0},
105 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
106 .type = INTEL_AGP_CACHED_MEMORY}
109 static struct _intel_private {
110 struct pci_dev *pcidev; /* device one */
111 u8 __iomem *registers;
112 u32 __iomem *gtt; /* I915G */
113 int num_dcache_entries;
114 /* gtt_entries is the number of gtt entries that are already mapped
115 * to stolen memory. Stolen memory is larger than the memory mapped
116 * through gtt_entries, as it includes some reserved space for the BIOS
117 * popup and for the GTT.
119 int gtt_entries; /* i830+ */
121 void __iomem *i9xx_flush_page;
122 void *i8xx_flush_page;
124 struct page *i8xx_page;
125 struct resource ifp_resource;
128 static int intel_i810_fetch_size(void)
131 struct aper_size_info_fixed *values;
133 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
134 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
136 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
137 printk(KERN_WARNING PFX "i810 is disabled\n");
140 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
141 agp_bridge->previous_size =
142 agp_bridge->current_size = (void *) (values + 1);
143 agp_bridge->aperture_size_idx = 1;
144 return values[1].size;
146 agp_bridge->previous_size =
147 agp_bridge->current_size = (void *) (values);
148 agp_bridge->aperture_size_idx = 0;
149 return values[0].size;
155 static int intel_i810_configure(void)
157 struct aper_size_info_fixed *current_size;
161 current_size = A_SIZE_FIX(agp_bridge->current_size);
163 if (!intel_private.registers) {
164 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
167 intel_private.registers = ioremap(temp, 128 * 4096);
168 if (!intel_private.registers) {
169 printk(KERN_ERR PFX "Unable to remap memory.\n");
174 if ((readl(intel_private.registers+I810_DRAM_CTL)
175 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
176 /* This will need to be dynamically assigned */
177 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
178 intel_private.num_dcache_entries = 1024;
180 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
181 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
182 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
183 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
185 if (agp_bridge->driver->needs_scratch_page) {
186 for (i = 0; i < current_size->num_entries; i++) {
187 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
188 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */
191 global_cache_flush();
195 static void intel_i810_cleanup(void)
197 writel(0, intel_private.registers+I810_PGETBL_CTL);
198 readl(intel_private.registers); /* PCI Posting. */
199 iounmap(intel_private.registers);
202 static void intel_i810_tlbflush(struct agp_memory *mem)
207 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
212 /* Exists to support ARGB cursors */
213 static void *i8xx_alloc_pages(void)
217 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
221 if (set_pages_uc(page, 4) < 0) {
222 set_pages_wb(page, 4);
223 __free_pages(page, 2);
227 atomic_inc(&agp_bridge->current_memory_agp);
228 return page_address(page);
231 static void i8xx_destroy_pages(void *addr)
238 page = virt_to_page(addr);
239 set_pages_wb(page, 4);
241 __free_pages(page, 2);
242 atomic_dec(&agp_bridge->current_memory_agp);
245 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
248 if (type < AGP_USER_TYPES)
250 else if (type == AGP_USER_CACHED_MEMORY)
251 return INTEL_AGP_CACHED_MEMORY;
256 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
259 int i, j, num_entries;
264 if (mem->page_count == 0)
267 temp = agp_bridge->current_size;
268 num_entries = A_SIZE_FIX(temp)->num_entries;
270 if ((pg_start + mem->page_count) > num_entries)
274 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
275 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
281 if (type != mem->type)
284 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
287 case AGP_DCACHE_MEMORY:
288 if (!mem->is_flushed)
289 global_cache_flush();
290 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
291 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
292 intel_private.registers+I810_PTE_BASE+(i*4));
294 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
296 case AGP_PHYS_MEMORY:
297 case AGP_NORMAL_MEMORY:
298 if (!mem->is_flushed)
299 global_cache_flush();
300 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
301 writel(agp_bridge->driver->mask_memory(agp_bridge,
304 intel_private.registers+I810_PTE_BASE+(j*4));
306 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
312 agp_bridge->driver->tlb_flush(mem);
320 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
325 if (mem->page_count == 0)
328 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
329 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
331 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
333 agp_bridge->driver->tlb_flush(mem);
338 * The i810/i830 requires a physical address to program its mouse
339 * pointer into hardware.
340 * However the Xserver still writes to it through the agp aperture.
342 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
344 struct agp_memory *new;
348 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
351 /* kludge to get 4 physical pages for ARGB cursor */
352 addr = i8xx_alloc_pages();
361 new = agp_create_memory(pg_count);
365 new->memory[0] = virt_to_gart(addr);
367 /* kludge to get 4 physical pages for ARGB cursor */
368 new->memory[1] = new->memory[0] + PAGE_SIZE;
369 new->memory[2] = new->memory[1] + PAGE_SIZE;
370 new->memory[3] = new->memory[2] + PAGE_SIZE;
372 new->page_count = pg_count;
373 new->num_scratch_pages = pg_count;
374 new->type = AGP_PHYS_MEMORY;
375 new->physical = new->memory[0];
379 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
381 struct agp_memory *new;
383 if (type == AGP_DCACHE_MEMORY) {
384 if (pg_count != intel_private.num_dcache_entries)
387 new = agp_create_memory(1);
391 new->type = AGP_DCACHE_MEMORY;
392 new->page_count = pg_count;
393 new->num_scratch_pages = 0;
394 agp_free_page_array(new);
397 if (type == AGP_PHYS_MEMORY)
398 return alloc_agpphysmem_i8xx(pg_count, type);
402 static void intel_i810_free_by_type(struct agp_memory *curr)
404 agp_free_key(curr->key);
405 if (curr->type == AGP_PHYS_MEMORY) {
406 if (curr->page_count == 4)
407 i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
409 agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]),
410 AGP_PAGE_DESTROY_UNMAP);
411 agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]),
412 AGP_PAGE_DESTROY_FREE);
414 agp_free_page_array(curr);
419 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
420 unsigned long addr, int type)
422 /* Type checking must be done elsewhere */
423 return addr | bridge->driver->masks[type].mask;
426 static struct aper_size_info_fixed intel_i830_sizes[] =
429 /* The 64M mode still requires a 128k gatt */
435 static void intel_i830_init_gtt_entries(void)
441 static const int ddt[4] = { 0, 16, 32, 64 };
442 int size; /* reserved space (in kb) at the top of stolen memory */
444 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
448 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
450 /* The 965 has a field telling us the size of the GTT,
451 * which may be larger than what is necessary to map the
454 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
455 case I965_PGETBL_SIZE_128KB:
458 case I965_PGETBL_SIZE_256KB:
461 case I965_PGETBL_SIZE_512KB:
465 printk(KERN_INFO PFX "Unknown page table size, "
469 size += 4; /* add in BIOS popup space */
471 /* G33's GTT size defined in gmch_ctrl */
472 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
473 case G33_PGETBL_SIZE_1M:
476 case G33_PGETBL_SIZE_2M:
480 printk(KERN_INFO PFX "Unknown page table size 0x%x, "
482 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
487 /* On previous hardware, the GTT size was just what was
488 * required to map the aperture.
490 size = agp_bridge->driver->fetch_size() + 4;
493 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
494 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
495 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
496 case I830_GMCH_GMS_STOLEN_512:
497 gtt_entries = KB(512) - KB(size);
499 case I830_GMCH_GMS_STOLEN_1024:
500 gtt_entries = MB(1) - KB(size);
502 case I830_GMCH_GMS_STOLEN_8192:
503 gtt_entries = MB(8) - KB(size);
505 case I830_GMCH_GMS_LOCAL:
506 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
507 gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
508 MB(ddt[I830_RDRAM_DDT(rdct)]);
516 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
517 case I855_GMCH_GMS_STOLEN_1M:
518 gtt_entries = MB(1) - KB(size);
520 case I855_GMCH_GMS_STOLEN_4M:
521 gtt_entries = MB(4) - KB(size);
523 case I855_GMCH_GMS_STOLEN_8M:
524 gtt_entries = MB(8) - KB(size);
526 case I855_GMCH_GMS_STOLEN_16M:
527 gtt_entries = MB(16) - KB(size);
529 case I855_GMCH_GMS_STOLEN_32M:
530 gtt_entries = MB(32) - KB(size);
532 case I915_GMCH_GMS_STOLEN_48M:
533 /* Check it's really I915G */
534 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB ||
535 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
536 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
537 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
538 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
539 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
541 gtt_entries = MB(48) - KB(size);
545 case I915_GMCH_GMS_STOLEN_64M:
546 /* Check it's really I915G */
547 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB ||
548 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
549 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
550 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
551 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
552 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
554 gtt_entries = MB(64) - KB(size);
558 case G33_GMCH_GMS_STOLEN_128M:
560 gtt_entries = MB(128) - KB(size);
564 case G33_GMCH_GMS_STOLEN_256M:
566 gtt_entries = MB(256) - KB(size);
576 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
577 gtt_entries / KB(1), local ? "local" : "stolen");
580 "No pre-allocated video memory detected.\n");
581 gtt_entries /= KB(4);
583 intel_private.gtt_entries = gtt_entries;
586 static void intel_i830_fini_flush(void)
588 kunmap(intel_private.i8xx_page);
589 intel_private.i8xx_flush_page = NULL;
590 unmap_page_from_agp(intel_private.i8xx_page);
591 flush_agp_mappings();
593 __free_page(intel_private.i8xx_page);
596 static void intel_i830_setup_flush(void)
599 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
600 if (!intel_private.i8xx_page) {
604 /* make page uncached */
605 map_page_into_agp(intel_private.i8xx_page);
606 flush_agp_mappings();
608 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
609 if (!intel_private.i8xx_flush_page)
610 intel_i830_fini_flush();
613 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
615 unsigned int *pg = intel_private.i8xx_flush_page;
618 for (i = 0; i < 256; i+=2)
624 /* The intel i830 automatically initializes the agp aperture during POST.
625 * Use the memory already set aside for in the GTT.
627 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
630 struct aper_size_info_fixed *size;
634 size = agp_bridge->current_size;
635 page_order = size->page_order;
636 num_entries = size->num_entries;
637 agp_bridge->gatt_table_real = NULL;
639 pci_read_config_dword(intel_private.pcidev,I810_MMADDR,&temp);
642 intel_private.registers = ioremap(temp,128 * 4096);
643 if (!intel_private.registers)
646 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
647 global_cache_flush(); /* FIXME: ?? */
649 /* we have to call this as early as possible after the MMIO base address is known */
650 intel_i830_init_gtt_entries();
652 agp_bridge->gatt_table = NULL;
654 agp_bridge->gatt_bus_addr = temp;
659 /* Return the gatt table to a sane state. Use the top of stolen
660 * memory for the GTT.
662 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
667 static int intel_i830_fetch_size(void)
670 struct aper_size_info_fixed *values;
672 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
674 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
675 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
676 /* 855GM/852GM/865G has 128MB aperture size */
677 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
678 agp_bridge->aperture_size_idx = 0;
679 return values[0].size;
682 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
684 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
685 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
686 agp_bridge->aperture_size_idx = 0;
687 return values[0].size;
689 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
690 agp_bridge->aperture_size_idx = 1;
691 return values[1].size;
697 static int intel_i830_configure(void)
699 struct aper_size_info_fixed *current_size;
704 current_size = A_SIZE_FIX(agp_bridge->current_size);
706 pci_read_config_dword(intel_private.pcidev,I810_GMADDR,&temp);
707 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
709 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
710 gmch_ctrl |= I830_GMCH_ENABLED;
711 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
713 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
714 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
716 if (agp_bridge->driver->needs_scratch_page) {
717 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
718 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
719 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
723 global_cache_flush();
725 intel_i830_setup_flush();
729 static void intel_i830_cleanup(void)
731 iounmap(intel_private.registers);
734 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
741 if (mem->page_count == 0)
744 temp = agp_bridge->current_size;
745 num_entries = A_SIZE_FIX(temp)->num_entries;
747 if (pg_start < intel_private.gtt_entries) {
748 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
749 pg_start,intel_private.gtt_entries);
751 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
755 if ((pg_start + mem->page_count) > num_entries)
758 /* The i830 can't check the GTT for entries since its read only,
759 * depend on the caller to make the correct offset decisions.
762 if (type != mem->type)
765 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
767 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
768 mask_type != INTEL_AGP_CACHED_MEMORY)
771 if (!mem->is_flushed)
772 global_cache_flush();
774 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
775 writel(agp_bridge->driver->mask_memory(agp_bridge,
776 mem->memory[i], mask_type),
777 intel_private.registers+I810_PTE_BASE+(j*4));
779 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
780 agp_bridge->driver->tlb_flush(mem);
789 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
794 if (mem->page_count == 0)
797 if (pg_start < intel_private.gtt_entries) {
798 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
802 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
803 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
805 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
807 agp_bridge->driver->tlb_flush(mem);
811 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
813 if (type == AGP_PHYS_MEMORY)
814 return alloc_agpphysmem_i8xx(pg_count, type);
815 /* always return NULL for other allocation types for now */
819 static int intel_alloc_chipset_flush_resource(void)
822 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
823 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
824 pcibios_align_resource, agp_bridge->dev);
829 static void intel_i915_setup_chipset_flush(void)
834 pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
836 intel_alloc_chipset_flush_resource();
838 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
842 intel_private.ifp_resource.start = temp;
843 intel_private.ifp_resource.end = temp + PAGE_SIZE;
844 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
846 intel_private.ifp_resource.start = 0;
847 printk("Failed inserting resource into tree\n");
852 static void intel_i965_g33_setup_chipset_flush(void)
854 u32 temp_hi, temp_lo;
857 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
858 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
860 if (!(temp_lo & 0x1)) {
862 intel_alloc_chipset_flush_resource();
864 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
865 upper_32_bits(intel_private.ifp_resource.start));
866 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
871 l64 = ((u64)temp_hi << 32) | temp_lo;
873 intel_private.ifp_resource.start = l64;
874 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
875 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
877 printk("Failed inserting resource into tree - continuing\n");
882 static void intel_i9xx_setup_flush(void)
884 /* setup a resource for this object */
885 memset(&intel_private.ifp_resource, 0, sizeof(intel_private.ifp_resource));
887 intel_private.ifp_resource.name = "Intel Flush Page";
888 intel_private.ifp_resource.flags = IORESOURCE_MEM;
890 /* Setup chipset flush for 915 */
891 if (IS_I965 || IS_G33) {
892 intel_i965_g33_setup_chipset_flush();
894 intel_i915_setup_chipset_flush();
897 if (intel_private.ifp_resource.start) {
898 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
899 if (!intel_private.i9xx_flush_page)
900 printk("unable to ioremap flush page - no chipset flushing");
904 static int intel_i915_configure(void)
906 struct aper_size_info_fixed *current_size;
911 current_size = A_SIZE_FIX(agp_bridge->current_size);
913 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
915 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
917 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
918 gmch_ctrl |= I830_GMCH_ENABLED;
919 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
921 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
922 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
924 if (agp_bridge->driver->needs_scratch_page) {
925 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
926 writel(agp_bridge->scratch_page, intel_private.gtt+i);
927 readl(intel_private.gtt+i); /* PCI Posting. */
931 global_cache_flush();
933 intel_i9xx_setup_flush();
938 static void intel_i915_cleanup(void)
940 if (intel_private.i9xx_flush_page)
941 iounmap(intel_private.i9xx_flush_page);
942 iounmap(intel_private.gtt);
943 iounmap(intel_private.registers);
946 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
948 if (intel_private.i9xx_flush_page)
949 writel(1, intel_private.i9xx_flush_page);
952 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
960 if (mem->page_count == 0)
963 temp = agp_bridge->current_size;
964 num_entries = A_SIZE_FIX(temp)->num_entries;
966 if (pg_start < intel_private.gtt_entries) {
967 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
968 pg_start,intel_private.gtt_entries);
970 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
974 if ((pg_start + mem->page_count) > num_entries)
977 /* The i915 can't check the GTT for entries since its read only,
978 * depend on the caller to make the correct offset decisions.
981 if (type != mem->type)
984 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
986 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
987 mask_type != INTEL_AGP_CACHED_MEMORY)
990 if (!mem->is_flushed)
991 global_cache_flush();
993 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
994 writel(agp_bridge->driver->mask_memory(agp_bridge,
995 mem->memory[i], mask_type), intel_private.gtt+j);
998 readl(intel_private.gtt+j-1);
999 agp_bridge->driver->tlb_flush(mem);
1004 mem->is_flushed = 1;
1008 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
1013 if (mem->page_count == 0)
1016 if (pg_start < intel_private.gtt_entries) {
1017 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
1021 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1022 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1024 readl(intel_private.gtt+i-1);
1026 agp_bridge->driver->tlb_flush(mem);
1030 /* Return the aperture size by just checking the resource length. The effect
1031 * described in the spec of the MSAC registers is just changing of the
1034 static int intel_i9xx_fetch_size(void)
1036 int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1037 int aper_size; /* size in megabytes */
1040 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1042 for (i = 0; i < num_sizes; i++) {
1043 if (aper_size == intel_i830_sizes[i].size) {
1044 agp_bridge->current_size = intel_i830_sizes + i;
1045 agp_bridge->previous_size = agp_bridge->current_size;
1053 /* The intel i915 automatically initializes the agp aperture during POST.
1054 * Use the memory already set aside for in the GTT.
1056 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1059 struct aper_size_info_fixed *size;
1062 int gtt_map_size = 256 * 1024;
1064 size = agp_bridge->current_size;
1065 page_order = size->page_order;
1066 num_entries = size->num_entries;
1067 agp_bridge->gatt_table_real = NULL;
1069 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1070 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR,&temp2);
1073 gtt_map_size = 1024 * 1024; /* 1M on G33 */
1074 intel_private.gtt = ioremap(temp2, gtt_map_size);
1075 if (!intel_private.gtt)
1080 intel_private.registers = ioremap(temp,128 * 4096);
1081 if (!intel_private.registers) {
1082 iounmap(intel_private.gtt);
1086 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1087 global_cache_flush(); /* FIXME: ? */
1089 /* we have to call this as early as possible after the MMIO base address is known */
1090 intel_i830_init_gtt_entries();
1092 agp_bridge->gatt_table = NULL;
1094 agp_bridge->gatt_bus_addr = temp;
1100 * The i965 supports 36-bit physical addresses, but to keep
1101 * the format of the GTT the same, the bits that don't fit
1102 * in a 32-bit word are shifted down to bits 4..7.
1104 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1105 * is always zero on 32-bit architectures, so no need to make
1108 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1109 unsigned long addr, int type)
1111 /* Shift high bits down */
1112 addr |= (addr >> 28) & 0xf0;
1114 /* Type checking must be done elsewhere */
1115 return addr | bridge->driver->masks[type].mask;
1118 /* The intel i965 automatically initializes the agp aperture during POST.
1119 * Use the memory already set aside for in the GTT.
1121 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1124 struct aper_size_info_fixed *size;
1128 size = agp_bridge->current_size;
1129 page_order = size->page_order;
1130 num_entries = size->num_entries;
1131 agp_bridge->gatt_table_real = NULL;
1133 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1136 intel_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024);
1138 if (!intel_private.gtt)
1142 intel_private.registers = ioremap(temp,128 * 4096);
1143 if (!intel_private.registers) {
1144 iounmap(intel_private.gtt);
1148 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1149 global_cache_flush(); /* FIXME: ? */
1151 /* we have to call this as early as possible after the MMIO base address is known */
1152 intel_i830_init_gtt_entries();
1154 agp_bridge->gatt_table = NULL;
1156 agp_bridge->gatt_bus_addr = temp;
1162 static int intel_fetch_size(void)
1166 struct aper_size_info_16 *values;
1168 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1169 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1171 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1172 if (temp == values[i].size_value) {
1173 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1174 agp_bridge->aperture_size_idx = i;
1175 return values[i].size;
1182 static int __intel_8xx_fetch_size(u8 temp)
1185 struct aper_size_info_8 *values;
1187 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1189 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1190 if (temp == values[i].size_value) {
1191 agp_bridge->previous_size =
1192 agp_bridge->current_size = (void *) (values + i);
1193 agp_bridge->aperture_size_idx = i;
1194 return values[i].size;
1200 static int intel_8xx_fetch_size(void)
1204 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1205 return __intel_8xx_fetch_size(temp);
1208 static int intel_815_fetch_size(void)
1212 /* Intel 815 chipsets have a _weird_ APSIZE register with only
1213 * one non-reserved bit, so mask the others out ... */
1214 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1217 return __intel_8xx_fetch_size(temp);
1220 static void intel_tlbflush(struct agp_memory *mem)
1222 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1223 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1227 static void intel_8xx_tlbflush(struct agp_memory *mem)
1230 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1231 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1232 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1233 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1237 static void intel_cleanup(void)
1240 struct aper_size_info_16 *previous_size;
1242 previous_size = A_SIZE_16(agp_bridge->previous_size);
1243 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1244 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1245 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1249 static void intel_8xx_cleanup(void)
1252 struct aper_size_info_8 *previous_size;
1254 previous_size = A_SIZE_8(agp_bridge->previous_size);
1255 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1256 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1257 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1261 static int intel_configure(void)
1265 struct aper_size_info_16 *current_size;
1267 current_size = A_SIZE_16(agp_bridge->current_size);
1270 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1272 /* address to map to */
1273 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1274 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1276 /* attbase - aperture base */
1277 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1280 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1283 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1284 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1285 (temp2 & ~(1 << 10)) | (1 << 9));
1286 /* clear any possible error conditions */
1287 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1291 static int intel_815_configure(void)
1295 struct aper_size_info_8 *current_size;
1297 /* attbase - aperture base */
1298 /* the Intel 815 chipset spec. says that bits 29-31 in the
1299 * ATTBASE register are reserved -> try not to write them */
1300 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1301 printk (KERN_EMERG PFX "gatt bus addr too high");
1305 current_size = A_SIZE_8(agp_bridge->current_size);
1308 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1309 current_size->size_value);
1311 /* address to map to */
1312 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1313 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1315 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1316 addr &= INTEL_815_ATTBASE_MASK;
1317 addr |= agp_bridge->gatt_bus_addr;
1318 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1321 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1324 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1325 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1327 /* clear any possible error conditions */
1328 /* Oddness : this chipset seems to have no ERRSTS register ! */
1332 static void intel_820_tlbflush(struct agp_memory *mem)
1337 static void intel_820_cleanup(void)
1340 struct aper_size_info_8 *previous_size;
1342 previous_size = A_SIZE_8(agp_bridge->previous_size);
1343 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1344 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1346 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1347 previous_size->size_value);
1351 static int intel_820_configure(void)
1355 struct aper_size_info_8 *current_size;
1357 current_size = A_SIZE_8(agp_bridge->current_size);
1360 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1362 /* address to map to */
1363 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1364 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1366 /* attbase - aperture base */
1367 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1370 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1372 /* global enable aperture access */
1373 /* This flag is not accessed through MCHCFG register as in */
1375 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1376 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1377 /* clear any possible AGP-related error conditions */
1378 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1382 static int intel_840_configure(void)
1386 struct aper_size_info_8 *current_size;
1388 current_size = A_SIZE_8(agp_bridge->current_size);
1391 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1393 /* address to map to */
1394 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1395 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1397 /* attbase - aperture base */
1398 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1401 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1404 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1405 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1406 /* clear any possible error conditions */
1407 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1411 static int intel_845_configure(void)
1415 struct aper_size_info_8 *current_size;
1417 current_size = A_SIZE_8(agp_bridge->current_size);
1420 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1422 if (agp_bridge->apbase_config != 0) {
1423 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1424 agp_bridge->apbase_config);
1426 /* address to map to */
1427 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1428 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1429 agp_bridge->apbase_config = temp;
1432 /* attbase - aperture base */
1433 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1436 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1439 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1440 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1441 /* clear any possible error conditions */
1442 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1444 intel_i830_setup_flush();
1448 static int intel_850_configure(void)
1452 struct aper_size_info_8 *current_size;
1454 current_size = A_SIZE_8(agp_bridge->current_size);
1457 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1459 /* address to map to */
1460 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1461 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1463 /* attbase - aperture base */
1464 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1467 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1470 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1471 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1472 /* clear any possible AGP-related error conditions */
1473 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1477 static int intel_860_configure(void)
1481 struct aper_size_info_8 *current_size;
1483 current_size = A_SIZE_8(agp_bridge->current_size);
1486 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1488 /* address to map to */
1489 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1490 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1492 /* attbase - aperture base */
1493 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1496 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1499 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1500 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1501 /* clear any possible AGP-related error conditions */
1502 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1506 static int intel_830mp_configure(void)
1510 struct aper_size_info_8 *current_size;
1512 current_size = A_SIZE_8(agp_bridge->current_size);
1515 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1517 /* address to map to */
1518 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1519 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1521 /* attbase - aperture base */
1522 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1525 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1528 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1529 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1530 /* clear any possible AGP-related error conditions */
1531 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1535 static int intel_7505_configure(void)
1539 struct aper_size_info_8 *current_size;
1541 current_size = A_SIZE_8(agp_bridge->current_size);
1544 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1546 /* address to map to */
1547 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1548 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1550 /* attbase - aperture base */
1551 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1554 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1557 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1558 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1563 /* Setup function */
1564 static const struct gatt_mask intel_generic_masks[] =
1566 {.mask = 0x00000017, .type = 0}
1569 static const struct aper_size_info_8 intel_815_sizes[2] =
1575 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1578 {128, 32768, 5, 32},
1586 static const struct aper_size_info_16 intel_generic_sizes[7] =
1589 {128, 32768, 5, 32},
1597 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1600 {128, 32768, 5, 32},
1605 static const struct agp_bridge_driver intel_generic_driver = {
1606 .owner = THIS_MODULE,
1607 .aperture_sizes = intel_generic_sizes,
1608 .size_type = U16_APER_SIZE,
1609 .num_aperture_sizes = 7,
1610 .configure = intel_configure,
1611 .fetch_size = intel_fetch_size,
1612 .cleanup = intel_cleanup,
1613 .tlb_flush = intel_tlbflush,
1614 .mask_memory = agp_generic_mask_memory,
1615 .masks = intel_generic_masks,
1616 .agp_enable = agp_generic_enable,
1617 .cache_flush = global_cache_flush,
1618 .create_gatt_table = agp_generic_create_gatt_table,
1619 .free_gatt_table = agp_generic_free_gatt_table,
1620 .insert_memory = agp_generic_insert_memory,
1621 .remove_memory = agp_generic_remove_memory,
1622 .alloc_by_type = agp_generic_alloc_by_type,
1623 .free_by_type = agp_generic_free_by_type,
1624 .agp_alloc_page = agp_generic_alloc_page,
1625 .agp_destroy_page = agp_generic_destroy_page,
1626 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1629 static const struct agp_bridge_driver intel_810_driver = {
1630 .owner = THIS_MODULE,
1631 .aperture_sizes = intel_i810_sizes,
1632 .size_type = FIXED_APER_SIZE,
1633 .num_aperture_sizes = 2,
1634 .needs_scratch_page = TRUE,
1635 .configure = intel_i810_configure,
1636 .fetch_size = intel_i810_fetch_size,
1637 .cleanup = intel_i810_cleanup,
1638 .tlb_flush = intel_i810_tlbflush,
1639 .mask_memory = intel_i810_mask_memory,
1640 .masks = intel_i810_masks,
1641 .agp_enable = intel_i810_agp_enable,
1642 .cache_flush = global_cache_flush,
1643 .create_gatt_table = agp_generic_create_gatt_table,
1644 .free_gatt_table = agp_generic_free_gatt_table,
1645 .insert_memory = intel_i810_insert_entries,
1646 .remove_memory = intel_i810_remove_entries,
1647 .alloc_by_type = intel_i810_alloc_by_type,
1648 .free_by_type = intel_i810_free_by_type,
1649 .agp_alloc_page = agp_generic_alloc_page,
1650 .agp_destroy_page = agp_generic_destroy_page,
1651 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1654 static const struct agp_bridge_driver intel_815_driver = {
1655 .owner = THIS_MODULE,
1656 .aperture_sizes = intel_815_sizes,
1657 .size_type = U8_APER_SIZE,
1658 .num_aperture_sizes = 2,
1659 .configure = intel_815_configure,
1660 .fetch_size = intel_815_fetch_size,
1661 .cleanup = intel_8xx_cleanup,
1662 .tlb_flush = intel_8xx_tlbflush,
1663 .mask_memory = agp_generic_mask_memory,
1664 .masks = intel_generic_masks,
1665 .agp_enable = agp_generic_enable,
1666 .cache_flush = global_cache_flush,
1667 .create_gatt_table = agp_generic_create_gatt_table,
1668 .free_gatt_table = agp_generic_free_gatt_table,
1669 .insert_memory = agp_generic_insert_memory,
1670 .remove_memory = agp_generic_remove_memory,
1671 .alloc_by_type = agp_generic_alloc_by_type,
1672 .free_by_type = agp_generic_free_by_type,
1673 .agp_alloc_page = agp_generic_alloc_page,
1674 .agp_destroy_page = agp_generic_destroy_page,
1675 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1678 static const struct agp_bridge_driver intel_830_driver = {
1679 .owner = THIS_MODULE,
1680 .aperture_sizes = intel_i830_sizes,
1681 .size_type = FIXED_APER_SIZE,
1682 .num_aperture_sizes = 4,
1683 .needs_scratch_page = TRUE,
1684 .configure = intel_i830_configure,
1685 .fetch_size = intel_i830_fetch_size,
1686 .cleanup = intel_i830_cleanup,
1687 .tlb_flush = intel_i810_tlbflush,
1688 .mask_memory = intel_i810_mask_memory,
1689 .masks = intel_i810_masks,
1690 .agp_enable = intel_i810_agp_enable,
1691 .cache_flush = global_cache_flush,
1692 .create_gatt_table = intel_i830_create_gatt_table,
1693 .free_gatt_table = intel_i830_free_gatt_table,
1694 .insert_memory = intel_i830_insert_entries,
1695 .remove_memory = intel_i830_remove_entries,
1696 .alloc_by_type = intel_i830_alloc_by_type,
1697 .free_by_type = intel_i810_free_by_type,
1698 .agp_alloc_page = agp_generic_alloc_page,
1699 .agp_destroy_page = agp_generic_destroy_page,
1700 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1701 .chipset_flush = intel_i830_chipset_flush,
1704 static const struct agp_bridge_driver intel_820_driver = {
1705 .owner = THIS_MODULE,
1706 .aperture_sizes = intel_8xx_sizes,
1707 .size_type = U8_APER_SIZE,
1708 .num_aperture_sizes = 7,
1709 .configure = intel_820_configure,
1710 .fetch_size = intel_8xx_fetch_size,
1711 .cleanup = intel_820_cleanup,
1712 .tlb_flush = intel_820_tlbflush,
1713 .mask_memory = agp_generic_mask_memory,
1714 .masks = intel_generic_masks,
1715 .agp_enable = agp_generic_enable,
1716 .cache_flush = global_cache_flush,
1717 .create_gatt_table = agp_generic_create_gatt_table,
1718 .free_gatt_table = agp_generic_free_gatt_table,
1719 .insert_memory = agp_generic_insert_memory,
1720 .remove_memory = agp_generic_remove_memory,
1721 .alloc_by_type = agp_generic_alloc_by_type,
1722 .free_by_type = agp_generic_free_by_type,
1723 .agp_alloc_page = agp_generic_alloc_page,
1724 .agp_destroy_page = agp_generic_destroy_page,
1725 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1728 static const struct agp_bridge_driver intel_830mp_driver = {
1729 .owner = THIS_MODULE,
1730 .aperture_sizes = intel_830mp_sizes,
1731 .size_type = U8_APER_SIZE,
1732 .num_aperture_sizes = 4,
1733 .configure = intel_830mp_configure,
1734 .fetch_size = intel_8xx_fetch_size,
1735 .cleanup = intel_8xx_cleanup,
1736 .tlb_flush = intel_8xx_tlbflush,
1737 .mask_memory = agp_generic_mask_memory,
1738 .masks = intel_generic_masks,
1739 .agp_enable = agp_generic_enable,
1740 .cache_flush = global_cache_flush,
1741 .create_gatt_table = agp_generic_create_gatt_table,
1742 .free_gatt_table = agp_generic_free_gatt_table,
1743 .insert_memory = agp_generic_insert_memory,
1744 .remove_memory = agp_generic_remove_memory,
1745 .alloc_by_type = agp_generic_alloc_by_type,
1746 .free_by_type = agp_generic_free_by_type,
1747 .agp_alloc_page = agp_generic_alloc_page,
1748 .agp_destroy_page = agp_generic_destroy_page,
1749 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1752 static const struct agp_bridge_driver intel_840_driver = {
1753 .owner = THIS_MODULE,
1754 .aperture_sizes = intel_8xx_sizes,
1755 .size_type = U8_APER_SIZE,
1756 .num_aperture_sizes = 7,
1757 .configure = intel_840_configure,
1758 .fetch_size = intel_8xx_fetch_size,
1759 .cleanup = intel_8xx_cleanup,
1760 .tlb_flush = intel_8xx_tlbflush,
1761 .mask_memory = agp_generic_mask_memory,
1762 .masks = intel_generic_masks,
1763 .agp_enable = agp_generic_enable,
1764 .cache_flush = global_cache_flush,
1765 .create_gatt_table = agp_generic_create_gatt_table,
1766 .free_gatt_table = agp_generic_free_gatt_table,
1767 .insert_memory = agp_generic_insert_memory,
1768 .remove_memory = agp_generic_remove_memory,
1769 .alloc_by_type = agp_generic_alloc_by_type,
1770 .free_by_type = agp_generic_free_by_type,
1771 .agp_alloc_page = agp_generic_alloc_page,
1772 .agp_destroy_page = agp_generic_destroy_page,
1773 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1776 static const struct agp_bridge_driver intel_845_driver = {
1777 .owner = THIS_MODULE,
1778 .aperture_sizes = intel_8xx_sizes,
1779 .size_type = U8_APER_SIZE,
1780 .num_aperture_sizes = 7,
1781 .configure = intel_845_configure,
1782 .fetch_size = intel_8xx_fetch_size,
1783 .cleanup = intel_8xx_cleanup,
1784 .tlb_flush = intel_8xx_tlbflush,
1785 .mask_memory = agp_generic_mask_memory,
1786 .masks = intel_generic_masks,
1787 .agp_enable = agp_generic_enable,
1788 .cache_flush = global_cache_flush,
1789 .create_gatt_table = agp_generic_create_gatt_table,
1790 .free_gatt_table = agp_generic_free_gatt_table,
1791 .insert_memory = agp_generic_insert_memory,
1792 .remove_memory = agp_generic_remove_memory,
1793 .alloc_by_type = agp_generic_alloc_by_type,
1794 .free_by_type = agp_generic_free_by_type,
1795 .agp_alloc_page = agp_generic_alloc_page,
1796 .agp_destroy_page = agp_generic_destroy_page,
1797 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1798 .chipset_flush = intel_i830_chipset_flush,
1801 static const struct agp_bridge_driver intel_850_driver = {
1802 .owner = THIS_MODULE,
1803 .aperture_sizes = intel_8xx_sizes,
1804 .size_type = U8_APER_SIZE,
1805 .num_aperture_sizes = 7,
1806 .configure = intel_850_configure,
1807 .fetch_size = intel_8xx_fetch_size,
1808 .cleanup = intel_8xx_cleanup,
1809 .tlb_flush = intel_8xx_tlbflush,
1810 .mask_memory = agp_generic_mask_memory,
1811 .masks = intel_generic_masks,
1812 .agp_enable = agp_generic_enable,
1813 .cache_flush = global_cache_flush,
1814 .create_gatt_table = agp_generic_create_gatt_table,
1815 .free_gatt_table = agp_generic_free_gatt_table,
1816 .insert_memory = agp_generic_insert_memory,
1817 .remove_memory = agp_generic_remove_memory,
1818 .alloc_by_type = agp_generic_alloc_by_type,
1819 .free_by_type = agp_generic_free_by_type,
1820 .agp_alloc_page = agp_generic_alloc_page,
1821 .agp_destroy_page = agp_generic_destroy_page,
1822 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1825 static const struct agp_bridge_driver intel_860_driver = {
1826 .owner = THIS_MODULE,
1827 .aperture_sizes = intel_8xx_sizes,
1828 .size_type = U8_APER_SIZE,
1829 .num_aperture_sizes = 7,
1830 .configure = intel_860_configure,
1831 .fetch_size = intel_8xx_fetch_size,
1832 .cleanup = intel_8xx_cleanup,
1833 .tlb_flush = intel_8xx_tlbflush,
1834 .mask_memory = agp_generic_mask_memory,
1835 .masks = intel_generic_masks,
1836 .agp_enable = agp_generic_enable,
1837 .cache_flush = global_cache_flush,
1838 .create_gatt_table = agp_generic_create_gatt_table,
1839 .free_gatt_table = agp_generic_free_gatt_table,
1840 .insert_memory = agp_generic_insert_memory,
1841 .remove_memory = agp_generic_remove_memory,
1842 .alloc_by_type = agp_generic_alloc_by_type,
1843 .free_by_type = agp_generic_free_by_type,
1844 .agp_alloc_page = agp_generic_alloc_page,
1845 .agp_destroy_page = agp_generic_destroy_page,
1846 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1849 static const struct agp_bridge_driver intel_915_driver = {
1850 .owner = THIS_MODULE,
1851 .aperture_sizes = intel_i830_sizes,
1852 .size_type = FIXED_APER_SIZE,
1853 .num_aperture_sizes = 4,
1854 .needs_scratch_page = TRUE,
1855 .configure = intel_i915_configure,
1856 .fetch_size = intel_i9xx_fetch_size,
1857 .cleanup = intel_i915_cleanup,
1858 .tlb_flush = intel_i810_tlbflush,
1859 .mask_memory = intel_i810_mask_memory,
1860 .masks = intel_i810_masks,
1861 .agp_enable = intel_i810_agp_enable,
1862 .cache_flush = global_cache_flush,
1863 .create_gatt_table = intel_i915_create_gatt_table,
1864 .free_gatt_table = intel_i830_free_gatt_table,
1865 .insert_memory = intel_i915_insert_entries,
1866 .remove_memory = intel_i915_remove_entries,
1867 .alloc_by_type = intel_i830_alloc_by_type,
1868 .free_by_type = intel_i810_free_by_type,
1869 .agp_alloc_page = agp_generic_alloc_page,
1870 .agp_destroy_page = agp_generic_destroy_page,
1871 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1872 .chipset_flush = intel_i915_chipset_flush,
1875 static const struct agp_bridge_driver intel_i965_driver = {
1876 .owner = THIS_MODULE,
1877 .aperture_sizes = intel_i830_sizes,
1878 .size_type = FIXED_APER_SIZE,
1879 .num_aperture_sizes = 4,
1880 .needs_scratch_page = TRUE,
1881 .configure = intel_i915_configure,
1882 .fetch_size = intel_i9xx_fetch_size,
1883 .cleanup = intel_i915_cleanup,
1884 .tlb_flush = intel_i810_tlbflush,
1885 .mask_memory = intel_i965_mask_memory,
1886 .masks = intel_i810_masks,
1887 .agp_enable = intel_i810_agp_enable,
1888 .cache_flush = global_cache_flush,
1889 .create_gatt_table = intel_i965_create_gatt_table,
1890 .free_gatt_table = intel_i830_free_gatt_table,
1891 .insert_memory = intel_i915_insert_entries,
1892 .remove_memory = intel_i915_remove_entries,
1893 .alloc_by_type = intel_i830_alloc_by_type,
1894 .free_by_type = intel_i810_free_by_type,
1895 .agp_alloc_page = agp_generic_alloc_page,
1896 .agp_destroy_page = agp_generic_destroy_page,
1897 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1898 .chipset_flush = intel_i915_chipset_flush,
1901 static const struct agp_bridge_driver intel_7505_driver = {
1902 .owner = THIS_MODULE,
1903 .aperture_sizes = intel_8xx_sizes,
1904 .size_type = U8_APER_SIZE,
1905 .num_aperture_sizes = 7,
1906 .configure = intel_7505_configure,
1907 .fetch_size = intel_8xx_fetch_size,
1908 .cleanup = intel_8xx_cleanup,
1909 .tlb_flush = intel_8xx_tlbflush,
1910 .mask_memory = agp_generic_mask_memory,
1911 .masks = intel_generic_masks,
1912 .agp_enable = agp_generic_enable,
1913 .cache_flush = global_cache_flush,
1914 .create_gatt_table = agp_generic_create_gatt_table,
1915 .free_gatt_table = agp_generic_free_gatt_table,
1916 .insert_memory = agp_generic_insert_memory,
1917 .remove_memory = agp_generic_remove_memory,
1918 .alloc_by_type = agp_generic_alloc_by_type,
1919 .free_by_type = agp_generic_free_by_type,
1920 .agp_alloc_page = agp_generic_alloc_page,
1921 .agp_destroy_page = agp_generic_destroy_page,
1922 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1925 static const struct agp_bridge_driver intel_g33_driver = {
1926 .owner = THIS_MODULE,
1927 .aperture_sizes = intel_i830_sizes,
1928 .size_type = FIXED_APER_SIZE,
1929 .num_aperture_sizes = 4,
1930 .needs_scratch_page = TRUE,
1931 .configure = intel_i915_configure,
1932 .fetch_size = intel_i9xx_fetch_size,
1933 .cleanup = intel_i915_cleanup,
1934 .tlb_flush = intel_i810_tlbflush,
1935 .mask_memory = intel_i965_mask_memory,
1936 .masks = intel_i810_masks,
1937 .agp_enable = intel_i810_agp_enable,
1938 .cache_flush = global_cache_flush,
1939 .create_gatt_table = intel_i915_create_gatt_table,
1940 .free_gatt_table = intel_i830_free_gatt_table,
1941 .insert_memory = intel_i915_insert_entries,
1942 .remove_memory = intel_i915_remove_entries,
1943 .alloc_by_type = intel_i830_alloc_by_type,
1944 .free_by_type = intel_i810_free_by_type,
1945 .agp_alloc_page = agp_generic_alloc_page,
1946 .agp_destroy_page = agp_generic_destroy_page,
1947 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1948 .chipset_flush = intel_i915_chipset_flush,
1951 static int find_gmch(u16 device)
1953 struct pci_dev *gmch_device;
1955 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1956 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1957 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1958 device, gmch_device);
1964 intel_private.pcidev = gmch_device;
1968 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1969 * driver and gmch_driver must be non-null, and find_gmch will determine
1970 * which one should be used if a gmch_chip_id is present.
1972 static const struct intel_driver_description {
1973 unsigned int chip_id;
1974 unsigned int gmch_chip_id;
1975 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
1977 const struct agp_bridge_driver *driver;
1978 const struct agp_bridge_driver *gmch_driver;
1979 } intel_agp_chipsets[] = {
1980 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
1981 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
1982 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
1983 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
1984 NULL, &intel_810_driver },
1985 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
1986 NULL, &intel_810_driver },
1987 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
1988 NULL, &intel_810_driver },
1989 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
1990 &intel_815_driver, &intel_810_driver },
1991 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
1992 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
1993 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
1994 &intel_830mp_driver, &intel_830_driver },
1995 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
1996 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
1997 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
1998 &intel_845_driver, &intel_830_driver },
1999 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2000 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2001 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2002 &intel_845_driver, &intel_830_driver },
2003 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2004 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2005 &intel_845_driver, &intel_830_driver },
2006 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2007 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2008 NULL, &intel_915_driver },
2009 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2010 NULL, &intel_915_driver },
2011 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2012 NULL, &intel_915_driver },
2013 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2014 NULL, &intel_915_driver },
2015 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2016 NULL, &intel_915_driver },
2017 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2018 NULL, &intel_915_driver },
2019 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2020 NULL, &intel_i965_driver },
2021 { PCI_DEVICE_ID_INTEL_82965G_1_HB, PCI_DEVICE_ID_INTEL_82965G_1_IG, 0, "965G",
2022 NULL, &intel_i965_driver },
2023 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2024 NULL, &intel_i965_driver },
2025 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2026 NULL, &intel_i965_driver },
2027 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2028 NULL, &intel_i965_driver },
2029 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2030 NULL, &intel_i965_driver },
2031 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2032 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2033 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2034 NULL, &intel_g33_driver },
2035 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2036 NULL, &intel_g33_driver },
2037 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2038 NULL, &intel_g33_driver },
2039 { 0, 0, 0, NULL, NULL, NULL }
2042 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2043 const struct pci_device_id *ent)
2045 struct agp_bridge_data *bridge;
2050 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2052 bridge = agp_alloc_bridge();
2056 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2057 /* In case that multiple models of gfx chip may
2058 stand on same host bridge type, this can be
2059 sure we detect the right IGD. */
2060 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2061 if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2062 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2064 intel_agp_chipsets[i].gmch_driver;
2066 } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2069 bridge->driver = intel_agp_chipsets[i].driver;
2075 if (intel_agp_chipsets[i].name == NULL) {
2077 printk(KERN_WARNING PFX "Unsupported Intel chipset"
2078 "(device id: %04x)\n", pdev->device);
2079 agp_put_bridge(bridge);
2083 if (bridge->driver == NULL) {
2084 /* bridge has no AGP and no IGD detected */
2086 printk(KERN_WARNING PFX "Failed to find bridge device "
2087 "(chip_id: %04x)\n",
2088 intel_agp_chipsets[i].gmch_chip_id);
2089 agp_put_bridge(bridge);
2094 bridge->capndx = cap_ptr;
2095 bridge->dev_private_data = &intel_private;
2097 printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n",
2098 intel_agp_chipsets[i].name);
2101 * The following fixes the case where the BIOS has "forgotten" to
2102 * provide an address range for the GART.
2103 * 20030610 - hamish@zot.org
2105 r = &pdev->resource[0];
2106 if (!r->start && r->end) {
2107 if (pci_assign_resource(pdev, 0)) {
2108 printk(KERN_ERR PFX "could not assign resource 0\n");
2109 agp_put_bridge(bridge);
2115 * If the device has not been properly setup, the following will catch
2116 * the problem and should stop the system from crashing.
2117 * 20030610 - hamish@zot.org
2119 if (pci_enable_device(pdev)) {
2120 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
2121 agp_put_bridge(bridge);
2125 /* Fill in the mode register */
2127 pci_read_config_dword(pdev,
2128 bridge->capndx+PCI_AGP_STATUS,
2132 pci_set_drvdata(pdev, bridge);
2133 return agp_add_bridge(bridge);
2136 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2138 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2140 agp_remove_bridge(bridge);
2142 if (intel_private.pcidev)
2143 pci_dev_put(intel_private.pcidev);
2145 agp_put_bridge(bridge);
2149 static int agp_intel_resume(struct pci_dev *pdev)
2151 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2153 pci_restore_state(pdev);
2155 /* We should restore our graphics device's config space,
2156 * as host bridge (00:00) resumes before graphics device (02:00),
2157 * then our access to its pci space can work right.
2159 if (intel_private.pcidev)
2160 pci_restore_state(intel_private.pcidev);
2162 if (bridge->driver == &intel_generic_driver)
2164 else if (bridge->driver == &intel_850_driver)
2165 intel_850_configure();
2166 else if (bridge->driver == &intel_845_driver)
2167 intel_845_configure();
2168 else if (bridge->driver == &intel_830mp_driver)
2169 intel_830mp_configure();
2170 else if (bridge->driver == &intel_915_driver)
2171 intel_i915_configure();
2172 else if (bridge->driver == &intel_830_driver)
2173 intel_i830_configure();
2174 else if (bridge->driver == &intel_810_driver)
2175 intel_i810_configure();
2176 else if (bridge->driver == &intel_i965_driver)
2177 intel_i915_configure();
2183 static struct pci_device_id agp_intel_pci_table[] = {
2186 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
2188 .vendor = PCI_VENDOR_ID_INTEL, \
2190 .subvendor = PCI_ANY_ID, \
2191 .subdevice = PCI_ANY_ID, \
2193 ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2194 ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2195 ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2196 ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2197 ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2198 ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2199 ID(PCI_DEVICE_ID_INTEL_82815_MC),
2200 ID(PCI_DEVICE_ID_INTEL_82820_HB),
2201 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2202 ID(PCI_DEVICE_ID_INTEL_82830_HB),
2203 ID(PCI_DEVICE_ID_INTEL_82840_HB),
2204 ID(PCI_DEVICE_ID_INTEL_82845_HB),
2205 ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2206 ID(PCI_DEVICE_ID_INTEL_82850_HB),
2207 ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2208 ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2209 ID(PCI_DEVICE_ID_INTEL_82860_HB),
2210 ID(PCI_DEVICE_ID_INTEL_82865_HB),
2211 ID(PCI_DEVICE_ID_INTEL_82875_HB),
2212 ID(PCI_DEVICE_ID_INTEL_7505_0),
2213 ID(PCI_DEVICE_ID_INTEL_7205_0),
2214 ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2215 ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2216 ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2217 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2218 ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2219 ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2220 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2221 ID(PCI_DEVICE_ID_INTEL_82965G_1_HB),
2222 ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2223 ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2224 ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2225 ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2226 ID(PCI_DEVICE_ID_INTEL_G33_HB),
2227 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2228 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2232 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2234 static struct pci_driver agp_intel_pci_driver = {
2235 .name = "agpgart-intel",
2236 .id_table = agp_intel_pci_table,
2237 .probe = agp_intel_probe,
2238 .remove = __devexit_p(agp_intel_remove),
2240 .resume = agp_intel_resume,
2244 static int __init agp_intel_init(void)
2248 return pci_register_driver(&agp_intel_pci_driver);
2251 static void __exit agp_intel_cleanup(void)
2253 pci_unregister_driver(&agp_intel_pci_driver);
2256 module_init(agp_intel_init);
2257 module_exit(agp_intel_cleanup);
2259 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2260 MODULE_LICENSE("GPL and additional rights");