2 Driver for Philips tda1004xh OFDM Demodulator
4 (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * This driver needs external firmware. Please use the commands
24 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045",
25 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to
26 * download/extract them, and then copy them to /usr/lib/hotplug/firmware.
28 #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
29 #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
31 #include <linux/init.h>
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/device.h>
35 #include <linux/jiffies.h>
36 #include <linux/string.h>
37 #include <linux/slab.h>
39 #include "dvb_frontend.h"
43 TDA1004X_DEMOD_TDA10045,
44 TDA1004X_DEMOD_TDA10046,
47 struct tda1004x_state {
48 struct i2c_adapter* i2c;
49 struct dvb_frontend_ops ops;
50 const struct tda1004x_config* config;
51 struct dvb_frontend frontend;
53 /* private demod data */
55 enum tda1004x_demod demod_type;
59 #define dprintk(args...) \
61 if (debug) printk(KERN_DEBUG "tda1004x: " args); \
64 #define TDA1004X_CHIPID 0x00
65 #define TDA1004X_AUTO 0x01
66 #define TDA1004X_IN_CONF1 0x02
67 #define TDA1004X_IN_CONF2 0x03
68 #define TDA1004X_OUT_CONF1 0x04
69 #define TDA1004X_OUT_CONF2 0x05
70 #define TDA1004X_STATUS_CD 0x06
71 #define TDA1004X_CONFC4 0x07
72 #define TDA1004X_DSSPARE2 0x0C
73 #define TDA10045H_CODE_IN 0x0D
74 #define TDA10045H_FWPAGE 0x0E
75 #define TDA1004X_SCAN_CPT 0x10
76 #define TDA1004X_DSP_CMD 0x11
77 #define TDA1004X_DSP_ARG 0x12
78 #define TDA1004X_DSP_DATA1 0x13
79 #define TDA1004X_DSP_DATA2 0x14
80 #define TDA1004X_CONFADC1 0x15
81 #define TDA1004X_CONFC1 0x16
82 #define TDA10045H_S_AGC 0x1a
83 #define TDA10046H_AGC_TUN_LEVEL 0x1a
84 #define TDA1004X_SNR 0x1c
85 #define TDA1004X_CONF_TS1 0x1e
86 #define TDA1004X_CONF_TS2 0x1f
87 #define TDA1004X_CBER_RESET 0x20
88 #define TDA1004X_CBER_MSB 0x21
89 #define TDA1004X_CBER_LSB 0x22
90 #define TDA1004X_CVBER_LUT 0x23
91 #define TDA1004X_VBER_MSB 0x24
92 #define TDA1004X_VBER_MID 0x25
93 #define TDA1004X_VBER_LSB 0x26
94 #define TDA1004X_UNCOR 0x27
96 #define TDA10045H_CONFPLL_P 0x2D
97 #define TDA10045H_CONFPLL_M_MSB 0x2E
98 #define TDA10045H_CONFPLL_M_LSB 0x2F
99 #define TDA10045H_CONFPLL_N 0x30
101 #define TDA10046H_CONFPLL1 0x2D
102 #define TDA10046H_CONFPLL2 0x2F
103 #define TDA10046H_CONFPLL3 0x30
104 #define TDA10046H_TIME_WREF1 0x31
105 #define TDA10046H_TIME_WREF2 0x32
106 #define TDA10046H_TIME_WREF3 0x33
107 #define TDA10046H_TIME_WREF4 0x34
108 #define TDA10046H_TIME_WREF5 0x35
110 #define TDA10045H_UNSURW_MSB 0x31
111 #define TDA10045H_UNSURW_LSB 0x32
112 #define TDA10045H_WREF_MSB 0x33
113 #define TDA10045H_WREF_MID 0x34
114 #define TDA10045H_WREF_LSB 0x35
115 #define TDA10045H_MUXOUT 0x36
116 #define TDA1004X_CONFADC2 0x37
118 #define TDA10045H_IOFFSET 0x38
120 #define TDA10046H_CONF_TRISTATE1 0x3B
121 #define TDA10046H_CONF_TRISTATE2 0x3C
122 #define TDA10046H_CONF_POLARITY 0x3D
123 #define TDA10046H_FREQ_OFFSET 0x3E
124 #define TDA10046H_GPIO_OUT_SEL 0x41
125 #define TDA10046H_GPIO_SELECT 0x42
126 #define TDA10046H_AGC_CONF 0x43
127 #define TDA10046H_AGC_THR 0x44
128 #define TDA10046H_AGC_RENORM 0x45
129 #define TDA10046H_AGC_GAINS 0x46
130 #define TDA10046H_AGC_TUN_MIN 0x47
131 #define TDA10046H_AGC_TUN_MAX 0x48
132 #define TDA10046H_AGC_IF_MIN 0x49
133 #define TDA10046H_AGC_IF_MAX 0x4A
135 #define TDA10046H_FREQ_PHY2_MSB 0x4D
136 #define TDA10046H_FREQ_PHY2_LSB 0x4E
138 #define TDA10046H_CVBER_CTRL 0x4F
139 #define TDA10046H_AGC_IF_LEVEL 0x52
140 #define TDA10046H_CODE_CPT 0x57
141 #define TDA10046H_CODE_IN 0x58
144 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
147 u8 buf[] = { reg, data };
148 struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
150 dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
152 msg.addr = state->config->demod_address;
153 ret = i2c_transfer(state->i2c, &msg, 1);
156 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
157 __FUNCTION__, reg, data, ret);
159 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
161 return (ret != 1) ? -1 : 0;
164 static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
169 struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
170 { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
172 dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
174 msg[0].addr = state->config->demod_address;
175 msg[1].addr = state->config->demod_address;
176 ret = i2c_transfer(state->i2c, msg, 2);
179 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
184 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
189 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
192 dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
195 // read a byte and check
196 val = tda1004x_read_byte(state, reg);
204 // write it out again
205 return tda1004x_write_byteI(state, reg, val);
208 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
213 dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
216 for (i = 0; i < len; i++) {
217 result = tda1004x_write_byteI(state, reg + i, buf[i]);
225 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
228 dprintk("%s\n", __FUNCTION__);
230 result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
235 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
237 dprintk("%s\n", __FUNCTION__);
239 return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
242 static int tda10045h_set_bandwidth(struct tda1004x_state *state,
243 fe_bandwidth_t bandwidth)
245 static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
246 static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
247 static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
250 case BANDWIDTH_6_MHZ:
251 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
254 case BANDWIDTH_7_MHZ:
255 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
258 case BANDWIDTH_8_MHZ:
259 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
266 tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
271 static int tda10046h_set_bandwidth(struct tda1004x_state *state,
272 fe_bandwidth_t bandwidth)
274 static u8 bandwidth_6mhz[] = { 0x80, 0x15, 0xfe, 0xab, 0x8e };
275 static u8 bandwidth_7mhz[] = { 0x6e, 0x02, 0x53, 0xc8, 0x25 };
276 static u8 bandwidth_8mhz[] = { 0x60, 0x12, 0xa8, 0xe4, 0xbd };
279 case BANDWIDTH_6_MHZ:
280 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz, sizeof(bandwidth_6mhz));
281 if (state->config->if_freq == TDA10046_FREQ_045) {
282 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x09);
283 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x4f);
287 case BANDWIDTH_7_MHZ:
288 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz, sizeof(bandwidth_7mhz));
289 if (state->config->if_freq == TDA10046_FREQ_045) {
290 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
291 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x79);
295 case BANDWIDTH_8_MHZ:
296 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz, sizeof(bandwidth_8mhz));
297 if (state->config->if_freq == TDA10046_FREQ_045) {
298 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0b);
299 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xa3);
310 static int tda1004x_do_upload(struct tda1004x_state *state,
311 unsigned char *mem, unsigned int len,
312 u8 dspCodeCounterReg, u8 dspCodeInReg)
315 struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
319 /* clear code counter */
320 tda1004x_write_byteI(state, dspCodeCounterReg, 0);
321 fw_msg.addr = state->config->demod_address;
323 buf[0] = dspCodeInReg;
325 // work out how much to send this time
331 memcpy(buf + 1, mem + pos, tx_size);
332 fw_msg.len = tx_size + 1;
333 if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
334 printk(KERN_ERR "tda1004x: Error during firmware upload\n");
339 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, pos);
341 // give the DSP a chance to settle 03/10/05 Hac
347 static int tda1004x_check_upload_ok(struct tda1004x_state *state)
350 unsigned long timeout;
352 if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
353 timeout = jiffies + 2 * HZ;
354 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
355 if (time_after(jiffies, timeout)) {
356 printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
364 // check upload was OK
365 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
366 tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
368 data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
369 data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
370 if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) {
371 printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
374 printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
378 static int tda10045_fwupload(struct dvb_frontend* fe)
380 struct tda1004x_state* state = fe->demodulator_priv;
382 const struct firmware *fw;
384 /* don't re-upload unless necessary */
385 if (tda1004x_check_upload_ok(state) == 0)
388 /* request the firmware, this will block until someone uploads it */
389 printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
390 ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
392 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
397 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
398 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
399 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
403 tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ);
405 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
406 release_firmware(fw);
409 printk(KERN_INFO "tda1004x: firmware upload complete\n");
411 /* wait for DSP to initialise */
412 /* DSPREADY doesn't seem to work on the TDA10045H */
415 return tda1004x_check_upload_ok(state);
418 static void tda10046_init_plls(struct dvb_frontend* fe)
420 struct tda1004x_state* state = fe->demodulator_priv;
422 tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
423 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x0a); // PLL M = 10
424 if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
425 dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __FUNCTION__);
426 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
428 dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __FUNCTION__);
429 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
431 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99);
432 switch (state->config->if_freq) {
433 case TDA10046_FREQ_3617:
434 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
435 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c);
437 case TDA10046_FREQ_3613:
438 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
439 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x13);
441 case TDA10046_FREQ_045:
442 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0b);
443 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xa3);
445 case TDA10046_FREQ_052:
446 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
447 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x06);
450 tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
453 static int tda10046_fwupload(struct dvb_frontend* fe)
455 struct tda1004x_state* state = fe->demodulator_priv;
457 const struct firmware *fw;
459 /* reset + wake up chip */
460 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0);
461 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
462 /* let the clocks recover from sleep */
465 /* don't re-upload unless necessary */
466 if (tda1004x_check_upload_ok(state) == 0)
470 tda10046_init_plls(fe);
472 if (state->config->request_firmware != NULL) {
473 /* request the firmware, this will block until someone uploads it */
474 printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
475 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
477 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
480 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
481 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
482 release_firmware(fw);
486 /* boot from firmware eeprom */
487 /* Hac Note: we might need to do some GPIO Magic here */
488 printk(KERN_INFO "tda1004x: booting from eeprom\n");
489 tda1004x_write_mask(state, TDA1004X_CONFC4, 4, 4);
492 return tda1004x_check_upload_ok(state);
495 static int tda1004x_encode_fec(int fec)
497 // convert known FEC values
515 static int tda1004x_decode_fec(int tdafec)
517 // convert known FEC values
535 int tda1004x_write_byte(struct dvb_frontend* fe, int reg, int data)
537 struct tda1004x_state* state = fe->demodulator_priv;
539 return tda1004x_write_byteI(state, reg, data);
542 static int tda10045_init(struct dvb_frontend* fe)
544 struct tda1004x_state* state = fe->demodulator_priv;
546 dprintk("%s\n", __FUNCTION__);
548 if (state->initialised)
551 if (tda10045_fwupload(fe)) {
552 printk("tda1004x: firmware upload failed\n");
556 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
559 if (state->config->pll_init) {
560 tda1004x_enable_tuner_i2c(state);
561 state->config->pll_init(fe);
562 tda1004x_disable_tuner_i2c(state);
566 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
567 tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
568 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
569 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
570 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
571 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
572 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
573 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
574 tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
575 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
576 tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
578 tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
580 state->initialised = 1;
584 static int tda10046_init(struct dvb_frontend* fe)
586 struct tda1004x_state* state = fe->demodulator_priv;
587 dprintk("%s\n", __FUNCTION__);
589 if (state->initialised)
592 if (tda10046_fwupload(fe)) {
593 printk("tda1004x: firmware upload failed\n");
597 // Init the tuner PLL
598 if (state->config->pll_init) {
599 tda1004x_enable_tuner_i2c(state);
600 if (state->config->pll_init(fe)) {
601 printk(KERN_ERR "tda1004x: pll init failed\n");
604 tda1004x_disable_tuner_i2c(state);
608 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
609 tda1004x_write_byteI(state, TDA1004X_AUTO, 7); // select HP stream
610 tda1004x_write_byteI(state, TDA1004X_CONFC1, 8); // disable pulse killer
612 tda10046_init_plls(fe);
613 switch (state->config->agc_config) {
614 case TDA10046_AGC_DEFAULT:
615 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
616 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
618 case TDA10046_AGC_IFO_AUTO_NEG:
619 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
620 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
622 case TDA10046_AGC_IFO_AUTO_POS:
623 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
624 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x00); // set AGC polarities
626 case TDA10046_AGC_TDA827X:
627 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup
628 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold
629 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x0E); // Gain Renormalize
630 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
633 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0x61); // Turn both AGC outputs on
634 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // }
635 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
636 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // }
637 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // }
638 tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 1); // IF gain 2, TUN gain 1
639 tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
640 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
641 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
642 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
644 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0xe1); // tristate setup
645 tda1004x_write_byteI(state, TDA10046H_GPIO_OUT_SEL, 0xcc); // GPIO output config
646 tda1004x_write_byteI(state, TDA10046H_GPIO_SELECT, 8); // GPIO select
648 state->initialised = 1;
652 static int tda1004x_set_fe(struct dvb_frontend* fe,
653 struct dvb_frontend_parameters *fe_params)
655 struct tda1004x_state* state = fe->demodulator_priv;
659 dprintk("%s\n", __FUNCTION__);
661 if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
663 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
664 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
665 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
667 // disable agc_conf[2]
668 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
672 tda1004x_enable_tuner_i2c(state);
673 if (state->config->pll_set(fe, fe_params)) {
674 printk(KERN_ERR "tda1004x: pll set failed\n");
677 tda1004x_disable_tuner_i2c(state);
679 // Hardcoded to use auto as much as possible on the TDA10045 as it
680 // is very unreliable if AUTO mode is _not_ used.
681 if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
682 fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
683 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
684 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
687 // Set standard params.. or put them to auto
688 if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
689 (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
690 (fe_params->u.ofdm.constellation == QAM_AUTO) ||
691 (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
692 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto
693 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
694 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
695 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
697 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto
700 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
703 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
706 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
709 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
712 switch (fe_params->u.ofdm.constellation) {
714 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
718 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
722 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
730 switch (fe_params->u.ofdm.hierarchy_information) {
732 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
736 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
740 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
744 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
753 switch (state->demod_type) {
754 case TDA1004X_DEMOD_TDA10045:
755 tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
758 case TDA1004X_DEMOD_TDA10046:
759 tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
764 inversion = fe_params->inversion;
765 if (state->config->invert)
766 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
769 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
773 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
780 // set guard interval
781 switch (fe_params->u.ofdm.guard_interval) {
782 case GUARD_INTERVAL_1_32:
783 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
784 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
787 case GUARD_INTERVAL_1_16:
788 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
789 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
792 case GUARD_INTERVAL_1_8:
793 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
794 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
797 case GUARD_INTERVAL_1_4:
798 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
799 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
802 case GUARD_INTERVAL_AUTO:
803 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
804 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
811 // set transmission mode
812 switch (fe_params->u.ofdm.transmission_mode) {
813 case TRANSMISSION_MODE_2K:
814 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
815 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
818 case TRANSMISSION_MODE_8K:
819 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
820 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
823 case TRANSMISSION_MODE_AUTO:
824 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
825 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
833 switch (state->demod_type) {
834 case TDA1004X_DEMOD_TDA10045:
835 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
836 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
839 case TDA1004X_DEMOD_TDA10046:
840 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
842 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1);
851 static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params)
853 struct tda1004x_state* state = fe->demodulator_priv;
854 dprintk("%s\n", __FUNCTION__);
857 fe_params->inversion = INVERSION_OFF;
858 if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
859 fe_params->inversion = INVERSION_ON;
860 if (state->config->invert)
861 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
864 switch (state->demod_type) {
865 case TDA1004X_DEMOD_TDA10045:
866 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
868 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
871 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
874 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
879 case TDA1004X_DEMOD_TDA10046:
880 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
882 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
885 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
888 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
895 fe_params->u.ofdm.code_rate_HP =
896 tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
897 fe_params->u.ofdm.code_rate_LP =
898 tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
901 switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
903 fe_params->u.ofdm.constellation = QPSK;
906 fe_params->u.ofdm.constellation = QAM_16;
909 fe_params->u.ofdm.constellation = QAM_64;
914 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
915 if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
916 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
919 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
921 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
924 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
927 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
930 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
935 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
937 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
940 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
943 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
946 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
953 static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status)
955 struct tda1004x_state* state = fe->demodulator_priv;
960 dprintk("%s\n", __FUNCTION__);
963 status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
970 *fe_status |= FE_HAS_SIGNAL;
972 *fe_status |= FE_HAS_CARRIER;
974 *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
976 // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
977 // is getting anything valid
978 if (!(*fe_status & FE_HAS_VITERBI)) {
980 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
983 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
986 cber |= (status << 8);
987 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
990 *fe_status |= FE_HAS_VITERBI;
993 // if we DO have some valid VITERBI output, but don't already have SYNC
994 // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
995 if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
997 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
1000 status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
1003 vber |= (status << 8);
1004 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
1007 vber |= ((status << 16) & 0x0f);
1008 tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
1010 // if RS has passed some valid TS packets, then we must be
1011 // getting some SYNC bytes
1013 *fe_status |= FE_HAS_SYNC;
1017 dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
1021 static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
1023 struct tda1004x_state* state = fe->demodulator_priv;
1027 dprintk("%s\n", __FUNCTION__);
1029 // determine the register to use
1030 switch (state->demod_type) {
1031 case TDA1004X_DEMOD_TDA10045:
1032 reg = TDA10045H_S_AGC;
1035 case TDA1004X_DEMOD_TDA10046:
1036 reg = TDA10046H_AGC_IF_LEVEL;
1041 tmp = tda1004x_read_byte(state, reg);
1045 *signal = (tmp << 8) | tmp;
1046 dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
1050 static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
1052 struct tda1004x_state* state = fe->demodulator_priv;
1055 dprintk("%s\n", __FUNCTION__);
1058 tmp = tda1004x_read_byte(state, TDA1004X_SNR);
1063 *snr = ((tmp << 8) | tmp);
1064 dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
1068 static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
1070 struct tda1004x_state* state = fe->demodulator_priv;
1075 dprintk("%s\n", __FUNCTION__);
1077 // read the UCBLOCKS and reset
1079 tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
1083 while (counter++ < 5) {
1084 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1085 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1086 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1088 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
1092 if ((tmp2 < tmp) || (tmp2 == 0))
1099 *ucblocks = 0xffffffff;
1101 dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1105 static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
1107 struct tda1004x_state* state = fe->demodulator_priv;
1110 dprintk("%s\n", __FUNCTION__);
1113 tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1117 tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1121 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1123 dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1127 static int tda1004x_sleep(struct dvb_frontend* fe)
1129 struct tda1004x_state* state = fe->demodulator_priv;
1131 switch (state->demod_type) {
1132 case TDA1004X_DEMOD_TDA10045:
1133 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1136 case TDA1004X_DEMOD_TDA10046:
1137 if (state->config->pll_sleep != NULL) {
1138 tda1004x_enable_tuner_i2c(state);
1139 state->config->pll_sleep(fe);
1140 if (state->config->if_freq != TDA10046_FREQ_052) {
1141 /* special hack for Philips EUROPA Based boards:
1142 * keep the I2c bridge open for tuner access in analog mode
1144 tda1004x_disable_tuner_i2c(state);
1147 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
1150 state->initialised = 0;
1155 static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1157 fesettings->min_delay_ms = 800;
1158 /* Drift compensation makes no sense for DVB-T */
1159 fesettings->step_size = 0;
1160 fesettings->max_drift = 0;
1164 static void tda1004x_release(struct dvb_frontend* fe)
1166 struct tda1004x_state *state = fe->demodulator_priv;
1170 static struct dvb_frontend_ops tda10045_ops = {
1172 .name = "Philips TDA10045H DVB-T",
1174 .frequency_min = 51000000,
1175 .frequency_max = 858000000,
1176 .frequency_stepsize = 166667,
1178 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1179 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1180 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1181 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1184 .release = tda1004x_release,
1186 .init = tda10045_init,
1187 .sleep = tda1004x_sleep,
1189 .set_frontend = tda1004x_set_fe,
1190 .get_frontend = tda1004x_get_fe,
1191 .get_tune_settings = tda1004x_get_tune_settings,
1193 .read_status = tda1004x_read_status,
1194 .read_ber = tda1004x_read_ber,
1195 .read_signal_strength = tda1004x_read_signal_strength,
1196 .read_snr = tda1004x_read_snr,
1197 .read_ucblocks = tda1004x_read_ucblocks,
1200 struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1201 struct i2c_adapter* i2c)
1203 struct tda1004x_state *state;
1205 /* allocate memory for the internal state */
1206 state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1210 /* setup the state */
1211 state->config = config;
1213 memcpy(&state->ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
1214 state->initialised = 0;
1215 state->demod_type = TDA1004X_DEMOD_TDA10045;
1217 /* check if the demod is there */
1218 if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x25) {
1223 /* create dvb_frontend */
1224 state->frontend.ops = &state->ops;
1225 state->frontend.demodulator_priv = state;
1226 return &state->frontend;
1229 static struct dvb_frontend_ops tda10046_ops = {
1231 .name = "Philips TDA10046H DVB-T",
1233 .frequency_min = 51000000,
1234 .frequency_max = 858000000,
1235 .frequency_stepsize = 166667,
1237 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1238 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1239 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1240 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1243 .release = tda1004x_release,
1245 .init = tda10046_init,
1246 .sleep = tda1004x_sleep,
1248 .set_frontend = tda1004x_set_fe,
1249 .get_frontend = tda1004x_get_fe,
1250 .get_tune_settings = tda1004x_get_tune_settings,
1252 .read_status = tda1004x_read_status,
1253 .read_ber = tda1004x_read_ber,
1254 .read_signal_strength = tda1004x_read_signal_strength,
1255 .read_snr = tda1004x_read_snr,
1256 .read_ucblocks = tda1004x_read_ucblocks,
1259 struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1260 struct i2c_adapter* i2c)
1262 struct tda1004x_state *state;
1264 /* allocate memory for the internal state */
1265 state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1269 /* setup the state */
1270 state->config = config;
1272 memcpy(&state->ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1273 state->initialised = 0;
1274 state->demod_type = TDA1004X_DEMOD_TDA10046;
1276 /* check if the demod is there */
1277 if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) {
1282 /* create dvb_frontend */
1283 state->frontend.ops = &state->ops;
1284 state->frontend.demodulator_priv = state;
1285 return &state->frontend;
1288 module_param(debug, int, 0644);
1289 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1291 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1292 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1293 MODULE_LICENSE("GPL");
1295 EXPORT_SYMBOL(tda10045_attach);
1296 EXPORT_SYMBOL(tda10046_attach);
1297 EXPORT_SYMBOL(tda1004x_write_byte);