git.oblomov.eu Git - linux-2.6/blob - drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc_helper.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35
  36 /* Really want an OS-independent resettable timer.  Would like to have
  37  * this loop run for (eg) 3 sec, but have the timer reset every time
  38  * the head pointer changes, so that EBUSY only happens if the ring
  39  * actually stalls for (eg) 3 seconds.
  40  */
  41 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
  42 {
  43         drm_i915_private_t *dev_priv = dev->dev_private;
  44         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  45         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  46         u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
  47         u32 last_acthd = I915_READ(acthd_reg);
  48         u32 acthd;
  49         u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  50         int i;
  51
  52         for (i = 0; i < 100000; i++) {
  53                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  54                 acthd = I915_READ(acthd_reg);
  55                 ring->space = ring->head - (ring->tail + 8);
  56                 if (ring->space < 0)
  57                         ring->space += ring->Size;
  58                 if (ring->space >= n)
  59                         return 0;
  60
  61                 if (master_priv->sarea_priv)
  62                         master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  63
  64                 if (ring->head != last_head)
  65                         i = 0;
  66                 if (acthd != last_acthd)
  67                         i = 0;
  68
  69                 last_head = ring->head;
  70                 last_acthd = acthd;
  71                 msleep_interruptible(10);
  72
  73         }
  74
  75         return -EBUSY;
  76 }
  77
  78 /**
  79  * Sets up the hardware status page for devices that need a physical address
  80  * in the register.
  81  */
  82 static int i915_init_phys_hws(struct drm_device *dev)
  83 {
  84         drm_i915_private_t *dev_priv = dev->dev_private;
  85         /* Program Hardware Status Page */
  86         dev_priv->status_page_dmah =
  87                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
  88
  89         if (!dev_priv->status_page_dmah) {
  90                 DRM_ERROR("Can not allocate hardware status page\n");
  91                 return -ENOMEM;
  92         }
  93         dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
  94         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  95
  96         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  97
  98         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  99         DRM_DEBUG("Enabled hardware status page\n");
 100         return 0;
 101 }
 102
 103 /**
 104  * Frees the hardware status page, whether it's a physical address or a virtual
 105  * address set up by the X Server.
 106  */
 107 static void i915_free_hws(struct drm_device *dev)
 108 {
 109         drm_i915_private_t *dev_priv = dev->dev_private;
 110         if (dev_priv->status_page_dmah) {
 111                 drm_pci_free(dev, dev_priv->status_page_dmah);
 112                 dev_priv->status_page_dmah = NULL;
 113         }
 114
 115         if (dev_priv->status_gfx_addr) {
 116                 dev_priv->status_gfx_addr = 0;
 117                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 118         }
 119
 120         /* Need to rewrite hardware status page */
 121         I915_WRITE(HWS_PGA, 0x1ffff000);
 122 }
 123
 124 void i915_kernel_lost_context(struct drm_device * dev)
 125 {
 126         drm_i915_private_t *dev_priv = dev->dev_private;
 127         struct drm_i915_master_private *master_priv;
 128         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
 129
 130         /*
 131          * We should never lose context on the ring with modesetting
 132          * as we don't expose it to userspace
 133          */
 134         if (drm_core_check_feature(dev, DRIVER_MODESET))
 135                 return;
 136
 137         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 138         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
 139         ring->space = ring->head - (ring->tail + 8);
 140         if (ring->space < 0)
 141                 ring->space += ring->Size;
 142
 143         if (!dev->primary->master)
 144                 return;
 145
 146         master_priv = dev->primary->master->driver_priv;
 147         if (ring->head == ring->tail && master_priv->sarea_priv)
 148                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 149 }
 150
 151 static int i915_dma_cleanup(struct drm_device * dev)
 152 {
 153         drm_i915_private_t *dev_priv = dev->dev_private;
 154         /* Make sure interrupts are disabled here because the uninstall ioctl
 155          * may not have been called from userspace and after dev_private
 156          * is freed, it's too late.
 157          */
 158         if (dev->irq_enabled)
 159                 drm_irq_uninstall(dev);
 160
 161         if (dev_priv->ring.virtual_start) {
 162                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
 163                 dev_priv->ring.virtual_start = NULL;
 164                 dev_priv->ring.map.handle = NULL;
 165                 dev_priv->ring.map.size = 0;
 166         }
 167
 168         /* Clear the HWS virtual address at teardown */
 169         if (I915_NEED_GFX_HWS(dev))
 170                 i915_free_hws(dev);
 171
 172         return 0;
 173 }
 174
 175 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 176 {
 177         drm_i915_private_t *dev_priv = dev->dev_private;
 178         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 179
 180         master_priv->sarea = drm_getsarea(dev);
 181         if (master_priv->sarea) {
 182                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 183                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 184         } else {
 185                 DRM_DEBUG("sarea not found assuming DRI2 userspace\n");
 186         }
 187
 188         if (init->ring_size != 0) {
 189                 if (dev_priv->ring.ring_obj != NULL) {
 190                         i915_dma_cleanup(dev);
 191                         DRM_ERROR("Client tried to initialize ringbuffer in "
 192                                   "GEM mode\n");
 193                         return -EINVAL;
 194                 }
 195
 196                 dev_priv->ring.Size = init->ring_size;
 197                 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 198
 199                 dev_priv->ring.map.offset = init->ring_start;
 200                 dev_priv->ring.map.size = init->ring_size;
 201                 dev_priv->ring.map.type = 0;
 202                 dev_priv->ring.map.flags = 0;
 203                 dev_priv->ring.map.mtrr = 0;
 204
 205                 drm_core_ioremap_wc(&dev_priv->ring.map, dev);
 206
 207                 if (dev_priv->ring.map.handle == NULL) {
 208                         i915_dma_cleanup(dev);
 209                         DRM_ERROR("can not ioremap virtual address for"
 210                                   " ring buffer\n");
 211                         return -ENOMEM;
 212                 }
 213         }
 214
 215         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 216
 217         dev_priv->cpp = init->cpp;
 218         dev_priv->back_offset = init->back_offset;
 219         dev_priv->front_offset = init->front_offset;
 220         dev_priv->current_page = 0;
 221         if (master_priv->sarea_priv)
 222                 master_priv->sarea_priv->pf_current_page = 0;
 223
 224         /* Allow hardware batchbuffers unless told otherwise.
 225          */
 226         dev_priv->allow_batchbuffer = 1;
 227
 228         return 0;
 229 }
 230
 231 static int i915_dma_resume(struct drm_device * dev)
 232 {
 233         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 234
 235         DRM_DEBUG("%s\n", __func__);
 236
 237         if (dev_priv->ring.map.handle == NULL) {
 238                 DRM_ERROR("can not ioremap virtual address for"
 239                           " ring buffer\n");
 240                 return -ENOMEM;
 241         }
 242
 243         /* Program Hardware Status Page */
 244         if (!dev_priv->hw_status_page) {
 245                 DRM_ERROR("Can not find hardware status page\n");
 246                 return -EINVAL;
 247         }
 248         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 249
 250         if (dev_priv->status_gfx_addr != 0)
 251                 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 252         else
 253                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 254         DRM_DEBUG("Enabled hardware status page\n");
 255
 256         return 0;
 257 }
 258
 259 static int i915_dma_init(struct drm_device *dev, void *data,
 260                          struct drm_file *file_priv)
 261 {
 262         drm_i915_init_t *init = data;
 263         int retcode = 0;
 264
 265         switch (init->func) {
 266         case I915_INIT_DMA:
 267                 retcode = i915_initialize(dev, init);
 268                 break;
 269         case I915_CLEANUP_DMA:
 270                 retcode = i915_dma_cleanup(dev);
 271                 break;
 272         case I915_RESUME_DMA:
 273                 retcode = i915_dma_resume(dev);
 274                 break;
 275         default:
 276                 retcode = -EINVAL;
 277                 break;
 278         }
 279
 280         return retcode;
 281 }
 282
 283 /* Implement basically the same security restrictions as hardware does
 284  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 285  *
 286  * Most of the calculations below involve calculating the size of a
 287  * particular instruction.  It's important to get the size right as
 288  * that tells us where the next instruction to check is.  Any illegal
 289  * instruction detected will be given a size of zero, which is a
 290  * signal to abort the rest of the buffer.
 291  */
 292 static int do_validate_cmd(int cmd)
 293 {
 294         switch (((cmd >> 29) & 0x7)) {
 295         case 0x0:
 296                 switch ((cmd >> 23) & 0x3f) {
 297                 case 0x0:
 298                         return 1;       /* MI_NOOP */
 299                 case 0x4:
 300                         return 1;       /* MI_FLUSH */
 301                 default:
 302                         return 0;       /* disallow everything else */
 303                 }
 304                 break;
 305         case 0x1:
 306                 return 0;       /* reserved */
 307         case 0x2:
 308                 return (cmd & 0xff) + 2;        /* 2d commands */
 309         case 0x3:
 310                 if (((cmd >> 24) & 0x1f) <= 0x18)
 311                         return 1;
 312
 313                 switch ((cmd >> 24) & 0x1f) {
 314                 case 0x1c:
 315                         return 1;
 316                 case 0x1d:
 317                         switch ((cmd >> 16) & 0xff) {
 318                         case 0x3:
 319                                 return (cmd & 0x1f) + 2;
 320                         case 0x4:
 321                                 return (cmd & 0xf) + 2;
 322                         default:
 323                                 return (cmd & 0xffff) + 2;
 324                         }
 325                 case 0x1e:
 326                         if (cmd & (1 << 23))
 327                                 return (cmd & 0xffff) + 1;
 328                         else
 329                                 return 1;
 330                 case 0x1f:
 331                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 332                                 return (cmd & 0x1ffff) + 2;
 333                         else if (cmd & (1 << 17))       /* indirect random */
 334                                 if ((cmd & 0xffff) == 0)
 335                                         return 0;       /* unknown length, too hard */
 336                                 else
 337                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 338                         else
 339                                 return 2;       /* indirect sequential */
 340                 default:
 341                         return 0;
 342                 }
 343         default:
 344                 return 0;
 345         }
 346
 347         return 0;
 348 }
 349
 350 static int validate_cmd(int cmd)
 351 {
 352         int ret = do_validate_cmd(cmd);
 353
 354 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 355
 356         return ret;
 357 }
 358
 359 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 360 {
 361         drm_i915_private_t *dev_priv = dev->dev_private;
 362         int i;
 363         RING_LOCALS;
 364
 365         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 366                 return -EINVAL;
 367
 368         BEGIN_LP_RING((dwords+1)&~1);
 369
 370         for (i = 0; i < dwords;) {
 371                 int cmd, sz;
 372
 373                 cmd = buffer[i];
 374
 375                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 376                         return -EINVAL;
 377
 378                 OUT_RING(cmd);
 379
 380                 while (++i, --sz) {
 381                         OUT_RING(buffer[i]);
 382                 }
 383         }
 384
 385         if (dwords & 1)
 386                 OUT_RING(0);
 387
 388         ADVANCE_LP_RING();
 389
 390         return 0;
 391 }
 392
 393 int
 394 i915_emit_box(struct drm_device *dev,
 395               struct drm_clip_rect *boxes,
 396               int i, int DR1, int DR4)
 397 {
 398         drm_i915_private_t *dev_priv = dev->dev_private;
 399         struct drm_clip_rect box = boxes[i];
 400         RING_LOCALS;
 401
 402         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 403                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 404                           box.x1, box.y1, box.x2, box.y2);
 405                 return -EINVAL;
 406         }
 407
 408         if (IS_I965G(dev)) {
 409                 BEGIN_LP_RING(4);
 410                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 411                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 412                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 413                 OUT_RING(DR4);
 414                 ADVANCE_LP_RING();
 415         } else {
 416                 BEGIN_LP_RING(6);
 417                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 418                 OUT_RING(DR1);
 419                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 420                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 421                 OUT_RING(DR4);
 422                 OUT_RING(0);
 423                 ADVANCE_LP_RING();
 424         }
 425
 426         return 0;
 427 }
 428
 429 /* XXX: Emitting the counter should really be moved to part of the IRQ
 430  * emit. For now, do it in both places:
 431  */
 432
 433 static void i915_emit_breadcrumb(struct drm_device *dev)
 434 {
 435         drm_i915_private_t *dev_priv = dev->dev_private;
 436         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 437         RING_LOCALS;
 438
 439         dev_priv->counter++;
 440         if (dev_priv->counter > 0x7FFFFFFFUL)
 441                 dev_priv->counter = 0;
 442         if (master_priv->sarea_priv)
 443                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 444
 445         BEGIN_LP_RING(4);
 446         OUT_RING(MI_STORE_DWORD_INDEX);
 447         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 448         OUT_RING(dev_priv->counter);
 449         OUT_RING(0);
 450         ADVANCE_LP_RING();
 451 }
 452
 453 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 454                                    drm_i915_cmdbuffer_t *cmd,
 455                                    struct drm_clip_rect *cliprects,
 456                                    void *cmdbuf)
 457 {
 458         int nbox = cmd->num_cliprects;
 459         int i = 0, count, ret;
 460
 461         if (cmd->sz & 0x3) {
 462                 DRM_ERROR("alignment");
 463                 return -EINVAL;
 464         }
 465
 466         i915_kernel_lost_context(dev);
 467
 468         count = nbox ? nbox : 1;
 469
 470         for (i = 0; i < count; i++) {
 471                 if (i < nbox) {
 472                         ret = i915_emit_box(dev, cliprects, i,
 473                                             cmd->DR1, cmd->DR4);
 474                         if (ret)
 475                                 return ret;
 476                 }
 477
 478                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 479                 if (ret)
 480                         return ret;
 481         }
 482
 483         i915_emit_breadcrumb(dev);
 484         return 0;
 485 }
 486
 487 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 488                                      drm_i915_batchbuffer_t * batch,
 489                                      struct drm_clip_rect *cliprects)
 490 {
 491         drm_i915_private_t *dev_priv = dev->dev_private;
 492         int nbox = batch->num_cliprects;
 493         int i = 0, count;
 494         RING_LOCALS;
 495
 496         if ((batch->start | batch->used) & 0x7) {
 497                 DRM_ERROR("alignment");
 498                 return -EINVAL;
 499         }
 500
 501         i915_kernel_lost_context(dev);
 502
 503         count = nbox ? nbox : 1;
 504
 505         for (i = 0; i < count; i++) {
 506                 if (i < nbox) {
 507                         int ret = i915_emit_box(dev, cliprects, i,
 508                                                 batch->DR1, batch->DR4);
 509                         if (ret)
 510                                 return ret;
 511                 }
 512
 513                 if (!IS_I830(dev) && !IS_845G(dev)) {
 514                         BEGIN_LP_RING(2);
 515                         if (IS_I965G(dev)) {
 516                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 517                                 OUT_RING(batch->start);
 518                         } else {
 519                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 520                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 521                         }
 522                         ADVANCE_LP_RING();
 523                 } else {
 524                         BEGIN_LP_RING(4);
 525                         OUT_RING(MI_BATCH_BUFFER);
 526                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 527                         OUT_RING(batch->start + batch->used - 4);
 528                         OUT_RING(0);
 529                         ADVANCE_LP_RING();
 530                 }
 531         }
 532
 533         i915_emit_breadcrumb(dev);
 534
 535         return 0;
 536 }
 537
 538 static int i915_dispatch_flip(struct drm_device * dev)
 539 {
 540         drm_i915_private_t *dev_priv = dev->dev_private;
 541         struct drm_i915_master_private *master_priv =
 542                 dev->primary->master->driver_priv;
 543         RING_LOCALS;
 544
 545         if (!master_priv->sarea_priv)
 546                 return -EINVAL;
 547
 548         DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
 549                   __func__,
 550                   dev_priv->current_page,
 551                   master_priv->sarea_priv->pf_current_page);
 552
 553         i915_kernel_lost_context(dev);
 554
 555         BEGIN_LP_RING(2);
 556         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 557         OUT_RING(0);
 558         ADVANCE_LP_RING();
 559
 560         BEGIN_LP_RING(6);
 561         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 562         OUT_RING(0);
 563         if (dev_priv->current_page == 0) {
 564                 OUT_RING(dev_priv->back_offset);
 565                 dev_priv->current_page = 1;
 566         } else {
 567                 OUT_RING(dev_priv->front_offset);
 568                 dev_priv->current_page = 0;
 569         }
 570         OUT_RING(0);
 571         ADVANCE_LP_RING();
 572
 573         BEGIN_LP_RING(2);
 574         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 575         OUT_RING(0);
 576         ADVANCE_LP_RING();
 577
 578         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 579
 580         BEGIN_LP_RING(4);
 581         OUT_RING(MI_STORE_DWORD_INDEX);
 582         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 583         OUT_RING(dev_priv->counter);
 584         OUT_RING(0);
 585         ADVANCE_LP_RING();
 586
 587         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 588         return 0;
 589 }
 590
 591 static int i915_quiescent(struct drm_device * dev)
 592 {
 593         drm_i915_private_t *dev_priv = dev->dev_private;
 594
 595         i915_kernel_lost_context(dev);
 596         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
 597 }
 598
 599 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 600                             struct drm_file *file_priv)
 601 {
 602         int ret;
 603
 604         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 605
 606         mutex_lock(&dev->struct_mutex);
 607         ret = i915_quiescent(dev);
 608         mutex_unlock(&dev->struct_mutex);
 609
 610         return ret;
 611 }
 612
 613 static int i915_batchbuffer(struct drm_device *dev, void *data,
 614                             struct drm_file *file_priv)
 615 {
 616         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 617         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 618         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 619             master_priv->sarea_priv;
 620         drm_i915_batchbuffer_t *batch = data;
 621         int ret;
 622         struct drm_clip_rect *cliprects = NULL;
 623
 624         if (!dev_priv->allow_batchbuffer) {
 625                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 626                 return -EINVAL;
 627         }
 628
 629         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 630                   batch->start, batch->used, batch->num_cliprects);
 631
 632         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 633
 634         if (batch->num_cliprects < 0)
 635                 return -EINVAL;
 636
 637         if (batch->num_cliprects) {
 638                 cliprects = drm_calloc(batch->num_cliprects,
 639                                        sizeof(struct drm_clip_rect),
 640                                        DRM_MEM_DRIVER);
 641                 if (cliprects == NULL)
 642                         return -ENOMEM;
 643
 644                 ret = copy_from_user(cliprects, batch->cliprects,
 645                                      batch->num_cliprects *
 646                                      sizeof(struct drm_clip_rect));
 647                 if (ret != 0)
 648                         goto fail_free;
 649         }
 650
 651         mutex_lock(&dev->struct_mutex);
 652         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 653         mutex_unlock(&dev->struct_mutex);
 654
 655         if (sarea_priv)
 656                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 657
 658 fail_free:
 659         drm_free(cliprects,
 660                  batch->num_cliprects * sizeof(struct drm_clip_rect),
 661                  DRM_MEM_DRIVER);
 662
 663         return ret;
 664 }
 665
 666 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 667                           struct drm_file *file_priv)
 668 {
 669         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 670         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 671         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 672             master_priv->sarea_priv;
 673         drm_i915_cmdbuffer_t *cmdbuf = data;
 674         struct drm_clip_rect *cliprects = NULL;
 675         void *batch_data;
 676         int ret;
 677
 678         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 679                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 680
 681         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 682
 683         if (cmdbuf->num_cliprects < 0)
 684                 return -EINVAL;
 685
 686         batch_data = drm_alloc(cmdbuf->sz, DRM_MEM_DRIVER);
 687         if (batch_data == NULL)
 688                 return -ENOMEM;
 689
 690         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 691         if (ret != 0)
 692                 goto fail_batch_free;
 693
 694         if (cmdbuf->num_cliprects) {
 695                 cliprects = drm_calloc(cmdbuf->num_cliprects,
 696                                        sizeof(struct drm_clip_rect),
 697                                        DRM_MEM_DRIVER);
 698                 if (cliprects == NULL)
 699                         goto fail_batch_free;
 700
 701                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 702                                      cmdbuf->num_cliprects *
 703                                      sizeof(struct drm_clip_rect));
 704                 if (ret != 0)
 705                         goto fail_clip_free;
 706         }
 707
 708         mutex_lock(&dev->struct_mutex);
 709         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 710         mutex_unlock(&dev->struct_mutex);
 711         if (ret) {
 712                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 713                 goto fail_batch_free;
 714         }
 715
 716         if (sarea_priv)
 717                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 718
 719 fail_batch_free:
 720         drm_free(batch_data, cmdbuf->sz, DRM_MEM_DRIVER);
 721 fail_clip_free:
 722         drm_free(cliprects,
 723                  cmdbuf->num_cliprects * sizeof(struct drm_clip_rect),
 724                  DRM_MEM_DRIVER);
 725
 726         return ret;
 727 }
 728
 729 static int i915_flip_bufs(struct drm_device *dev, void *data,
 730                           struct drm_file *file_priv)
 731 {
 732         int ret;
 733
 734         DRM_DEBUG("%s\n", __func__);
 735
 736         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 737
 738         mutex_lock(&dev->struct_mutex);
 739         ret = i915_dispatch_flip(dev);
 740         mutex_unlock(&dev->struct_mutex);
 741
 742         return ret;
 743 }
 744
 745 static int i915_getparam(struct drm_device *dev, void *data,
 746                          struct drm_file *file_priv)
 747 {
 748         drm_i915_private_t *dev_priv = dev->dev_private;
 749         drm_i915_getparam_t *param = data;
 750         int value;
 751
 752         if (!dev_priv) {
 753                 DRM_ERROR("called with no initialization\n");
 754                 return -EINVAL;
 755         }
 756
 757         switch (param->param) {
 758         case I915_PARAM_IRQ_ACTIVE:
 759                 value = dev->pdev->irq ? 1 : 0;
 760                 break;
 761         case I915_PARAM_ALLOW_BATCHBUFFER:
 762                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 763                 break;
 764         case I915_PARAM_LAST_DISPATCH:
 765                 value = READ_BREADCRUMB(dev_priv);
 766                 break;
 767         case I915_PARAM_CHIPSET_ID:
 768                 value = dev->pci_device;
 769                 break;
 770         case I915_PARAM_HAS_GEM:
 771                 value = dev_priv->has_gem;
 772                 break;
 773         case I915_PARAM_NUM_FENCES_AVAIL:
 774                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 775                 break;
 776         default:
 777                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 778                 return -EINVAL;
 779         }
 780
 781         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 782                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 783                 return -EFAULT;
 784         }
 785
 786         return 0;
 787 }
 788
 789 static int i915_setparam(struct drm_device *dev, void *data,
 790                          struct drm_file *file_priv)
 791 {
 792         drm_i915_private_t *dev_priv = dev->dev_private;
 793         drm_i915_setparam_t *param = data;
 794
 795         if (!dev_priv) {
 796                 DRM_ERROR("called with no initialization\n");
 797                 return -EINVAL;
 798         }
 799
 800         switch (param->param) {
 801         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 802                 break;
 803         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 804                 dev_priv->tex_lru_log_granularity = param->value;
 805                 break;
 806         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 807                 dev_priv->allow_batchbuffer = param->value;
 808                 break;
 809         case I915_SETPARAM_NUM_USED_FENCES:
 810                 if (param->value > dev_priv->num_fence_regs ||
 811                     param->value < 0)
 812                         return -EINVAL;
 813                 /* Userspace can use first N regs */
 814                 dev_priv->fence_reg_start = param->value;
 815                 break;
 816         default:
 817                 DRM_DEBUG("unknown parameter %d\n", param->param);
 818                 return -EINVAL;
 819         }
 820
 821         return 0;
 822 }
 823
 824 static int i915_set_status_page(struct drm_device *dev, void *data,
 825                                 struct drm_file *file_priv)
 826 {
 827         drm_i915_private_t *dev_priv = dev->dev_private;
 828         drm_i915_hws_addr_t *hws = data;
 829
 830         if (!I915_NEED_GFX_HWS(dev))
 831                 return -EINVAL;
 832
 833         if (!dev_priv) {
 834                 DRM_ERROR("called with no initialization\n");
 835                 return -EINVAL;
 836         }
 837
 838         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 839                 WARN(1, "tried to set status page when mode setting active\n");
 840                 return 0;
 841         }
 842
 843         printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws->addr);
 844
 845         dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
 846
 847         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 848         dev_priv->hws_map.size = 4*1024;
 849         dev_priv->hws_map.type = 0;
 850         dev_priv->hws_map.flags = 0;
 851         dev_priv->hws_map.mtrr = 0;
 852
 853         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 854         if (dev_priv->hws_map.handle == NULL) {
 855                 i915_dma_cleanup(dev);
 856                 dev_priv->status_gfx_addr = 0;
 857                 DRM_ERROR("can not ioremap virtual address for"
 858                                 " G33 hw status page\n");
 859                 return -ENOMEM;
 860         }
 861         dev_priv->hw_status_page = dev_priv->hws_map.handle;
 862
 863         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 864         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 865         DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
 866                         dev_priv->status_gfx_addr);
 867         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
 868         return 0;
 869 }
 870
 871 /**
 872  * i915_probe_agp - get AGP bootup configuration
 873  * @pdev: PCI device
 874  * @aperture_size: returns AGP aperture configured size
 875  * @preallocated_size: returns size of BIOS preallocated AGP space
 876  *
 877  * Since Intel integrated graphics are UMA, the BIOS has to set aside
 878  * some RAM for the framebuffer at early boot.  This code figures out
 879  * how much was set aside so we can use it for our own purposes.
 880  */
 881 static int i915_probe_agp(struct drm_device *dev, unsigned long *aperture_size,
 882                           unsigned long *preallocated_size)
 883 {
 884         struct pci_dev *bridge_dev;
 885         u16 tmp = 0;
 886         unsigned long overhead;
 887         unsigned long stolen;
 888
 889         bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
 890         if (!bridge_dev) {
 891                 DRM_ERROR("bridge device not found\n");
 892                 return -1;
 893         }
 894
 895         /* Get the fb aperture size and "stolen" memory amount. */
 896         pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
 897         pci_dev_put(bridge_dev);
 898
 899         *aperture_size = 1024 * 1024;
 900         *preallocated_size = 1024 * 1024;
 901
 902         switch (dev->pdev->device) {
 903         case PCI_DEVICE_ID_INTEL_82830_CGC:
 904         case PCI_DEVICE_ID_INTEL_82845G_IG:
 905         case PCI_DEVICE_ID_INTEL_82855GM_IG:
 906         case PCI_DEVICE_ID_INTEL_82865_IG:
 907                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
 908                         *aperture_size *= 64;
 909                 else
 910                         *aperture_size *= 128;
 911                 break;
 912         default:
 913                 /* 9xx supports large sizes, just look at the length */
 914                 *aperture_size = pci_resource_len(dev->pdev, 2);
 915                 break;
 916         }
 917
 918         /*
 919          * Some of the preallocated space is taken by the GTT
 920          * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.
 921          */
 922         if (IS_G4X(dev))
 923                 overhead = 4096;
 924         else
 925                 overhead = (*aperture_size / 1024) + 4096;
 926
 927         switch (tmp & INTEL_GMCH_GMS_MASK) {
 928         case INTEL_855_GMCH_GMS_DISABLED:
 929                 DRM_ERROR("video memory is disabled\n");
 930                 return -1;
 931         case INTEL_855_GMCH_GMS_STOLEN_1M:
 932                 stolen = 1 * 1024 * 1024;
 933                 break;
 934         case INTEL_855_GMCH_GMS_STOLEN_4M:
 935                 stolen = 4 * 1024 * 1024;
 936                 break;
 937         case INTEL_855_GMCH_GMS_STOLEN_8M:
 938                 stolen = 8 * 1024 * 1024;
 939                 break;
 940         case INTEL_855_GMCH_GMS_STOLEN_16M:
 941                 stolen = 16 * 1024 * 1024;
 942                 break;
 943         case INTEL_855_GMCH_GMS_STOLEN_32M:
 944                 stolen = 32 * 1024 * 1024;
 945                 break;
 946         case INTEL_915G_GMCH_GMS_STOLEN_48M:
 947                 stolen = 48 * 1024 * 1024;
 948                 break;
 949         case INTEL_915G_GMCH_GMS_STOLEN_64M:
 950                 stolen = 64 * 1024 * 1024;
 951                 break;
 952         case INTEL_GMCH_GMS_STOLEN_128M:
 953                 stolen = 128 * 1024 * 1024;
 954                 break;
 955         case INTEL_GMCH_GMS_STOLEN_256M:
 956                 stolen = 256 * 1024 * 1024;
 957                 break;
 958         case INTEL_GMCH_GMS_STOLEN_96M:
 959                 stolen = 96 * 1024 * 1024;
 960                 break;
 961         case INTEL_GMCH_GMS_STOLEN_160M:
 962                 stolen = 160 * 1024 * 1024;
 963                 break;
 964         case INTEL_GMCH_GMS_STOLEN_224M:
 965                 stolen = 224 * 1024 * 1024;
 966                 break;
 967         case INTEL_GMCH_GMS_STOLEN_352M:
 968                 stolen = 352 * 1024 * 1024;
 969                 break;
 970         default:
 971                 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
 972                         tmp & INTEL_GMCH_GMS_MASK);
 973                 return -1;
 974         }
 975         *preallocated_size = stolen - overhead;
 976
 977         return 0;
 978 }
 979
 980 static int i915_load_modeset_init(struct drm_device *dev)
 981 {
 982         struct drm_i915_private *dev_priv = dev->dev_private;
 983         unsigned long agp_size, prealloc_size;
 984         int fb_bar = IS_I9XX(dev) ? 2 : 0;
 985         int ret = 0;
 986
 987         dev->devname = kstrdup(DRIVER_NAME, GFP_KERNEL);
 988         if (!dev->devname) {
 989                 ret = -ENOMEM;
 990                 goto out;
 991         }
 992
 993         dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
 994                 0xff000000;
 995
 996         if (IS_MOBILE(dev) || IS_I9XX(dev))
 997                 dev_priv->cursor_needs_physical = true;
 998         else
 999                 dev_priv->cursor_needs_physical = false;
1000
1001         if (IS_I965G(dev) || IS_G33(dev))
1002                 dev_priv->cursor_needs_physical = false;
1003
1004         ret = i915_probe_agp(dev, &agp_size, &prealloc_size);
1005         if (ret)
1006                 goto kfree_devname;
1007
1008         /* Basic memrange allocator for stolen space (aka vram) */
1009         drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1010
1011         /* Let GEM Manage from end of prealloc space to end of aperture */
1012         i915_gem_do_init(dev, prealloc_size, agp_size);
1013
1014         ret = i915_gem_init_ringbuffer(dev);
1015         if (ret)
1016                 goto kfree_devname;
1017
1018         /* Allow hardware batchbuffers unless told otherwise.
1019          */
1020         dev_priv->allow_batchbuffer = 1;
1021
1022         ret = intel_init_bios(dev);
1023         if (ret)
1024                 DRM_INFO("failed to find VBIOS tables\n");
1025
1026         ret = drm_irq_install(dev);
1027         if (ret)
1028                 goto destroy_ringbuffer;
1029
1030         /* FIXME: re-add hotplug support */
1031 #if 0
1032         ret = drm_hotplug_init(dev);
1033         if (ret)
1034                 goto destroy_ringbuffer;
1035 #endif
1036
1037         /* Always safe in the mode setting case. */
1038         /* FIXME: do pre/post-mode set stuff in core KMS code */
1039         dev->vblank_disable_allowed = 1;
1040
1041         /*
1042          * Initialize the hardware status page IRQ location.
1043          */
1044
1045         I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1046
1047         intel_modeset_init(dev);
1048
1049         drm_helper_initial_config(dev, false);
1050
1051         return 0;
1052
1053 destroy_ringbuffer:
1054         i915_gem_cleanup_ringbuffer(dev);
1055 kfree_devname:
1056         kfree(dev->devname);
1057 out:
1058         return ret;
1059 }
1060
1061 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1062 {
1063         struct drm_i915_master_private *master_priv;
1064
1065         master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
1066         if (!master_priv)
1067                 return -ENOMEM;
1068
1069         master->driver_priv = master_priv;
1070         return 0;
1071 }
1072
1073 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1074 {
1075         struct drm_i915_master_private *master_priv = master->driver_priv;
1076
1077         if (!master_priv)
1078                 return;
1079
1080         drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
1081
1082         master->driver_priv = NULL;
1083 }
1084
1085 /**
1086  * i915_driver_load - setup chip and create an initial config
1087  * @dev: DRM device
1088  * @flags: startup flags
1089  *
1090  * The driver load routine has to do several things:
1091  *   - drive output discovery via intel_modeset_init()
1092  *   - initialize the memory manager
1093  *   - allocate initial config memory
1094  *   - setup the DRM framebuffer with the allocated memory
1095  */
1096 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1097 {
1098         struct drm_i915_private *dev_priv = dev->dev_private;
1099         unsigned long base, size;
1100         int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
1101
1102         /* i915 has 4 more counters */
1103         dev->counters += 4;
1104         dev->types[6] = _DRM_STAT_IRQ;
1105         dev->types[7] = _DRM_STAT_PRIMARY;
1106         dev->types[8] = _DRM_STAT_SECONDARY;
1107         dev->types[9] = _DRM_STAT_DMA;
1108
1109         dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
1110         if (dev_priv == NULL)
1111                 return -ENOMEM;
1112
1113         memset(dev_priv, 0, sizeof(drm_i915_private_t));
1114
1115         dev->dev_private = (void *)dev_priv;
1116         dev_priv->dev = dev;
1117
1118         /* Add register map (needed for suspend/resume) */
1119         base = drm_get_resource_start(dev, mmio_bar);
1120         size = drm_get_resource_len(dev, mmio_bar);
1121
1122         dev_priv->regs = ioremap(base, size);
1123         if (!dev_priv->regs) {
1124                 DRM_ERROR("failed to map registers\n");
1125                 ret = -EIO;
1126                 goto free_priv;
1127         }
1128
1129         dev_priv->mm.gtt_mapping =
1130                 io_mapping_create_wc(dev->agp->base,
1131                                      dev->agp->agp_info.aper_size * 1024*1024);
1132         if (dev_priv->mm.gtt_mapping == NULL) {
1133                 ret = -EIO;
1134                 goto out_rmmap;
1135         }
1136
1137         /* Set up a WC MTRR for non-PAT systems.  This is more common than
1138          * one would think, because the kernel disables PAT on first
1139          * generation Core chips because WC PAT gets overridden by a UC
1140          * MTRR if present.  Even if a UC MTRR isn't present.
1141          */
1142         dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1143                                          dev->agp->agp_info.aper_size *
1144                                          1024 * 1024,
1145                                          MTRR_TYPE_WRCOMB, 1);
1146         if (dev_priv->mm.gtt_mtrr < 0) {
1147                 DRM_INFO("MTRR allocation failed.  Graphics "
1148                          "performance may suffer.\n");
1149         }
1150
1151 #ifdef CONFIG_HIGHMEM64G
1152         /* don't enable GEM on PAE - needs agp + set_memory_* interface fixes */
1153         dev_priv->has_gem = 0;
1154 #else
1155         /* enable GEM by default */
1156         dev_priv->has_gem = 1;
1157 #endif
1158
1159         dev->driver->get_vblank_counter = i915_get_vblank_counter;
1160         if (IS_GM45(dev))
1161                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1162
1163         i915_gem_load(dev);
1164
1165         /* Init HWS */
1166         if (!I915_NEED_GFX_HWS(dev)) {
1167                 ret = i915_init_phys_hws(dev);
1168                 if (ret != 0)
1169                         goto out_iomapfree;
1170         }
1171
1172         /* On the 945G/GM, the chipset reports the MSI capability on the
1173          * integrated graphics even though the support isn't actually there
1174          * according to the published specs.  It doesn't appear to function
1175          * correctly in testing on 945G.
1176          * This may be a side effect of MSI having been made available for PEG
1177          * and the registers being closely associated.
1178          *
1179          * According to chipset errata, on the 965GM, MSI interrupts may
1180          * be lost or delayed, but we use them anyways to avoid
1181          * stuck interrupts on some machines.
1182          */
1183         if (!IS_I945G(dev) && !IS_I945GM(dev))
1184                 pci_enable_msi(dev->pdev);
1185
1186         intel_opregion_init(dev);
1187
1188         spin_lock_init(&dev_priv->user_irq_lock);
1189         dev_priv->user_irq_refcount = 0;
1190
1191         ret = drm_vblank_init(dev, I915_NUM_PIPE);
1192
1193         if (ret) {
1194                 (void) i915_driver_unload(dev);
1195                 return ret;
1196         }
1197
1198         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1199                 ret = i915_load_modeset_init(dev);
1200                 if (ret < 0) {
1201                         DRM_ERROR("failed to init modeset\n");
1202                         goto out_rmmap;
1203                 }
1204         }
1205
1206         return 0;
1207
1208 out_iomapfree:
1209         io_mapping_free(dev_priv->mm.gtt_mapping);
1210 out_rmmap:
1211         iounmap(dev_priv->regs);
1212 free_priv:
1213         drm_free(dev_priv, sizeof(struct drm_i915_private), DRM_MEM_DRIVER);
1214         return ret;
1215 }
1216
1217 int i915_driver_unload(struct drm_device *dev)
1218 {
1219         struct drm_i915_private *dev_priv = dev->dev_private;
1220
1221         io_mapping_free(dev_priv->mm.gtt_mapping);
1222         if (dev_priv->mm.gtt_mtrr >= 0) {
1223                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
1224                          dev->agp->agp_info.aper_size * 1024 * 1024);
1225                 dev_priv->mm.gtt_mtrr = -1;
1226         }
1227
1228         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1229                 drm_irq_uninstall(dev);
1230         }
1231
1232         if (dev->pdev->msi_enabled)
1233                 pci_disable_msi(dev->pdev);
1234
1235         if (dev_priv->regs != NULL)
1236                 iounmap(dev_priv->regs);
1237
1238         intel_opregion_free(dev);
1239
1240         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1241                 intel_modeset_cleanup(dev);
1242
1243                 i915_gem_free_all_phys_object(dev);
1244
1245                 mutex_lock(&dev->struct_mutex);
1246                 i915_gem_cleanup_ringbuffer(dev);
1247                 mutex_unlock(&dev->struct_mutex);
1248                 drm_mm_takedown(&dev_priv->vram);
1249                 i915_gem_lastclose(dev);
1250         }
1251
1252         drm_free(dev->dev_private, sizeof(drm_i915_private_t),
1253                  DRM_MEM_DRIVER);
1254
1255         return 0;
1256 }
1257
1258 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1259 {
1260         struct drm_i915_file_private *i915_file_priv;
1261
1262         DRM_DEBUG("\n");
1263         i915_file_priv = (struct drm_i915_file_private *)
1264             drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES);
1265
1266         if (!i915_file_priv)
1267                 return -ENOMEM;
1268
1269         file_priv->driver_priv = i915_file_priv;
1270
1271         i915_file_priv->mm.last_gem_seqno = 0;
1272         i915_file_priv->mm.last_gem_throttle_seqno = 0;
1273
1274         return 0;
1275 }
1276
1277 /**
1278  * i915_driver_lastclose - clean up after all DRM clients have exited
1279  * @dev: DRM device
1280  *
1281  * Take care of cleaning up after all DRM clients have exited.  In the
1282  * mode setting case, we want to restore the kernel's initial mode (just
1283  * in case the last client left us in a bad state).
1284  *
1285  * Additionally, in the non-mode setting case, we'll tear down the AGP
1286  * and DMA structures, since the kernel won't be using them, and clea
1287  * up any GEM state.
1288  */
1289 void i915_driver_lastclose(struct drm_device * dev)
1290 {
1291         drm_i915_private_t *dev_priv = dev->dev_private;
1292
1293         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1294                 intelfb_restore();
1295                 return;
1296         }
1297
1298         i915_gem_lastclose(dev);
1299
1300         if (dev_priv->agp_heap)
1301                 i915_mem_takedown(&(dev_priv->agp_heap));
1302
1303         i915_dma_cleanup(dev);
1304 }
1305
1306 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1307 {
1308         drm_i915_private_t *dev_priv = dev->dev_private;
1309         if (!drm_core_check_feature(dev, DRIVER_MODESET))
1310                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1311 }
1312
1313 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1314 {
1315         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1316
1317         drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES);
1318 }
1319
1320 struct drm_ioctl_desc i915_ioctls[] = {
1321         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1322         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1323         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1324         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1325         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1326         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1327         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1328         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1329         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1330         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1331         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1332         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1333         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1334         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1335         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1336         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1337         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1338         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1339         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1340         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1341         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1342         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
1343         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1344         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1345         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1346         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1347         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
1348         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
1349         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1350         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, 0),
1351         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
1352         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
1353         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1354         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1355         DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),
1356 };
1357
1358 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1359
1360 /**
1361  * Determine if the device really is AGP or not.
1362  *
1363  * All Intel graphics chipsets are treated as AGP, even if they are really
1364  * PCI-e.
1365  *
1366  * \param dev   The device to be tested.
1367  *
1368  * \returns
1369  * A value of 1 is always retured to indictate every i9x5 is AGP.
1370  */
1371 int i915_driver_device_is_agp(struct drm_device * dev)
1372 {
1373         return 1;
1374 }