Merge branch 'proc' of git://git.kernel.org/pub/scm/linux/kernel/git/adobriyan/proc
[linux-2.6] / arch / mips / alchemy / common / au1xxx_irqmap.c
1 /*
2  * BRIEF MODULE DESCRIPTION
3  *      Au1xxx processor specific IRQ tables
4  *
5  * Copyright 2004 Embedded Edge, LLC
6  *      dan@embeddededge.com
7  *
8  *  This program is free software; you can redistribute  it and/or modify it
9  *  under  the terms of  the GNU General  Public License as published by the
10  *  Free Software Foundation;  either version 2 of the  License, or (at your
11  *  option) any later version.
12  *
13  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
14  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
15  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
16  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
17  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
19  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
21  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23  *
24  *  You should have received a copy of the  GNU General Public License along
25  *  with this program; if not, write  to the Free Software Foundation, Inc.,
26  *  675 Mass Ave, Cambridge, MA 02139, USA.
27  */
28 #include <linux/init.h>
29 #include <linux/kernel.h>
30
31 #include <au1000.h>
32
33 /* The IC0 interrupt table.  This is processor, rather than
34  * board dependent, so no reason to keep this info in the board
35  * dependent files.
36  *
37  * Careful if you change match 2 request!
38  * The interrupt handler is called directly from the low level dispatch code.
39  */
40 struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = {
41
42 #if defined(CONFIG_SOC_AU1000)
43         { AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
44         { AU1000_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },
45         { AU1000_UART2_INT, INTC_INT_HIGH_LEVEL, 0 },
46         { AU1000_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },
47         { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0 },
48         { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0 },
49         { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 },
50         { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 },
51         { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 },
52         { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 },
53         { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 },
54         { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 },
55         { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 },
56         { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 },
57         { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
58         { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
59         { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
60         { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
61         { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
62         { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
63         { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
64         { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
65         { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0 },
66         { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0 },
67         { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
68         { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
69         { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
70         { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },
71         { AU1000_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
72         { AU1000_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
73         { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },
74
75 #elif defined(CONFIG_SOC_AU1500)
76
77         { AU1500_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
78         { AU1000_PCI_INTA, INTC_INT_LOW_LEVEL, 0 },
79         { AU1000_PCI_INTB, INTC_INT_LOW_LEVEL, 0 },
80         { AU1500_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },
81         { AU1000_PCI_INTC, INTC_INT_LOW_LEVEL, 0 },
82         { AU1000_PCI_INTD, INTC_INT_LOW_LEVEL, 0 },
83         { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 },
84         { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 },
85         { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 },
86         { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 },
87         { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 },
88         { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 },
89         { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 },
90         { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 },
91         { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
92         { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
93         { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
94         { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
95         { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
96         { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
97         { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
98         { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
99         { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
100         { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
101         { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
102         { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },
103         { AU1500_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
104         { AU1500_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
105         { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },
106
107 #elif defined(CONFIG_SOC_AU1100)
108
109         { AU1100_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
110         { AU1100_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },
111         { AU1100_SD_INT, INTC_INT_HIGH_LEVEL, 0 },
112         { AU1100_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },
113         { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0 },
114         { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0 },
115         { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 },
116         { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 },
117         { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 },
118         { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 },
119         { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 },
120         { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 },
121         { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 },
122         { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 },
123         { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
124         { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
125         { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
126         { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
127         { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
128         { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
129         { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
130         { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
131         { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0 },
132         { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0 },
133         { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
134         { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
135         { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
136         { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },
137         { AU1100_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
138         /* { AU1000_GPIO215_208_INT, INTC_INT_HIGH_LEVEL, 0 }, */
139         { AU1100_LCD_INT, INTC_INT_HIGH_LEVEL, 0 },
140         { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },
141
142 #elif defined(CONFIG_SOC_AU1550)
143
144         { AU1550_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
145         { AU1550_PCI_INTA, INTC_INT_LOW_LEVEL, 0 },
146         { AU1550_PCI_INTB, INTC_INT_LOW_LEVEL, 0 },
147         { AU1550_DDMA_INT, INTC_INT_HIGH_LEVEL, 0 },
148         { AU1550_CRYPTO_INT, INTC_INT_HIGH_LEVEL, 0 },
149         { AU1550_PCI_INTC, INTC_INT_LOW_LEVEL, 0 },
150         { AU1550_PCI_INTD, INTC_INT_LOW_LEVEL, 0 },
151         { AU1550_PCI_RST_INT, INTC_INT_LOW_LEVEL, 0 },
152         { AU1550_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },
153         { AU1550_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },
154         { AU1550_PSC0_INT, INTC_INT_HIGH_LEVEL, 0 },
155         { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0 },
156         { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0 },
157         { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0 },
158         { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
159         { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
160         { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
161         { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
162         { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
163         { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
164         { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
165         { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
166         { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0 },
167         { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
168         { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
169         { AU1550_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
170         { AU1550_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
171         { AU1550_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
172
173 #elif defined(CONFIG_SOC_AU1200)
174
175         { AU1200_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
176         { AU1200_SWT_INT, INTC_INT_RISE_EDGE, 0 },
177         { AU1200_SD_INT, INTC_INT_HIGH_LEVEL, 0 },
178         { AU1200_DDMA_INT, INTC_INT_HIGH_LEVEL, 0 },
179         { AU1200_MAE_BE_INT, INTC_INT_HIGH_LEVEL, 0 },
180         { AU1200_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },
181         { AU1200_MAE_FE_INT, INTC_INT_HIGH_LEVEL, 0 },
182         { AU1200_PSC0_INT, INTC_INT_HIGH_LEVEL, 0 },
183         { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0 },
184         { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0 },
185         { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0 },
186         { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
187         { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
188         { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
189         { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
190         { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
191         { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
192         { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
193         { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
194         { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0 },
195         { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 },
196         { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0 },
197         { AU1200_MAE_BOTH_INT, INTC_INT_HIGH_LEVEL, 0 },
198
199 #else
200 #error "Error: Unknown Alchemy SOC"
201 #endif
202
203 };
204
205 int __initdata au1xxx_ic0_nr_irqs = ARRAY_SIZE(au1xxx_ic0_map);