git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/iwlwifi/iwl-5000.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  23  *
  24  *****************************************************************************/
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/version.h>
  29 #include <linux/init.h>
  30 #include <linux/pci.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/delay.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/wireless.h>
  36 #include <net/mac80211.h>
  37 #include <linux/etherdevice.h>
  38 #include <asm/unaligned.h>
  39
  40 #include "iwl-eeprom.h"
  41 #include "iwl-dev.h"
  42 #include "iwl-core.h"
  43 #include "iwl-io.h"
  44 #include "iwl-helpers.h"
  45 #include "iwl-5000-hw.h"
  46
  47 #define IWL5000_UCODE_API  "-1"
  48
  49 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
  50         IWL_TX_FIFO_AC3,
  51         IWL_TX_FIFO_AC2,
  52         IWL_TX_FIFO_AC1,
  53         IWL_TX_FIFO_AC0,
  54         IWL50_CMD_FIFO_NUM,
  55         IWL_TX_FIFO_HCCA_1,
  56         IWL_TX_FIFO_HCCA_2
  57 };
  58
  59 /* FIXME: same implementation as 4965 */
  60 static int iwl5000_apm_stop_master(struct iwl_priv *priv)
  61 {
  62         int ret = 0;
  63         unsigned long flags;
  64
  65         spin_lock_irqsave(&priv->lock, flags);
  66
  67         /* set stop master bit */
  68         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  69
  70         ret = iwl_poll_bit(priv, CSR_RESET,
  71                                   CSR_RESET_REG_FLAG_MASTER_DISABLED,
  72                                   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  73         if (ret < 0)
  74                 goto out;
  75
  76 out:
  77         spin_unlock_irqrestore(&priv->lock, flags);
  78         IWL_DEBUG_INFO("stop master\n");
  79
  80         return ret;
  81 }
  82
  83
  84 static int iwl5000_apm_init(struct iwl_priv *priv)
  85 {
  86         int ret = 0;
  87
  88         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  89                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  90
  91         /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
  92         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  93                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  94
  95         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
  96
  97         /* set "initialization complete" bit to move adapter
  98          * D0U* --> D0A* state */
  99         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 100
 101         /* wait for clock stabilization */
 102         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
 103                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 104                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 105         if (ret < 0) {
 106                 IWL_DEBUG_INFO("Failed to init the card\n");
 107                 return ret;
 108         }
 109
 110         ret = iwl_grab_nic_access(priv);
 111         if (ret)
 112                 return ret;
 113
 114         /* enable DMA */
 115         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 116
 117         udelay(20);
 118
 119         /* disable L1-Active */
 120         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 121                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 122
 123         iwl_release_nic_access(priv);
 124
 125         return ret;
 126 }
 127
 128 /* FIXME: this is indentical to 4965 */
 129 static void iwl5000_apm_stop(struct iwl_priv *priv)
 130 {
 131         unsigned long flags;
 132
 133         iwl5000_apm_stop_master(priv);
 134
 135         spin_lock_irqsave(&priv->lock, flags);
 136
 137         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 138
 139         udelay(10);
 140
 141         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 142
 143         spin_unlock_irqrestore(&priv->lock, flags);
 144 }
 145
 146
 147 static int iwl5000_apm_reset(struct iwl_priv *priv)
 148 {
 149         int ret = 0;
 150         unsigned long flags;
 151
 152         iwl5000_apm_stop_master(priv);
 153
 154         spin_lock_irqsave(&priv->lock, flags);
 155
 156         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 157
 158         udelay(10);
 159
 160
 161         /* FIXME: put here L1A -L0S w/a */
 162
 163         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 164
 165         /* set "initialization complete" bit to move adapter
 166          * D0U* --> D0A* state */
 167         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 168
 169         /* wait for clock stabilization */
 170         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
 171                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 172                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 173         if (ret < 0) {
 174                 IWL_DEBUG_INFO("Failed to init the card\n");
 175                 goto out;
 176         }
 177
 178         ret = iwl_grab_nic_access(priv);
 179         if (ret)
 180                 goto out;
 181
 182         /* enable DMA */
 183         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 184
 185         udelay(20);
 186
 187         /* disable L1-Active */
 188         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 189                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 190
 191         iwl_release_nic_access(priv);
 192
 193 out:
 194         spin_unlock_irqrestore(&priv->lock, flags);
 195
 196         return ret;
 197 }
 198
 199
 200 static void iwl5000_nic_config(struct iwl_priv *priv)
 201 {
 202         unsigned long flags;
 203         u16 radio_cfg;
 204         u8 val_link;
 205
 206         spin_lock_irqsave(&priv->lock, flags);
 207
 208         pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
 209
 210         /* L1 is enabled by BIOS */
 211         if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN)
 212                 /* diable L0S disabled L1A enabled */
 213                 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 214         else
 215                 /* L0S enabled L1A disabled */
 216                 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 217
 218         radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
 219
 220         /* write radio config values to register */
 221         if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
 222                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 223                             EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
 224                             EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
 225                             EEPROM_RF_CFG_DASH_MSK(radio_cfg));
 226
 227         /* set CSR_HW_CONFIG_REG for uCode use */
 228         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 229                     CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
 230                     CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
 231
 232         spin_unlock_irqrestore(&priv->lock, flags);
 233 }
 234
 235
 236
 237 /*
 238  * EEPROM
 239  */
 240 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 241 {
 242         u16 offset = 0;
 243
 244         if ((address & INDIRECT_ADDRESS) == 0)
 245                 return address;
 246
 247         switch (address & INDIRECT_TYPE_MSK) {
 248         case INDIRECT_HOST:
 249                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
 250                 break;
 251         case INDIRECT_GENERAL:
 252                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
 253                 break;
 254         case INDIRECT_REGULATORY:
 255                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
 256                 break;
 257         case INDIRECT_CALIBRATION:
 258                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
 259                 break;
 260         case INDIRECT_PROCESS_ADJST:
 261                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
 262                 break;
 263         case INDIRECT_OTHERS:
 264                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
 265                 break;
 266         default:
 267                 IWL_ERROR("illegal indirect type: 0x%X\n",
 268                 address & INDIRECT_TYPE_MSK);
 269                 break;
 270         }
 271
 272         /* translate the offset from words to byte */
 273         return (address & ADDRESS_MSK) + (offset << 1);
 274 }
 275
 276 static int iwl5000_eeprom_check_version(struct iwl_priv *priv)
 277 {
 278         u16 eeprom_ver;
 279         struct iwl_eeprom_calib_hdr {
 280                 u8 version;
 281                 u8 pa_type;
 282                 u16 voltage;
 283         } *hdr;
 284
 285         eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
 286
 287         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 288                                                         EEPROM_5000_CALIB_ALL);
 289
 290         if (eeprom_ver < EEPROM_5000_EEPROM_VERSION ||
 291             hdr->version < EEPROM_5000_TX_POWER_VERSION)
 292                 goto err;
 293
 294         return 0;
 295 err:
 296         IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
 297                   eeprom_ver, EEPROM_5000_EEPROM_VERSION,
 298                   hdr->version, EEPROM_5000_TX_POWER_VERSION);
 299         return -EINVAL;
 300
 301 }
 302
 303 static void iwl5000_gain_computation(struct iwl_priv *priv,
 304                 u32 average_noise[NUM_RX_CHAINS],
 305                 u16 min_average_noise_antenna_i,
 306                 u32 min_average_noise)
 307 {
 308         int i;
 309         s32 delta_g;
 310         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 311
 312         /* Find Gain Code for the antennas B and C */
 313         for (i = 1; i < NUM_RX_CHAINS; i++) {
 314                 if ((data->disconn_array[i])) {
 315                         data->delta_gain_code[i] = 0;
 316                         continue;
 317                 }
 318                 delta_g = (1000 * ((s32)average_noise[0] -
 319                         (s32)average_noise[i])) / 1500;
 320                 /* bound gain by 2 bits value max, 3rd bit is sign */
 321                 data->delta_gain_code[i] =
 322                         min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
 323
 324                 if (delta_g < 0)
 325                         /* set negative sign */
 326                         data->delta_gain_code[i] |= (1 << 2);
 327         }
 328
 329         IWL_DEBUG_CALIB("Delta gains: ANT_B = %d  ANT_C = %d\n",
 330                         data->delta_gain_code[1], data->delta_gain_code[2]);
 331
 332         if (!data->radio_write) {
 333                 struct iwl5000_calibration_chain_noise_gain_cmd cmd;
 334                 memset(&cmd, 0, sizeof(cmd));
 335
 336                 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
 337                 cmd.delta_gain_1 = data->delta_gain_code[1];
 338                 cmd.delta_gain_2 = data->delta_gain_code[2];
 339                 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
 340                         sizeof(cmd), &cmd, NULL);
 341
 342                 data->radio_write = 1;
 343                 data->state = IWL_CHAIN_NOISE_CALIBRATED;
 344         }
 345
 346         data->chain_noise_a = 0;
 347         data->chain_noise_b = 0;
 348         data->chain_noise_c = 0;
 349         data->chain_signal_a = 0;
 350         data->chain_signal_b = 0;
 351         data->chain_signal_c = 0;
 352         data->beacon_count = 0;
 353 }
 354
 355 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
 356 {
 357         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 358
 359         if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
 360                 struct iwl5000_calibration_chain_noise_reset_cmd cmd;
 361
 362                 memset(&cmd, 0, sizeof(cmd));
 363                 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
 364                 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
 365                         sizeof(cmd), &cmd))
 366                         IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
 367                 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
 368                 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
 369         }
 370 }
 371
 372 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
 373         .min_nrg_cck = 95,
 374         .max_nrg_cck = 0,
 375         .auto_corr_min_ofdm = 90,
 376         .auto_corr_min_ofdm_mrc = 170,
 377         .auto_corr_min_ofdm_x1 = 120,
 378         .auto_corr_min_ofdm_mrc_x1 = 240,
 379
 380         .auto_corr_max_ofdm = 120,
 381         .auto_corr_max_ofdm_mrc = 210,
 382         .auto_corr_max_ofdm_x1 = 155,
 383         .auto_corr_max_ofdm_mrc_x1 = 290,
 384
 385         .auto_corr_min_cck = 125,
 386         .auto_corr_max_cck = 200,
 387         .auto_corr_min_cck_mrc = 170,
 388         .auto_corr_max_cck_mrc = 400,
 389         .nrg_th_cck = 95,
 390         .nrg_th_ofdm = 95,
 391 };
 392
 393 static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
 394                                            size_t offset)
 395 {
 396         u32 address = eeprom_indirect_address(priv, offset);
 397         BUG_ON(address >= priv->cfg->eeprom_size);
 398         return &priv->eeprom[address];
 399 }
 400
 401 /*
 402  *  Calibration
 403  */
 404 static int iwl5000_send_Xtal_calib(struct iwl_priv *priv)
 405 {
 406         u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
 407
 408         struct iwl5000_calibration cal_cmd = {
 409                 .op_code = IWL5000_PHY_CALIBRATE_CRYSTAL_FRQ_CMD,
 410                 .data = {
 411                         (u8)xtal_calib[0],
 412                         (u8)xtal_calib[1],
 413                 }
 414         };
 415
 416         return iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
 417                                 sizeof(cal_cmd), &cal_cmd);
 418 }
 419
 420 static int iwl5000_send_calib_results(struct iwl_priv *priv)
 421 {
 422         int ret = 0;
 423
 424         struct iwl_host_cmd hcmd = {
 425                 .id = REPLY_PHY_CALIBRATION_CMD,
 426                 .meta.flags = CMD_SIZE_HUGE,
 427         };
 428
 429         if (priv->calib_results.lo_res) {
 430                 hcmd.len = priv->calib_results.lo_res_len;
 431                 hcmd.data = priv->calib_results.lo_res;
 432                 ret = iwl_send_cmd_sync(priv, &hcmd);
 433
 434                 if (ret)
 435                         goto err;
 436         }
 437
 438         if (priv->calib_results.tx_iq_res) {
 439                 hcmd.len = priv->calib_results.tx_iq_res_len;
 440                 hcmd.data = priv->calib_results.tx_iq_res;
 441                 ret = iwl_send_cmd_sync(priv, &hcmd);
 442
 443                 if (ret)
 444                         goto err;
 445         }
 446
 447         if (priv->calib_results.tx_iq_perd_res) {
 448                 hcmd.len = priv->calib_results.tx_iq_perd_res_len;
 449                 hcmd.data = priv->calib_results.tx_iq_perd_res;
 450                 ret = iwl_send_cmd_sync(priv, &hcmd);
 451
 452                 if (ret)
 453                         goto err;
 454         }
 455
 456         return 0;
 457 err:
 458         IWL_ERROR("Error %d\n", ret);
 459         return ret;
 460 }
 461
 462 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
 463 {
 464         struct iwl5000_calib_cfg_cmd calib_cfg_cmd;
 465         struct iwl_host_cmd cmd = {
 466                 .id = CALIBRATION_CFG_CMD,
 467                 .len = sizeof(struct iwl5000_calib_cfg_cmd),
 468                 .data = &calib_cfg_cmd,
 469         };
 470
 471         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
 472         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
 473         calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
 474         calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
 475         calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
 476
 477         return iwl_send_cmd(priv, &cmd);
 478 }
 479
 480 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
 481                              struct iwl_rx_mem_buffer *rxb)
 482 {
 483         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 484         struct iwl5000_calib_hdr *hdr = (struct iwl5000_calib_hdr *)pkt->u.raw;
 485         int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
 486
 487         iwl_free_calib_results(priv);
 488
 489         /* reduce the size of the length field itself */
 490         len -= 4;
 491
 492         switch (hdr->op_code) {
 493         case IWL5000_PHY_CALIBRATE_LO_CMD:
 494                 priv->calib_results.lo_res = kzalloc(len, GFP_ATOMIC);
 495                 priv->calib_results.lo_res_len = len;
 496                 memcpy(priv->calib_results.lo_res, pkt->u.raw, len);
 497                 break;
 498         case IWL5000_PHY_CALIBRATE_TX_IQ_CMD:
 499                 priv->calib_results.tx_iq_res = kzalloc(len, GFP_ATOMIC);
 500                 priv->calib_results.tx_iq_res_len = len;
 501                 memcpy(priv->calib_results.tx_iq_res, pkt->u.raw, len);
 502                 break;
 503         case IWL5000_PHY_CALIBRATE_TX_IQ_PERD_CMD:
 504                 priv->calib_results.tx_iq_perd_res = kzalloc(len, GFP_ATOMIC);
 505                 priv->calib_results.tx_iq_perd_res_len = len;
 506                 memcpy(priv->calib_results.tx_iq_perd_res, pkt->u.raw, len);
 507                 break;
 508         default:
 509                 IWL_ERROR("Unknown calibration notification %d\n",
 510                           hdr->op_code);
 511                 return;
 512         }
 513 }
 514
 515 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
 516                                struct iwl_rx_mem_buffer *rxb)
 517 {
 518         IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n");
 519         queue_work(priv->workqueue, &priv->restart);
 520 }
 521
 522 /*
 523  * ucode
 524  */
 525 static int iwl5000_load_section(struct iwl_priv *priv,
 526                                 struct fw_desc *image,
 527                                 u32 dst_addr)
 528 {
 529         int ret = 0;
 530         unsigned long flags;
 531
 532         dma_addr_t phy_addr = image->p_addr;
 533         u32 byte_cnt = image->len;
 534
 535         spin_lock_irqsave(&priv->lock, flags);
 536         ret = iwl_grab_nic_access(priv);
 537         if (ret) {
 538                 spin_unlock_irqrestore(&priv->lock, flags);
 539                 return ret;
 540         }
 541
 542         iwl_write_direct32(priv,
 543                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 544                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 545
 546         iwl_write_direct32(priv,
 547                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 548
 549         iwl_write_direct32(priv,
 550                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 551                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 552
 553         /* FIME: write the MSB of the phy_addr in CTRL1
 554          * iwl_write_direct32(priv,
 555                 IWL_FH_TFDIB_CTRL1_REG(IWL_FH_SRVC_CHNL),
 556                 ((phy_addr & MSB_MSK)
 557                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_count);
 558          */
 559         iwl_write_direct32(priv,
 560                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), byte_cnt);
 561         iwl_write_direct32(priv,
 562                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 563                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 564                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 565                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 566
 567         iwl_write_direct32(priv,
 568                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 569                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 570                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL |
 571                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 572
 573         iwl_release_nic_access(priv);
 574         spin_unlock_irqrestore(&priv->lock, flags);
 575         return 0;
 576 }
 577
 578 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
 579                 struct fw_desc *inst_image,
 580                 struct fw_desc *data_image)
 581 {
 582         int ret = 0;
 583
 584         ret = iwl5000_load_section(
 585                 priv, inst_image, RTC_INST_LOWER_BOUND);
 586         if (ret)
 587                 return ret;
 588
 589         IWL_DEBUG_INFO("INST uCode section being loaded...\n");
 590         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 591                                 priv->ucode_write_complete, 5 * HZ);
 592         if (ret == -ERESTARTSYS) {
 593                 IWL_ERROR("Could not load the INST uCode section due "
 594                         "to interrupt\n");
 595                 return ret;
 596         }
 597         if (!ret) {
 598                 IWL_ERROR("Could not load the INST uCode section\n");
 599                 return -ETIMEDOUT;
 600         }
 601
 602         priv->ucode_write_complete = 0;
 603
 604         ret = iwl5000_load_section(
 605                 priv, data_image, RTC_DATA_LOWER_BOUND);
 606         if (ret)
 607                 return ret;
 608
 609         IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
 610
 611         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 612                                 priv->ucode_write_complete, 5 * HZ);
 613         if (ret == -ERESTARTSYS) {
 614                 IWL_ERROR("Could not load the INST uCode section due "
 615                         "to interrupt\n");
 616                 return ret;
 617         } else if (!ret) {
 618                 IWL_ERROR("Could not load the DATA uCode section\n");
 619                 return -ETIMEDOUT;
 620         } else
 621                 ret = 0;
 622
 623         priv->ucode_write_complete = 0;
 624
 625         return ret;
 626 }
 627
 628 static int iwl5000_load_ucode(struct iwl_priv *priv)
 629 {
 630         int ret = 0;
 631
 632         /* check whether init ucode should be loaded, or rather runtime ucode */
 633         if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
 634                 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
 635                 ret = iwl5000_load_given_ucode(priv,
 636                         &priv->ucode_init, &priv->ucode_init_data);
 637                 if (!ret) {
 638                         IWL_DEBUG_INFO("Init ucode load complete.\n");
 639                         priv->ucode_type = UCODE_INIT;
 640                 }
 641         } else {
 642                 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
 643                         "Loading runtime ucode...\n");
 644                 ret = iwl5000_load_given_ucode(priv,
 645                         &priv->ucode_code, &priv->ucode_data);
 646                 if (!ret) {
 647                         IWL_DEBUG_INFO("Runtime ucode load complete.\n");
 648                         priv->ucode_type = UCODE_RT;
 649                 }
 650         }
 651
 652         return ret;
 653 }
 654
 655 static void iwl5000_init_alive_start(struct iwl_priv *priv)
 656 {
 657         int ret = 0;
 658
 659         /* Check alive response for "valid" sign from uCode */
 660         if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
 661                 /* We had an error bringing up the hardware, so take it
 662                  * all the way back down so we can try again */
 663                 IWL_DEBUG_INFO("Initialize Alive failed.\n");
 664                 goto restart;
 665         }
 666
 667         /* initialize uCode was loaded... verify inst image.
 668          * This is a paranoid check, because we would not have gotten the
 669          * "initialize" alive if code weren't properly loaded.  */
 670         if (iwl_verify_ucode(priv)) {
 671                 /* Runtime instruction load was bad;
 672                  * take it all the way back down so we can try again */
 673                 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
 674                 goto restart;
 675         }
 676
 677         iwlcore_clear_stations_table(priv);
 678         ret = priv->cfg->ops->lib->alive_notify(priv);
 679         if (ret) {
 680                 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
 681                 goto restart;
 682         }
 683
 684         iwl5000_send_calib_cfg(priv);
 685         return;
 686
 687 restart:
 688         /* real restart (first load init_ucode) */
 689         queue_work(priv->workqueue, &priv->restart);
 690 }
 691
 692 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
 693                                 int txq_id, u32 index)
 694 {
 695         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
 696                         (index & 0xff) | (txq_id << 8));
 697         iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
 698 }
 699
 700 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
 701                                         struct iwl_tx_queue *txq,
 702                                         int tx_fifo_id, int scd_retry)
 703 {
 704         int txq_id = txq->q.id;
 705         int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
 706
 707         iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 708                         (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 709                         (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
 710                         (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
 711                         IWL50_SCD_QUEUE_STTS_REG_MSK);
 712
 713         txq->sched_retry = scd_retry;
 714
 715         IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
 716                        active ? "Activate" : "Deactivate",
 717                        scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
 718 }
 719
 720 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
 721 {
 722         struct iwl_wimax_coex_cmd coex_cmd;
 723
 724         memset(&coex_cmd, 0, sizeof(coex_cmd));
 725
 726         return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
 727                                 sizeof(coex_cmd), &coex_cmd);
 728 }
 729
 730 static int iwl5000_alive_notify(struct iwl_priv *priv)
 731 {
 732         u32 a;
 733         int i = 0;
 734         unsigned long flags;
 735         int ret;
 736
 737         spin_lock_irqsave(&priv->lock, flags);
 738
 739         ret = iwl_grab_nic_access(priv);
 740         if (ret) {
 741                 spin_unlock_irqrestore(&priv->lock, flags);
 742                 return ret;
 743         }
 744
 745         priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
 746         a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
 747         for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
 748                 a += 4)
 749                 iwl_write_targ_mem(priv, a, 0);
 750         for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
 751                 a += 4)
 752                 iwl_write_targ_mem(priv, a, 0);
 753         for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
 754                 iwl_write_targ_mem(priv, a, 0);
 755
 756         iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
 757                 (priv->shared_phys +
 758                  offsetof(struct iwl5000_shared, queues_byte_cnt_tbls)) >> 10);
 759         iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
 760                 IWL50_SCD_QUEUECHAIN_SEL_ALL(
 761                         priv->hw_params.max_txq_num));
 762         iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
 763
 764         /* initiate the queues */
 765         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
 766                 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
 767                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
 768                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 769                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 770                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 771                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
 772                                 sizeof(u32),
 773                                 ((SCD_WIN_SIZE <<
 774                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 775                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 776                                 ((SCD_FRAME_LIMIT <<
 777                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 778                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 779         }
 780
 781         iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
 782                         IWL_MASK(0, priv->hw_params.max_txq_num));
 783
 784         /* Activate all Tx DMA/FIFO channels */
 785         priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
 786
 787         iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
 788         /* map qos queues to fifos one-to-one */
 789         for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
 790                 int ac = iwl5000_default_queue_to_tx_fifo[i];
 791                 iwl_txq_ctx_activate(priv, i);
 792                 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
 793         }
 794         /* TODO - need to initialize those FIFOs inside the loop above,
 795          * not only mark them as active */
 796         iwl_txq_ctx_activate(priv, 4);
 797         iwl_txq_ctx_activate(priv, 7);
 798         iwl_txq_ctx_activate(priv, 8);
 799         iwl_txq_ctx_activate(priv, 9);
 800
 801         iwl_release_nic_access(priv);
 802         spin_unlock_irqrestore(&priv->lock, flags);
 803
 804
 805         iwl5000_send_wimax_coex(priv);
 806
 807         iwl5000_send_Xtal_calib(priv);
 808
 809         if (priv->ucode_type == UCODE_RT) {
 810                 iwl5000_send_calib_results(priv);
 811                 set_bit(STATUS_READY, &priv->status);
 812                 priv->is_open = 1;
 813         }
 814
 815         return 0;
 816 }
 817
 818 static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
 819 {
 820         if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
 821             (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
 822                 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
 823                           IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
 824                 return -EINVAL;
 825         }
 826
 827         priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
 828         priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
 829         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
 830         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
 831         if (priv->cfg->mod_params->amsdu_size_8K)
 832                 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
 833         else
 834                 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
 835         priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
 836         priv->hw_params.max_stations = IWL5000_STATION_COUNT;
 837         priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
 838         priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
 839         priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
 840         priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
 841         priv->hw_params.fat_channel =  BIT(IEEE80211_BAND_2GHZ) |
 842                                         BIT(IEEE80211_BAND_5GHZ);
 843         priv->hw_params.sens = &iwl5000_sensitivity;
 844
 845         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 846         case CSR_HW_REV_TYPE_5100:
 847         case CSR_HW_REV_TYPE_5150:
 848                 priv->hw_params.tx_chains_num = 1;
 849                 priv->hw_params.rx_chains_num = 2;
 850                 /* FIXME: move to ANT_A, ANT_B, ANT_C enum */
 851                 priv->hw_params.valid_tx_ant = ANT_A;
 852                 priv->hw_params.valid_rx_ant = ANT_AB;
 853                 break;
 854         case CSR_HW_REV_TYPE_5300:
 855         case CSR_HW_REV_TYPE_5350:
 856                 priv->hw_params.tx_chains_num = 3;
 857                 priv->hw_params.rx_chains_num = 3;
 858                 priv->hw_params.valid_tx_ant = ANT_ABC;
 859                 priv->hw_params.valid_rx_ant = ANT_ABC;
 860                 break;
 861         }
 862
 863         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 864         case CSR_HW_REV_TYPE_5100:
 865         case CSR_HW_REV_TYPE_5300:
 866                 /* 5X00 wants in Celsius */
 867                 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
 868                 break;
 869         case CSR_HW_REV_TYPE_5150:
 870         case CSR_HW_REV_TYPE_5350:
 871                 /* 5X50 wants in Kelvin */
 872                 priv->hw_params.ct_kill_threshold =
 873                                 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
 874                 break;
 875         }
 876
 877         return 0;
 878 }
 879
 880 static int iwl5000_alloc_shared_mem(struct iwl_priv *priv)
 881 {
 882         priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
 883                                         sizeof(struct iwl5000_shared),
 884                                         &priv->shared_phys);
 885         if (!priv->shared_virt)
 886                 return -ENOMEM;
 887
 888         memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared));
 889
 890         priv->rb_closed_offset = offsetof(struct iwl5000_shared, rb_closed);
 891
 892         return 0;
 893 }
 894
 895 static void iwl5000_free_shared_mem(struct iwl_priv *priv)
 896 {
 897         if (priv->shared_virt)
 898                 pci_free_consistent(priv->pci_dev,
 899                                     sizeof(struct iwl5000_shared),
 900                                     priv->shared_virt,
 901                                     priv->shared_phys);
 902 }
 903
 904 static int iwl5000_shared_mem_rx_idx(struct iwl_priv *priv)
 905 {
 906         struct iwl5000_shared *s = priv->shared_virt;
 907         return le32_to_cpu(s->rb_closed) & 0xFFF;
 908 }
 909
 910 /**
 911  * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 912  */
 913 static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
 914                                             struct iwl_tx_queue *txq,
 915                                             u16 byte_cnt)
 916 {
 917         struct iwl5000_shared *shared_data = priv->shared_virt;
 918         int txq_id = txq->q.id;
 919         u8 sec_ctl = 0;
 920         u8 sta = 0;
 921         int len;
 922
 923         len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 924
 925         if (txq_id != IWL_CMD_QUEUE_NUM) {
 926                 sta = txq->cmd[txq->q.write_ptr].cmd.tx.sta_id;
 927                 sec_ctl = txq->cmd[txq->q.write_ptr].cmd.tx.sec_ctl;
 928
 929                 switch (sec_ctl & TX_CMD_SEC_MSK) {
 930                 case TX_CMD_SEC_CCM:
 931                         len += CCMP_MIC_LEN;
 932                         break;
 933                 case TX_CMD_SEC_TKIP:
 934                         len += TKIP_ICV_LEN;
 935                         break;
 936                 case TX_CMD_SEC_WEP:
 937                         len += WEP_IV_LEN + WEP_ICV_LEN;
 938                         break;
 939                 }
 940         }
 941
 942         IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
 943                        tfd_offset[txq->q.write_ptr], byte_cnt, len);
 944
 945         IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
 946                        tfd_offset[txq->q.write_ptr], sta_id, sta);
 947
 948         if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
 949                 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
 950                         tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
 951                         byte_cnt, len);
 952                 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
 953                         tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
 954                         sta_id, sta);
 955         }
 956 }
 957
 958 static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
 959                                            struct iwl_tx_queue *txq)
 960 {
 961         int txq_id = txq->q.id;
 962         struct iwl5000_shared *shared_data = priv->shared_virt;
 963         u8 sta = 0;
 964
 965         if (txq_id != IWL_CMD_QUEUE_NUM)
 966                 sta = txq->cmd[txq->q.read_ptr].cmd.tx.sta_id;
 967
 968         shared_data->queues_byte_cnt_tbls[txq_id].tfd_offset[txq->q.read_ptr].
 969                                         val = cpu_to_le16(1 | (sta << 12));
 970
 971         if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
 972                 shared_data->queues_byte_cnt_tbls[txq_id].
 973                         tfd_offset[IWL50_QUEUE_SIZE + txq->q.read_ptr].
 974                                 val = cpu_to_le16(1 | (sta << 12));
 975         }
 976 }
 977
 978 static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
 979 {
 980         u16 size = (u16)sizeof(struct iwl_addsta_cmd);
 981         memcpy(data, cmd, size);
 982         return size;
 983 }
 984
 985
 986 /*
 987  * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
 988  * must be called under priv->lock and mac access
 989  */
 990 static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
 991 {
 992         iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
 993 }
 994
 995
 996 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
 997 {
 998         __le32 *scd_ssn = (__le32 *)((u32 *)&tx_resp->status +
 999                                 tx_resp->frame_count);
1000         return le32_to_cpu(*scd_ssn) & MAX_SN;
1001
1002 }
1003
1004 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1005                                       struct iwl_ht_agg *agg,
1006                                       struct iwl5000_tx_resp *tx_resp,
1007                                       u16 start_idx)
1008 {
1009         u16 status;
1010         struct agg_tx_status *frame_status = &tx_resp->status;
1011         struct ieee80211_tx_info *info = NULL;
1012         struct ieee80211_hdr *hdr = NULL;
1013         int i, sh;
1014         int txq_id, idx;
1015         u16 seq;
1016
1017         if (agg->wait_for_ba)
1018                 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
1019
1020         agg->frame_count = tx_resp->frame_count;
1021         agg->start_idx = start_idx;
1022         agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1023         agg->bitmap = 0;
1024
1025         /* # frames attempted by Tx command */
1026         if (agg->frame_count == 1) {
1027                 /* Only one frame was attempted; no block-ack will arrive */
1028                 status = le16_to_cpu(frame_status[0].status);
1029                 seq  = le16_to_cpu(frame_status[0].sequence);
1030                 idx = SEQ_TO_INDEX(seq);
1031                 txq_id = SEQ_TO_QUEUE(seq);
1032
1033                 /* FIXME: code repetition */
1034                 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
1035                                    agg->frame_count, agg->start_idx, idx);
1036
1037                 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1038                 info->status.retry_count = tx_resp->failure_frame;
1039                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1040                 info->flags |= iwl_is_tx_success(status)?
1041                         IEEE80211_TX_STAT_ACK : 0;
1042                 iwl4965_hwrate_to_tx_control(priv,
1043                                              le32_to_cpu(tx_resp->rate_n_flags),
1044                                              info);
1045                 /* FIXME: code repetition end */
1046
1047                 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
1048                                     status & 0xff, tx_resp->failure_frame);
1049                 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n",
1050                         iwl4965_hw_get_rate_n_flags(tx_resp->rate_n_flags));
1051
1052                 agg->wait_for_ba = 0;
1053         } else {
1054                 /* Two or more frames were attempted; expect block-ack */
1055                 u64 bitmap = 0;
1056                 int start = agg->start_idx;
1057
1058                 /* Construct bit-map of pending frames within Tx window */
1059                 for (i = 0; i < agg->frame_count; i++) {
1060                         u16 sc;
1061                         status = le16_to_cpu(frame_status[i].status);
1062                         seq  = le16_to_cpu(frame_status[i].sequence);
1063                         idx = SEQ_TO_INDEX(seq);
1064                         txq_id = SEQ_TO_QUEUE(seq);
1065
1066                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1067                                       AGG_TX_STATE_ABORT_MSK))
1068                                 continue;
1069
1070                         IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
1071                                            agg->frame_count, txq_id, idx);
1072
1073                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1074
1075                         sc = le16_to_cpu(hdr->seq_ctrl);
1076                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1077                                 IWL_ERROR("BUG_ON idx doesn't match seq control"
1078                                           " idx=%d, seq_idx=%d, seq=%d\n",
1079                                           idx, SEQ_TO_SN(sc),
1080                                           hdr->seq_ctrl);
1081                                 return -1;
1082                         }
1083
1084                         IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
1085                                            i, idx, SEQ_TO_SN(sc));
1086
1087                         sh = idx - start;
1088                         if (sh > 64) {
1089                                 sh = (start - idx) + 0xff;
1090                                 bitmap = bitmap << sh;
1091                                 sh = 0;
1092                                 start = idx;
1093                         } else if (sh < -64)
1094                                 sh  = 0xff - (start - idx);
1095                         else if (sh < 0) {
1096                                 sh = start - idx;
1097                                 start = idx;
1098                                 bitmap = bitmap << sh;
1099                                 sh = 0;
1100                         }
1101                         bitmap |= (1 << sh);
1102                         IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n",
1103                                            start, (u32)(bitmap & 0xFFFFFFFF));
1104                 }
1105
1106                 agg->bitmap = bitmap;
1107                 agg->start_idx = start;
1108                 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1109                 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
1110                                    agg->frame_count, agg->start_idx,
1111                                    (unsigned long long)agg->bitmap);
1112
1113                 if (bitmap)
1114                         agg->wait_for_ba = 1;
1115         }
1116         return 0;
1117 }
1118
1119 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1120                                 struct iwl_rx_mem_buffer *rxb)
1121 {
1122         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1123         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1124         int txq_id = SEQ_TO_QUEUE(sequence);
1125         int index = SEQ_TO_INDEX(sequence);
1126         struct iwl_tx_queue *txq = &priv->txq[txq_id];
1127         struct ieee80211_tx_info *info;
1128         struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1129         u32  status = le16_to_cpu(tx_resp->status.status);
1130         int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION;
1131         u16 fc;
1132         struct ieee80211_hdr *hdr;
1133         u8 *qc = NULL;
1134
1135         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1136                 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
1137                           "is out of range [0-%d] %d %d\n", txq_id,
1138                           index, txq->q.n_bd, txq->q.write_ptr,
1139                           txq->q.read_ptr);
1140                 return;
1141         }
1142
1143         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1144         memset(&info->status, 0, sizeof(info->status));
1145
1146         hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
1147         fc = le16_to_cpu(hdr->frame_control);
1148         if (ieee80211_is_qos_data(fc)) {
1149                 qc = ieee80211_get_qos_ctrl(hdr, ieee80211_get_hdrlen(fc));
1150                 tid = qc[0] & 0xf;
1151         }
1152
1153         sta_id = iwl_get_ra_sta_id(priv, hdr);
1154         if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
1155                 IWL_ERROR("Station not known\n");
1156                 return;
1157         }
1158
1159         if (txq->sched_retry) {
1160                 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1161                 struct iwl_ht_agg *agg = NULL;
1162
1163                 if (!qc)
1164                         return;
1165
1166                 agg = &priv->stations[sta_id].tid[tid].agg;
1167
1168                 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, index);
1169
1170                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) {
1171                         /* TODO: send BAR */
1172                 }
1173
1174                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1175                         int freed, ampdu_q;
1176                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1177                         IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
1178                                            "%d index %d\n", scd_ssn , index);
1179                         freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1180                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1181
1182                         if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1183                             txq_id >= 0 && priv->mac80211_registered &&
1184                             agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) {
1185                                 /* calculate mac80211 ampdu sw queue to wake */
1186                                 ampdu_q = txq_id - IWL_BACK_QUEUE_FIRST_ID +
1187                                           priv->hw->queues;
1188                                 if (agg->state == IWL_AGG_OFF)
1189                                         ieee80211_wake_queue(priv->hw, txq_id);
1190                                 else
1191                                         ieee80211_wake_queue(priv->hw, ampdu_q);
1192                         }
1193                         iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1194                 }
1195         } else {
1196                 info->status.retry_count = tx_resp->failure_frame;
1197                 info->flags =
1198                         iwl_is_tx_success(status) ? IEEE80211_TX_STAT_ACK : 0;
1199                 iwl4965_hwrate_to_tx_control(priv,
1200                                         le32_to_cpu(tx_resp->rate_n_flags),
1201                                         info);
1202
1203                 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags "
1204                              "0x%x retries %d\n", txq_id,
1205                                 iwl_get_tx_fail_reason(status),
1206                                 status, le32_to_cpu(tx_resp->rate_n_flags),
1207                                 tx_resp->failure_frame);
1208
1209                 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
1210                 if (index != -1) {
1211                     int freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1212                     if (tid != MAX_TID_COUNT)
1213                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1214                     if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1215                         (txq_id >= 0) && priv->mac80211_registered)
1216                         ieee80211_wake_queue(priv->hw, txq_id);
1217                     if (tid != MAX_TID_COUNT)
1218                         iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1219                 }
1220         }
1221
1222         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1223                 IWL_ERROR("TODO:  Implement Tx ABORT REQUIRED!!!\n");
1224 }
1225
1226 /* Currently 5000 is the supperset of everything */
1227 static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1228 {
1229         return len;
1230 }
1231
1232 static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1233 {
1234         /* in 5000 the tx power calibration is done in uCode */
1235         priv->disable_tx_power_cal = 1;
1236 }
1237
1238 static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1239 {
1240         /* init calibration handlers */
1241         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1242                                         iwl5000_rx_calib_result;
1243         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1244                                         iwl5000_rx_calib_complete;
1245         priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1246 }
1247
1248
1249 static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1250 {
1251         return (addr >= RTC_DATA_LOWER_BOUND) &&
1252                 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1253 }
1254
1255 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1256 {
1257         int ret = 0;
1258         struct iwl5000_rxon_assoc_cmd rxon_assoc;
1259         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1260         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1261
1262         if ((rxon1->flags == rxon2->flags) &&
1263             (rxon1->filter_flags == rxon2->filter_flags) &&
1264             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1265             (rxon1->ofdm_ht_single_stream_basic_rates ==
1266              rxon2->ofdm_ht_single_stream_basic_rates) &&
1267             (rxon1->ofdm_ht_dual_stream_basic_rates ==
1268              rxon2->ofdm_ht_dual_stream_basic_rates) &&
1269             (rxon1->ofdm_ht_triple_stream_basic_rates ==
1270              rxon2->ofdm_ht_triple_stream_basic_rates) &&
1271             (rxon1->acquisition_data == rxon2->acquisition_data) &&
1272             (rxon1->rx_chain == rxon2->rx_chain) &&
1273             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1274                 IWL_DEBUG_INFO("Using current RXON_ASSOC.  Not resending.\n");
1275                 return 0;
1276         }
1277
1278         rxon_assoc.flags = priv->staging_rxon.flags;
1279         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1280         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1281         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1282         rxon_assoc.reserved1 = 0;
1283         rxon_assoc.reserved2 = 0;
1284         rxon_assoc.reserved3 = 0;
1285         rxon_assoc.ofdm_ht_single_stream_basic_rates =
1286             priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1287         rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1288             priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1289         rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1290         rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1291                  priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1292         rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1293
1294         ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1295                                      sizeof(rxon_assoc), &rxon_assoc, NULL);
1296         if (ret)
1297                 return ret;
1298
1299         return ret;
1300 }
1301
1302 static struct iwl_hcmd_ops iwl5000_hcmd = {
1303         .rxon_assoc = iwl5000_send_rxon_assoc,
1304 };
1305
1306 static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1307         .get_hcmd_size = iwl5000_get_hcmd_size,
1308         .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1309         .gain_computation = iwl5000_gain_computation,
1310         .chain_noise_reset = iwl5000_chain_noise_reset,
1311 };
1312
1313 static struct iwl_lib_ops iwl5000_lib = {
1314         .set_hw_params = iwl5000_hw_set_hw_params,
1315         .alloc_shared_mem = iwl5000_alloc_shared_mem,
1316         .free_shared_mem = iwl5000_free_shared_mem,
1317         .shared_mem_rx_idx = iwl5000_shared_mem_rx_idx,
1318         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1319         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1320         .txq_set_sched = iwl5000_txq_set_sched,
1321         .rx_handler_setup = iwl5000_rx_handler_setup,
1322         .setup_deferred_work = iwl5000_setup_deferred_work,
1323         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1324         .load_ucode = iwl5000_load_ucode,
1325         .init_alive_start = iwl5000_init_alive_start,
1326         .alive_notify = iwl5000_alive_notify,
1327         .apm_ops = {
1328                 .init = iwl5000_apm_init,
1329                 .reset = iwl5000_apm_reset,
1330                 .stop = iwl5000_apm_stop,
1331                 .config = iwl5000_nic_config,
1332                 .set_pwr_src = iwl4965_set_pwr_src,
1333         },
1334         .eeprom_ops = {
1335                 .regulatory_bands = {
1336                         EEPROM_5000_REG_BAND_1_CHANNELS,
1337                         EEPROM_5000_REG_BAND_2_CHANNELS,
1338                         EEPROM_5000_REG_BAND_3_CHANNELS,
1339                         EEPROM_5000_REG_BAND_4_CHANNELS,
1340                         EEPROM_5000_REG_BAND_5_CHANNELS,
1341                         EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1342                         EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1343                 },
1344                 .verify_signature  = iwlcore_eeprom_verify_signature,
1345                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1346                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1347                 .check_version  = iwl5000_eeprom_check_version,
1348                 .query_addr = iwl5000_eeprom_query_addr,
1349         },
1350 };
1351
1352 static struct iwl_ops iwl5000_ops = {
1353         .lib = &iwl5000_lib,
1354         .hcmd = &iwl5000_hcmd,
1355         .utils = &iwl5000_hcmd_utils,
1356 };
1357
1358 static struct iwl_mod_params iwl50_mod_params = {
1359         .num_of_queues = IWL50_NUM_QUEUES,
1360         .enable_qos = 1,
1361         .amsdu_size_8K = 1,
1362         .restart_fw = 1,
1363         /* the rest are 0 by default */
1364 };
1365
1366
1367 struct iwl_cfg iwl5300_agn_cfg = {
1368         .name = "5300AGN",
1369         .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1370         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1371         .ops = &iwl5000_ops,
1372         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1373         .mod_params = &iwl50_mod_params,
1374 };
1375
1376 struct iwl_cfg iwl5100_agn_cfg = {
1377         .name = "5100AGN",
1378         .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1379         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1380         .ops = &iwl5000_ops,
1381         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1382         .mod_params = &iwl50_mod_params,
1383 };
1384
1385 struct iwl_cfg iwl5350_agn_cfg = {
1386         .name = "5350AGN",
1387         .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1388         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1389         .ops = &iwl5000_ops,
1390         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1391         .mod_params = &iwl50_mod_params,
1392 };
1393
1394 module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
1395 MODULE_PARM_DESC(disable50,
1396                   "manually disable the 50XX radio (default 0 [radio on])");
1397 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1398 MODULE_PARM_DESC(swcrypto50,
1399                   "using software crypto engine (default 0 [hardware])\n");
1400 module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
1401 MODULE_PARM_DESC(debug50, "50XX debug output mask");
1402 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1403 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1404 module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
1405 MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
1406 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1407 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1408 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1409 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");