2 * linux/arch/arm/mach-omap2/clock24xx.h
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
17 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
23 #include "prm-regbits-24xx.h"
24 #include "cm-regbits-24xx.h"
27 static void omap2_table_mpu_recalc(struct clk *clk);
28 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
29 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
30 static void omap2_sys_clk_recalc(struct clk *clk);
31 static void omap2_osc_clk_recalc(struct clk *clk);
32 static void omap2_sys_clk_recalc(struct clk *clk);
33 static void omap2_dpllcore_recalc(struct clk *clk);
34 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
36 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
37 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
38 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
41 unsigned long xtal_speed; /* crystal rate */
42 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
43 unsigned long mpu_speed; /* speed of MPU */
44 unsigned long cm_clksel_mpu; /* mpu divider */
45 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
46 unsigned long cm_clksel_gfx; /* gfx dividers */
47 unsigned long cm_clksel1_core; /* major subsystem dividers */
48 unsigned long cm_clksel1_pll; /* m,n */
49 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
50 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
51 unsigned long base_sdrc_rfr; /* base refresh timing for a set */
56 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
57 * These configurations are characterized by voltage and speed for clocks.
58 * The device is only validated for certain combinations. One way to express
59 * these combinations is via the 'ratio's' which the clocks operate with
60 * respect to each other. These ratio sets are for a given voltage/DPLL
61 * setting. All configurations can be described by a DPLL setting and a ratio
62 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
64 * 2430 differs from 2420 in that there are no more phase synchronizers used.
65 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
66 * 2430 (iva2.1, NOdsp, mdm)
69 /* Core fields for cm_clksel, not ratio governed */
70 #define RX_CLKSEL_DSS1 (0x10 << 8)
71 #define RX_CLKSEL_DSS2 (0x0 << 13)
72 #define RX_CLKSEL_SSI (0x5 << 20)
74 /*-------------------------------------------------------------------------
76 *-------------------------------------------------------------------------*/
78 /* 2430 Ratio's, 2430-Ratio Config 1 */
79 #define R1_CLKSEL_L3 (4 << 0)
80 #define R1_CLKSEL_L4 (2 << 5)
81 #define R1_CLKSEL_USB (4 << 25)
82 #define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \
83 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
84 R1_CLKSEL_L4 | R1_CLKSEL_L3
85 #define R1_CLKSEL_MPU (2 << 0)
86 #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
87 #define R1_CLKSEL_DSP (2 << 0)
88 #define R1_CLKSEL_DSP_IF (2 << 5)
89 #define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
90 #define R1_CLKSEL_GFX (2 << 0)
91 #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
92 #define R1_CLKSEL_MDM (4 << 0)
93 #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
95 /* 2430-Ratio Config 2 */
96 #define R2_CLKSEL_L3 (6 << 0)
97 #define R2_CLKSEL_L4 (2 << 5)
98 #define R2_CLKSEL_USB (2 << 25)
99 #define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \
100 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
101 R2_CLKSEL_L4 | R2_CLKSEL_L3
102 #define R2_CLKSEL_MPU (2 << 0)
103 #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
104 #define R2_CLKSEL_DSP (2 << 0)
105 #define R2_CLKSEL_DSP_IF (3 << 5)
106 #define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
107 #define R2_CLKSEL_GFX (2 << 0)
108 #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
109 #define R2_CLKSEL_MDM (6 << 0)
110 #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
112 /* 2430-Ratio Bootm (BYPASS) */
113 #define RB_CLKSEL_L3 (1 << 0)
114 #define RB_CLKSEL_L4 (1 << 5)
115 #define RB_CLKSEL_USB (1 << 25)
116 #define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \
117 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
118 RB_CLKSEL_L4 | RB_CLKSEL_L3
119 #define RB_CLKSEL_MPU (1 << 0)
120 #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
121 #define RB_CLKSEL_DSP (1 << 0)
122 #define RB_CLKSEL_DSP_IF (1 << 5)
123 #define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
124 #define RB_CLKSEL_GFX (1 << 0)
125 #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
126 #define RB_CLKSEL_MDM (1 << 0)
127 #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
129 /* 2420 Ratio Equivalents */
130 #define RXX_CLKSEL_VLYNQ (0x12 << 15)
131 #define RXX_CLKSEL_SSI (0x8 << 20)
133 /* 2420-PRCM III 532MHz core */
134 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
135 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
136 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
137 #define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
138 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
139 RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
141 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
142 #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
143 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
144 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
145 #define RIII_SYNC_DSP (1 << 7) /* Enable sync */
146 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
147 #define RIII_SYNC_IVA (1 << 13) /* Enable sync */
148 #define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
149 RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
151 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
152 #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
154 /* 2420-PRCM II 600MHz core */
155 #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
156 #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
157 #define RII_CLKSEL_USB (2 << 25) /* 50MHz */
158 #define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \
159 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
160 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
161 RII_CLKSEL_L4 | RII_CLKSEL_L3
162 #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
163 #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
164 #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
165 #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
166 #define RII_SYNC_DSP (0 << 7) /* Bypass sync */
167 #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
168 #define RII_SYNC_IVA (0 << 13) /* Bypass sync */
169 #define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \
170 RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
172 #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
173 #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
175 /* 2420-PRCM I 660MHz core */
176 #define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
177 #define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
178 #define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
179 #define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \
180 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
181 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
182 RI_CLKSEL_L4 | RI_CLKSEL_L3
183 #define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
184 #define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
185 #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
186 #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
187 #define RI_SYNC_DSP (1 << 7) /* Activate sync */
188 #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
189 #define RI_SYNC_IVA (0 << 13) /* Bypass sync */
190 #define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \
191 RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
193 #define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
194 #define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
196 /* 2420-PRCM VII (boot) */
197 #define RVII_CLKSEL_L3 (1 << 0)
198 #define RVII_CLKSEL_L4 (1 << 5)
199 #define RVII_CLKSEL_DSS1 (1 << 8)
200 #define RVII_CLKSEL_DSS2 (0 << 13)
201 #define RVII_CLKSEL_VLYNQ (1 << 15)
202 #define RVII_CLKSEL_SSI (1 << 20)
203 #define RVII_CLKSEL_USB (1 << 25)
205 #define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
206 RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
207 RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
209 #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
210 #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
212 #define RVII_CLKSEL_DSP (1 << 0)
213 #define RVII_CLKSEL_DSP_IF (1 << 5)
214 #define RVII_SYNC_DSP (0 << 7)
215 #define RVII_CLKSEL_IVA (1 << 8)
216 #define RVII_SYNC_IVA (0 << 13)
217 #define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
218 RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
220 #define RVII_CLKSEL_GFX (1 << 0)
221 #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
223 /*-------------------------------------------------------------------------
224 * 2430 Target modes: Along with each configuration the CPU has several
225 * modes which goes along with them. Modes mainly are the addition of
226 * describe DPLL combinations to go along with a ratio.
227 *-------------------------------------------------------------------------*/
229 /* Hardware governed */
230 #define MX_48M_SRC (0 << 3)
231 #define MX_54M_SRC (0 << 5)
232 #define MX_APLLS_CLIKIN_12 (3 << 23)
233 #define MX_APLLS_CLIKIN_13 (2 << 23)
234 #define MX_APLLS_CLIKIN_19_2 (0 << 23)
237 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
238 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
240 #define M5A_DPLL_MULT_12 (133 << 12)
241 #define M5A_DPLL_DIV_12 (5 << 8)
242 #define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
243 M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
245 #define M5A_DPLL_MULT_13 (61 << 12)
246 #define M5A_DPLL_DIV_13 (2 << 8)
247 #define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
248 M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
250 #define M5A_DPLL_MULT_19 (55 << 12)
251 #define M5A_DPLL_DIV_19 (3 << 8)
252 #define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
253 M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
255 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
256 #define M5B_DPLL_MULT_12 (50 << 12)
257 #define M5B_DPLL_DIV_12 (2 << 8)
258 #define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
259 M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
261 #define M5B_DPLL_MULT_13 (200 << 12)
262 #define M5B_DPLL_DIV_13 (12 << 8)
264 #define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
265 M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
267 #define M5B_DPLL_MULT_19 (125 << 12)
268 #define M5B_DPLL_DIV_19 (31 << 8)
269 #define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
270 M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
273 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
275 #define M4_DPLL_MULT_12 (133 << 12)
276 #define M4_DPLL_DIV_12 (3 << 8)
277 #define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
278 M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
281 #define M4_DPLL_MULT_13 (399 << 12)
282 #define M4_DPLL_DIV_13 (12 << 8)
283 #define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
284 M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
287 #define M4_DPLL_MULT_19 (145 << 12)
288 #define M4_DPLL_DIV_19 (6 << 8)
289 #define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
290 M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
294 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
296 #define M3_DPLL_MULT_12 (55 << 12)
297 #define M3_DPLL_DIV_12 (1 << 8)
298 #define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
299 M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
301 #define M3_DPLL_MULT_13 (76 << 12)
302 #define M3_DPLL_DIV_13 (2 << 8)
303 #define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
304 M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
306 #define M3_DPLL_MULT_19 (17 << 12)
307 #define M3_DPLL_DIV_19 (0 << 8)
308 #define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
309 M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
313 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
315 #define M2_DPLL_MULT_12 (55 << 12)
316 #define M2_DPLL_DIV_12 (1 << 8)
317 #define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
318 M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
321 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
322 * relock time issue */
323 /* Core frequency changed from 330/165 to 329/164 MHz*/
324 #define M2_DPLL_MULT_13 (76 << 12)
325 #define M2_DPLL_DIV_13 (2 << 8)
326 #define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
327 M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
330 #define M2_DPLL_MULT_19 (17 << 12)
331 #define M2_DPLL_DIV_19 (0 << 8)
332 #define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
333 M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
337 #define MB_DPLL_MULT (1 << 12)
338 #define MB_DPLL_DIV (0 << 8)
339 #define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
340 MB_DPLL_MULT | MX_APLLS_CLIKIN_12
342 #define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
343 MB_DPLL_MULT | MX_APLLS_CLIKIN_13
345 #define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
346 MB_DPLL_MULT | MX_APLLS_CLIKIN_19
349 * 2430 - chassis (sedna)
350 * 165 (ratio1) same as above #2
352 * 133 (ratio2) same as above #4
353 * 110 (ratio2) same as above #3
358 /* PRCM I target DPLL = 2*330MHz = 660MHz */
359 #define MI_DPLL_MULT_12 (55 << 12)
360 #define MI_DPLL_DIV_12 (1 << 8)
361 #define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
362 MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
366 * 2420 Equivalent - mode registers
367 * PRCM II , target DPLL = 2*300MHz = 600MHz
369 #define MII_DPLL_MULT_12 (50 << 12)
370 #define MII_DPLL_DIV_12 (1 << 8)
371 #define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
372 MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
374 #define MII_DPLL_MULT_13 (300 << 12)
375 #define MII_DPLL_DIV_13 (12 << 8)
376 #define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
377 MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
380 /* PRCM III target DPLL = 2*266 = 532MHz*/
381 #define MIII_DPLL_MULT_12 (133 << 12)
382 #define MIII_DPLL_DIV_12 (5 << 8)
383 #define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
384 MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
386 #define MIII_DPLL_MULT_13 (266 << 12)
387 #define MIII_DPLL_DIV_13 (12 << 8)
388 #define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
389 MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
392 /* PRCM VII (boot bypass) */
393 #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
394 #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
396 /* High and low operation value */
397 #define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
398 #define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
400 /* MPU speed defines */
401 #define S12M 12000000
402 #define S13M 13000000
403 #define S19M 19200000
404 #define S26M 26000000
405 #define S100M 100000000
406 #define S133M 133000000
407 #define S150M 150000000
408 #define S164M 164000000
409 #define S165M 165000000
410 #define S199M 199000000
411 #define S200M 200000000
412 #define S266M 266000000
413 #define S300M 300000000
414 #define S329M 329000000
415 #define S330M 330000000
416 #define S399M 399000000
417 #define S400M 400000000
418 #define S532M 532000000
419 #define S600M 600000000
420 #define S658M 658000000
421 #define S660M 660000000
422 #define S798M 798000000
424 /*-------------------------------------------------------------------------
425 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
426 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
427 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
428 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
430 * Filling in table based on H4 boards and 2430-SDPs variants available.
431 * There are quite a few more rates combinations which could be defined.
433 * When multiple values are defined the start up will try and choose the
434 * fastest one. If a 'fast' value is defined, then automatically, the /2
435 * one should be included as it can be used. Generally having more that
436 * one fast set does not make sense, as static timings need to be changed
437 * to change the set. The exception is the bypass setting which is
438 * availble for low power bypass.
440 * Note: This table needs to be sorted, fastest to slowest.
441 *-------------------------------------------------------------------------*/
442 static struct prcm_config rate_table[] = {
444 {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
445 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
446 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
447 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
451 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
452 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
453 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
454 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
457 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
458 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
459 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
460 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
463 /* PRCM III - FAST */
464 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
465 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
466 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
467 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
470 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
471 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
472 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
473 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
477 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
478 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
479 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
480 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
483 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
484 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
485 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
486 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
489 /* PRCM III - SLOW */
490 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
491 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
492 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
493 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
496 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
497 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
498 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
499 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
502 /* PRCM-VII (boot-bypass) */
503 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
504 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
505 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
506 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
509 /* PRCM-VII (boot-bypass) */
510 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
511 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
512 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
513 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
516 /* PRCM #4 - ratio2 (ES2.1) - FAST */
517 {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
518 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
519 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
520 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
521 SDRC_RFR_CTRL_133MHz,
524 /* PRCM #2 - ratio1 (ES2) - FAST */
525 {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
526 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
527 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
528 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
529 SDRC_RFR_CTRL_165MHz,
532 /* PRCM #5a - ratio1 - FAST */
533 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
534 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
535 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
536 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
537 SDRC_RFR_CTRL_133MHz,
540 /* PRCM #5b - ratio1 - FAST */
541 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
542 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
543 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
544 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
545 SDRC_RFR_CTRL_100MHz,
548 /* PRCM #4 - ratio1 (ES2.1) - SLOW */
549 {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
550 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
551 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
552 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
553 SDRC_RFR_CTRL_133MHz,
556 /* PRCM #2 - ratio1 (ES2) - SLOW */
557 {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
558 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
559 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
560 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
561 SDRC_RFR_CTRL_165MHz,
564 /* PRCM #5a - ratio1 - SLOW */
565 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
566 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
567 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
568 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
569 SDRC_RFR_CTRL_133MHz,
572 /* PRCM #5b - ratio1 - SLOW*/
573 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
574 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
575 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
576 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
577 SDRC_RFR_CTRL_100MHz,
580 /* PRCM-boot/bypass */
581 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
582 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
583 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
584 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
585 SDRC_RFR_CTRL_BYPASS,
588 /* PRCM-boot/bypass */
589 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
590 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
591 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
592 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
593 SDRC_RFR_CTRL_BYPASS,
596 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
599 /*-------------------------------------------------------------------------
602 * NOTE:In many cases here we are assigning a 'default' parent. In many
603 * cases the parent is selectable. The get/set parent calls will also
606 * Many some clocks say always_enabled, but they can be auto idled for
607 * power savings. They will always be available upon clock request.
609 * Several sources are given initial rates which may be wrong, this will
610 * be fixed up in the init func.
612 * Things are broadly separated below by clock domains. It is
613 * noteworthy that most periferals have dependencies on multiple clock
614 * domains. Many get their interface clocks from the L4 domain, but get
615 * functional clocks from fixed sources or other core domain derived
617 *-------------------------------------------------------------------------*/
619 /* Base external input clocks */
620 static struct clk func_32k_ck = {
621 .name = "func_32k_ck",
624 .flags = RATE_FIXED | RATE_PROPAGATES,
625 .clkdm_name = "wkup_clkdm",
628 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
629 static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
631 .ops = &clkops_oscck,
632 .flags = RATE_PROPAGATES,
633 .clkdm_name = "wkup_clkdm",
634 .recalc = &omap2_osc_clk_recalc,
637 /* Without modem likely 12MHz, with modem likely 13MHz */
638 static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
639 .name = "sys_ck", /* ~ ref_clk also */
642 .flags = RATE_PROPAGATES,
643 .clkdm_name = "wkup_clkdm",
644 .recalc = &omap2_sys_clk_recalc,
647 static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
651 .flags = RATE_FIXED | RATE_PROPAGATES,
652 .clkdm_name = "wkup_clkdm",
656 * Analog domain root source clocks
659 /* dpll_ck, is broken out in to special cases through clksel */
660 /* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
664 static struct dpll_data dpll_dd = {
665 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
666 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
667 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
668 .max_multiplier = 1024,
670 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
674 * XXX Cannot add round_rate here yet, as this is still a composite clock,
677 static struct clk dpll_ck = {
680 .parent = &sys_ck, /* Can be func_32k also */
681 .dpll_data = &dpll_dd,
682 .flags = RATE_PROPAGATES,
683 .clkdm_name = "wkup_clkdm",
684 .recalc = &omap2_dpllcore_recalc,
685 .set_rate = &omap2_reprogram_dpllcore,
688 static struct clk apll96_ck = {
690 .ops = &clkops_fixed,
693 .flags = RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
694 .clkdm_name = "wkup_clkdm",
695 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
696 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
699 static struct clk apll54_ck = {
701 .ops = &clkops_fixed,
704 .flags = RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
705 .clkdm_name = "wkup_clkdm",
706 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
707 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
711 * PRCM digital base sources
716 static const struct clksel_rate func_54m_apll54_rates[] = {
717 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
721 static const struct clksel_rate func_54m_alt_rates[] = {
722 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
726 static const struct clksel func_54m_clksel[] = {
727 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
728 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
732 static struct clk func_54m_ck = {
733 .name = "func_54m_ck",
735 .parent = &apll54_ck, /* can also be alt_clk */
736 .flags = RATE_PROPAGATES,
737 .clkdm_name = "wkup_clkdm",
738 .init = &omap2_init_clksel_parent,
739 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
740 .clksel_mask = OMAP24XX_54M_SOURCE,
741 .clksel = func_54m_clksel,
742 .recalc = &omap2_clksel_recalc,
745 static struct clk core_ck = {
748 .parent = &dpll_ck, /* can also be 32k */
749 .flags = RATE_PROPAGATES,
750 .clkdm_name = "wkup_clkdm",
751 .recalc = &followparent_recalc,
755 static const struct clksel_rate func_96m_apll96_rates[] = {
756 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
760 static const struct clksel_rate func_96m_alt_rates[] = {
761 { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
765 static const struct clksel func_96m_clksel[] = {
766 { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
767 { .parent = &alt_ck, .rates = func_96m_alt_rates },
771 /* The parent of this clock is not selectable on 2420. */
772 static struct clk func_96m_ck = {
773 .name = "func_96m_ck",
775 .parent = &apll96_ck,
776 .flags = RATE_PROPAGATES,
777 .clkdm_name = "wkup_clkdm",
778 .init = &omap2_init_clksel_parent,
779 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
780 .clksel_mask = OMAP2430_96M_SOURCE,
781 .clksel = func_96m_clksel,
782 .recalc = &omap2_clksel_recalc,
783 .round_rate = &omap2_clksel_round_rate,
784 .set_rate = &omap2_clksel_set_rate
789 static const struct clksel_rate func_48m_apll96_rates[] = {
790 { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
794 static const struct clksel_rate func_48m_alt_rates[] = {
795 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
799 static const struct clksel func_48m_clksel[] = {
800 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
801 { .parent = &alt_ck, .rates = func_48m_alt_rates },
805 static struct clk func_48m_ck = {
806 .name = "func_48m_ck",
808 .parent = &apll96_ck, /* 96M or Alt */
809 .flags = RATE_PROPAGATES,
810 .clkdm_name = "wkup_clkdm",
811 .init = &omap2_init_clksel_parent,
812 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
813 .clksel_mask = OMAP24XX_48M_SOURCE,
814 .clksel = func_48m_clksel,
815 .recalc = &omap2_clksel_recalc,
816 .round_rate = &omap2_clksel_round_rate,
817 .set_rate = &omap2_clksel_set_rate
820 static struct clk func_12m_ck = {
821 .name = "func_12m_ck",
823 .parent = &func_48m_ck,
825 .flags = RATE_PROPAGATES,
826 .clkdm_name = "wkup_clkdm",
827 .recalc = &omap2_fixed_divisor_recalc,
830 /* Secure timer, only available in secure mode */
831 static struct clk wdt1_osc_ck = {
832 .name = "ck_wdt1_osc",
833 .ops = &clkops_null, /* RMK: missing? */
835 .recalc = &followparent_recalc,
839 * The common_clkout* clksel_rate structs are common to
840 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
841 * sys_clkout2_* are 2420-only, so the
842 * clksel_rate flags fields are inaccurate for those clocks. This is
843 * harmless since access to those clocks are gated by the struct clk
844 * flags fields, which mark them as 2420-only.
846 static const struct clksel_rate common_clkout_src_core_rates[] = {
847 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
851 static const struct clksel_rate common_clkout_src_sys_rates[] = {
852 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
856 static const struct clksel_rate common_clkout_src_96m_rates[] = {
857 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
861 static const struct clksel_rate common_clkout_src_54m_rates[] = {
862 { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
866 static const struct clksel common_clkout_src_clksel[] = {
867 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
868 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
869 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
870 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
874 static struct clk sys_clkout_src = {
875 .name = "sys_clkout_src",
876 .ops = &clkops_omap2_dflt,
877 .parent = &func_54m_ck,
878 .flags = RATE_PROPAGATES,
879 .clkdm_name = "wkup_clkdm",
880 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
881 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
882 .init = &omap2_init_clksel_parent,
883 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
884 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
885 .clksel = common_clkout_src_clksel,
886 .recalc = &omap2_clksel_recalc,
887 .round_rate = &omap2_clksel_round_rate,
888 .set_rate = &omap2_clksel_set_rate
891 static const struct clksel_rate common_clkout_rates[] = {
892 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
893 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
894 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
895 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
896 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
900 static const struct clksel sys_clkout_clksel[] = {
901 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
905 static struct clk sys_clkout = {
906 .name = "sys_clkout",
908 .parent = &sys_clkout_src,
909 .clkdm_name = "wkup_clkdm",
910 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
911 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
912 .clksel = sys_clkout_clksel,
913 .recalc = &omap2_clksel_recalc,
914 .round_rate = &omap2_clksel_round_rate,
915 .set_rate = &omap2_clksel_set_rate
918 /* In 2430, new in 2420 ES2 */
919 static struct clk sys_clkout2_src = {
920 .name = "sys_clkout2_src",
921 .ops = &clkops_omap2_dflt,
922 .parent = &func_54m_ck,
923 .flags = RATE_PROPAGATES,
924 .clkdm_name = "wkup_clkdm",
925 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
926 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
927 .init = &omap2_init_clksel_parent,
928 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
929 .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
930 .clksel = common_clkout_src_clksel,
931 .recalc = &omap2_clksel_recalc,
932 .round_rate = &omap2_clksel_round_rate,
933 .set_rate = &omap2_clksel_set_rate
936 static const struct clksel sys_clkout2_clksel[] = {
937 { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
941 /* In 2430, new in 2420 ES2 */
942 static struct clk sys_clkout2 = {
943 .name = "sys_clkout2",
945 .parent = &sys_clkout2_src,
946 .clkdm_name = "wkup_clkdm",
947 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
948 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
949 .clksel = sys_clkout2_clksel,
950 .recalc = &omap2_clksel_recalc,
951 .round_rate = &omap2_clksel_round_rate,
952 .set_rate = &omap2_clksel_set_rate
955 static struct clk emul_ck = {
957 .ops = &clkops_omap2_dflt,
958 .parent = &func_54m_ck,
959 .clkdm_name = "wkup_clkdm",
960 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
961 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
962 .recalc = &followparent_recalc,
970 * INT_M_FCLK, INT_M_I_CLK
972 * - Individual clocks are hardware managed.
973 * - Base divider comes from: CM_CLKSEL_MPU
976 static const struct clksel_rate mpu_core_rates[] = {
977 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
978 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
979 { .div = 4, .val = 4, .flags = RATE_IN_242X },
980 { .div = 6, .val = 6, .flags = RATE_IN_242X },
981 { .div = 8, .val = 8, .flags = RATE_IN_242X },
985 static const struct clksel mpu_clksel[] = {
986 { .parent = &core_ck, .rates = mpu_core_rates },
990 static struct clk mpu_ck = { /* Control cpu */
994 .flags = DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
995 .clkdm_name = "mpu_clkdm",
996 .init = &omap2_init_clksel_parent,
997 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
998 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
999 .clksel = mpu_clksel,
1000 .recalc = &omap2_clksel_recalc,
1001 .round_rate = &omap2_clksel_round_rate,
1002 .set_rate = &omap2_clksel_set_rate
1006 * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
1008 * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1009 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1011 * Won't be too specific here. The core clock comes into this block
1012 * it is divided then tee'ed. One branch goes directly to xyz enable
1013 * controls. The other branch gets further divided by 2 then possibly
1014 * routed into a synchronizer and out of clocks abc.
1016 static const struct clksel_rate dsp_fck_core_rates[] = {
1017 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1018 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1019 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1020 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1021 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1022 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1023 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1027 static const struct clksel dsp_fck_clksel[] = {
1028 { .parent = &core_ck, .rates = dsp_fck_core_rates },
1032 static struct clk dsp_fck = {
1034 .ops = &clkops_omap2_dflt_wait,
1036 .flags = DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
1037 .clkdm_name = "dsp_clkdm",
1038 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1039 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1040 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1041 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
1042 .clksel = dsp_fck_clksel,
1043 .recalc = &omap2_clksel_recalc,
1044 .round_rate = &omap2_clksel_round_rate,
1045 .set_rate = &omap2_clksel_set_rate
1048 /* DSP interface clock */
1049 static const struct clksel_rate dsp_irate_ick_rates[] = {
1050 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1051 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1052 { .div = 3, .val = 3, .flags = RATE_IN_243X },
1056 static const struct clksel dsp_irate_ick_clksel[] = {
1057 { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1061 /* This clock does not exist as such in the TRM. */
1062 static struct clk dsp_irate_ick = {
1063 .name = "dsp_irate_ick",
1064 .ops = &clkops_null,
1066 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1067 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1068 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
1069 .clksel = dsp_irate_ick_clksel,
1070 .recalc = &omap2_clksel_recalc,
1071 .round_rate = &omap2_clksel_round_rate,
1072 .set_rate = &omap2_clksel_set_rate
1076 static struct clk dsp_ick = {
1077 .name = "dsp_ick", /* apparently ipi and isp */
1078 .ops = &clkops_omap2_dflt_wait,
1079 .parent = &dsp_irate_ick,
1080 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1081 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1082 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
1085 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1086 static struct clk iva2_1_ick = {
1087 .name = "iva2_1_ick",
1088 .ops = &clkops_omap2_dflt_wait,
1089 .parent = &dsp_irate_ick,
1090 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1091 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1092 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1096 * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1097 * the C54x, but which is contained in the DSP powerdomain. Does not
1098 * exist on later OMAPs.
1100 static struct clk iva1_ifck = {
1101 .name = "iva1_ifck",
1102 .ops = &clkops_omap2_dflt_wait,
1104 .flags = CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
1105 .clkdm_name = "iva1_clkdm",
1106 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1107 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
1108 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1109 .clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
1110 .clksel = dsp_fck_clksel,
1111 .recalc = &omap2_clksel_recalc,
1112 .round_rate = &omap2_clksel_round_rate,
1113 .set_rate = &omap2_clksel_set_rate
1116 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1117 static struct clk iva1_mpu_int_ifck = {
1118 .name = "iva1_mpu_int_ifck",
1119 .ops = &clkops_omap2_dflt_wait,
1120 .parent = &iva1_ifck,
1121 .clkdm_name = "iva1_clkdm",
1122 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1123 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
1125 .recalc = &omap2_fixed_divisor_recalc,
1130 * L3 clocks are used for both interface and functional clocks to
1131 * multiple entities. Some of these clocks are completely managed
1132 * by hardware, and some others allow software control. Hardware
1133 * managed ones general are based on directly CLK_REQ signals and
1134 * various auto idle settings. The functional spec sets many of these
1135 * as 'tie-high' for their enables.
1138 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1143 * GPMC memories and SDRC have timing and clock sensitive registers which
1144 * may very well need notification when the clock changes. Currently for low
1145 * operating points, these are taken care of in sleep.S.
1147 static const struct clksel_rate core_l3_core_rates[] = {
1148 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1149 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1150 { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1151 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1152 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1153 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1154 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1158 static const struct clksel core_l3_clksel[] = {
1159 { .parent = &core_ck, .rates = core_l3_core_rates },
1163 static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
1164 .name = "core_l3_ck",
1165 .ops = &clkops_null,
1167 .flags = DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
1168 .clkdm_name = "core_l3_clkdm",
1169 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1170 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
1171 .clksel = core_l3_clksel,
1172 .recalc = &omap2_clksel_recalc,
1173 .round_rate = &omap2_clksel_round_rate,
1174 .set_rate = &omap2_clksel_set_rate
1178 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1179 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1180 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1181 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1185 static const struct clksel usb_l4_ick_clksel[] = {
1186 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1190 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1191 static struct clk usb_l4_ick = { /* FS-USB interface clock */
1192 .name = "usb_l4_ick",
1193 .ops = &clkops_omap2_dflt_wait,
1194 .parent = &core_l3_ck,
1195 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1196 .clkdm_name = "core_l4_clkdm",
1197 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1198 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1199 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1200 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
1201 .clksel = usb_l4_ick_clksel,
1202 .recalc = &omap2_clksel_recalc,
1203 .round_rate = &omap2_clksel_round_rate,
1204 .set_rate = &omap2_clksel_set_rate
1208 * L4 clock management domain
1210 * This domain contains lots of interface clocks from the L4 interface, some
1211 * functional clocks. Fixed APLL functional source clocks are managed in
1214 static const struct clksel_rate l4_core_l3_rates[] = {
1215 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1216 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1220 static const struct clksel l4_clksel[] = {
1221 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1225 static struct clk l4_ck = { /* used both as an ick and fck */
1227 .ops = &clkops_null,
1228 .parent = &core_l3_ck,
1229 .flags = DELAYED_APP | RATE_PROPAGATES,
1230 .clkdm_name = "core_l4_clkdm",
1231 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1232 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
1233 .clksel = l4_clksel,
1234 .recalc = &omap2_clksel_recalc,
1235 .round_rate = &omap2_clksel_round_rate,
1236 .set_rate = &omap2_clksel_set_rate
1240 * SSI is in L3 management domain, its direct parent is core not l3,
1241 * many core power domain entities are grouped into the L3 clock
1243 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
1245 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1247 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1248 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1249 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1250 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1251 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1252 { .div = 5, .val = 5, .flags = RATE_IN_243X },
1253 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1254 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1258 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1259 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1263 static struct clk ssi_ssr_sst_fck = {
1265 .ops = &clkops_omap2_dflt_wait,
1267 .flags = DELAYED_APP,
1268 .clkdm_name = "core_l3_clkdm",
1269 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1270 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1271 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1272 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
1273 .clksel = ssi_ssr_sst_fck_clksel,
1274 .recalc = &omap2_clksel_recalc,
1275 .round_rate = &omap2_clksel_round_rate,
1276 .set_rate = &omap2_clksel_set_rate
1280 * Presumably this is the same as SSI_ICLK.
1281 * TRM contradicts itself on what clockdomain SSI_ICLK is in
1283 static struct clk ssi_l4_ick = {
1284 .name = "ssi_l4_ick",
1285 .ops = &clkops_omap2_dflt_wait,
1287 .clkdm_name = "core_l4_clkdm",
1288 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1289 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1290 .recalc = &followparent_recalc,
1297 * GFX_FCLK, GFX_ICLK
1298 * GFX_CG1(2d), GFX_CG2(3d)
1300 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1301 * The 2d and 3d clocks run at a hardware determined
1302 * divided value of fclk.
1305 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1307 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1308 static const struct clksel gfx_fck_clksel[] = {
1309 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1313 static struct clk gfx_3d_fck = {
1314 .name = "gfx_3d_fck",
1315 .ops = &clkops_omap2_dflt_wait,
1316 .parent = &core_l3_ck,
1317 .clkdm_name = "gfx_clkdm",
1318 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1319 .enable_bit = OMAP24XX_EN_3D_SHIFT,
1320 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1321 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1322 .clksel = gfx_fck_clksel,
1323 .recalc = &omap2_clksel_recalc,
1324 .round_rate = &omap2_clksel_round_rate,
1325 .set_rate = &omap2_clksel_set_rate
1328 static struct clk gfx_2d_fck = {
1329 .name = "gfx_2d_fck",
1330 .ops = &clkops_omap2_dflt_wait,
1331 .parent = &core_l3_ck,
1332 .clkdm_name = "gfx_clkdm",
1333 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1334 .enable_bit = OMAP24XX_EN_2D_SHIFT,
1335 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1336 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1337 .clksel = gfx_fck_clksel,
1338 .recalc = &omap2_clksel_recalc,
1339 .round_rate = &omap2_clksel_round_rate,
1340 .set_rate = &omap2_clksel_set_rate
1343 static struct clk gfx_ick = {
1344 .name = "gfx_ick", /* From l3 */
1345 .ops = &clkops_omap2_dflt_wait,
1346 .parent = &core_l3_ck,
1347 .clkdm_name = "gfx_clkdm",
1348 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1349 .enable_bit = OMAP_EN_GFX_SHIFT,
1350 .recalc = &followparent_recalc,
1354 * Modem clock domain (2430)
1358 * These clocks are usable in chassis mode only.
1360 static const struct clksel_rate mdm_ick_core_rates[] = {
1361 { .div = 1, .val = 1, .flags = RATE_IN_243X },
1362 { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1363 { .div = 6, .val = 6, .flags = RATE_IN_243X },
1364 { .div = 9, .val = 9, .flags = RATE_IN_243X },
1368 static const struct clksel mdm_ick_clksel[] = {
1369 { .parent = &core_ck, .rates = mdm_ick_core_rates },
1373 static struct clk mdm_ick = { /* used both as a ick and fck */
1375 .ops = &clkops_omap2_dflt_wait,
1377 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1378 .clkdm_name = "mdm_clkdm",
1379 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1380 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1381 .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1382 .clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
1383 .clksel = mdm_ick_clksel,
1384 .recalc = &omap2_clksel_recalc,
1385 .round_rate = &omap2_clksel_round_rate,
1386 .set_rate = &omap2_clksel_set_rate
1389 static struct clk mdm_osc_ck = {
1390 .name = "mdm_osc_ck",
1391 .ops = &clkops_omap2_dflt_wait,
1393 .clkdm_name = "mdm_clkdm",
1394 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1395 .enable_bit = OMAP2430_EN_OSC_SHIFT,
1396 .recalc = &followparent_recalc,
1402 * DSS_L4_ICLK, DSS_L3_ICLK,
1403 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1405 * DSS is both initiator and target.
1407 /* XXX Add RATE_NOT_VALIDATED */
1409 static const struct clksel_rate dss1_fck_sys_rates[] = {
1410 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1414 static const struct clksel_rate dss1_fck_core_rates[] = {
1415 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1416 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1417 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1418 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1419 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1420 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1421 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1422 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1423 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1424 { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1428 static const struct clksel dss1_fck_clksel[] = {
1429 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
1430 { .parent = &core_ck, .rates = dss1_fck_core_rates },
1434 static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1436 .ops = &clkops_omap2_dflt,
1437 .parent = &l4_ck, /* really both l3 and l4 */
1438 .clkdm_name = "dss_clkdm",
1439 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1440 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1441 .recalc = &followparent_recalc,
1444 static struct clk dss1_fck = {
1446 .ops = &clkops_omap2_dflt,
1447 .parent = &core_ck, /* Core or sys */
1448 .flags = DELAYED_APP,
1449 .clkdm_name = "dss_clkdm",
1450 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1451 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1452 .init = &omap2_init_clksel_parent,
1453 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1454 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
1455 .clksel = dss1_fck_clksel,
1456 .recalc = &omap2_clksel_recalc,
1457 .round_rate = &omap2_clksel_round_rate,
1458 .set_rate = &omap2_clksel_set_rate
1461 static const struct clksel_rate dss2_fck_sys_rates[] = {
1462 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1466 static const struct clksel_rate dss2_fck_48m_rates[] = {
1467 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1471 static const struct clksel dss2_fck_clksel[] = {
1472 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
1473 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1477 static struct clk dss2_fck = { /* Alt clk used in power management */
1479 .ops = &clkops_omap2_dflt,
1480 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1481 .flags = DELAYED_APP,
1482 .clkdm_name = "dss_clkdm",
1483 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1484 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
1485 .init = &omap2_init_clksel_parent,
1486 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1487 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
1488 .clksel = dss2_fck_clksel,
1489 .recalc = &followparent_recalc,
1492 static struct clk dss_54m_fck = { /* Alt clk used in power management */
1493 .name = "dss_54m_fck", /* 54m tv clk */
1494 .ops = &clkops_omap2_dflt_wait,
1495 .parent = &func_54m_ck,
1496 .clkdm_name = "dss_clkdm",
1497 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1498 .enable_bit = OMAP24XX_EN_TV_SHIFT,
1499 .recalc = &followparent_recalc,
1503 * CORE power domain ICLK & FCLK defines.
1504 * Many of the these can have more than one possible parent. Entries
1505 * here will likely have an L4 interface parent, and may have multiple
1506 * functional clock parents.
1508 static const struct clksel_rate gpt_alt_rates[] = {
1509 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1513 static const struct clksel omap24xx_gpt_clksel[] = {
1514 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1515 { .parent = &sys_ck, .rates = gpt_sys_rates },
1516 { .parent = &alt_ck, .rates = gpt_alt_rates },
1520 static struct clk gpt1_ick = {
1522 .ops = &clkops_omap2_dflt_wait,
1524 .clkdm_name = "core_l4_clkdm",
1525 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1526 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1527 .recalc = &followparent_recalc,
1530 static struct clk gpt1_fck = {
1532 .ops = &clkops_omap2_dflt_wait,
1533 .parent = &func_32k_ck,
1534 .clkdm_name = "core_l4_clkdm",
1535 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1536 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1537 .init = &omap2_init_clksel_parent,
1538 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
1539 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
1540 .clksel = omap24xx_gpt_clksel,
1541 .recalc = &omap2_clksel_recalc,
1542 .round_rate = &omap2_clksel_round_rate,
1543 .set_rate = &omap2_clksel_set_rate
1546 static struct clk gpt2_ick = {
1548 .ops = &clkops_omap2_dflt_wait,
1550 .clkdm_name = "core_l4_clkdm",
1551 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1552 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1553 .recalc = &followparent_recalc,
1556 static struct clk gpt2_fck = {
1558 .ops = &clkops_omap2_dflt_wait,
1559 .parent = &func_32k_ck,
1560 .clkdm_name = "core_l4_clkdm",
1561 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1562 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1563 .init = &omap2_init_clksel_parent,
1564 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1565 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
1566 .clksel = omap24xx_gpt_clksel,
1567 .recalc = &omap2_clksel_recalc,
1570 static struct clk gpt3_ick = {
1572 .ops = &clkops_omap2_dflt_wait,
1574 .clkdm_name = "core_l4_clkdm",
1575 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1576 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1577 .recalc = &followparent_recalc,
1580 static struct clk gpt3_fck = {
1582 .ops = &clkops_omap2_dflt_wait,
1583 .parent = &func_32k_ck,
1584 .clkdm_name = "core_l4_clkdm",
1585 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1586 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1587 .init = &omap2_init_clksel_parent,
1588 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1589 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
1590 .clksel = omap24xx_gpt_clksel,
1591 .recalc = &omap2_clksel_recalc,
1594 static struct clk gpt4_ick = {
1596 .ops = &clkops_omap2_dflt_wait,
1598 .clkdm_name = "core_l4_clkdm",
1599 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1600 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1601 .recalc = &followparent_recalc,
1604 static struct clk gpt4_fck = {
1606 .ops = &clkops_omap2_dflt_wait,
1607 .parent = &func_32k_ck,
1608 .clkdm_name = "core_l4_clkdm",
1609 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1610 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1611 .init = &omap2_init_clksel_parent,
1612 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1613 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
1614 .clksel = omap24xx_gpt_clksel,
1615 .recalc = &omap2_clksel_recalc,
1618 static struct clk gpt5_ick = {
1620 .ops = &clkops_omap2_dflt_wait,
1622 .clkdm_name = "core_l4_clkdm",
1623 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1624 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1625 .recalc = &followparent_recalc,
1628 static struct clk gpt5_fck = {
1630 .ops = &clkops_omap2_dflt_wait,
1631 .parent = &func_32k_ck,
1632 .clkdm_name = "core_l4_clkdm",
1633 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1634 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1635 .init = &omap2_init_clksel_parent,
1636 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1637 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
1638 .clksel = omap24xx_gpt_clksel,
1639 .recalc = &omap2_clksel_recalc,
1642 static struct clk gpt6_ick = {
1644 .ops = &clkops_omap2_dflt_wait,
1646 .clkdm_name = "core_l4_clkdm",
1647 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1648 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1649 .recalc = &followparent_recalc,
1652 static struct clk gpt6_fck = {
1654 .ops = &clkops_omap2_dflt_wait,
1655 .parent = &func_32k_ck,
1656 .clkdm_name = "core_l4_clkdm",
1657 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1658 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1659 .init = &omap2_init_clksel_parent,
1660 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1661 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
1662 .clksel = omap24xx_gpt_clksel,
1663 .recalc = &omap2_clksel_recalc,
1666 static struct clk gpt7_ick = {
1668 .ops = &clkops_omap2_dflt_wait,
1670 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1671 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1672 .recalc = &followparent_recalc,
1675 static struct clk gpt7_fck = {
1677 .ops = &clkops_omap2_dflt_wait,
1678 .parent = &func_32k_ck,
1679 .clkdm_name = "core_l4_clkdm",
1680 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1681 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1682 .init = &omap2_init_clksel_parent,
1683 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1684 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
1685 .clksel = omap24xx_gpt_clksel,
1686 .recalc = &omap2_clksel_recalc,
1689 static struct clk gpt8_ick = {
1691 .ops = &clkops_omap2_dflt_wait,
1693 .clkdm_name = "core_l4_clkdm",
1694 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1695 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1696 .recalc = &followparent_recalc,
1699 static struct clk gpt8_fck = {
1701 .ops = &clkops_omap2_dflt_wait,
1702 .parent = &func_32k_ck,
1703 .clkdm_name = "core_l4_clkdm",
1704 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1705 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1706 .init = &omap2_init_clksel_parent,
1707 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1708 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1709 .clksel = omap24xx_gpt_clksel,
1710 .recalc = &omap2_clksel_recalc,
1713 static struct clk gpt9_ick = {
1715 .ops = &clkops_omap2_dflt_wait,
1717 .clkdm_name = "core_l4_clkdm",
1718 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1719 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1720 .recalc = &followparent_recalc,
1723 static struct clk gpt9_fck = {
1725 .ops = &clkops_omap2_dflt_wait,
1726 .parent = &func_32k_ck,
1727 .clkdm_name = "core_l4_clkdm",
1728 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1729 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1730 .init = &omap2_init_clksel_parent,
1731 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1732 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1733 .clksel = omap24xx_gpt_clksel,
1734 .recalc = &omap2_clksel_recalc,
1737 static struct clk gpt10_ick = {
1738 .name = "gpt10_ick",
1739 .ops = &clkops_omap2_dflt_wait,
1741 .clkdm_name = "core_l4_clkdm",
1742 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1743 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1744 .recalc = &followparent_recalc,
1747 static struct clk gpt10_fck = {
1748 .name = "gpt10_fck",
1749 .ops = &clkops_omap2_dflt_wait,
1750 .parent = &func_32k_ck,
1751 .clkdm_name = "core_l4_clkdm",
1752 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1753 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1754 .init = &omap2_init_clksel_parent,
1755 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1756 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1757 .clksel = omap24xx_gpt_clksel,
1758 .recalc = &omap2_clksel_recalc,
1761 static struct clk gpt11_ick = {
1762 .name = "gpt11_ick",
1763 .ops = &clkops_omap2_dflt_wait,
1765 .clkdm_name = "core_l4_clkdm",
1766 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1767 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1768 .recalc = &followparent_recalc,
1771 static struct clk gpt11_fck = {
1772 .name = "gpt11_fck",
1773 .ops = &clkops_omap2_dflt_wait,
1774 .parent = &func_32k_ck,
1775 .clkdm_name = "core_l4_clkdm",
1776 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1777 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1778 .init = &omap2_init_clksel_parent,
1779 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1780 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1781 .clksel = omap24xx_gpt_clksel,
1782 .recalc = &omap2_clksel_recalc,
1785 static struct clk gpt12_ick = {
1786 .name = "gpt12_ick",
1787 .ops = &clkops_omap2_dflt_wait,
1789 .clkdm_name = "core_l4_clkdm",
1790 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1791 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1792 .recalc = &followparent_recalc,
1795 static struct clk gpt12_fck = {
1796 .name = "gpt12_fck",
1797 .ops = &clkops_omap2_dflt_wait,
1798 .parent = &func_32k_ck,
1799 .clkdm_name = "core_l4_clkdm",
1800 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1801 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1802 .init = &omap2_init_clksel_parent,
1803 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1804 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1805 .clksel = omap24xx_gpt_clksel,
1806 .recalc = &omap2_clksel_recalc,
1809 static struct clk mcbsp1_ick = {
1810 .name = "mcbsp_ick",
1811 .ops = &clkops_omap2_dflt_wait,
1814 .clkdm_name = "core_l4_clkdm",
1815 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1816 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1817 .recalc = &followparent_recalc,
1820 static struct clk mcbsp1_fck = {
1821 .name = "mcbsp_fck",
1822 .ops = &clkops_omap2_dflt_wait,
1824 .parent = &func_96m_ck,
1825 .clkdm_name = "core_l4_clkdm",
1826 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1827 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1828 .recalc = &followparent_recalc,
1831 static struct clk mcbsp2_ick = {
1832 .name = "mcbsp_ick",
1833 .ops = &clkops_omap2_dflt_wait,
1836 .clkdm_name = "core_l4_clkdm",
1837 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1838 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1839 .recalc = &followparent_recalc,
1842 static struct clk mcbsp2_fck = {
1843 .name = "mcbsp_fck",
1844 .ops = &clkops_omap2_dflt_wait,
1846 .parent = &func_96m_ck,
1847 .clkdm_name = "core_l4_clkdm",
1848 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1849 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1850 .recalc = &followparent_recalc,
1853 static struct clk mcbsp3_ick = {
1854 .name = "mcbsp_ick",
1855 .ops = &clkops_omap2_dflt_wait,
1858 .clkdm_name = "core_l4_clkdm",
1859 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1860 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1861 .recalc = &followparent_recalc,
1864 static struct clk mcbsp3_fck = {
1865 .name = "mcbsp_fck",
1866 .ops = &clkops_omap2_dflt_wait,
1868 .parent = &func_96m_ck,
1869 .clkdm_name = "core_l4_clkdm",
1870 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1871 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1872 .recalc = &followparent_recalc,
1875 static struct clk mcbsp4_ick = {
1876 .name = "mcbsp_ick",
1877 .ops = &clkops_omap2_dflt_wait,
1880 .clkdm_name = "core_l4_clkdm",
1881 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1882 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1883 .recalc = &followparent_recalc,
1886 static struct clk mcbsp4_fck = {
1887 .name = "mcbsp_fck",
1888 .ops = &clkops_omap2_dflt_wait,
1890 .parent = &func_96m_ck,
1891 .clkdm_name = "core_l4_clkdm",
1892 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1893 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1894 .recalc = &followparent_recalc,
1897 static struct clk mcbsp5_ick = {
1898 .name = "mcbsp_ick",
1899 .ops = &clkops_omap2_dflt_wait,
1902 .clkdm_name = "core_l4_clkdm",
1903 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1904 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1905 .recalc = &followparent_recalc,
1908 static struct clk mcbsp5_fck = {
1909 .name = "mcbsp_fck",
1910 .ops = &clkops_omap2_dflt_wait,
1912 .parent = &func_96m_ck,
1913 .clkdm_name = "core_l4_clkdm",
1914 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1915 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1916 .recalc = &followparent_recalc,
1919 static struct clk mcspi1_ick = {
1920 .name = "mcspi_ick",
1921 .ops = &clkops_omap2_dflt_wait,
1924 .clkdm_name = "core_l4_clkdm",
1925 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1926 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1927 .recalc = &followparent_recalc,
1930 static struct clk mcspi1_fck = {
1931 .name = "mcspi_fck",
1932 .ops = &clkops_omap2_dflt_wait,
1934 .parent = &func_48m_ck,
1935 .clkdm_name = "core_l4_clkdm",
1936 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1937 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1938 .recalc = &followparent_recalc,
1941 static struct clk mcspi2_ick = {
1942 .name = "mcspi_ick",
1943 .ops = &clkops_omap2_dflt_wait,
1946 .clkdm_name = "core_l4_clkdm",
1947 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1948 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1949 .recalc = &followparent_recalc,
1952 static struct clk mcspi2_fck = {
1953 .name = "mcspi_fck",
1954 .ops = &clkops_omap2_dflt_wait,
1956 .parent = &func_48m_ck,
1957 .clkdm_name = "core_l4_clkdm",
1958 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1959 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1960 .recalc = &followparent_recalc,
1963 static struct clk mcspi3_ick = {
1964 .name = "mcspi_ick",
1965 .ops = &clkops_omap2_dflt_wait,
1968 .clkdm_name = "core_l4_clkdm",
1969 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1970 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1971 .recalc = &followparent_recalc,
1974 static struct clk mcspi3_fck = {
1975 .name = "mcspi_fck",
1976 .ops = &clkops_omap2_dflt_wait,
1978 .parent = &func_48m_ck,
1979 .clkdm_name = "core_l4_clkdm",
1980 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1981 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1982 .recalc = &followparent_recalc,
1985 static struct clk uart1_ick = {
1986 .name = "uart1_ick",
1987 .ops = &clkops_omap2_dflt_wait,
1989 .clkdm_name = "core_l4_clkdm",
1990 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1991 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1992 .recalc = &followparent_recalc,
1995 static struct clk uart1_fck = {
1996 .name = "uart1_fck",
1997 .ops = &clkops_omap2_dflt_wait,
1998 .parent = &func_48m_ck,
1999 .clkdm_name = "core_l4_clkdm",
2000 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2001 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
2002 .recalc = &followparent_recalc,
2005 static struct clk uart2_ick = {
2006 .name = "uart2_ick",
2007 .ops = &clkops_omap2_dflt_wait,
2009 .clkdm_name = "core_l4_clkdm",
2010 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2011 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
2012 .recalc = &followparent_recalc,
2015 static struct clk uart2_fck = {
2016 .name = "uart2_fck",
2017 .ops = &clkops_omap2_dflt_wait,
2018 .parent = &func_48m_ck,
2019 .clkdm_name = "core_l4_clkdm",
2020 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2021 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
2022 .recalc = &followparent_recalc,
2025 static struct clk uart3_ick = {
2026 .name = "uart3_ick",
2027 .ops = &clkops_omap2_dflt_wait,
2029 .clkdm_name = "core_l4_clkdm",
2030 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2031 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
2032 .recalc = &followparent_recalc,
2035 static struct clk uart3_fck = {
2036 .name = "uart3_fck",
2037 .ops = &clkops_omap2_dflt_wait,
2038 .parent = &func_48m_ck,
2039 .clkdm_name = "core_l4_clkdm",
2040 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2041 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
2042 .recalc = &followparent_recalc,
2045 static struct clk gpios_ick = {
2046 .name = "gpios_ick",
2047 .ops = &clkops_omap2_dflt_wait,
2049 .clkdm_name = "core_l4_clkdm",
2050 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2051 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
2052 .recalc = &followparent_recalc,
2055 static struct clk gpios_fck = {
2056 .name = "gpios_fck",
2057 .ops = &clkops_omap2_dflt_wait,
2058 .parent = &func_32k_ck,
2059 .clkdm_name = "wkup_clkdm",
2060 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2061 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
2062 .recalc = &followparent_recalc,
2065 static struct clk mpu_wdt_ick = {
2066 .name = "mpu_wdt_ick",
2067 .ops = &clkops_omap2_dflt_wait,
2069 .clkdm_name = "core_l4_clkdm",
2070 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2071 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
2072 .recalc = &followparent_recalc,
2075 static struct clk mpu_wdt_fck = {
2076 .name = "mpu_wdt_fck",
2077 .ops = &clkops_omap2_dflt_wait,
2078 .parent = &func_32k_ck,
2079 .clkdm_name = "wkup_clkdm",
2080 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2081 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
2082 .recalc = &followparent_recalc,
2085 static struct clk sync_32k_ick = {
2086 .name = "sync_32k_ick",
2087 .ops = &clkops_omap2_dflt_wait,
2089 .flags = ENABLE_ON_INIT,
2090 .clkdm_name = "core_l4_clkdm",
2091 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2092 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
2093 .recalc = &followparent_recalc,
2096 static struct clk wdt1_ick = {
2098 .ops = &clkops_omap2_dflt_wait,
2100 .clkdm_name = "core_l4_clkdm",
2101 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2102 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
2103 .recalc = &followparent_recalc,
2106 static struct clk omapctrl_ick = {
2107 .name = "omapctrl_ick",
2108 .ops = &clkops_omap2_dflt_wait,
2110 .flags = ENABLE_ON_INIT,
2111 .clkdm_name = "core_l4_clkdm",
2112 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2113 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
2114 .recalc = &followparent_recalc,
2117 static struct clk icr_ick = {
2119 .ops = &clkops_omap2_dflt_wait,
2121 .clkdm_name = "core_l4_clkdm",
2122 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2123 .enable_bit = OMAP2430_EN_ICR_SHIFT,
2124 .recalc = &followparent_recalc,
2127 static struct clk cam_ick = {
2129 .ops = &clkops_omap2_dflt,
2131 .clkdm_name = "core_l4_clkdm",
2132 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2133 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2134 .recalc = &followparent_recalc,
2138 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
2139 * split into two separate clocks, since the parent clocks are different
2140 * and the clockdomains are also different.
2142 static struct clk cam_fck = {
2144 .ops = &clkops_omap2_dflt,
2145 .parent = &func_96m_ck,
2146 .clkdm_name = "core_l3_clkdm",
2147 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2148 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2149 .recalc = &followparent_recalc,
2152 static struct clk mailboxes_ick = {
2153 .name = "mailboxes_ick",
2154 .ops = &clkops_omap2_dflt_wait,
2156 .clkdm_name = "core_l4_clkdm",
2157 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2158 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
2159 .recalc = &followparent_recalc,
2162 static struct clk wdt4_ick = {
2164 .ops = &clkops_omap2_dflt_wait,
2166 .clkdm_name = "core_l4_clkdm",
2167 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2168 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2169 .recalc = &followparent_recalc,
2172 static struct clk wdt4_fck = {
2174 .ops = &clkops_omap2_dflt_wait,
2175 .parent = &func_32k_ck,
2176 .clkdm_name = "core_l4_clkdm",
2177 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2178 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2179 .recalc = &followparent_recalc,
2182 static struct clk wdt3_ick = {
2184 .ops = &clkops_omap2_dflt_wait,
2186 .clkdm_name = "core_l4_clkdm",
2187 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2188 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2189 .recalc = &followparent_recalc,
2192 static struct clk wdt3_fck = {
2194 .ops = &clkops_omap2_dflt_wait,
2195 .parent = &func_32k_ck,
2196 .clkdm_name = "core_l4_clkdm",
2197 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2198 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2199 .recalc = &followparent_recalc,
2202 static struct clk mspro_ick = {
2203 .name = "mspro_ick",
2204 .ops = &clkops_omap2_dflt_wait,
2206 .clkdm_name = "core_l4_clkdm",
2207 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2208 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2209 .recalc = &followparent_recalc,
2212 static struct clk mspro_fck = {
2213 .name = "mspro_fck",
2214 .ops = &clkops_omap2_dflt_wait,
2215 .parent = &func_96m_ck,
2216 .clkdm_name = "core_l4_clkdm",
2217 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2218 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2219 .recalc = &followparent_recalc,
2222 static struct clk mmc_ick = {
2224 .ops = &clkops_omap2_dflt_wait,
2226 .clkdm_name = "core_l4_clkdm",
2227 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2228 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2229 .recalc = &followparent_recalc,
2232 static struct clk mmc_fck = {
2234 .ops = &clkops_omap2_dflt_wait,
2235 .parent = &func_96m_ck,
2236 .clkdm_name = "core_l4_clkdm",
2237 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2238 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2239 .recalc = &followparent_recalc,
2242 static struct clk fac_ick = {
2244 .ops = &clkops_omap2_dflt_wait,
2246 .clkdm_name = "core_l4_clkdm",
2247 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2248 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2249 .recalc = &followparent_recalc,
2252 static struct clk fac_fck = {
2254 .ops = &clkops_omap2_dflt_wait,
2255 .parent = &func_12m_ck,
2256 .clkdm_name = "core_l4_clkdm",
2257 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2258 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2259 .recalc = &followparent_recalc,
2262 static struct clk eac_ick = {
2264 .ops = &clkops_omap2_dflt_wait,
2266 .clkdm_name = "core_l4_clkdm",
2267 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2268 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2269 .recalc = &followparent_recalc,
2272 static struct clk eac_fck = {
2274 .ops = &clkops_omap2_dflt_wait,
2275 .parent = &func_96m_ck,
2276 .clkdm_name = "core_l4_clkdm",
2277 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2278 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2279 .recalc = &followparent_recalc,
2282 static struct clk hdq_ick = {
2284 .ops = &clkops_omap2_dflt_wait,
2286 .clkdm_name = "core_l4_clkdm",
2287 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2288 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2289 .recalc = &followparent_recalc,
2292 static struct clk hdq_fck = {
2294 .ops = &clkops_omap2_dflt_wait,
2295 .parent = &func_12m_ck,
2296 .clkdm_name = "core_l4_clkdm",
2297 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2298 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2299 .recalc = &followparent_recalc,
2302 static struct clk i2c2_ick = {
2304 .ops = &clkops_omap2_dflt_wait,
2307 .clkdm_name = "core_l4_clkdm",
2308 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2309 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2310 .recalc = &followparent_recalc,
2313 static struct clk i2c2_fck = {
2315 .ops = &clkops_omap2_dflt_wait,
2317 .parent = &func_12m_ck,
2318 .clkdm_name = "core_l4_clkdm",
2319 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2320 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2321 .recalc = &followparent_recalc,
2324 static struct clk i2chs2_fck = {
2326 .ops = &clkops_omap2_dflt_wait,
2328 .parent = &func_96m_ck,
2329 .clkdm_name = "core_l4_clkdm",
2330 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2331 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
2332 .recalc = &followparent_recalc,
2335 static struct clk i2c1_ick = {
2337 .ops = &clkops_omap2_dflt_wait,
2340 .clkdm_name = "core_l4_clkdm",
2341 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2342 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2343 .recalc = &followparent_recalc,
2346 static struct clk i2c1_fck = {
2348 .ops = &clkops_omap2_dflt_wait,
2350 .parent = &func_12m_ck,
2351 .clkdm_name = "core_l4_clkdm",
2352 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2353 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2354 .recalc = &followparent_recalc,
2357 static struct clk i2chs1_fck = {
2359 .ops = &clkops_omap2_dflt_wait,
2361 .parent = &func_96m_ck,
2362 .clkdm_name = "core_l4_clkdm",
2363 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2364 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
2365 .recalc = &followparent_recalc,
2368 static struct clk gpmc_fck = {
2370 .ops = &clkops_null, /* RMK: missing? */
2371 .parent = &core_l3_ck,
2372 .flags = ENABLE_ON_INIT,
2373 .clkdm_name = "core_l3_clkdm",
2374 .recalc = &followparent_recalc,
2377 static struct clk sdma_fck = {
2379 .ops = &clkops_null, /* RMK: missing? */
2380 .parent = &core_l3_ck,
2381 .clkdm_name = "core_l3_clkdm",
2382 .recalc = &followparent_recalc,
2385 static struct clk sdma_ick = {
2387 .ops = &clkops_null, /* RMK: missing? */
2389 .clkdm_name = "core_l3_clkdm",
2390 .recalc = &followparent_recalc,
2393 static struct clk vlynq_ick = {
2394 .name = "vlynq_ick",
2395 .ops = &clkops_omap2_dflt_wait,
2396 .parent = &core_l3_ck,
2397 .clkdm_name = "core_l3_clkdm",
2398 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2399 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2400 .recalc = &followparent_recalc,
2403 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2404 { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2408 static const struct clksel_rate vlynq_fck_core_rates[] = {
2409 { .div = 1, .val = 1, .flags = RATE_IN_242X },
2410 { .div = 2, .val = 2, .flags = RATE_IN_242X },
2411 { .div = 3, .val = 3, .flags = RATE_IN_242X },
2412 { .div = 4, .val = 4, .flags = RATE_IN_242X },
2413 { .div = 6, .val = 6, .flags = RATE_IN_242X },
2414 { .div = 8, .val = 8, .flags = RATE_IN_242X },
2415 { .div = 9, .val = 9, .flags = RATE_IN_242X },
2416 { .div = 12, .val = 12, .flags = RATE_IN_242X },
2417 { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2418 { .div = 18, .val = 18, .flags = RATE_IN_242X },
2422 static const struct clksel vlynq_fck_clksel[] = {
2423 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2424 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
2428 static struct clk vlynq_fck = {
2429 .name = "vlynq_fck",
2430 .ops = &clkops_omap2_dflt_wait,
2431 .parent = &func_96m_ck,
2432 .flags = DELAYED_APP,
2433 .clkdm_name = "core_l3_clkdm",
2434 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2435 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2436 .init = &omap2_init_clksel_parent,
2437 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2438 .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
2439 .clksel = vlynq_fck_clksel,
2440 .recalc = &omap2_clksel_recalc,
2441 .round_rate = &omap2_clksel_round_rate,
2442 .set_rate = &omap2_clksel_set_rate
2445 static struct clk sdrc_ick = {
2447 .ops = &clkops_omap2_dflt_wait,
2449 .flags = ENABLE_ON_INIT,
2450 .clkdm_name = "core_l4_clkdm",
2451 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2452 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
2453 .recalc = &followparent_recalc,
2456 static struct clk des_ick = {
2458 .ops = &clkops_omap2_dflt_wait,
2460 .clkdm_name = "core_l4_clkdm",
2461 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2462 .enable_bit = OMAP24XX_EN_DES_SHIFT,
2463 .recalc = &followparent_recalc,
2466 static struct clk sha_ick = {
2468 .ops = &clkops_omap2_dflt_wait,
2470 .clkdm_name = "core_l4_clkdm",
2471 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2472 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
2473 .recalc = &followparent_recalc,
2476 static struct clk rng_ick = {
2478 .ops = &clkops_omap2_dflt_wait,
2480 .clkdm_name = "core_l4_clkdm",
2481 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2482 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
2483 .recalc = &followparent_recalc,
2486 static struct clk aes_ick = {
2488 .ops = &clkops_omap2_dflt_wait,
2490 .clkdm_name = "core_l4_clkdm",
2491 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2492 .enable_bit = OMAP24XX_EN_AES_SHIFT,
2493 .recalc = &followparent_recalc,
2496 static struct clk pka_ick = {
2498 .ops = &clkops_omap2_dflt_wait,
2500 .clkdm_name = "core_l4_clkdm",
2501 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2502 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
2503 .recalc = &followparent_recalc,
2506 static struct clk usb_fck = {
2508 .ops = &clkops_omap2_dflt_wait,
2509 .parent = &func_48m_ck,
2510 .clkdm_name = "core_l3_clkdm",
2511 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2512 .enable_bit = OMAP24XX_EN_USB_SHIFT,
2513 .recalc = &followparent_recalc,
2516 static struct clk usbhs_ick = {
2517 .name = "usbhs_ick",
2518 .ops = &clkops_omap2_dflt_wait,
2519 .parent = &core_l3_ck,
2520 .clkdm_name = "core_l3_clkdm",
2521 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2522 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
2523 .recalc = &followparent_recalc,
2526 static struct clk mmchs1_ick = {
2527 .name = "mmchs_ick",
2528 .ops = &clkops_omap2_dflt_wait,
2530 .clkdm_name = "core_l4_clkdm",
2531 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2532 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2533 .recalc = &followparent_recalc,
2536 static struct clk mmchs1_fck = {
2537 .name = "mmchs_fck",
2538 .ops = &clkops_omap2_dflt_wait,
2539 .parent = &func_96m_ck,
2540 .clkdm_name = "core_l3_clkdm",
2541 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2542 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2543 .recalc = &followparent_recalc,
2546 static struct clk mmchs2_ick = {
2547 .name = "mmchs_ick",
2548 .ops = &clkops_omap2_dflt_wait,
2551 .clkdm_name = "core_l4_clkdm",
2552 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2553 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2554 .recalc = &followparent_recalc,
2557 static struct clk mmchs2_fck = {
2558 .name = "mmchs_fck",
2559 .ops = &clkops_omap2_dflt_wait,
2561 .parent = &func_96m_ck,
2562 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2563 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2564 .recalc = &followparent_recalc,
2567 static struct clk gpio5_ick = {
2568 .name = "gpio5_ick",
2569 .ops = &clkops_omap2_dflt_wait,
2571 .clkdm_name = "core_l4_clkdm",
2572 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2573 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2574 .recalc = &followparent_recalc,
2577 static struct clk gpio5_fck = {
2578 .name = "gpio5_fck",
2579 .ops = &clkops_omap2_dflt_wait,
2580 .parent = &func_32k_ck,
2581 .clkdm_name = "core_l4_clkdm",
2582 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2583 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2584 .recalc = &followparent_recalc,
2587 static struct clk mdm_intc_ick = {
2588 .name = "mdm_intc_ick",
2589 .ops = &clkops_omap2_dflt_wait,
2591 .clkdm_name = "core_l4_clkdm",
2592 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2593 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
2594 .recalc = &followparent_recalc,
2597 static struct clk mmchsdb1_fck = {
2598 .name = "mmchsdb_fck",
2599 .ops = &clkops_omap2_dflt_wait,
2600 .parent = &func_32k_ck,
2601 .clkdm_name = "core_l4_clkdm",
2602 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2603 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
2604 .recalc = &followparent_recalc,
2607 static struct clk mmchsdb2_fck = {
2608 .name = "mmchsdb_fck",
2609 .ops = &clkops_omap2_dflt_wait,
2611 .parent = &func_32k_ck,
2612 .clkdm_name = "core_l4_clkdm",
2613 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2614 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
2615 .recalc = &followparent_recalc,
2619 * This clock is a composite clock which does entire set changes then
2620 * forces a rebalance. It keys on the MPU speed, but it really could
2621 * be any key speed part of a set in the rate table.
2623 * to really change a set, you need memory table sets which get changed
2624 * in sram, pre-notifiers & post notifiers, changing the top set, without
2625 * having low level display recalc's won't work... this is why dpm notifiers
2626 * work, isr's off, walk a list of clocks already _off_ and not messing with
2629 * This clock should have no parent. It embodies the entire upper level
2630 * active set. A parent will mess up some of the init also.
2632 static struct clk virt_prcm_set = {
2633 .name = "virt_prcm_set",
2634 .ops = &clkops_null,
2635 .flags = DELAYED_APP,
2636 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
2637 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
2638 .set_rate = &omap2_select_table_rate,
2639 .round_rate = &omap2_round_to_table_rate,