2 * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family
3 * of PCI-SCSI IO processors.
5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
6 * Copyright (c) 2003-2005 Matthew Wilcox <matthew@wil.cx>
8 * This driver is derived from the Linux sym53c8xx driver.
9 * Copyright (C) 1998-2000 Gerard Roudier
11 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been
12 * a port of the FreeBSD ncr driver to Linux-1.2.13.
14 * The original ncr driver has been written for 386bsd and FreeBSD by
15 * Wolfgang Stanglmeier <wolf@cologne.de>
16 * Stefan Esser <se@mi.Uni-Koeln.de>
17 * Copyright (C) 1994 Wolfgang Stanglmeier
19 * Other major contributions:
21 * NVRAM detection and reading.
22 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
24 *-----------------------------------------------------------------------------
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License as published by
28 * the Free Software Foundation; either version 2 of the License, or
29 * (at your option) any later version.
31 * This program is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 * GNU General Public License for more details.
36 * You should have received a copy of the GNU General Public License
37 * along with this program; if not, write to the Free Software
38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
41 #include <linux/slab.h>
42 #include <asm/param.h> /* for timeouts in units of HZ */
45 #include "sym_nvram.h"
48 #define SYM_DEBUG_GENERIC_SUPPORT
52 * Needed function prototypes.
54 static void sym_int_ma (struct sym_hcb *np);
55 static void sym_int_sir (struct sym_hcb *np);
56 static struct sym_ccb *sym_alloc_ccb(struct sym_hcb *np);
57 static struct sym_ccb *sym_ccb_from_dsa(struct sym_hcb *np, u32 dsa);
58 static void sym_alloc_lcb_tags (struct sym_hcb *np, u_char tn, u_char ln);
59 static void sym_complete_error (struct sym_hcb *np, struct sym_ccb *cp);
60 static void sym_complete_ok (struct sym_hcb *np, struct sym_ccb *cp);
61 static int sym_compute_residual(struct sym_hcb *np, struct sym_ccb *cp);
64 * Print a buffer in hexadecimal format with a ".\n" at end.
66 static void sym_printl_hex(u_char *p, int n)
73 static void sym_print_msg(struct sym_ccb *cp, char *label, u_char *msg)
76 sym_print_addr(cp->cmd, "%s: ", label);
78 sym_print_addr(cp->cmd, "");
84 static void sym_print_nego_msg(struct sym_hcb *np, int target, char *label, u_char *msg)
86 struct sym_tcb *tp = &np->target[target];
87 dev_info(&tp->starget->dev, "%s: ", label);
94 * Print something that tells about extended errors.
96 void sym_print_xerr(struct scsi_cmnd *cmd, int x_status)
98 if (x_status & XE_PARITY_ERR) {
99 sym_print_addr(cmd, "unrecovered SCSI parity error.\n");
101 if (x_status & XE_EXTRA_DATA) {
102 sym_print_addr(cmd, "extraneous data discarded.\n");
104 if (x_status & XE_BAD_PHASE) {
105 sym_print_addr(cmd, "illegal scsi phase (4/5).\n");
107 if (x_status & XE_SODL_UNRUN) {
108 sym_print_addr(cmd, "ODD transfer in DATA OUT phase.\n");
110 if (x_status & XE_SWIDE_OVRUN) {
111 sym_print_addr(cmd, "ODD transfer in DATA IN phase.\n");
116 * Return a string for SCSI BUS mode.
118 static char *sym_scsi_bus_mode(int mode)
121 case SMODE_HVD: return "HVD";
122 case SMODE_SE: return "SE";
123 case SMODE_LVD: return "LVD";
129 * Soft reset the chip.
131 * Raising SRST when the chip is running may cause
132 * problems on dual function chips (see below).
133 * On the other hand, LVD devices need some delay
134 * to settle and report actual BUS mode in STEST4.
136 static void sym_chip_reset (struct sym_hcb *np)
138 OUTB(np, nc_istat, SRST);
141 OUTB(np, nc_istat, 0);
143 udelay(2000); /* For BUS MODE to settle */
147 * Really soft reset the chip.:)
149 * Some 896 and 876 chip revisions may hang-up if we set
150 * the SRST (soft reset) bit at the wrong time when SCRIPTS
152 * So, we need to abort the current operation prior to
153 * soft resetting the chip.
155 static void sym_soft_reset (struct sym_hcb *np)
160 if (!(np->features & FE_ISTAT1) || !(INB(np, nc_istat1) & SCRUN))
163 OUTB(np, nc_istat, CABRT);
164 for (i = 100000 ; i ; --i) {
165 istat = INB(np, nc_istat);
169 else if (istat & DIP) {
170 if (INB(np, nc_dstat) & ABRT)
175 OUTB(np, nc_istat, 0);
177 printf("%s: unable to abort current chip operation, "
178 "ISTAT=0x%02x.\n", sym_name(np), istat);
184 * Start reset process.
186 * The interrupt handler will reinitialize the chip.
188 static void sym_start_reset(struct sym_hcb *np)
190 sym_reset_scsi_bus(np, 1);
193 int sym_reset_scsi_bus(struct sym_hcb *np, int enab_int)
198 sym_soft_reset(np); /* Soft reset the chip */
200 OUTW(np, nc_sien, RST);
202 * Enable Tolerant, reset IRQD if present and
203 * properly set IRQ mode, prior to resetting the bus.
205 OUTB(np, nc_stest3, TE);
206 OUTB(np, nc_dcntl, (np->rv_dcntl & IRQM));
207 OUTB(np, nc_scntl1, CRST);
211 if (!SYM_SETUP_SCSI_BUS_CHECK)
214 * Check for no terminators or SCSI bus shorts to ground.
215 * Read SCSI data bus, data parity bits and control signals.
216 * We are expecting RESET to be TRUE and other signals to be
219 term = INB(np, nc_sstat0);
220 term = ((term & 2) << 7) + ((term & 1) << 17); /* rst sdp0 */
221 term |= ((INB(np, nc_sstat2) & 0x01) << 26) | /* sdp1 */
222 ((INW(np, nc_sbdl) & 0xff) << 9) | /* d7-0 */
223 ((INW(np, nc_sbdl) & 0xff00) << 10) | /* d15-8 */
224 INB(np, nc_sbcl); /* req ack bsy sel atn msg cd io */
229 if (term != (2<<7)) {
230 printf("%s: suspicious SCSI data while resetting the BUS.\n",
232 printf("%s: %sdp0,d7-0,rst,req,ack,bsy,sel,atn,msg,c/d,i/o = "
233 "0x%lx, expecting 0x%lx\n",
235 (np->features & FE_WIDE) ? "dp1,d15-8," : "",
236 (u_long)term, (u_long)(2<<7));
237 if (SYM_SETUP_SCSI_BUS_CHECK == 1)
241 OUTB(np, nc_scntl1, 0);
246 * Select SCSI clock frequency
248 static void sym_selectclock(struct sym_hcb *np, u_char scntl3)
251 * If multiplier not present or not selected, leave here.
253 if (np->multiplier <= 1) {
254 OUTB(np, nc_scntl3, scntl3);
258 if (sym_verbose >= 2)
259 printf ("%s: enabling clock multiplier\n", sym_name(np));
261 OUTB(np, nc_stest1, DBLEN); /* Enable clock multiplier */
263 * Wait for the LCKFRQ bit to be set if supported by the chip.
264 * Otherwise wait 50 micro-seconds (at least).
266 if (np->features & FE_LCKFRQ) {
268 while (!(INB(np, nc_stest4) & LCKFRQ) && --i > 0)
271 printf("%s: the chip cannot lock the frequency\n",
277 OUTB(np, nc_stest3, HSC); /* Halt the scsi clock */
278 OUTB(np, nc_scntl3, scntl3);
279 OUTB(np, nc_stest1, (DBLEN|DBLSEL));/* Select clock multiplier */
280 OUTB(np, nc_stest3, 0x00); /* Restart scsi clock */
285 * Determine the chip's clock frequency.
287 * This is essential for the negotiation of the synchronous
290 * Note: we have to return the correct value.
291 * THERE IS NO SAFE DEFAULT VALUE.
293 * Most NCR/SYMBIOS boards are delivered with a 40 Mhz clock.
294 * 53C860 and 53C875 rev. 1 support fast20 transfers but
295 * do not have a clock doubler and so are provided with a
296 * 80 MHz clock. All other fast20 boards incorporate a doubler
297 * and so should be delivered with a 40 MHz clock.
298 * The recent fast40 chips (895/896/895A/1010) use a 40 Mhz base
299 * clock and provide a clock quadrupler (160 Mhz).
303 * calculate SCSI clock frequency (in KHz)
305 static unsigned getfreq (struct sym_hcb *np, int gen)
311 * Measure GEN timer delay in order
312 * to calculate SCSI clock frequency
314 * This code will never execute too
315 * many loop iterations (if DELAY is
316 * reasonably correct). It could get
317 * too low a delay (too high a freq.)
318 * if the CPU is slow executing the
319 * loop for some reason (an NMI, for
320 * example). For this reason we will
321 * if multiple measurements are to be
322 * performed trust the higher delay
323 * (lower frequency returned).
325 OUTW(np, nc_sien, 0); /* mask all scsi interrupts */
326 INW(np, nc_sist); /* clear pending scsi interrupt */
327 OUTB(np, nc_dien, 0); /* mask all dma interrupts */
328 INW(np, nc_sist); /* another one, just to be sure :) */
330 * The C1010-33 core does not report GEN in SIST,
331 * if this interrupt is masked in SIEN.
332 * I don't know yet if the C1010-66 behaves the same way.
334 if (np->features & FE_C10) {
335 OUTW(np, nc_sien, GEN);
336 OUTB(np, nc_istat1, SIRQD);
338 OUTB(np, nc_scntl3, 4); /* set pre-scaler to divide by 3 */
339 OUTB(np, nc_stime1, 0); /* disable general purpose timer */
340 OUTB(np, nc_stime1, gen); /* set to nominal delay of 1<<gen * 125us */
341 while (!(INW(np, nc_sist) & GEN) && ms++ < 100000)
342 udelay(1000/4); /* count in 1/4 of ms */
343 OUTB(np, nc_stime1, 0); /* disable general purpose timer */
345 * Undo C1010-33 specific settings.
347 if (np->features & FE_C10) {
348 OUTW(np, nc_sien, 0);
349 OUTB(np, nc_istat1, 0);
352 * set prescaler to divide by whatever 0 means
353 * 0 ought to choose divide by 2, but appears
354 * to set divide by 3.5 mode in my 53c810 ...
356 OUTB(np, nc_scntl3, 0);
359 * adjust for prescaler, and convert into KHz
361 f = ms ? ((1 << gen) * (4340*4)) / ms : 0;
364 * The C1010-33 result is biased by a factor
365 * of 2/3 compared to earlier chips.
367 if (np->features & FE_C10)
370 if (sym_verbose >= 2)
371 printf ("%s: Delay (GEN=%d): %u msec, %u KHz\n",
372 sym_name(np), gen, ms/4, f);
377 static unsigned sym_getfreq (struct sym_hcb *np)
382 getfreq (np, gen); /* throw away first result */
383 f1 = getfreq (np, gen);
384 f2 = getfreq (np, gen);
385 if (f1 > f2) f1 = f2; /* trust lower result */
390 * Get/probe chip SCSI clock frequency
392 static void sym_getclock (struct sym_hcb *np, int mult)
394 unsigned char scntl3 = np->sv_scntl3;
395 unsigned char stest1 = np->sv_stest1;
401 * True with 875/895/896/895A with clock multiplier selected
403 if (mult > 1 && (stest1 & (DBLEN+DBLSEL)) == DBLEN+DBLSEL) {
404 if (sym_verbose >= 2)
405 printf ("%s: clock multiplier found\n", sym_name(np));
406 np->multiplier = mult;
410 * If multiplier not found or scntl3 not 7,5,3,
411 * reset chip and get frequency from general purpose timer.
412 * Otherwise trust scntl3 BIOS setting.
414 if (np->multiplier != mult || (scntl3 & 7) < 3 || !(scntl3 & 1)) {
415 OUTB(np, nc_stest1, 0); /* make sure doubler is OFF */
416 f1 = sym_getfreq (np);
419 printf ("%s: chip clock is %uKHz\n", sym_name(np), f1);
421 if (f1 < 45000) f1 = 40000;
422 else if (f1 < 55000) f1 = 50000;
425 if (f1 < 80000 && mult > 1) {
426 if (sym_verbose >= 2)
427 printf ("%s: clock multiplier assumed\n",
429 np->multiplier = mult;
432 if ((scntl3 & 7) == 3) f1 = 40000;
433 else if ((scntl3 & 7) == 5) f1 = 80000;
436 f1 /= np->multiplier;
440 * Compute controller synchronous parameters.
442 f1 *= np->multiplier;
447 * Get/probe PCI clock frequency
449 static int sym_getpciclock (struct sym_hcb *np)
454 * For now, we only need to know about the actual
455 * PCI BUS clock frequency for C1010-66 chips.
458 if (np->features & FE_66MHZ) {
462 OUTB(np, nc_stest1, SCLK); /* Use the PCI clock as SCSI clock */
464 OUTB(np, nc_stest1, 0);
472 * SYMBIOS chip clock divisor table.
474 * Divisors are multiplied by 10,000,000 in order to make
475 * calculations more simple.
478 static const u32 div_10M[] = {2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M};
481 * Get clock factor and sync divisor for a given
482 * synchronous factor period.
485 sym_getsync(struct sym_hcb *np, u_char dt, u_char sfac, u_char *divp, u_char *fakp)
487 u32 clk = np->clock_khz; /* SCSI clock frequency in kHz */
488 int div = np->clock_divn; /* Number of divisors supported */
489 u32 fak; /* Sync factor in sxfer */
490 u32 per; /* Period in tenths of ns */
491 u32 kpc; /* (per * clk) */
495 * Compute the synchronous period in tenths of nano-seconds
497 if (dt && sfac <= 9) per = 125;
498 else if (sfac <= 10) per = 250;
499 else if (sfac == 11) per = 303;
500 else if (sfac == 12) per = 500;
501 else per = 40 * sfac;
509 * For earliest C10 revision 0, we cannot use extra
510 * clocks for the setting of the SCSI clocking.
511 * Note that this limits the lowest sync data transfer
512 * to 5 Mega-transfers per second and may result in
513 * using higher clock divisors.
516 if ((np->features & (FE_C10|FE_U3EN)) == FE_C10) {
518 * Look for the lowest clock divisor that allows an
519 * output speed not faster than the period.
523 if (kpc > (div_10M[div] << 2)) {
528 fak = 0; /* No extra clocks */
529 if (div == np->clock_divn) { /* Are we too fast ? */
539 * Look for the greatest clock divisor that allows an
540 * input speed faster than the period.
543 if (kpc >= (div_10M[div] << 2)) break;
546 * Calculate the lowest clock factor that allows an output
547 * speed not faster than the period, and the max output speed.
548 * If fak >= 1 we will set both XCLKH_ST and XCLKH_DT.
549 * If fak >= 2 we will also set XCLKS_ST and XCLKS_DT.
552 fak = (kpc - 1) / (div_10M[div] << 1) + 1 - 2;
553 /* ret = ((2+fak)*div_10M[div])/np->clock_khz; */
555 fak = (kpc - 1) / div_10M[div] + 1 - 4;
556 /* ret = ((4+fak)*div_10M[div])/np->clock_khz; */
560 * Check against our hardware limits, or bugs :).
568 * Compute and return sync parameters.
577 * SYMBIOS chips allow burst lengths of 2, 4, 8, 16, 32, 64,
578 * 128 transfers. All chips support at least 16 transfers
579 * bursts. The 825A, 875 and 895 chips support bursts of up
580 * to 128 transfers and the 895A and 896 support bursts of up
581 * to 64 transfers. All other chips support up to 16
584 * For PCI 32 bit data transfers each transfer is a DWORD.
585 * It is a QUADWORD (8 bytes) for PCI 64 bit data transfers.
587 * We use log base 2 (burst length) as internal code, with
588 * value 0 meaning "burst disabled".
592 * Burst length from burst code.
594 #define burst_length(bc) (!(bc))? 0 : 1 << (bc)
597 * Burst code from io register bits.
599 #define burst_code(dmode, ctest4, ctest5) \
600 (ctest4) & 0x80? 0 : (((dmode) & 0xc0) >> 6) + ((ctest5) & 0x04) + 1
603 * Set initial io register bits from burst code.
605 static __inline void sym_init_burst(struct sym_hcb *np, u_char bc)
607 np->rv_ctest4 &= ~0x80;
608 np->rv_dmode &= ~(0x3 << 6);
609 np->rv_ctest5 &= ~0x4;
612 np->rv_ctest4 |= 0x80;
616 np->rv_dmode |= ((bc & 0x3) << 6);
617 np->rv_ctest5 |= (bc & 0x4);
622 * Save initial settings of some IO registers.
623 * Assumed to have been set by BIOS.
624 * We cannot reset the chip prior to reading the
625 * IO registers, since informations will be lost.
626 * Since the SCRIPTS processor may be running, this
627 * is not safe on paper, but it seems to work quite
630 static void sym_save_initial_setting (struct sym_hcb *np)
632 np->sv_scntl0 = INB(np, nc_scntl0) & 0x0a;
633 np->sv_scntl3 = INB(np, nc_scntl3) & 0x07;
634 np->sv_dmode = INB(np, nc_dmode) & 0xce;
635 np->sv_dcntl = INB(np, nc_dcntl) & 0xa8;
636 np->sv_ctest3 = INB(np, nc_ctest3) & 0x01;
637 np->sv_ctest4 = INB(np, nc_ctest4) & 0x80;
638 np->sv_gpcntl = INB(np, nc_gpcntl);
639 np->sv_stest1 = INB(np, nc_stest1);
640 np->sv_stest2 = INB(np, nc_stest2) & 0x20;
641 np->sv_stest4 = INB(np, nc_stest4);
642 if (np->features & FE_C10) { /* Always large DMA fifo + ultra3 */
643 np->sv_scntl4 = INB(np, nc_scntl4);
644 np->sv_ctest5 = INB(np, nc_ctest5) & 0x04;
647 np->sv_ctest5 = INB(np, nc_ctest5) & 0x24;
652 * - LVD capable chips (895/895A/896/1010) report the current BUS mode
653 * through the STEST4 IO register.
654 * - For previous generation chips (825/825A/875), the user has to tell us
655 * how to check against HVD, since a 100% safe algorithm is not possible.
657 static void sym_set_bus_mode(struct sym_hcb *np, struct sym_nvram *nvram)
662 np->scsi_mode = SMODE_SE;
663 if (np->features & (FE_ULTRA2|FE_ULTRA3))
664 np->scsi_mode = (np->sv_stest4 & SMODE);
665 else if (np->features & FE_DIFF) {
666 if (SYM_SETUP_SCSI_DIFF == 1) {
668 if (np->sv_stest2 & 0x20)
669 np->scsi_mode = SMODE_HVD;
670 } else if (nvram->type == SYM_SYMBIOS_NVRAM) {
671 if (!(INB(np, nc_gpreg) & 0x08))
672 np->scsi_mode = SMODE_HVD;
674 } else if (SYM_SETUP_SCSI_DIFF == 2)
675 np->scsi_mode = SMODE_HVD;
677 if (np->scsi_mode == SMODE_HVD)
678 np->rv_stest2 |= 0x20;
682 * Prepare io register values used by sym_start_up()
683 * according to selected and supported features.
685 static int sym_prepare_setting(struct Scsi_Host *shost, struct sym_hcb *np, struct sym_nvram *nvram)
691 np->maxwide = (np->features & FE_WIDE) ? 1 : 0;
694 * Guess the frequency of the chip's clock.
696 if (np->features & (FE_ULTRA3 | FE_ULTRA2))
697 np->clock_khz = 160000;
698 else if (np->features & FE_ULTRA)
699 np->clock_khz = 80000;
701 np->clock_khz = 40000;
704 * Get the clock multiplier factor.
706 if (np->features & FE_QUAD)
708 else if (np->features & FE_DBLR)
714 * Measure SCSI clock frequency for chips
715 * it may vary from assumed one.
717 if (np->features & FE_VARCLK)
718 sym_getclock(np, np->multiplier);
721 * Divisor to be used for async (timer pre-scaler).
723 i = np->clock_divn - 1;
725 if (10ul * SYM_CONF_MIN_ASYNC * np->clock_khz > div_10M[i]) {
733 * The C1010 uses hardwired divisors for async.
734 * So, we just throw away, the async. divisor.:-)
736 if (np->features & FE_C10)
740 * Minimum synchronous period factor supported by the chip.
741 * Btw, 'period' is in tenths of nanoseconds.
743 period = (4 * div_10M[0] + np->clock_khz - 1) / np->clock_khz;
745 if (period <= 250) np->minsync = 10;
746 else if (period <= 303) np->minsync = 11;
747 else if (period <= 500) np->minsync = 12;
748 else np->minsync = (period + 40 - 1) / 40;
751 * Check against chip SCSI standard support (SCSI-2,ULTRA,ULTRA2).
753 if (np->minsync < 25 &&
754 !(np->features & (FE_ULTRA|FE_ULTRA2|FE_ULTRA3)))
756 else if (np->minsync < 12 &&
757 !(np->features & (FE_ULTRA2|FE_ULTRA3)))
761 * Maximum synchronous period factor supported by the chip.
763 period = (11 * div_10M[np->clock_divn - 1]) / (4 * np->clock_khz);
764 np->maxsync = period > 2540 ? 254 : period / 10;
767 * If chip is a C1010, guess the sync limits in DT mode.
769 if ((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3)) {
770 if (np->clock_khz == 160000) {
773 np->maxoffs_dt = nvram->type ? 62 : 31;
778 * 64 bit addressing (895A/896/1010) ?
780 if (np->features & FE_DAC) {
781 #if SYM_CONF_DMA_ADDRESSING_MODE == 0
782 np->rv_ccntl1 |= (DDAC);
783 #elif SYM_CONF_DMA_ADDRESSING_MODE == 1
785 np->rv_ccntl1 |= (DDAC);
787 np->rv_ccntl1 |= (XTIMOD | EXTIBMV);
788 #elif SYM_CONF_DMA_ADDRESSING_MODE == 2
790 np->rv_ccntl1 |= (DDAC);
792 np->rv_ccntl1 |= (0 | EXTIBMV);
797 * Phase mismatch handled by SCRIPTS (895A/896/1010) ?
799 if (np->features & FE_NOPM)
800 np->rv_ccntl0 |= (ENPMJ);
803 * C1010-33 Errata: Part Number:609-039638 (rev. 1) is fixed.
804 * In dual channel mode, contention occurs if internal cycles
805 * are used. Disable internal cycles.
807 if (np->device_id == PCI_DEVICE_ID_LSI_53C1010_33 &&
808 np->revision_id < 0x1)
809 np->rv_ccntl0 |= DILS;
812 * Select burst length (dwords)
814 burst_max = SYM_SETUP_BURST_ORDER;
815 if (burst_max == 255)
816 burst_max = burst_code(np->sv_dmode, np->sv_ctest4,
820 if (burst_max > np->maxburst)
821 burst_max = np->maxburst;
824 * DEL 352 - 53C810 Rev x11 - Part Number 609-0392140 - ITEM 2.
825 * This chip and the 860 Rev 1 may wrongly use PCI cache line
826 * based transactions on LOAD/STORE instructions. So we have
827 * to prevent these chips from using such PCI transactions in
828 * this driver. The generic ncr driver that does not use
829 * LOAD/STORE instructions does not need this work-around.
831 if ((np->device_id == PCI_DEVICE_ID_NCR_53C810 &&
832 np->revision_id >= 0x10 && np->revision_id <= 0x11) ||
833 (np->device_id == PCI_DEVICE_ID_NCR_53C860 &&
834 np->revision_id <= 0x1))
835 np->features &= ~(FE_WRIE|FE_ERL|FE_ERMP);
838 * Select all supported special features.
839 * If we are using on-board RAM for scripts, prefetch (PFEN)
840 * does not help, but burst op fetch (BOF) does.
841 * Disabling PFEN makes sure BOF will be used.
843 if (np->features & FE_ERL)
844 np->rv_dmode |= ERL; /* Enable Read Line */
845 if (np->features & FE_BOF)
846 np->rv_dmode |= BOF; /* Burst Opcode Fetch */
847 if (np->features & FE_ERMP)
848 np->rv_dmode |= ERMP; /* Enable Read Multiple */
850 if ((np->features & FE_PFEN) && !np->ram_ba)
852 if (np->features & FE_PFEN)
854 np->rv_dcntl |= PFEN; /* Prefetch Enable */
855 if (np->features & FE_CLSE)
856 np->rv_dcntl |= CLSE; /* Cache Line Size Enable */
857 if (np->features & FE_WRIE)
858 np->rv_ctest3 |= WRIE; /* Write and Invalidate */
859 if (np->features & FE_DFS)
860 np->rv_ctest5 |= DFS; /* Dma Fifo Size */
865 np->rv_ctest4 |= MPEE; /* Master parity checking */
866 np->rv_scntl0 |= 0x0a; /* full arb., ena parity, par->ATN */
869 * Get parity checking, host ID and verbose mode from NVRAM
873 sym_nvram_setup_host(shost, np, nvram);
876 * Get SCSI addr of host adapter (set by bios?).
878 if (np->myaddr == 255) {
879 np->myaddr = INB(np, nc_scid) & 0x07;
881 np->myaddr = SYM_SETUP_HOST_ID;
885 * Prepare initial io register bits for burst length
887 sym_init_burst(np, burst_max);
889 sym_set_bus_mode(np, nvram);
892 * Set LED support from SCRIPTS.
893 * Ignore this feature for boards known to use a
894 * specific GPIO wiring and for the 895A, 896
895 * and 1010 that drive the LED directly.
897 if ((SYM_SETUP_SCSI_LED ||
898 (nvram->type == SYM_SYMBIOS_NVRAM ||
899 (nvram->type == SYM_TEKRAM_NVRAM &&
900 np->device_id == PCI_DEVICE_ID_NCR_53C895))) &&
901 !(np->features & FE_LEDC) && !(np->sv_gpcntl & 0x01))
902 np->features |= FE_LED0;
907 switch(SYM_SETUP_IRQ_MODE & 3) {
909 np->rv_dcntl |= IRQM;
912 np->rv_dcntl |= (np->sv_dcntl & IRQM);
919 * Configure targets according to driver setup.
920 * If NVRAM present get targets setup from NVRAM.
922 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) {
923 struct sym_tcb *tp = &np->target[i];
925 tp->usrflags |= (SYM_DISC_ENABLED | SYM_TAGS_ENABLED);
926 tp->usrtags = SYM_SETUP_MAX_TAG;
927 tp->usr_width = np->maxwide;
930 sym_nvram_setup_target(tp, i, nvram);
933 tp->usrflags &= ~SYM_TAGS_ENABLED;
937 * Let user know about the settings.
939 printf("%s: %s, ID %d, Fast-%d, %s, %s\n", sym_name(np),
940 sym_nvram_type(nvram), np->myaddr,
941 (np->features & FE_ULTRA3) ? 80 :
942 (np->features & FE_ULTRA2) ? 40 :
943 (np->features & FE_ULTRA) ? 20 : 10,
944 sym_scsi_bus_mode(np->scsi_mode),
945 (np->rv_scntl0 & 0xa) ? "parity checking" : "NO parity");
947 * Tell him more on demand.
950 printf("%s: %s IRQ line driver%s\n",
952 np->rv_dcntl & IRQM ? "totem pole" : "open drain",
953 np->ram_ba ? ", using on-chip SRAM" : "");
954 printf("%s: using %s firmware.\n", sym_name(np), np->fw_name);
955 if (np->features & FE_NOPM)
956 printf("%s: handling phase mismatch from SCRIPTS.\n",
962 if (sym_verbose >= 2) {
963 printf ("%s: initial SCNTL3/DMODE/DCNTL/CTEST3/4/5 = "
964 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n",
965 sym_name(np), np->sv_scntl3, np->sv_dmode, np->sv_dcntl,
966 np->sv_ctest3, np->sv_ctest4, np->sv_ctest5);
968 printf ("%s: final SCNTL3/DMODE/DCNTL/CTEST3/4/5 = "
969 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n",
970 sym_name(np), np->rv_scntl3, np->rv_dmode, np->rv_dcntl,
971 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5);
978 * Test the pci bus snoop logic :-(
980 * Has to be called with interrupts disabled.
982 #ifdef CONFIG_SCSI_SYM53C8XX_MMIO
983 static int sym_regtest(struct sym_hcb *np)
985 register volatile u32 data;
987 * chip registers may NOT be cached.
988 * write 0xffffffff to a read only register area,
989 * and try to read it back.
992 OUTL(np, nc_dstat, data);
993 data = INL(np, nc_dstat);
995 if (data == 0xffffffff) {
997 if ((data & 0xe2f0fffd) != 0x02000080) {
999 printf ("CACHE TEST FAILED: reg dstat-sstat2 readback %x.\n",
1006 static inline int sym_regtest(struct sym_hcb *np)
1012 static int sym_snooptest(struct sym_hcb *np)
1014 u32 sym_rd, sym_wr, sym_bk, host_rd, host_wr, pc, dstat;
1017 err = sym_regtest(np);
1022 * Enable Master Parity Checking as we intend
1023 * to enable it for normal operations.
1025 OUTB(np, nc_ctest4, (np->rv_ctest4 & MPEE));
1029 pc = SCRIPTZ_BA(np, snooptest);
1033 * Set memory and register.
1035 np->scratch = cpu_to_scr(host_wr);
1036 OUTL(np, nc_temp, sym_wr);
1038 * Start script (exchange values)
1040 OUTL(np, nc_dsa, np->hcb_ba);
1043 * Wait 'til done (with timeout)
1045 for (i=0; i<SYM_SNOOP_TIMEOUT; i++)
1046 if (INB(np, nc_istat) & (INTF|SIP|DIP))
1048 if (i>=SYM_SNOOP_TIMEOUT) {
1049 printf ("CACHE TEST FAILED: timeout.\n");
1053 * Check for fatal DMA errors.
1055 dstat = INB(np, nc_dstat);
1056 #if 1 /* Band aiding for broken hardwares that fail PCI parity */
1057 if ((dstat & MDPE) && (np->rv_ctest4 & MPEE)) {
1058 printf ("%s: PCI DATA PARITY ERROR DETECTED - "
1059 "DISABLING MASTER DATA PARITY CHECKING.\n",
1061 np->rv_ctest4 &= ~MPEE;
1065 if (dstat & (MDPE|BF|IID)) {
1066 printf ("CACHE TEST FAILED: DMA error (dstat=0x%02x).", dstat);
1070 * Save termination position.
1072 pc = INL(np, nc_dsp);
1074 * Read memory and register.
1076 host_rd = scr_to_cpu(np->scratch);
1077 sym_rd = INL(np, nc_scratcha);
1078 sym_bk = INL(np, nc_temp);
1080 * Check termination position.
1082 if (pc != SCRIPTZ_BA(np, snoopend)+8) {
1083 printf ("CACHE TEST FAILED: script execution failed.\n");
1084 printf ("start=%08lx, pc=%08lx, end=%08lx\n",
1085 (u_long) SCRIPTZ_BA(np, snooptest), (u_long) pc,
1086 (u_long) SCRIPTZ_BA(np, snoopend) +8);
1092 if (host_wr != sym_rd) {
1093 printf ("CACHE TEST FAILED: host wrote %d, chip read %d.\n",
1094 (int) host_wr, (int) sym_rd);
1097 if (host_rd != sym_wr) {
1098 printf ("CACHE TEST FAILED: chip wrote %d, host read %d.\n",
1099 (int) sym_wr, (int) host_rd);
1102 if (sym_bk != sym_wr) {
1103 printf ("CACHE TEST FAILED: chip wrote %d, read back %d.\n",
1104 (int) sym_wr, (int) sym_bk);
1112 * log message for real hard errors
1114 * sym0 targ 0?: ERROR (ds:si) (so-si-sd) (sx/s3/s4) @ name (dsp:dbc).
1115 * reg: r0 r1 r2 r3 r4 r5 r6 ..... rf.
1117 * exception register:
1122 * so: control lines as driven by chip.
1123 * si: control lines as seen by chip.
1124 * sd: scsi data lines as seen by chip.
1127 * sx: sxfer (see the manual)
1128 * s3: scntl3 (see the manual)
1129 * s4: scntl4 (see the manual)
1131 * current script command:
1132 * dsp: script address (relative to start of script).
1133 * dbc: first word of script command.
1135 * First 24 register of the chip:
1138 static void sym_log_hard_error(struct sym_hcb *np, u_short sist, u_char dstat)
1144 u_char *script_base;
1147 dsp = INL(np, nc_dsp);
1149 if (dsp > np->scripta_ba &&
1150 dsp <= np->scripta_ba + np->scripta_sz) {
1151 script_ofs = dsp - np->scripta_ba;
1152 script_size = np->scripta_sz;
1153 script_base = (u_char *) np->scripta0;
1154 script_name = "scripta";
1156 else if (np->scriptb_ba < dsp &&
1157 dsp <= np->scriptb_ba + np->scriptb_sz) {
1158 script_ofs = dsp - np->scriptb_ba;
1159 script_size = np->scriptb_sz;
1160 script_base = (u_char *) np->scriptb0;
1161 script_name = "scriptb";
1166 script_name = "mem";
1169 printf ("%s:%d: ERROR (%x:%x) (%x-%x-%x) (%x/%x/%x) @ (%s %x:%08x).\n",
1170 sym_name(np), (unsigned)INB(np, nc_sdid)&0x0f, dstat, sist,
1171 (unsigned)INB(np, nc_socl), (unsigned)INB(np, nc_sbcl),
1172 (unsigned)INB(np, nc_sbdl), (unsigned)INB(np, nc_sxfer),
1173 (unsigned)INB(np, nc_scntl3),
1174 (np->features & FE_C10) ? (unsigned)INB(np, nc_scntl4) : 0,
1175 script_name, script_ofs, (unsigned)INL(np, nc_dbc));
1177 if (((script_ofs & 3) == 0) &&
1178 (unsigned)script_ofs < script_size) {
1179 printf ("%s: script cmd = %08x\n", sym_name(np),
1180 scr_to_cpu((int) *(u32 *)(script_base + script_ofs)));
1183 printf ("%s: regdump:", sym_name(np));
1185 printf (" %02x", (unsigned)INB_OFF(np, i));
1191 if (dstat & (MDPE|BF))
1192 sym_log_bus_error(np);
1195 static struct sym_chip sym_dev_table[] = {
1196 {PCI_DEVICE_ID_NCR_53C810, 0x0f, "810", 4, 8, 4, 64,
1199 #ifdef SYM_DEBUG_GENERIC_SUPPORT
1200 {PCI_DEVICE_ID_NCR_53C810, 0xff, "810a", 4, 8, 4, 1,
1204 {PCI_DEVICE_ID_NCR_53C810, 0xff, "810a", 4, 8, 4, 1,
1205 FE_CACHE_SET|FE_LDSTR|FE_PFEN|FE_BOF}
1208 {PCI_DEVICE_ID_NCR_53C815, 0xff, "815", 4, 8, 4, 64,
1211 {PCI_DEVICE_ID_NCR_53C825, 0x0f, "825", 6, 8, 4, 64,
1212 FE_WIDE|FE_BOF|FE_ERL|FE_DIFF}
1214 {PCI_DEVICE_ID_NCR_53C825, 0xff, "825a", 6, 8, 4, 2,
1215 FE_WIDE|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM|FE_DIFF}
1217 {PCI_DEVICE_ID_NCR_53C860, 0xff, "860", 4, 8, 5, 1,
1218 FE_ULTRA|FE_CACHE_SET|FE_BOF|FE_LDSTR|FE_PFEN}
1220 {PCI_DEVICE_ID_NCR_53C875, 0x01, "875", 6, 16, 5, 2,
1221 FE_WIDE|FE_ULTRA|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1222 FE_RAM|FE_DIFF|FE_VARCLK}
1224 {PCI_DEVICE_ID_NCR_53C875, 0xff, "875", 6, 16, 5, 2,
1225 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1226 FE_RAM|FE_DIFF|FE_VARCLK}
1228 {PCI_DEVICE_ID_NCR_53C875J, 0xff, "875J", 6, 16, 5, 2,
1229 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1230 FE_RAM|FE_DIFF|FE_VARCLK}
1232 {PCI_DEVICE_ID_NCR_53C885, 0xff, "885", 6, 16, 5, 2,
1233 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1234 FE_RAM|FE_DIFF|FE_VARCLK}
1236 #ifdef SYM_DEBUG_GENERIC_SUPPORT
1237 {PCI_DEVICE_ID_NCR_53C895, 0xff, "895", 6, 31, 7, 2,
1238 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|
1242 {PCI_DEVICE_ID_NCR_53C895, 0xff, "895", 6, 31, 7, 2,
1243 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1247 {PCI_DEVICE_ID_NCR_53C896, 0xff, "896", 6, 31, 7, 4,
1248 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1249 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ}
1251 {PCI_DEVICE_ID_LSI_53C895A, 0xff, "895a", 6, 31, 7, 4,
1252 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1253 FE_RAM|FE_RAM8K|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ}
1255 {PCI_DEVICE_ID_LSI_53C875A, 0xff, "875a", 6, 31, 7, 4,
1256 FE_WIDE|FE_ULTRA|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1257 FE_RAM|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ}
1259 {PCI_DEVICE_ID_LSI_53C1010_33, 0x00, "1010-33", 6, 31, 7, 8,
1260 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN|
1261 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC|
1264 {PCI_DEVICE_ID_LSI_53C1010_33, 0xff, "1010-33", 6, 31, 7, 8,
1265 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN|
1266 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC|
1269 {PCI_DEVICE_ID_LSI_53C1010_66, 0xff, "1010-66", 6, 31, 7, 8,
1270 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN|
1271 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_66MHZ|FE_CRC|
1274 {PCI_DEVICE_ID_LSI_53C1510, 0xff, "1510d", 6, 31, 7, 4,
1275 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1276 FE_RAM|FE_IO256|FE_LEDC}
1279 #define sym_num_devs \
1280 (sizeof(sym_dev_table) / sizeof(sym_dev_table[0]))
1283 * Look up the chip table.
1285 * Return a pointer to the chip entry if found,
1289 sym_lookup_chip_table (u_short device_id, u_char revision)
1291 struct sym_chip *chip;
1294 for (i = 0; i < sym_num_devs; i++) {
1295 chip = &sym_dev_table[i];
1296 if (device_id != chip->device_id)
1298 if (revision > chip->revision_id)
1306 #if SYM_CONF_DMA_ADDRESSING_MODE == 2
1308 * Lookup the 64 bit DMA segments map.
1309 * This is only used if the direct mapping
1310 * has been unsuccessful.
1312 int sym_lookup_dmap(struct sym_hcb *np, u32 h, int s)
1319 /* Look up existing mappings */
1320 for (i = SYM_DMAP_SIZE-1; i > 0; i--) {
1321 if (h == np->dmap_bah[i])
1324 /* If direct mapping is free, get it */
1325 if (!np->dmap_bah[s])
1327 /* Collision -> lookup free mappings */
1328 for (s = SYM_DMAP_SIZE-1; s > 0; s--) {
1329 if (!np->dmap_bah[s])
1333 panic("sym: ran out of 64 bit DMA segment registers");
1336 np->dmap_bah[s] = h;
1342 * Update IO registers scratch C..R so they will be
1343 * in sync. with queued CCB expectations.
1345 static void sym_update_dmap_regs(struct sym_hcb *np)
1349 if (!np->dmap_dirty)
1351 o = offsetof(struct sym_reg, nc_scrx[0]);
1352 for (i = 0; i < SYM_DMAP_SIZE; i++) {
1353 OUTL_OFF(np, o, np->dmap_bah[i]);
1360 /* Enforce all the fiddly SPI rules and the chip limitations */
1361 static void sym_check_goals(struct sym_hcb *np, struct scsi_target *starget,
1362 struct sym_trans *goal)
1364 if (!spi_support_wide(starget))
1367 if (!spi_support_sync(starget)) {
1375 if (spi_support_dt(starget)) {
1376 if (spi_support_dt_only(starget))
1379 if (goal->offset == 0)
1385 /* Some targets fail to properly negotiate DT in SE mode */
1386 if ((np->scsi_mode != SMODE_LVD) || !(np->features & FE_U3EN))
1390 /* all DT transfers must be wide */
1392 if (goal->offset > np->maxoffs_dt)
1393 goal->offset = np->maxoffs_dt;
1394 if (goal->period < np->minsync_dt)
1395 goal->period = np->minsync_dt;
1396 if (goal->period > np->maxsync_dt)
1397 goal->period = np->maxsync_dt;
1399 goal->iu = goal->qas = 0;
1400 if (goal->offset > np->maxoffs)
1401 goal->offset = np->maxoffs;
1402 if (goal->period < np->minsync)
1403 goal->period = np->minsync;
1404 if (goal->period > np->maxsync)
1405 goal->period = np->maxsync;
1410 * Prepare the next negotiation message if needed.
1412 * Fill in the part of message buffer that contains the
1413 * negotiation and the nego_status field of the CCB.
1414 * Returns the size of the message in bytes.
1416 static int sym_prepare_nego(struct sym_hcb *np, struct sym_ccb *cp, u_char *msgptr)
1418 struct sym_tcb *tp = &np->target[cp->target];
1419 struct scsi_target *starget = tp->starget;
1420 struct sym_trans *goal = &tp->tgoal;
1424 sym_check_goals(np, starget, goal);
1427 * Many devices implement PPR in a buggy way, so only use it if we
1431 (goal->iu || goal->dt || goal->qas || (goal->period < 0xa))) {
1433 } else if (spi_width(starget) != goal->width) {
1435 } else if (spi_period(starget) != goal->period ||
1436 spi_offset(starget) != goal->offset) {
1439 goal->check_nego = 0;
1445 msglen += spi_populate_sync_msg(msgptr + msglen, goal->period,
1449 msglen += spi_populate_width_msg(msgptr + msglen, goal->width);
1452 msglen += spi_populate_ppr_msg(msgptr + msglen, goal->period,
1453 goal->offset, goal->width,
1454 (goal->iu ? PPR_OPT_IU : 0) |
1455 (goal->dt ? PPR_OPT_DT : 0) |
1456 (goal->qas ? PPR_OPT_QAS : 0));
1460 cp->nego_status = nego;
1463 tp->nego_cp = cp; /* Keep track a nego will be performed */
1464 if (DEBUG_FLAGS & DEBUG_NEGO) {
1465 sym_print_nego_msg(np, cp->target,
1466 nego == NS_SYNC ? "sync msgout" :
1467 nego == NS_WIDE ? "wide msgout" :
1468 "ppr msgout", msgptr);
1476 * Insert a job into the start queue.
1478 void sym_put_start_queue(struct sym_hcb *np, struct sym_ccb *cp)
1482 #ifdef SYM_CONF_IARB_SUPPORT
1484 * If the previously queued CCB is not yet done,
1485 * set the IARB hint. The SCRIPTS will go with IARB
1486 * for this job when starting the previous one.
1487 * We leave devices a chance to win arbitration by
1488 * not using more than 'iarb_max' consecutive
1489 * immediate arbitrations.
1491 if (np->last_cp && np->iarb_count < np->iarb_max) {
1492 np->last_cp->host_flags |= HF_HINT_IARB;
1500 #if SYM_CONF_DMA_ADDRESSING_MODE == 2
1502 * Make SCRIPTS aware of the 64 bit DMA
1503 * segment registers not being up-to-date.
1506 cp->host_xflags |= HX_DMAP_DIRTY;
1510 * Insert first the idle task and then our job.
1511 * The MBs should ensure proper ordering.
1513 qidx = np->squeueput + 2;
1514 if (qidx >= MAX_QUEUE*2) qidx = 0;
1516 np->squeue [qidx] = cpu_to_scr(np->idletask_ba);
1517 MEMORY_WRITE_BARRIER();
1518 np->squeue [np->squeueput] = cpu_to_scr(cp->ccb_ba);
1520 np->squeueput = qidx;
1522 if (DEBUG_FLAGS & DEBUG_QUEUE)
1523 printf ("%s: queuepos=%d.\n", sym_name (np), np->squeueput);
1526 * Script processor may be waiting for reselect.
1529 MEMORY_WRITE_BARRIER();
1530 OUTB(np, nc_istat, SIGP|np->istat_sem);
1533 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
1535 * Start next ready-to-start CCBs.
1537 void sym_start_next_ccbs(struct sym_hcb *np, struct sym_lcb *lp, int maxn)
1543 * Paranoia, as usual. :-)
1545 assert(!lp->started_tags || !lp->started_no_tag);
1548 * Try to start as many commands as asked by caller.
1549 * Prevent from having both tagged and untagged
1550 * commands queued to the device at the same time.
1553 qp = sym_remque_head(&lp->waiting_ccbq);
1556 cp = sym_que_entry(qp, struct sym_ccb, link2_ccbq);
1557 if (cp->tag != NO_TAG) {
1558 if (lp->started_no_tag ||
1559 lp->started_tags >= lp->started_max) {
1560 sym_insque_head(qp, &lp->waiting_ccbq);
1563 lp->itlq_tbl[cp->tag] = cpu_to_scr(cp->ccb_ba);
1565 cpu_to_scr(SCRIPTA_BA(np, resel_tag));
1568 if (lp->started_no_tag || lp->started_tags) {
1569 sym_insque_head(qp, &lp->waiting_ccbq);
1572 lp->head.itl_task_sa = cpu_to_scr(cp->ccb_ba);
1574 cpu_to_scr(SCRIPTA_BA(np, resel_no_tag));
1575 ++lp->started_no_tag;
1578 sym_insque_tail(qp, &lp->started_ccbq);
1579 sym_put_start_queue(np, cp);
1582 #endif /* SYM_OPT_HANDLE_DEVICE_QUEUEING */
1585 * The chip may have completed jobs. Look at the DONE QUEUE.
1587 * On paper, memory read barriers may be needed here to
1588 * prevent out of order LOADs by the CPU from having
1589 * prefetched stale data prior to DMA having occurred.
1591 static int sym_wakeup_done (struct sym_hcb *np)
1600 /* MEMORY_READ_BARRIER(); */
1602 dsa = scr_to_cpu(np->dqueue[i]);
1606 if ((i = i+2) >= MAX_QUEUE*2)
1609 cp = sym_ccb_from_dsa(np, dsa);
1611 MEMORY_READ_BARRIER();
1612 sym_complete_ok (np, cp);
1616 printf ("%s: bad DSA (%x) in done queue.\n",
1617 sym_name(np), (u_int) dsa);
1625 * Complete all CCBs queued to the COMP queue.
1627 * These CCBs are assumed:
1628 * - Not to be referenced either by devices or
1629 * SCRIPTS-related queues and datas.
1630 * - To have to be completed with an error condition
1633 * The device queue freeze count is incremented
1634 * for each CCB that does not prevent this.
1635 * This function is called when all CCBs involved
1636 * in error handling/recovery have been reaped.
1638 static void sym_flush_comp_queue(struct sym_hcb *np, int cam_status)
1643 while ((qp = sym_remque_head(&np->comp_ccbq)) != 0) {
1644 struct scsi_cmnd *cmd;
1645 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
1646 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq);
1647 /* Leave quiet CCBs waiting for resources */
1648 if (cp->host_status == HS_WAIT)
1652 sym_set_cam_status(cmd, cam_status);
1653 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
1654 if (sym_get_cam_status(cmd) == DID_SOFT_ERROR) {
1655 struct sym_tcb *tp = &np->target[cp->target];
1656 struct sym_lcb *lp = sym_lp(tp, cp->lun);
1658 sym_remque(&cp->link2_ccbq);
1659 sym_insque_tail(&cp->link2_ccbq,
1662 if (cp->tag != NO_TAG)
1665 --lp->started_no_tag;
1672 sym_free_ccb(np, cp);
1673 sym_xpt_done(np, cmd);
1678 * Complete all active CCBs with error.
1679 * Used on CHIP/SCSI RESET.
1681 static void sym_flush_busy_queue (struct sym_hcb *np, int cam_status)
1684 * Move all active CCBs to the COMP queue
1685 * and flush this queue.
1687 sym_que_splice(&np->busy_ccbq, &np->comp_ccbq);
1688 sym_que_init(&np->busy_ccbq);
1689 sym_flush_comp_queue(np, cam_status);
1696 * 0: initialisation.
1697 * 1: SCSI BUS RESET delivered or received.
1698 * 2: SCSI BUS MODE changed.
1700 void sym_start_up (struct sym_hcb *np, int reason)
1706 * Reset chip if asked, otherwise just clear fifos.
1711 OUTB(np, nc_stest3, TE|CSF);
1712 OUTONB(np, nc_ctest3, CLF);
1718 phys = np->squeue_ba;
1719 for (i = 0; i < MAX_QUEUE*2; i += 2) {
1720 np->squeue[i] = cpu_to_scr(np->idletask_ba);
1721 np->squeue[i+1] = cpu_to_scr(phys + (i+2)*4);
1723 np->squeue[MAX_QUEUE*2-1] = cpu_to_scr(phys);
1726 * Start at first entry.
1733 phys = np->dqueue_ba;
1734 for (i = 0; i < MAX_QUEUE*2; i += 2) {
1736 np->dqueue[i+1] = cpu_to_scr(phys + (i+2)*4);
1738 np->dqueue[MAX_QUEUE*2-1] = cpu_to_scr(phys);
1741 * Start at first entry.
1746 * Install patches in scripts.
1747 * This also let point to first position the start
1748 * and done queue pointers used from SCRIPTS.
1753 * Wakeup all pending jobs.
1755 sym_flush_busy_queue(np, DID_RESET);
1760 OUTB(np, nc_istat, 0x00); /* Remove Reset, abort */
1762 udelay(2000); /* The 895 needs time for the bus mode to settle */
1764 OUTB(np, nc_scntl0, np->rv_scntl0 | 0xc0);
1765 /* full arb., ena parity, par->ATN */
1766 OUTB(np, nc_scntl1, 0x00); /* odd parity, and remove CRST!! */
1768 sym_selectclock(np, np->rv_scntl3); /* Select SCSI clock */
1770 OUTB(np, nc_scid , RRE|np->myaddr); /* Adapter SCSI address */
1771 OUTW(np, nc_respid, 1ul<<np->myaddr); /* Id to respond to */
1772 OUTB(np, nc_istat , SIGP ); /* Signal Process */
1773 OUTB(np, nc_dmode , np->rv_dmode); /* Burst length, dma mode */
1774 OUTB(np, nc_ctest5, np->rv_ctest5); /* Large fifo + large burst */
1776 OUTB(np, nc_dcntl , NOCOM|np->rv_dcntl); /* Protect SFBR */
1777 OUTB(np, nc_ctest3, np->rv_ctest3); /* Write and invalidate */
1778 OUTB(np, nc_ctest4, np->rv_ctest4); /* Master parity checking */
1780 /* Extended Sreq/Sack filtering not supported on the C10 */
1781 if (np->features & FE_C10)
1782 OUTB(np, nc_stest2, np->rv_stest2);
1784 OUTB(np, nc_stest2, EXT|np->rv_stest2);
1786 OUTB(np, nc_stest3, TE); /* TolerANT enable */
1787 OUTB(np, nc_stime0, 0x0c); /* HTH disabled STO 0.25 sec */
1790 * For now, disable AIP generation on C1010-66.
1792 if (np->device_id == PCI_DEVICE_ID_LSI_53C1010_66)
1793 OUTB(np, nc_aipcntl1, DISAIP);
1796 * C10101 rev. 0 errata.
1797 * Errant SGE's when in narrow. Write bits 4 & 5 of
1798 * STEST1 register to disable SGE. We probably should do
1799 * that from SCRIPTS for each selection/reselection, but
1800 * I just don't want. :)
1802 if (np->device_id == PCI_DEVICE_ID_LSI_53C1010_33 &&
1803 np->revision_id < 1)
1804 OUTB(np, nc_stest1, INB(np, nc_stest1) | 0x30);
1807 * DEL 441 - 53C876 Rev 5 - Part Number 609-0392787/2788 - ITEM 2.
1808 * Disable overlapped arbitration for some dual function devices,
1809 * regardless revision id (kind of post-chip-design feature. ;-))
1811 if (np->device_id == PCI_DEVICE_ID_NCR_53C875)
1812 OUTB(np, nc_ctest0, (1<<5));
1813 else if (np->device_id == PCI_DEVICE_ID_NCR_53C896)
1814 np->rv_ccntl0 |= DPR;
1817 * Write CCNTL0/CCNTL1 for chips capable of 64 bit addressing
1818 * and/or hardware phase mismatch, since only such chips
1819 * seem to support those IO registers.
1821 if (np->features & (FE_DAC|FE_NOPM)) {
1822 OUTB(np, nc_ccntl0, np->rv_ccntl0);
1823 OUTB(np, nc_ccntl1, np->rv_ccntl1);
1826 #if SYM_CONF_DMA_ADDRESSING_MODE == 2
1828 * Set up scratch C and DRS IO registers to map the 32 bit
1829 * DMA address range our data structures are located in.
1832 np->dmap_bah[0] = 0; /* ??? */
1833 OUTL(np, nc_scrx[0], np->dmap_bah[0]);
1834 OUTL(np, nc_drs, np->dmap_bah[0]);
1839 * If phase mismatch handled by scripts (895A/896/1010),
1840 * set PM jump addresses.
1842 if (np->features & FE_NOPM) {
1843 OUTL(np, nc_pmjad1, SCRIPTB_BA(np, pm_handle));
1844 OUTL(np, nc_pmjad2, SCRIPTB_BA(np, pm_handle));
1848 * Enable GPIO0 pin for writing if LED support from SCRIPTS.
1849 * Also set GPIO5 and clear GPIO6 if hardware LED control.
1851 if (np->features & FE_LED0)
1852 OUTB(np, nc_gpcntl, INB(np, nc_gpcntl) & ~0x01);
1853 else if (np->features & FE_LEDC)
1854 OUTB(np, nc_gpcntl, (INB(np, nc_gpcntl) & ~0x41) | 0x20);
1859 OUTW(np, nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR);
1860 OUTB(np, nc_dien , MDPE|BF|SSI|SIR|IID);
1863 * For 895/6 enable SBMC interrupt and save current SCSI bus mode.
1864 * Try to eat the spurious SBMC interrupt that may occur when
1865 * we reset the chip but not the SCSI BUS (at initialization).
1867 if (np->features & (FE_ULTRA2|FE_ULTRA3)) {
1868 OUTONW(np, nc_sien, SBMC);
1874 np->scsi_mode = INB(np, nc_stest4) & SMODE;
1878 * Fill in target structure.
1879 * Reinitialize usrsync.
1880 * Reinitialize usrwide.
1881 * Prepare sync negotiation according to actual SCSI bus mode.
1883 for (i=0;i<SYM_CONF_MAX_TARGET;i++) {
1884 struct sym_tcb *tp = &np->target[i];
1888 tp->head.wval = np->rv_scntl3;
1893 * Download SCSI SCRIPTS to on-chip RAM if present,
1894 * and start script processor.
1895 * We do the download preferently from the CPU.
1896 * For platforms that may not support PCI memory mapping,
1897 * we use simple SCRIPTS that performs MEMORY MOVEs.
1899 phys = SCRIPTA_BA(np, init);
1901 if (sym_verbose >= 2)
1902 printf("%s: Downloading SCSI SCRIPTS.\n", sym_name(np));
1903 memcpy_toio(np->s.ramaddr, np->scripta0, np->scripta_sz);
1904 if (np->ram_ws == 8192) {
1905 memcpy_toio(np->s.ramaddr + 4096, np->scriptb0, np->scriptb_sz);
1906 phys = scr_to_cpu(np->scr_ram_seg);
1907 OUTL(np, nc_mmws, phys);
1908 OUTL(np, nc_mmrs, phys);
1909 OUTL(np, nc_sfs, phys);
1910 phys = SCRIPTB_BA(np, start64);
1916 OUTL(np, nc_dsa, np->hcb_ba);
1920 * Notify the XPT about the RESET condition.
1923 sym_xpt_async_bus_reset(np);
1927 * Switch trans mode for current job and its target.
1929 static void sym_settrans(struct sym_hcb *np, int target, u_char opts, u_char ofs,
1930 u_char per, u_char wide, u_char div, u_char fak)
1933 u_char sval, wval, uval;
1934 struct sym_tcb *tp = &np->target[target];
1936 assert(target == (INB(np, nc_sdid) & 0x0f));
1938 sval = tp->head.sval;
1939 wval = tp->head.wval;
1940 uval = tp->head.uval;
1943 printf("XXXX sval=%x wval=%x uval=%x (%x)\n",
1944 sval, wval, uval, np->rv_scntl3);
1949 if (!(np->features & FE_C10))
1950 sval = (sval & ~0x1f) | ofs;
1952 sval = (sval & ~0x3f) | ofs;
1955 * Set the sync divisor and extra clock factor.
1958 wval = (wval & ~0x70) | ((div+1) << 4);
1959 if (!(np->features & FE_C10))
1960 sval = (sval & ~0xe0) | (fak << 5);
1962 uval = uval & ~(XCLKH_ST|XCLKH_DT|XCLKS_ST|XCLKS_DT);
1963 if (fak >= 1) uval |= (XCLKH_ST|XCLKH_DT);
1964 if (fak >= 2) uval |= (XCLKS_ST|XCLKS_DT);
1969 * Set the bus width.
1976 * Set misc. ultra enable bits.
1978 if (np->features & FE_C10) {
1979 uval = uval & ~(U3EN|AIPCKEN);
1981 assert(np->features & FE_U3EN);
1985 wval = wval & ~ULTRA;
1986 if (per <= 12) wval |= ULTRA;
1990 * Stop there if sync parameters are unchanged.
1992 if (tp->head.sval == sval &&
1993 tp->head.wval == wval &&
1994 tp->head.uval == uval)
1996 tp->head.sval = sval;
1997 tp->head.wval = wval;
1998 tp->head.uval = uval;
2001 * Disable extended Sreq/Sack filtering if per < 50.
2002 * Not supported on the C1010.
2004 if (per < 50 && !(np->features & FE_C10))
2005 OUTOFFB(np, nc_stest2, EXT);
2008 * set actual value and sync_status
2010 OUTB(np, nc_sxfer, tp->head.sval);
2011 OUTB(np, nc_scntl3, tp->head.wval);
2013 if (np->features & FE_C10) {
2014 OUTB(np, nc_scntl4, tp->head.uval);
2018 * patch ALL busy ccbs of this target.
2020 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
2022 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
2023 if (cp->target != target)
2025 cp->phys.select.sel_scntl3 = tp->head.wval;
2026 cp->phys.select.sel_sxfer = tp->head.sval;
2027 if (np->features & FE_C10) {
2028 cp->phys.select.sel_scntl4 = tp->head.uval;
2034 * We received a WDTR.
2035 * Let everything be aware of the changes.
2037 static void sym_setwide(struct sym_hcb *np, int target, u_char wide)
2039 struct sym_tcb *tp = &np->target[target];
2040 struct scsi_target *starget = tp->starget;
2042 if (spi_width(starget) == wide)
2045 sym_settrans(np, target, 0, 0, 0, wide, 0, 0);
2047 tp->tgoal.width = wide;
2048 spi_offset(starget) = 0;
2049 spi_period(starget) = 0;
2050 spi_width(starget) = wide;
2051 spi_iu(starget) = 0;
2052 spi_dt(starget) = 0;
2053 spi_qas(starget) = 0;
2055 if (sym_verbose >= 3)
2056 spi_display_xfer_agreement(starget);
2060 * We received a SDTR.
2061 * Let everything be aware of the changes.
2064 sym_setsync(struct sym_hcb *np, int target,
2065 u_char ofs, u_char per, u_char div, u_char fak)
2067 struct sym_tcb *tp = &np->target[target];
2068 struct scsi_target *starget = tp->starget;
2069 u_char wide = (tp->head.wval & EWS) ? BUS_16_BIT : BUS_8_BIT;
2071 sym_settrans(np, target, 0, ofs, per, wide, div, fak);
2073 spi_period(starget) = per;
2074 spi_offset(starget) = ofs;
2075 spi_iu(starget) = spi_dt(starget) = spi_qas(starget) = 0;
2077 if (!tp->tgoal.dt && !tp->tgoal.iu && !tp->tgoal.qas) {
2078 tp->tgoal.period = per;
2079 tp->tgoal.offset = ofs;
2080 tp->tgoal.check_nego = 0;
2083 spi_display_xfer_agreement(starget);
2087 * We received a PPR.
2088 * Let everything be aware of the changes.
2091 sym_setpprot(struct sym_hcb *np, int target, u_char opts, u_char ofs,
2092 u_char per, u_char wide, u_char div, u_char fak)
2094 struct sym_tcb *tp = &np->target[target];
2095 struct scsi_target *starget = tp->starget;
2097 sym_settrans(np, target, opts, ofs, per, wide, div, fak);
2099 spi_width(starget) = tp->tgoal.width = wide;
2100 spi_period(starget) = tp->tgoal.period = per;
2101 spi_offset(starget) = tp->tgoal.offset = ofs;
2102 spi_iu(starget) = tp->tgoal.iu = !!(opts & PPR_OPT_IU);
2103 spi_dt(starget) = tp->tgoal.dt = !!(opts & PPR_OPT_DT);
2104 spi_qas(starget) = tp->tgoal.qas = !!(opts & PPR_OPT_QAS);
2105 tp->tgoal.check_nego = 0;
2107 spi_display_xfer_agreement(starget);
2111 * generic recovery from scsi interrupt
2113 * The doc says that when the chip gets an SCSI interrupt,
2114 * it tries to stop in an orderly fashion, by completing
2115 * an instruction fetch that had started or by flushing
2116 * the DMA fifo for a write to memory that was executing.
2117 * Such a fashion is not enough to know if the instruction
2118 * that was just before the current DSP value has been
2121 * There are some small SCRIPTS sections that deal with
2122 * the start queue and the done queue that may break any
2123 * assomption from the C code if we are interrupted
2124 * inside, so we reset if this happens. Btw, since these
2125 * SCRIPTS sections are executed while the SCRIPTS hasn't
2126 * started SCSI operations, it is very unlikely to happen.
2128 * All the driver data structures are supposed to be
2129 * allocated from the same 4 GB memory window, so there
2130 * is a 1 to 1 relationship between DSA and driver data
2131 * structures. Since we are careful :) to invalidate the
2132 * DSA when we complete a command or when the SCRIPTS
2133 * pushes a DSA into a queue, we can trust it when it
2136 static void sym_recover_scsi_int (struct sym_hcb *np, u_char hsts)
2138 u32 dsp = INL(np, nc_dsp);
2139 u32 dsa = INL(np, nc_dsa);
2140 struct sym_ccb *cp = sym_ccb_from_dsa(np, dsa);
2143 * If we haven't been interrupted inside the SCRIPTS
2144 * critical pathes, we can safely restart the SCRIPTS
2145 * and trust the DSA value if it matches a CCB.
2147 if ((!(dsp > SCRIPTA_BA(np, getjob_begin) &&
2148 dsp < SCRIPTA_BA(np, getjob_end) + 1)) &&
2149 (!(dsp > SCRIPTA_BA(np, ungetjob) &&
2150 dsp < SCRIPTA_BA(np, reselect) + 1)) &&
2151 (!(dsp > SCRIPTB_BA(np, sel_for_abort) &&
2152 dsp < SCRIPTB_BA(np, sel_for_abort_1) + 1)) &&
2153 (!(dsp > SCRIPTA_BA(np, done) &&
2154 dsp < SCRIPTA_BA(np, done_end) + 1))) {
2155 OUTB(np, nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */
2156 OUTB(np, nc_stest3, TE|CSF); /* clear scsi fifo */
2158 * If we have a CCB, let the SCRIPTS call us back for
2159 * the handling of the error with SCRATCHA filled with
2160 * STARTPOS. This way, we will be able to freeze the
2161 * device queue and requeue awaiting IOs.
2164 cp->host_status = hsts;
2165 OUTL_DSP(np, SCRIPTA_BA(np, complete_error));
2168 * Otherwise just restart the SCRIPTS.
2171 OUTL(np, nc_dsa, 0xffffff);
2172 OUTL_DSP(np, SCRIPTA_BA(np, start));
2181 sym_start_reset(np);
2185 * chip exception handler for selection timeout
2187 static void sym_int_sto (struct sym_hcb *np)
2189 u32 dsp = INL(np, nc_dsp);
2191 if (DEBUG_FLAGS & DEBUG_TINY) printf ("T");
2193 if (dsp == SCRIPTA_BA(np, wf_sel_done) + 8)
2194 sym_recover_scsi_int(np, HS_SEL_TIMEOUT);
2196 sym_start_reset(np);
2200 * chip exception handler for unexpected disconnect
2202 static void sym_int_udc (struct sym_hcb *np)
2204 printf ("%s: unexpected disconnect\n", sym_name(np));
2205 sym_recover_scsi_int(np, HS_UNEXPECTED);
2209 * chip exception handler for SCSI bus mode change
2211 * spi2-r12 11.2.3 says a transceiver mode change must
2212 * generate a reset event and a device that detects a reset
2213 * event shall initiate a hard reset. It says also that a
2214 * device that detects a mode change shall set data transfer
2215 * mode to eight bit asynchronous, etc...
2216 * So, just reinitializing all except chip should be enough.
2218 static void sym_int_sbmc (struct sym_hcb *np)
2220 u_char scsi_mode = INB(np, nc_stest4) & SMODE;
2225 printf("%s: SCSI BUS mode change from %s to %s.\n", sym_name(np),
2226 sym_scsi_bus_mode(np->scsi_mode), sym_scsi_bus_mode(scsi_mode));
2229 * Should suspend command processing for a few seconds and
2230 * reinitialize all except the chip.
2232 sym_start_up (np, 2);
2236 * chip exception handler for SCSI parity error.
2238 * When the chip detects a SCSI parity error and is
2239 * currently executing a (CH)MOV instruction, it does
2240 * not interrupt immediately, but tries to finish the
2241 * transfer of the current scatter entry before
2242 * interrupting. The following situations may occur:
2244 * - The complete scatter entry has been transferred
2245 * without the device having changed phase.
2246 * The chip will then interrupt with the DSP pointing
2247 * to the instruction that follows the MOV.
2249 * - A phase mismatch occurs before the MOV finished
2250 * and phase errors are to be handled by the C code.
2251 * The chip will then interrupt with both PAR and MA
2254 * - A phase mismatch occurs before the MOV finished and
2255 * phase errors are to be handled by SCRIPTS.
2256 * The chip will load the DSP with the phase mismatch
2257 * JUMP address and interrupt the host processor.
2259 static void sym_int_par (struct sym_hcb *np, u_short sist)
2261 u_char hsts = INB(np, HS_PRT);
2262 u32 dsp = INL(np, nc_dsp);
2263 u32 dbc = INL(np, nc_dbc);
2264 u32 dsa = INL(np, nc_dsa);
2265 u_char sbcl = INB(np, nc_sbcl);
2266 u_char cmd = dbc >> 24;
2267 int phase = cmd & 7;
2268 struct sym_ccb *cp = sym_ccb_from_dsa(np, dsa);
2270 printf("%s: SCSI parity error detected: SCR1=%d DBC=%x SBCL=%x\n",
2271 sym_name(np), hsts, dbc, sbcl);
2274 * Check that the chip is connected to the SCSI BUS.
2276 if (!(INB(np, nc_scntl1) & ISCON)) {
2277 sym_recover_scsi_int(np, HS_UNEXPECTED);
2282 * If the nexus is not clearly identified, reset the bus.
2283 * We will try to do better later.
2289 * Check instruction was a MOV, direction was INPUT and
2292 if ((cmd & 0xc0) || !(phase & 1) || !(sbcl & 0x8))
2296 * Keep track of the parity error.
2298 OUTONB(np, HF_PRT, HF_EXT_ERR);
2299 cp->xerr_status |= XE_PARITY_ERR;
2302 * Prepare the message to send to the device.
2304 np->msgout[0] = (phase == 7) ? M_PARITY : M_ID_ERROR;
2307 * If the old phase was DATA IN phase, we have to deal with
2308 * the 3 situations described above.
2309 * For other input phases (MSG IN and STATUS), the device
2310 * must resend the whole thing that failed parity checking
2311 * or signal error. So, jumping to dispatcher should be OK.
2313 if (phase == 1 || phase == 5) {
2314 /* Phase mismatch handled by SCRIPTS */
2315 if (dsp == SCRIPTB_BA(np, pm_handle))
2317 /* Phase mismatch handled by the C code */
2320 /* No phase mismatch occurred */
2322 sym_set_script_dp (np, cp, dsp);
2323 OUTL_DSP(np, SCRIPTA_BA(np, dispatch));
2326 else if (phase == 7) /* We definitely cannot handle parity errors */
2327 #if 1 /* in message-in phase due to the relection */
2328 goto reset_all; /* path and various message anticipations. */
2330 OUTL_DSP(np, SCRIPTA_BA(np, clrack));
2333 OUTL_DSP(np, SCRIPTA_BA(np, dispatch));
2337 sym_start_reset(np);
2342 * chip exception handler for phase errors.
2344 * We have to construct a new transfer descriptor,
2345 * to transfer the rest of the current block.
2347 static void sym_int_ma (struct sym_hcb *np)
2360 u_char hflags, hflags0;
2364 dsp = INL(np, nc_dsp);
2365 dbc = INL(np, nc_dbc);
2366 dsa = INL(np, nc_dsa);
2369 rest = dbc & 0xffffff;
2373 * locate matching cp if any.
2375 cp = sym_ccb_from_dsa(np, dsa);
2378 * Donnot take into account dma fifo and various buffers in
2379 * INPUT phase since the chip flushes everything before
2380 * raising the MA interrupt for interrupted INPUT phases.
2381 * For DATA IN phase, we will check for the SWIDE later.
2383 if ((cmd & 7) != 1 && (cmd & 7) != 5) {
2386 if (np->features & FE_DFBC)
2387 delta = INW(np, nc_dfbc);
2392 * Read DFIFO, CTEST[4-6] using 1 PCI bus ownership.
2394 dfifo = INL(np, nc_dfifo);
2397 * Calculate remaining bytes in DMA fifo.
2398 * (CTEST5 = dfifo >> 16)
2400 if (dfifo & (DFS << 16))
2401 delta = ((((dfifo >> 8) & 0x300) |
2402 (dfifo & 0xff)) - rest) & 0x3ff;
2404 delta = ((dfifo & 0xff) - rest) & 0x7f;
2408 * The data in the dma fifo has not been transfered to
2409 * the target -> add the amount to the rest
2410 * and clear the data.
2411 * Check the sstat2 register in case of wide transfer.
2414 ss0 = INB(np, nc_sstat0);
2415 if (ss0 & OLF) rest++;
2416 if (!(np->features & FE_C10))
2417 if (ss0 & ORF) rest++;
2418 if (cp && (cp->phys.select.sel_scntl3 & EWS)) {
2419 ss2 = INB(np, nc_sstat2);
2420 if (ss2 & OLF1) rest++;
2421 if (!(np->features & FE_C10))
2422 if (ss2 & ORF1) rest++;
2428 OUTB(np, nc_ctest3, np->rv_ctest3 | CLF); /* dma fifo */
2429 OUTB(np, nc_stest3, TE|CSF); /* scsi fifo */
2433 * log the information
2435 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_PHASE))
2436 printf ("P%x%x RL=%d D=%d ", cmd&7, INB(np, nc_sbcl)&7,
2437 (unsigned) rest, (unsigned) delta);
2440 * try to find the interrupted script command,
2441 * and the address at which to continue.
2445 if (dsp > np->scripta_ba &&
2446 dsp <= np->scripta_ba + np->scripta_sz) {
2447 vdsp = (u32 *)((char*)np->scripta0 + (dsp-np->scripta_ba-8));
2450 else if (dsp > np->scriptb_ba &&
2451 dsp <= np->scriptb_ba + np->scriptb_sz) {
2452 vdsp = (u32 *)((char*)np->scriptb0 + (dsp-np->scriptb_ba-8));
2457 * log the information
2459 if (DEBUG_FLAGS & DEBUG_PHASE) {
2460 printf ("\nCP=%p DSP=%x NXT=%x VDSP=%p CMD=%x ",
2461 cp, (unsigned)dsp, (unsigned)nxtdsp, vdsp, cmd);
2465 printf ("%s: interrupted SCRIPT address not found.\n",
2471 printf ("%s: SCSI phase error fixup: CCB already dequeued.\n",
2477 * get old startaddress and old length.
2479 oadr = scr_to_cpu(vdsp[1]);
2481 if (cmd & 0x10) { /* Table indirect */
2482 tblp = (u32 *) ((char*) &cp->phys + oadr);
2483 olen = scr_to_cpu(tblp[0]);
2484 oadr = scr_to_cpu(tblp[1]);
2487 olen = scr_to_cpu(vdsp[0]) & 0xffffff;
2490 if (DEBUG_FLAGS & DEBUG_PHASE) {
2491 printf ("OCMD=%x\nTBLP=%p OLEN=%x OADR=%x\n",
2492 (unsigned) (scr_to_cpu(vdsp[0]) >> 24),
2499 * check cmd against assumed interrupted script command.
2500 * If dt data phase, the MOVE instruction hasn't bit 4 of
2503 if (((cmd & 2) ? cmd : (cmd & ~4)) != (scr_to_cpu(vdsp[0]) >> 24)) {
2504 sym_print_addr(cp->cmd,
2505 "internal error: cmd=%02x != %02x=(vdsp[0] >> 24)\n",
2506 cmd, scr_to_cpu(vdsp[0]) >> 24);
2512 * if old phase not dataphase, leave here.
2515 sym_print_addr(cp->cmd,
2516 "phase change %x-%x %d@%08x resid=%d.\n",
2517 cmd&7, INB(np, nc_sbcl)&7, (unsigned)olen,
2518 (unsigned)oadr, (unsigned)rest);
2519 goto unexpected_phase;
2523 * Choose the correct PM save area.
2525 * Look at the PM_SAVE SCRIPT if you want to understand
2526 * this stuff. The equivalent code is implemented in
2527 * SCRIPTS for the 895A, 896 and 1010 that are able to
2528 * handle PM from the SCRIPTS processor.
2530 hflags0 = INB(np, HF_PRT);
2533 if (hflags & (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED)) {
2534 if (hflags & HF_IN_PM0)
2535 nxtdsp = scr_to_cpu(cp->phys.pm0.ret);
2536 else if (hflags & HF_IN_PM1)
2537 nxtdsp = scr_to_cpu(cp->phys.pm1.ret);
2539 if (hflags & HF_DP_SAVED)
2540 hflags ^= HF_ACT_PM;
2543 if (!(hflags & HF_ACT_PM)) {
2545 newcmd = SCRIPTA_BA(np, pm0_data);
2549 newcmd = SCRIPTA_BA(np, pm1_data);
2552 hflags &= ~(HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED);
2553 if (hflags != hflags0)
2554 OUTB(np, HF_PRT, hflags);
2557 * fillin the phase mismatch context
2559 pm->sg.addr = cpu_to_scr(oadr + olen - rest);
2560 pm->sg.size = cpu_to_scr(rest);
2561 pm->ret = cpu_to_scr(nxtdsp);
2564 * If we have a SWIDE,
2565 * - prepare the address to write the SWIDE from SCRIPTS,
2566 * - compute the SCRIPTS address to restart from,
2567 * - move current data pointer context by one byte.
2569 nxtdsp = SCRIPTA_BA(np, dispatch);
2570 if ((cmd & 7) == 1 && cp && (cp->phys.select.sel_scntl3 & EWS) &&
2571 (INB(np, nc_scntl2) & WSR)) {
2575 * Set up the table indirect for the MOVE
2576 * of the residual byte and adjust the data
2579 tmp = scr_to_cpu(pm->sg.addr);
2580 cp->phys.wresid.addr = cpu_to_scr(tmp);
2581 pm->sg.addr = cpu_to_scr(tmp + 1);
2582 tmp = scr_to_cpu(pm->sg.size);
2583 cp->phys.wresid.size = cpu_to_scr((tmp&0xff000000) | 1);
2584 pm->sg.size = cpu_to_scr(tmp - 1);
2587 * If only the residual byte is to be moved,
2588 * no PM context is needed.
2590 if ((tmp&0xffffff) == 1)
2594 * Prepare the address of SCRIPTS that will
2595 * move the residual byte to memory.
2597 nxtdsp = SCRIPTB_BA(np, wsr_ma_helper);
2600 if (DEBUG_FLAGS & DEBUG_PHASE) {
2601 sym_print_addr(cp->cmd, "PM %x %x %x / %x %x %x.\n",
2602 hflags0, hflags, newcmd,
2603 (unsigned)scr_to_cpu(pm->sg.addr),
2604 (unsigned)scr_to_cpu(pm->sg.size),
2605 (unsigned)scr_to_cpu(pm->ret));
2609 * Restart the SCRIPTS processor.
2611 sym_set_script_dp (np, cp, newcmd);
2612 OUTL_DSP(np, nxtdsp);
2616 * Unexpected phase changes that occurs when the current phase
2617 * is not a DATA IN or DATA OUT phase are due to error conditions.
2618 * Such event may only happen when the SCRIPTS is using a
2619 * multibyte SCSI MOVE.
2621 * Phase change Some possible cause
2623 * COMMAND --> MSG IN SCSI parity error detected by target.
2624 * COMMAND --> STATUS Bad command or refused by target.
2625 * MSG OUT --> MSG IN Message rejected by target.
2626 * MSG OUT --> COMMAND Bogus target that discards extended
2627 * negotiation messages.
2629 * The code below does not care of the new phase and so
2630 * trusts the target. Why to annoy it ?
2631 * If the interrupted phase is COMMAND phase, we restart at
2633 * If a target does not get all the messages after selection,
2634 * the code assumes blindly that the target discards extended
2635 * messages and clears the negotiation status.
2636 * If the target does not want all our response to negotiation,
2637 * we force a SIR_NEGO_PROTO interrupt (it is a hack that avoids
2638 * bloat for such a should_not_happen situation).
2639 * In all other situation, we reset the BUS.
2640 * Are these assumptions reasonnable ? (Wait and see ...)
2647 case 2: /* COMMAND phase */
2648 nxtdsp = SCRIPTA_BA(np, dispatch);
2651 case 3: /* STATUS phase */
2652 nxtdsp = SCRIPTA_BA(np, dispatch);
2655 case 6: /* MSG OUT phase */
2657 * If the device may want to use untagged when we want
2658 * tagged, we prepare an IDENTIFY without disc. granted,
2659 * since we will not be able to handle reselect.
2660 * Otherwise, we just don't care.
2662 if (dsp == SCRIPTA_BA(np, send_ident)) {
2663 if (cp->tag != NO_TAG && olen - rest <= 3) {
2664 cp->host_status = HS_BUSY;
2665 np->msgout[0] = IDENTIFY(0, cp->lun);
2666 nxtdsp = SCRIPTB_BA(np, ident_break_atn);
2669 nxtdsp = SCRIPTB_BA(np, ident_break);
2671 else if (dsp == SCRIPTB_BA(np, send_wdtr) ||
2672 dsp == SCRIPTB_BA(np, send_sdtr) ||
2673 dsp == SCRIPTB_BA(np, send_ppr)) {
2674 nxtdsp = SCRIPTB_BA(np, nego_bad_phase);
2675 if (dsp == SCRIPTB_BA(np, send_ppr)) {
2676 struct scsi_device *dev = cp->cmd->device;
2682 case 7: /* MSG IN phase */
2683 nxtdsp = SCRIPTA_BA(np, clrack);
2689 OUTL_DSP(np, nxtdsp);
2694 sym_start_reset(np);
2698 * chip interrupt handler
2700 * In normal situations, interrupt conditions occur one at
2701 * a time. But when something bad happens on the SCSI BUS,
2702 * the chip may raise several interrupt flags before
2703 * stopping and interrupting the CPU. The additionnal
2704 * interrupt flags are stacked in some extra registers
2705 * after the SIP and/or DIP flag has been raised in the
2706 * ISTAT. After the CPU has read the interrupt condition
2707 * flag from SIST or DSTAT, the chip unstacks the other
2708 * interrupt flags and sets the corresponding bits in
2709 * SIST or DSTAT. Since the chip starts stacking once the
2710 * SIP or DIP flag is set, there is a small window of time
2711 * where the stacking does not occur.
2713 * Typically, multiple interrupt conditions may happen in
2714 * the following situations:
2716 * - SCSI parity error + Phase mismatch (PAR|MA)
2717 * When an parity error is detected in input phase
2718 * and the device switches to msg-in phase inside a
2720 * - SCSI parity error + Unexpected disconnect (PAR|UDC)
2721 * When a stupid device does not want to handle the
2722 * recovery of an SCSI parity error.
2723 * - Some combinations of STO, PAR, UDC, ...
2724 * When using non compliant SCSI stuff, when user is
2725 * doing non compliant hot tampering on the BUS, when
2726 * something really bad happens to a device, etc ...
2728 * The heuristic suggested by SYMBIOS to handle
2729 * multiple interrupts is to try unstacking all
2730 * interrupts conditions and to handle them on some
2731 * priority based on error severity.
2732 * This will work when the unstacking has been
2733 * successful, but we cannot be 100 % sure of that,
2734 * since the CPU may have been faster to unstack than
2735 * the chip is able to stack. Hmmm ... But it seems that
2736 * such a situation is very unlikely to happen.
2738 * If this happen, for example STO caught by the CPU
2739 * then UDC happenning before the CPU have restarted
2740 * the SCRIPTS, the driver may wrongly complete the
2741 * same command on UDC, since the SCRIPTS didn't restart
2742 * and the DSA still points to the same command.
2743 * We avoid this situation by setting the DSA to an
2744 * invalid value when the CCB is completed and before
2745 * restarting the SCRIPTS.
2747 * Another issue is that we need some section of our
2748 * recovery procedures to be somehow uninterruptible but
2749 * the SCRIPTS processor does not provides such a
2750 * feature. For this reason, we handle recovery preferently
2751 * from the C code and check against some SCRIPTS critical
2752 * sections from the C code.
2754 * Hopefully, the interrupt handling of the driver is now
2755 * able to resist to weird BUS error conditions, but donnot
2756 * ask me for any guarantee that it will never fail. :-)
2757 * Use at your own decision and risk.
2760 void sym_interrupt (struct sym_hcb *np)
2762 u_char istat, istatc;
2767 * interrupt on the fly ?
2768 * (SCRIPTS may still be running)
2770 * A `dummy read' is needed to ensure that the
2771 * clear of the INTF flag reaches the device
2772 * and that posted writes are flushed to memory
2773 * before the scanning of the DONE queue.
2774 * Note that SCRIPTS also (dummy) read to memory
2775 * prior to deliver the INTF interrupt condition.
2777 istat = INB(np, nc_istat);
2779 OUTB(np, nc_istat, (istat & SIGP) | INTF | np->istat_sem);
2780 istat = INB(np, nc_istat); /* DUMMY READ */
2781 if (DEBUG_FLAGS & DEBUG_TINY) printf ("F ");
2782 sym_wakeup_done(np);
2785 if (!(istat & (SIP|DIP)))
2788 #if 0 /* We should never get this one */
2790 OUTB(np, nc_istat, CABRT);
2794 * PAR and MA interrupts may occur at the same time,
2795 * and we need to know of both in order to handle
2796 * this situation properly. We try to unstack SCSI
2797 * interrupts for that reason. BTW, I dislike a LOT
2798 * such a loop inside the interrupt routine.
2799 * Even if DMA interrupt stacking is very unlikely to
2800 * happen, we also try unstacking these ones, since
2801 * this has no performance impact.
2808 sist |= INW(np, nc_sist);
2810 dstat |= INB(np, nc_dstat);
2811 istatc = INB(np, nc_istat);
2813 } while (istatc & (SIP|DIP));
2815 if (DEBUG_FLAGS & DEBUG_TINY)
2816 printf ("<%d|%x:%x|%x:%x>",
2817 (int)INB(np, nc_scr0),
2819 (unsigned)INL(np, nc_dsp),
2820 (unsigned)INL(np, nc_dbc));
2822 * On paper, a memory read barrier may be needed here to
2823 * prevent out of order LOADs by the CPU from having
2824 * prefetched stale data prior to DMA having occurred.
2825 * And since we are paranoid ... :)
2827 MEMORY_READ_BARRIER();
2830 * First, interrupts we want to service cleanly.
2832 * Phase mismatch (MA) is the most frequent interrupt
2833 * for chip earlier than the 896 and so we have to service
2834 * it as quickly as possible.
2835 * A SCSI parity error (PAR) may be combined with a phase
2836 * mismatch condition (MA).
2837 * Programmed interrupts (SIR) are used to call the C code
2839 * The single step interrupt (SSI) is not used in this
2842 if (!(sist & (STO|GEN|HTH|SGE|UDC|SBMC|RST)) &&
2843 !(dstat & (MDPE|BF|ABRT|IID))) {
2844 if (sist & PAR) sym_int_par (np, sist);
2845 else if (sist & MA) sym_int_ma (np);
2846 else if (dstat & SIR) sym_int_sir (np);
2847 else if (dstat & SSI) OUTONB_STD();
2848 else goto unknown_int;
2853 * Now, interrupts that donnot happen in normal
2854 * situations and that we may need to recover from.
2856 * On SCSI RESET (RST), we reset everything.
2857 * On SCSI BUS MODE CHANGE (SBMC), we complete all
2858 * active CCBs with RESET status, prepare all devices
2859 * for negotiating again and restart the SCRIPTS.
2860 * On STO and UDC, we complete the CCB with the corres-
2861 * ponding status and restart the SCRIPTS.
2864 printf("%s: SCSI BUS reset detected.\n", sym_name(np));
2865 sym_start_up (np, 1);
2869 OUTB(np, nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */
2870 OUTB(np, nc_stest3, TE|CSF); /* clear scsi fifo */
2872 if (!(sist & (GEN|HTH|SGE)) &&
2873 !(dstat & (MDPE|BF|ABRT|IID))) {
2874 if (sist & SBMC) sym_int_sbmc (np);
2875 else if (sist & STO) sym_int_sto (np);
2876 else if (sist & UDC) sym_int_udc (np);
2877 else goto unknown_int;
2882 * Now, interrupts we are not able to recover cleanly.
2884 * Log message for hard errors.
2888 sym_log_hard_error(np, sist, dstat);
2890 if ((sist & (GEN|HTH|SGE)) ||
2891 (dstat & (MDPE|BF|ABRT|IID))) {
2892 sym_start_reset(np);
2898 * We just miss the cause of the interrupt. :(
2899 * Print a message. The timeout will do the real work.
2901 printf( "%s: unknown interrupt(s) ignored, "
2902 "ISTAT=0x%x DSTAT=0x%x SIST=0x%x\n",
2903 sym_name(np), istat, dstat, sist);
2907 * Dequeue from the START queue all CCBs that match
2908 * a given target/lun/task condition (-1 means all),
2909 * and move them from the BUSY queue to the COMP queue
2910 * with DID_SOFT_ERROR status condition.
2911 * This function is used during error handling/recovery.
2912 * It is called with SCRIPTS not running.
2915 sym_dequeue_from_squeue(struct sym_hcb *np, int i, int target, int lun, int task)
2921 * Make sure the starting index is within range.
2923 assert((i >= 0) && (i < 2*MAX_QUEUE));
2926 * Walk until end of START queue and dequeue every job
2927 * that matches the target/lun/task condition.
2930 while (i != np->squeueput) {
2931 cp = sym_ccb_from_dsa(np, scr_to_cpu(np->squeue[i]));
2933 #ifdef SYM_CONF_IARB_SUPPORT
2934 /* Forget hints for IARB, they may be no longer relevant */
2935 cp->host_flags &= ~HF_HINT_IARB;
2937 if ((target == -1 || cp->target == target) &&
2938 (lun == -1 || cp->lun == lun) &&
2939 (task == -1 || cp->tag == task)) {
2940 sym_set_cam_status(cp->cmd, DID_SOFT_ERROR);
2941 sym_remque(&cp->link_ccbq);
2942 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq);
2946 np->squeue[j] = np->squeue[i];
2947 if ((j += 2) >= MAX_QUEUE*2) j = 0;
2949 if ((i += 2) >= MAX_QUEUE*2) i = 0;
2951 if (i != j) /* Copy back the idle task if needed */
2952 np->squeue[j] = np->squeue[i];
2953 np->squeueput = j; /* Update our current start queue pointer */
2959 * chip handler for bad SCSI status condition
2961 * In case of bad SCSI status, we unqueue all the tasks
2962 * currently queued to the controller but not yet started
2963 * and then restart the SCRIPTS processor immediately.
2965 * QUEUE FULL and BUSY conditions are handled the same way.
2966 * Basically all the not yet started tasks are requeued in
2967 * device queue and the queue is frozen until a completion.
2969 * For CHECK CONDITION and COMMAND TERMINATED status, we use
2970 * the CCB of the failed command to prepare a REQUEST SENSE
2971 * SCSI command and queue it to the controller queue.
2973 * SCRATCHA is assumed to have been loaded with STARTPOS
2974 * before the SCRIPTS called the C code.
2976 static void sym_sir_bad_scsi_status(struct sym_hcb *np, int num, struct sym_ccb *cp)
2979 u_char s_status = cp->ssss_status;
2980 u_char h_flags = cp->host_flags;
2985 * Compute the index of the next job to start from SCRIPTS.
2987 i = (INL(np, nc_scratcha) - np->squeue_ba) / 4;
2990 * The last CCB queued used for IARB hint may be
2991 * no longer relevant. Forget it.
2993 #ifdef SYM_CONF_IARB_SUPPORT
2999 * Now deal with the SCSI status.
3004 if (sym_verbose >= 2) {
3005 sym_print_addr(cp->cmd, "%s\n",
3006 s_status == S_BUSY ? "BUSY" : "QUEUE FULL\n");
3008 default: /* S_INT, S_INT_COND_MET, S_CONFLICT */
3009 sym_complete_error (np, cp);
3014 * If we get an SCSI error when requesting sense, give up.
3016 if (h_flags & HF_SENSE) {
3017 sym_complete_error (np, cp);
3022 * Dequeue all queued CCBs for that device not yet started,
3023 * and restart the SCRIPTS processor immediately.
3025 sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1);
3026 OUTL_DSP(np, SCRIPTA_BA(np, start));
3029 * Save some info of the actual IO.
3030 * Compute the data residual.
3032 cp->sv_scsi_status = cp->ssss_status;
3033 cp->sv_xerr_status = cp->xerr_status;
3034 cp->sv_resid = sym_compute_residual(np, cp);
3037 * Prepare all needed data structures for
3038 * requesting sense data.
3041 cp->scsi_smsg2[0] = IDENTIFY(0, cp->lun);
3045 * If we are currently using anything different from
3046 * async. 8 bit data transfers with that target,
3047 * start a negotiation, since the device may want
3048 * to report us a UNIT ATTENTION condition due to
3049 * a cause we currently ignore, and we donnot want
3050 * to be stuck with WIDE and/or SYNC data transfer.
3052 * cp->nego_status is filled by sym_prepare_nego().
3054 cp->nego_status = 0;
3055 msglen += sym_prepare_nego(np, cp, &cp->scsi_smsg2[msglen]);
3057 * Message table indirect structure.
3059 cp->phys.smsg.addr = CCB_BA(cp, scsi_smsg2);
3060 cp->phys.smsg.size = cpu_to_scr(msglen);
3065 cp->phys.cmd.addr = CCB_BA(cp, sensecmd);
3066 cp->phys.cmd.size = cpu_to_scr(6);
3069 * patch requested size into sense command
3071 cp->sensecmd[0] = REQUEST_SENSE;
3072 cp->sensecmd[1] = 0;
3073 if (cp->cmd->device->scsi_level <= SCSI_2 && cp->lun <= 7)
3074 cp->sensecmd[1] = cp->lun << 5;
3075 cp->sensecmd[4] = SYM_SNS_BBUF_LEN;
3076 cp->data_len = SYM_SNS_BBUF_LEN;
3081 memset(cp->sns_bbuf, 0, SYM_SNS_BBUF_LEN);
3082 cp->phys.sense.addr = CCB_BA(cp, sns_bbuf);
3083 cp->phys.sense.size = cpu_to_scr(SYM_SNS_BBUF_LEN);
3086 * requeue the command.
3088 startp = SCRIPTB_BA(np, sdata_in);
3090 cp->phys.head.savep = cpu_to_scr(startp);
3091 cp->phys.head.lastp = cpu_to_scr(startp);
3092 cp->startp = cpu_to_scr(startp);
3093 cp->goalp = cpu_to_scr(startp + 16);
3095 cp->host_xflags = 0;
3096 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY;
3097 cp->ssss_status = S_ILLEGAL;
3098 cp->host_flags = (HF_SENSE|HF_DATA_IN);
3099 cp->xerr_status = 0;
3100 cp->extra_bytes = 0;
3102 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA(np, select));
3105 * Requeue the command.
3107 sym_put_start_queue(np, cp);
3110 * Give back to upper layer everything we have dequeued.
3112 sym_flush_comp_queue(np, 0);
3118 * After a device has accepted some management message
3119 * as BUS DEVICE RESET, ABORT TASK, etc ..., or when
3120 * a device signals a UNIT ATTENTION condition, some
3121 * tasks are thrown away by the device. We are required
3122 * to reflect that on our tasks list since the device
3123 * will never complete these tasks.
3125 * This function move from the BUSY queue to the COMP
3126 * queue all disconnected CCBs for a given target that
3127 * match the following criteria:
3128 * - lun=-1 means any logical UNIT otherwise a given one.
3129 * - task=-1 means any task, otherwise a given one.
3131 int sym_clear_tasks(struct sym_hcb *np, int cam_status, int target, int lun, int task)
3133 SYM_QUEHEAD qtmp, *qp;
3138 * Move the entire BUSY queue to our temporary queue.
3140 sym_que_init(&qtmp);
3141 sym_que_splice(&np->busy_ccbq, &qtmp);
3142 sym_que_init(&np->busy_ccbq);
3145 * Put all CCBs that matches our criteria into
3146 * the COMP queue and put back other ones into
3149 while ((qp = sym_remque_head(&qtmp)) != 0) {
3150 struct scsi_cmnd *cmd;
3151 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
3153 if (cp->host_status != HS_DISCONNECT ||
3154 cp->target != target ||
3155 (lun != -1 && cp->lun != lun) ||
3157 (cp->tag != NO_TAG && cp->scsi_smsg[2] != task))) {
3158 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq);
3161 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq);
3163 /* Preserve the software timeout condition */
3164 if (sym_get_cam_status(cmd) != DID_TIME_OUT)
3165 sym_set_cam_status(cmd, cam_status);
3168 printf("XXXX TASK @%p CLEARED\n", cp);
3175 * chip handler for TASKS recovery
3177 * We cannot safely abort a command, while the SCRIPTS
3178 * processor is running, since we just would be in race
3181 * As long as we have tasks to abort, we keep the SEM
3182 * bit set in the ISTAT. When this bit is set, the
3183 * SCRIPTS processor interrupts (SIR_SCRIPT_STOPPED)
3184 * each time it enters the scheduler.
3186 * If we have to reset a target, clear tasks of a unit,
3187 * or to perform the abort of a disconnected job, we
3188 * restart the SCRIPTS for selecting the target. Once
3189 * selected, the SCRIPTS interrupts (SIR_TARGET_SELECTED).
3190 * If it loses arbitration, the SCRIPTS will interrupt again
3191 * the next time it will enter its scheduler, and so on ...
3193 * On SIR_TARGET_SELECTED, we scan for the more
3194 * appropriate thing to do:
3196 * - If nothing, we just sent a M_ABORT message to the
3197 * target to get rid of the useless SCSI bus ownership.
3198 * According to the specs, no tasks shall be affected.
3199 * - If the target is to be reset, we send it a M_RESET
3201 * - If a logical UNIT is to be cleared , we send the
3202 * IDENTIFY(lun) + M_ABORT.
3203 * - If an untagged task is to be aborted, we send the
3204 * IDENTIFY(lun) + M_ABORT.
3205 * - If a tagged task is to be aborted, we send the
3206 * IDENTIFY(lun) + task attributes + M_ABORT_TAG.
3208 * Once our 'kiss of death' :) message has been accepted
3209 * by the target, the SCRIPTS interrupts again
3210 * (SIR_ABORT_SENT). On this interrupt, we complete
3211 * all the CCBs that should have been aborted by the
3212 * target according to our message.
3214 static void sym_sir_task_recovery(struct sym_hcb *np, int num)
3218 struct sym_tcb *tp = NULL; /* gcc isn't quite smart enough yet */
3219 struct scsi_target *starget;
3220 int target=-1, lun=-1, task;
3225 * The SCRIPTS processor stopped before starting
3226 * the next command in order to allow us to perform
3227 * some task recovery.
3229 case SIR_SCRIPT_STOPPED:
3231 * Do we have any target to reset or unit to clear ?
3233 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) {
3234 tp = &np->target[i];
3236 (tp->lun0p && tp->lun0p->to_clear)) {
3242 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) {
3243 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) {
3253 * If not, walk the busy queue for any
3254 * disconnected CCB to be aborted.
3257 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
3258 cp = sym_que_entry(qp,struct sym_ccb,link_ccbq);
3259 if (cp->host_status != HS_DISCONNECT)
3262 target = cp->target;
3269 * If some target is to be selected,
3270 * prepare and start the selection.
3273 tp = &np->target[target];
3274 np->abrt_sel.sel_id = target;
3275 np->abrt_sel.sel_scntl3 = tp->head.wval;
3276 np->abrt_sel.sel_sxfer = tp->head.sval;
3277 OUTL(np, nc_dsa, np->hcb_ba);
3278 OUTL_DSP(np, SCRIPTB_BA(np, sel_for_abort));
3283 * Now look for a CCB to abort that haven't started yet.
3284 * Btw, the SCRIPTS processor is still stopped, so
3285 * we are not in race.
3289 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
3290 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
3291 if (cp->host_status != HS_BUSY &&
3292 cp->host_status != HS_NEGOTIATE)
3296 #ifdef SYM_CONF_IARB_SUPPORT
3298 * If we are using IMMEDIATE ARBITRATION, we donnot
3299 * want to cancel the last queued CCB, since the
3300 * SCRIPTS may have anticipated the selection.
3302 if (cp == np->last_cp) {
3307 i = 1; /* Means we have found some */
3312 * We are done, so we donnot need
3313 * to synchronize with the SCRIPTS anylonger.
3314 * Remove the SEM flag from the ISTAT.
3317 OUTB(np, nc_istat, SIGP);
3321 * Compute index of next position in the start
3322 * queue the SCRIPTS intends to start and dequeue
3323 * all CCBs for that device that haven't been started.
3325 i = (INL(np, nc_scratcha) - np->squeue_ba) / 4;
3326 i = sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1);
3329 * Make sure at least our IO to abort has been dequeued.
3331 #ifndef SYM_OPT_HANDLE_DEVICE_QUEUEING
3332 assert(i && sym_get_cam_status(cp->cmd) == DID_SOFT_ERROR);
3334 sym_remque(&cp->link_ccbq);
3335 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq);
3338 * Keep track in cam status of the reason of the abort.
3340 if (cp->to_abort == 2)
3341 sym_set_cam_status(cp->cmd, DID_TIME_OUT);
3343 sym_set_cam_status(cp->cmd, DID_ABORT);
3346 * Complete with error everything that we have dequeued.
3348 sym_flush_comp_queue(np, 0);
3351 * The SCRIPTS processor has selected a target
3352 * we may have some manual recovery to perform for.
3354 case SIR_TARGET_SELECTED:
3355 target = INB(np, nc_sdid) & 0xf;
3356 tp = &np->target[target];
3358 np->abrt_tbl.addr = cpu_to_scr(vtobus(np->abrt_msg));
3361 * If the target is to be reset, prepare a
3362 * M_RESET message and clear the to_reset flag
3363 * since we donnot expect this operation to fail.
3366 np->abrt_msg[0] = M_RESET;
3367 np->abrt_tbl.size = 1;
3373 * Otherwise, look for some logical unit to be cleared.
3375 if (tp->lun0p && tp->lun0p->to_clear)
3377 else if (tp->lunmp) {
3378 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) {
3379 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) {
3387 * If a logical unit is to be cleared, prepare
3388 * an IDENTIFY(lun) + ABORT MESSAGE.
3391 struct sym_lcb *lp = sym_lp(tp, lun);
3392 lp->to_clear = 0; /* We don't expect to fail here */
3393 np->abrt_msg[0] = IDENTIFY(0, lun);
3394 np->abrt_msg[1] = M_ABORT;
3395 np->abrt_tbl.size = 2;
3400 * Otherwise, look for some disconnected job to
3401 * abort for this target.
3405 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
3406 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
3407 if (cp->host_status != HS_DISCONNECT)
3409 if (cp->target != target)
3413 i = 1; /* Means we have some */
3418 * If we have none, probably since the device has
3419 * completed the command before we won abitration,
3420 * send a M_ABORT message without IDENTIFY.
3421 * According to the specs, the device must just
3422 * disconnect the BUS and not abort any task.
3425 np->abrt_msg[0] = M_ABORT;
3426 np->abrt_tbl.size = 1;
3431 * We have some task to abort.
3432 * Set the IDENTIFY(lun)
3434 np->abrt_msg[0] = IDENTIFY(0, cp->lun);
3437 * If we want to abort an untagged command, we
3438 * will send a IDENTIFY + M_ABORT.
3439 * Otherwise (tagged command), we will send
3440 * a IDENTITFY + task attributes + ABORT TAG.
3442 if (cp->tag == NO_TAG) {
3443 np->abrt_msg[1] = M_ABORT;
3444 np->abrt_tbl.size = 2;
3446 np->abrt_msg[1] = cp->scsi_smsg[1];
3447 np->abrt_msg[2] = cp->scsi_smsg[2];
3448 np->abrt_msg[3] = M_ABORT_TAG;
3449 np->abrt_tbl.size = 4;
3452 * Keep track of software timeout condition, since the
3453 * peripheral driver may not count retries on abort
3454 * conditions not due to timeout.
3456 if (cp->to_abort == 2)
3457 sym_set_cam_status(cp->cmd, DID_TIME_OUT);
3458 cp->to_abort = 0; /* We donnot expect to fail here */
3462 * The target has accepted our message and switched
3463 * to BUS FREE phase as we expected.
3465 case SIR_ABORT_SENT:
3466 target = INB(np, nc_sdid) & 0xf;
3467 tp = &np->target[target];
3468 starget = tp->starget;
3471 ** If we didn't abort anything, leave here.
3473 if (np->abrt_msg[0] == M_ABORT)
3477 * If we sent a M_RESET, then a hardware reset has
3478 * been performed by the target.
3479 * - Reset everything to async 8 bit
3480 * - Tell ourself to negotiate next time :-)
3481 * - Prepare to clear all disconnected CCBs for
3482 * this target from our task list (lun=task=-1)
3486 if (np->abrt_msg[0] == M_RESET) {
3488 tp->head.wval = np->rv_scntl3;
3490 spi_period(starget) = 0;
3491 spi_offset(starget) = 0;
3492 spi_width(starget) = 0;
3493 spi_iu(starget) = 0;
3494 spi_dt(starget) = 0;
3495 spi_qas(starget) = 0;
3496 tp->tgoal.check_nego = 1;
3500 * Otherwise, check for the LUN and TASK(s)
3501 * concerned by the cancelation.
3502 * If it is not ABORT_TAG then it is CLEAR_QUEUE
3503 * or an ABORT message :-)
3506 lun = np->abrt_msg[0] & 0x3f;
3507 if (np->abrt_msg[1] == M_ABORT_TAG)
3508 task = np->abrt_msg[2];
3512 * Complete all the CCBs the device should have
3513 * aborted due to our 'kiss of death' message.
3515 i = (INL(np, nc_scratcha) - np->squeue_ba) / 4;
3516 sym_dequeue_from_squeue(np, i, target, lun, -1);
3517 sym_clear_tasks(np, DID_ABORT, target, lun, task);
3518 sym_flush_comp_queue(np, 0);
3521 * If we sent a BDR, make upper layer aware of that.
3523 if (np->abrt_msg[0] == M_RESET)
3524 sym_xpt_async_sent_bdr(np, target);
3529 * Print to the log the message we intend to send.
3531 if (num == SIR_TARGET_SELECTED) {
3532 dev_info(&tp->starget->dev, "control msgout:");
3533 sym_printl_hex(np->abrt_msg, np->abrt_tbl.size);
3534 np->abrt_tbl.size = cpu_to_scr(np->abrt_tbl.size);
3538 * Let the SCRIPTS processor continue.
3544 * Gerard's alchemy:) that deals with with the data
3545 * pointer for both MDP and the residual calculation.
3547 * I didn't want to bloat the code by more than 200
3548 * lines for the handling of both MDP and the residual.
3549 * This has been achieved by using a data pointer
3550 * representation consisting in an index in the data
3551 * array (dp_sg) and a negative offset (dp_ofs) that
3552 * have the following meaning:
3554 * - dp_sg = SYM_CONF_MAX_SG
3555 * we are at the end of the data script.
3556 * - dp_sg < SYM_CONF_MAX_SG
3557 * dp_sg points to the next entry of the scatter array
3558 * we want to transfer.
3560 * dp_ofs represents the residual of bytes of the
3561 * previous entry scatter entry we will send first.
3563 * no residual to send first.
3565 * The function sym_evaluate_dp() accepts an arbitray
3566 * offset (basically from the MDP message) and returns
3567 * the corresponding values of dp_sg and dp_ofs.
3570 static int sym_evaluate_dp(struct sym_hcb *np, struct sym_ccb *cp, u32 scr, int *ofs)
3573 int dp_ofs, dp_sg, dp_sgmin;
3578 * Compute the resulted data pointer in term of a script
3579 * address within some DATA script and a signed byte offset.
3583 if (dp_scr == SCRIPTA_BA(np, pm0_data))
3585 else if (dp_scr == SCRIPTA_BA(np, pm1_data))
3591 dp_scr = scr_to_cpu(pm->ret);
3592 dp_ofs -= scr_to_cpu(pm->sg.size) & 0x00ffffff;
3596 * If we are auto-sensing, then we are done.
3598 if (cp->host_flags & HF_SENSE) {
3604 * Deduce the index of the sg entry.
3605 * Keep track of the index of the first valid entry.
3606 * If result is dp_sg = SYM_CONF_MAX_SG, then we are at the
3609 tmp = scr_to_cpu(cp->goalp);
3610 dp_sg = SYM_CONF_MAX_SG;
3612 dp_sg -= (tmp - 8 - (int)dp_scr) / (2*4);
3613 dp_sgmin = SYM_CONF_MAX_SG - cp->segments;
3616 * Move to the sg entry the data pointer belongs to.
3618 * If we are inside the data area, we expect result to be:
3621 * dp_ofs = 0 and dp_sg is the index of the sg entry
3622 * the data pointer belongs to (or the end of the data)
3624 * dp_ofs < 0 and dp_sg is the index of the sg entry
3625 * the data pointer belongs to + 1.
3629 while (dp_sg > dp_sgmin) {
3631 tmp = scr_to_cpu(cp->phys.data[dp_sg].size);
3632 n = dp_ofs + (tmp & 0xffffff);
3640 else if (dp_ofs > 0) {
3641 while (dp_sg < SYM_CONF_MAX_SG) {
3642 tmp = scr_to_cpu(cp->phys.data[dp_sg].size);
3643 dp_ofs -= (tmp & 0xffffff);
3651 * Make sure the data pointer is inside the data area.
3652 * If not, return some error.
3654 if (dp_sg < dp_sgmin || (dp_sg == dp_sgmin && dp_ofs < 0))
3656 else if (dp_sg > SYM_CONF_MAX_SG ||
3657 (dp_sg == SYM_CONF_MAX_SG && dp_ofs > 0))
3661 * Save the extreme pointer if needed.
3663 if (dp_sg > cp->ext_sg ||
3664 (dp_sg == cp->ext_sg && dp_ofs > cp->ext_ofs)) {
3666 cp->ext_ofs = dp_ofs;
3680 * chip handler for MODIFY DATA POINTER MESSAGE
3682 * We also call this function on IGNORE WIDE RESIDUE
3683 * messages that do not match a SWIDE full condition.
3684 * Btw, we assume in that situation that such a message
3685 * is equivalent to a MODIFY DATA POINTER (offset=-1).
3688 static void sym_modify_dp(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp, int ofs)
3691 u32 dp_scr = sym_get_script_dp (np, cp);
3699 * Not supported for auto-sense.
3701 if (cp->host_flags & HF_SENSE)
3705 * Apply our alchemy:) (see comments in sym_evaluate_dp()),
3706 * to the resulted data pointer.
3708 dp_sg = sym_evaluate_dp(np, cp, dp_scr, &dp_ofs);
3713 * And our alchemy:) allows to easily calculate the data
3714 * script address we want to return for the next data phase.
3716 dp_ret = cpu_to_scr(cp->goalp);
3717 dp_ret = dp_ret - 8 - (SYM_CONF_MAX_SG - dp_sg) * (2*4);
3720 * If offset / scatter entry is zero we donnot need
3721 * a context for the new current data pointer.
3729 * Get a context for the new current data pointer.
3731 hflags = INB(np, HF_PRT);
3733 if (hflags & HF_DP_SAVED)
3734 hflags ^= HF_ACT_PM;
3736 if (!(hflags & HF_ACT_PM)) {
3738 dp_scr = SCRIPTA_BA(np, pm0_data);
3742 dp_scr = SCRIPTA_BA(np, pm1_data);
3745 hflags &= ~(HF_DP_SAVED);
3747 OUTB(np, HF_PRT, hflags);
3750 * Set up the new current data pointer.
3751 * ofs < 0 there, and for the next data phase, we
3752 * want to transfer part of the data of the sg entry
3753 * corresponding to index dp_sg-1 prior to returning
3754 * to the main data script.
3756 pm->ret = cpu_to_scr(dp_ret);
3757 tmp = scr_to_cpu(cp->phys.data[dp_sg-1].addr);
3758 tmp += scr_to_cpu(cp->phys.data[dp_sg-1].size) + dp_ofs;
3759 pm->sg.addr = cpu_to_scr(tmp);
3760 pm->sg.size = cpu_to_scr(-dp_ofs);
3763 sym_set_script_dp (np, cp, dp_scr);
3764 OUTL_DSP(np, SCRIPTA_BA(np, clrack));
3768 OUTL_DSP(np, SCRIPTB_BA(np, msg_bad));
3773 * chip calculation of the data residual.
3775 * As I used to say, the requirement of data residual
3776 * in SCSI is broken, useless and cannot be achieved
3777 * without huge complexity.
3778 * But most OSes and even the official CAM require it.
3779 * When stupidity happens to be so widely spread inside
3780 * a community, it gets hard to convince.
3782 * Anyway, I don't care, since I am not going to use
3783 * any software that considers this data residual as
3784 * a relevant information. :)
3787 int sym_compute_residual(struct sym_hcb *np, struct sym_ccb *cp)
3789 int dp_sg, dp_sgmin, resid = 0;
3793 * Check for some data lost or just thrown away.
3794 * We are not required to be quite accurate in this
3795 * situation. Btw, if we are odd for output and the
3796 * device claims some more data, it may well happen
3797 * than our residual be zero. :-)
3799 if (cp->xerr_status & (XE_EXTRA_DATA|XE_SODL_UNRUN|XE_SWIDE_OVRUN)) {
3800 if (cp->xerr_status & XE_EXTRA_DATA)
3801 resid -= cp->extra_bytes;
3802 if (cp->xerr_status & XE_SODL_UNRUN)
3804 if (cp->xerr_status & XE_SWIDE_OVRUN)
3809 * If all data has been transferred,
3810 * there is no residual.
3812 if (cp->phys.head.lastp == cp->goalp)
3816 * If no data transfer occurs, or if the data
3817 * pointer is weird, return full residual.
3819 if (cp->startp == cp->phys.head.lastp ||
3820 sym_evaluate_dp(np, cp, scr_to_cpu(cp->phys.head.lastp),
3822 return cp->data_len;
3826 * If we were auto-sensing, then we are done.
3828 if (cp->host_flags & HF_SENSE) {
3833 * We are now full comfortable in the computation
3834 * of the data residual (2's complement).
3836 dp_sgmin = SYM_CONF_MAX_SG - cp->segments;
3837 resid = -cp->ext_ofs;
3838 for (dp_sg = cp->ext_sg; dp_sg < SYM_CONF_MAX_SG; ++dp_sg) {
3839 u_int tmp = scr_to_cpu(cp->phys.data[dp_sg].size);
3840 resid += (tmp & 0xffffff);
3843 resid -= cp->odd_byte_adjustment;
3846 * Hopefully, the result is not too wrong.
3852 * Negotiation for WIDE and SYNCHRONOUS DATA TRANSFER.
3854 * When we try to negotiate, we append the negotiation message
3855 * to the identify and (maybe) simple tag message.
3856 * The host status field is set to HS_NEGOTIATE to mark this
3859 * If the target doesn't answer this message immediately
3860 * (as required by the standard), the SIR_NEGO_FAILED interrupt
3861 * will be raised eventually.
3862 * The handler removes the HS_NEGOTIATE status, and sets the
3863 * negotiated value to the default (async / nowide).
3865 * If we receive a matching answer immediately, we check it
3866 * for validity, and set the values.
3868 * If we receive a Reject message immediately, we assume the
3869 * negotiation has failed, and fall back to standard values.
3871 * If we receive a negotiation message while not in HS_NEGOTIATE
3872 * state, it's a target initiated negotiation. We prepare a
3873 * (hopefully) valid answer, set our parameters, and send back
3874 * this answer to the target.
3876 * If the target doesn't fetch the answer (no message out phase),
3877 * we assume the negotiation has failed, and fall back to default
3878 * settings (SIR_NEGO_PROTO interrupt).
3880 * When we set the values, we adjust them in all ccbs belonging
3881 * to this target, in the controller's register, and in the "phys"
3882 * field of the controller's struct sym_hcb.
3886 * chip handler for SYNCHRONOUS DATA TRANSFER REQUEST (SDTR) message.
3889 sym_sync_nego_check(struct sym_hcb *np, int req, struct sym_ccb *cp)
3891 int target = cp->target;
3892 u_char chg, ofs, per, fak, div;
3894 if (DEBUG_FLAGS & DEBUG_NEGO) {
3895 sym_print_nego_msg(np, target, "sync msgin", np->msgin);
3899 * Get requested values.
3906 * Check values against our limits.
3909 if (ofs > np->maxoffs)
3910 {chg = 1; ofs = np->maxoffs;}
3914 if (per < np->minsync)
3915 {chg = 1; per = np->minsync;}
3919 * Get new chip synchronous parameters value.
3922 if (ofs && sym_getsync(np, 0, per, &div, &fak) < 0)
3925 if (DEBUG_FLAGS & DEBUG_NEGO) {
3926 sym_print_addr(cp->cmd,
3927 "sdtr: ofs=%d per=%d div=%d fak=%d chg=%d.\n",
3928 ofs, per, div, fak, chg);
3932 * If it was an answer we want to change,
3933 * then it isn't acceptable. Reject it.
3941 sym_setsync (np, target, ofs, per, div, fak);
3944 * It was an answer. We are done.
3950 * It was a request. Prepare an answer message.
3952 spi_populate_sync_msg(np->msgout, per, ofs);
3954 if (DEBUG_FLAGS & DEBUG_NEGO) {
3955 sym_print_nego_msg(np, target, "sync msgout", np->msgout);
3958 np->msgin [0] = M_NOOP;
3963 sym_setsync (np, target, 0, 0, 0, 0);
3967 static void sym_sync_nego(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp)
3973 * Request or answer ?
3975 if (INB(np, HS_PRT) == HS_NEGOTIATE) {
3976 OUTB(np, HS_PRT, HS_BUSY);
3977 if (cp->nego_status && cp->nego_status != NS_SYNC)
3983 * Check and apply new values.
3985 result = sym_sync_nego_check(np, req, cp);
3986 if (result) /* Not acceptable, reject it */
3988 if (req) { /* Was a request, send response. */
3989 cp->nego_status = NS_SYNC;
3990 OUTL_DSP(np, SCRIPTB_BA(np, sdtr_resp));
3992 else /* Was a response, we are done. */
3993 OUTL_DSP(np, SCRIPTA_BA(np, clrack));
3997 OUTL_DSP(np, SCRIPTB_BA(np, msg_bad));
4001 * chip handler for PARALLEL PROTOCOL REQUEST (PPR) message.
4004 sym_ppr_nego_check(struct sym_hcb *np, int req, int target)
4006 struct sym_tcb *tp = &np->target[target];
4007 unsigned char fak, div;
4010 unsigned char per = np->msgin[3];
4011 unsigned char ofs = np->msgin[5];
4012 unsigned char wide = np->msgin[6];
4013 unsigned char opts = np->msgin[7] & PPR_OPT_MASK;
4015 if (DEBUG_FLAGS & DEBUG_NEGO) {
4016 sym_print_nego_msg(np, target, "ppr msgin", np->msgin);
4020 * Check values against our limits.
4022 if (wide > np->maxwide) {
4026 if (!wide || !(np->features & FE_U3EN))
4029 if (opts != (np->msgin[7] & PPR_OPT_MASK))
4032 dt = opts & PPR_OPT_DT;
4035 unsigned char maxoffs = dt ? np->maxoffs_dt : np->maxoffs;
4036 if (ofs > maxoffs) {
4043 unsigned char minsync = dt ? np->minsync_dt : np->minsync;
4044 if (per < minsync) {
4051 * Get new chip synchronous parameters value.
4054 if (ofs && sym_getsync(np, dt, per, &div, &fak) < 0)
4058 * If it was an answer we want to change,
4059 * then it isn't acceptable. Reject it.
4067 sym_setpprot(np, target, opts, ofs, per, wide, div, fak);
4070 * It was an answer. We are done.
4076 * It was a request. Prepare an answer message.
4078 spi_populate_ppr_msg(np->msgout, per, ofs, wide, opts);
4080 if (DEBUG_FLAGS & DEBUG_NEGO) {
4081 sym_print_nego_msg(np, target, "ppr msgout", np->msgout);
4084 np->msgin [0] = M_NOOP;
4089 sym_setpprot (np, target, 0, 0, 0, 0, 0, 0);
4091 * If it is a device response that should result in
4092 * ST, we may want to try a legacy negotiation later.
4094 if (!req && !opts) {
4095 tp->tgoal.period = per;
4096 tp->tgoal.offset = ofs;
4097 tp->tgoal.width = wide;
4098 tp->tgoal.iu = tp->tgoal.dt = tp->tgoal.qas = 0;
4099 tp->tgoal.check_nego = 1;
4104 static void sym_ppr_nego(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp)
4110 * Request or answer ?
4112 if (INB(np, HS_PRT) == HS_NEGOTIATE) {
4113 OUTB(np, HS_PRT, HS_BUSY);
4114 if (cp->nego_status && cp->nego_status != NS_PPR)
4120 * Check and apply new values.
4122 result = sym_ppr_nego_check(np, req, cp->target);
4123 if (result) /* Not acceptable, reject it */
4125 if (req) { /* Was a request, send response. */
4126 cp->nego_status = NS_PPR;
4127 OUTL_DSP(np, SCRIPTB_BA(np, ppr_resp));
4129 else /* Was a response, we are done. */
4130 OUTL_DSP(np, SCRIPTA_BA(np, clrack));
4134 OUTL_DSP(np, SCRIPTB_BA(np, msg_bad));
4138 * chip handler for WIDE DATA TRANSFER REQUEST (WDTR) message.
4141 sym_wide_nego_check(struct sym_hcb *np, int req, struct sym_ccb *cp)
4143 int target = cp->target;
4146 if (DEBUG_FLAGS & DEBUG_NEGO) {
4147 sym_print_nego_msg(np, target, "wide msgin", np->msgin);
4151 * Get requested values.
4154 wide = np->msgin[3];
4157 * Check values against our limits.
4159 if (wide > np->maxwide) {
4164 if (DEBUG_FLAGS & DEBUG_NEGO) {
4165 sym_print_addr(cp->cmd, "wdtr: wide=%d chg=%d.\n",
4170 * If it was an answer we want to change,
4171 * then it isn't acceptable. Reject it.
4179 sym_setwide (np, target, wide);
4182 * It was an answer. We are done.
4188 * It was a request. Prepare an answer message.
4190 spi_populate_width_msg(np->msgout, wide);
4192 np->msgin [0] = M_NOOP;
4194 if (DEBUG_FLAGS & DEBUG_NEGO) {
4195 sym_print_nego_msg(np, target, "wide msgout", np->msgout);
4204 static void sym_wide_nego(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp)
4210 * Request or answer ?
4212 if (INB(np, HS_PRT) == HS_NEGOTIATE) {
4213 OUTB(np, HS_PRT, HS_BUSY);
4214 if (cp->nego_status && cp->nego_status != NS_WIDE)
4220 * Check and apply new values.
4222 result = sym_wide_nego_check(np, req, cp);
4223 if (result) /* Not acceptable, reject it */
4225 if (req) { /* Was a request, send response. */
4226 cp->nego_status = NS_WIDE;
4227 OUTL_DSP(np, SCRIPTB_BA(np, wdtr_resp));
4228 } else { /* Was a response. */
4230 * Negotiate for SYNC immediately after WIDE response.
4231 * This allows to negotiate for both WIDE and SYNC on
4232 * a single SCSI command (Suggested by Justin Gibbs).
4234 if (tp->tgoal.offset) {
4235 spi_populate_sync_msg(np->msgout, tp->tgoal.period,
4238 if (DEBUG_FLAGS & DEBUG_NEGO) {
4239 sym_print_nego_msg(np, cp->target,
4240 "sync msgout", np->msgout);
4243 cp->nego_status = NS_SYNC;
4244 OUTB(np, HS_PRT, HS_NEGOTIATE);
4245 OUTL_DSP(np, SCRIPTB_BA(np, sdtr_resp));
4248 OUTL_DSP(np, SCRIPTA_BA(np, clrack));
4254 OUTL_DSP(np, SCRIPTB_BA(np, msg_bad));
4258 * Reset DT, SYNC or WIDE to default settings.
4260 * Called when a negotiation does not succeed either
4261 * on rejection or on protocol error.
4263 * A target that understands a PPR message should never
4264 * reject it, and messing with it is very unlikely.
4265 * So, if a PPR makes problems, we may just want to
4266 * try a legacy negotiation later.
4268 static void sym_nego_default(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp)
4270 switch (cp->nego_status) {
4273 sym_setpprot (np, cp->target, 0, 0, 0, 0, 0, 0);
4275 if (tp->tgoal.period < np->minsync)
4276 tp->tgoal.period = np->minsync;
4277 if (tp->tgoal.offset > np->maxoffs)
4278 tp->tgoal.offset = np->maxoffs;
4279 tp->tgoal.iu = tp->tgoal.dt = tp->tgoal.qas = 0;
4280 tp->tgoal.check_nego = 1;
4284 sym_setsync (np, cp->target, 0, 0, 0, 0);
4287 sym_setwide (np, cp->target, 0);
4290 np->msgin [0] = M_NOOP;
4291 np->msgout[0] = M_NOOP;
4292 cp->nego_status = 0;
4296 * chip handler for MESSAGE REJECT received in response to
4297 * PPR, WIDE or SYNCHRONOUS negotiation.
4299 static void sym_nego_rejected(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp)
4301 sym_nego_default(np, tp, cp);
4302 OUTB(np, HS_PRT, HS_BUSY);
4306 * chip exception handler for programmed interrupts.
4308 static void sym_int_sir (struct sym_hcb *np)
4310 u_char num = INB(np, nc_dsps);
4311 u32 dsa = INL(np, nc_dsa);
4312 struct sym_ccb *cp = sym_ccb_from_dsa(np, dsa);
4313 u_char target = INB(np, nc_sdid) & 0x0f;
4314 struct sym_tcb *tp = &np->target[target];
4317 if (DEBUG_FLAGS & DEBUG_TINY) printf ("I#%d", num);
4320 #if SYM_CONF_DMA_ADDRESSING_MODE == 2
4322 * SCRIPTS tell us that we may have to update
4323 * 64 bit DMA segment registers.
4325 case SIR_DMAP_DIRTY:
4326 sym_update_dmap_regs(np);
4330 * Command has been completed with error condition
4331 * or has been auto-sensed.
4333 case SIR_COMPLETE_ERROR:
4334 sym_complete_error(np, cp);
4337 * The C code is currently trying to recover from something.
4338 * Typically, user want to abort some command.
4340 case SIR_SCRIPT_STOPPED:
4341 case SIR_TARGET_SELECTED:
4342 case SIR_ABORT_SENT:
4343 sym_sir_task_recovery(np, num);
4346 * The device didn't go to MSG OUT phase after having
4347 * been selected with ATN. We donnot want to handle
4350 case SIR_SEL_ATN_NO_MSG_OUT:
4351 printf ("%s:%d: No MSG OUT phase after selection with ATN.\n",
4352 sym_name (np), target);
4355 * The device didn't switch to MSG IN phase after
4356 * having reseleted the initiator.
4358 case SIR_RESEL_NO_MSG_IN:
4359 printf ("%s:%d: No MSG IN phase after reselection.\n",
4360 sym_name (np), target);
4363 * After reselection, the device sent a message that wasn't
4366 case SIR_RESEL_NO_IDENTIFY:
4367 printf ("%s:%d: No IDENTIFY after reselection.\n",
4368 sym_name (np), target);
4371 * The device reselected a LUN we donnot know about.
4373 case SIR_RESEL_BAD_LUN:
4374 np->msgout[0] = M_RESET;
4377 * The device reselected for an untagged nexus and we
4380 case SIR_RESEL_BAD_I_T_L:
4381 np->msgout[0] = M_ABORT;
4384 * The device reselected for a tagged nexus that we donnot
4387 case SIR_RESEL_BAD_I_T_L_Q:
4388 np->msgout[0] = M_ABORT_TAG;
4391 * The SCRIPTS let us know that the device has grabbed
4392 * our message and will abort the job.
4394 case SIR_RESEL_ABORTED:
4395 np->lastmsg = np->msgout[0];
4396 np->msgout[0] = M_NOOP;
4397 printf ("%s:%d: message %x sent on bad reselection.\n",
4398 sym_name (np), target, np->lastmsg);
4401 * The SCRIPTS let us know that a message has been
4402 * successfully sent to the device.
4404 case SIR_MSG_OUT_DONE:
4405 np->lastmsg = np->msgout[0];
4406 np->msgout[0] = M_NOOP;
4407 /* Should we really care of that */
4408 if (np->lastmsg == M_PARITY || np->lastmsg == M_ID_ERROR) {
4410 cp->xerr_status &= ~XE_PARITY_ERR;
4411 if (!cp->xerr_status)
4412 OUTOFFB(np, HF_PRT, HF_EXT_ERR);
4417 * The device didn't send a GOOD SCSI status.
4418 * We may have some work to do prior to allow
4419 * the SCRIPTS processor to continue.
4421 case SIR_BAD_SCSI_STATUS:
4424 sym_sir_bad_scsi_status(np, num, cp);
4427 * We are asked by the SCRIPTS to prepare a
4430 case SIR_REJECT_TO_SEND:
4431 sym_print_msg(cp, "M_REJECT to send for ", np->msgin);
4432 np->msgout[0] = M_REJECT;
4435 * We have been ODD at the end of a DATA IN
4436 * transfer and the device didn't send a
4437 * IGNORE WIDE RESIDUE message.
4438 * It is a data overrun condition.
4440 case SIR_SWIDE_OVERRUN:
4442 OUTONB(np, HF_PRT, HF_EXT_ERR);
4443 cp->xerr_status |= XE_SWIDE_OVRUN;
4447 * We have been ODD at the end of a DATA OUT
4449 * It is a data underrun condition.
4451 case SIR_SODL_UNDERRUN:
4453 OUTONB(np, HF_PRT, HF_EXT_ERR);
4454 cp->xerr_status |= XE_SODL_UNRUN;
4458 * The device wants us to tranfer more data than
4459 * expected or in the wrong direction.
4460 * The number of extra bytes is in scratcha.
4461 * It is a data overrun condition.
4463 case SIR_DATA_OVERRUN:
4465 OUTONB(np, HF_PRT, HF_EXT_ERR);
4466 cp->xerr_status |= XE_EXTRA_DATA;
4467 cp->extra_bytes += INL(np, nc_scratcha);
4471 * The device switched to an illegal phase (4/5).
4475 OUTONB(np, HF_PRT, HF_EXT_ERR);
4476 cp->xerr_status |= XE_BAD_PHASE;
4480 * We received a message.
4482 case SIR_MSG_RECEIVED:
4485 switch (np->msgin [0]) {
4487 * We received an extended message.
4488 * We handle MODIFY DATA POINTER, SDTR, WDTR
4489 * and reject all other extended messages.
4492 switch (np->msgin [2]) {
4494 if (DEBUG_FLAGS & DEBUG_POINTER)
4495 sym_print_msg(cp, NULL, np->msgin);
4496 tmp = (np->msgin[3]<<24) + (np->msgin[4]<<16) +
4497 (np->msgin[5]<<8) + (np->msgin[6]);
4498 sym_modify_dp(np, tp, cp, tmp);
4501 sym_sync_nego(np, tp, cp);
4504 sym_ppr_nego(np, tp, cp);
4507 sym_wide_nego(np, tp, cp);
4514 * We received a 1/2 byte message not handled from SCRIPTS.
4515 * We are only expecting MESSAGE REJECT and IGNORE WIDE
4516 * RESIDUE messages that haven't been anticipated by
4517 * SCRIPTS on SWIDE full condition. Unanticipated IGNORE
4518 * WIDE RESIDUE messages are aliased as MODIFY DP (-1).
4521 if (DEBUG_FLAGS & DEBUG_POINTER)
4522 sym_print_msg(cp, NULL, np->msgin);
4523 if (cp->host_flags & HF_SENSE)
4524 OUTL_DSP(np, SCRIPTA_BA(np, clrack));
4526 sym_modify_dp(np, tp, cp, -1);
4529 if (INB(np, HS_PRT) == HS_NEGOTIATE)
4530 sym_nego_rejected(np, tp, cp);
4532 sym_print_addr(cp->cmd,
4533 "M_REJECT received (%x:%x).\n",
4534 scr_to_cpu(np->lastmsg), np->msgout[0]);
4543 * We received an unknown message.
4544 * Ignore all MSG IN phases and reject it.
4547 sym_print_msg(cp, "WEIRD message received", np->msgin);
4548 OUTL_DSP(np, SCRIPTB_BA(np, msg_weird));
4551 * Negotiation failed.
4552 * Target does not send us the reply.
4553 * Remove the HS_NEGOTIATE status.
4555 case SIR_NEGO_FAILED:
4556 OUTB(np, HS_PRT, HS_BUSY);
4558 * Negotiation failed.
4559 * Target does not want answer message.
4561 case SIR_NEGO_PROTO:
4562 sym_nego_default(np, tp, cp);
4570 OUTL_DSP(np, SCRIPTB_BA(np, msg_bad));
4573 OUTL_DSP(np, SCRIPTA_BA(np, clrack));
4580 * Acquire a control block
4582 struct sym_ccb *sym_get_ccb (struct sym_hcb *np, struct scsi_cmnd *cmd, u_char tag_order)
4584 u_char tn = cmd->device->id;
4585 u_char ln = cmd->device->lun;
4586 struct sym_tcb *tp = &np->target[tn];
4587 struct sym_lcb *lp = sym_lp(tp, ln);
4588 u_short tag = NO_TAG;
4590 struct sym_ccb *cp = NULL;
4593 * Look for a free CCB
4595 if (sym_que_empty(&np->free_ccbq))
4597 qp = sym_remque_head(&np->free_ccbq);
4600 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
4604 * If we have been asked for a tagged command.
4608 * Debugging purpose.
4610 #ifndef SYM_OPT_HANDLE_DEVICE_QUEUEING
4611 if (lp->busy_itl != 0)
4615 * Allocate resources for tags if not yet.
4618 sym_alloc_lcb_tags(np, tn, ln);
4623 * Get a tag for this SCSI IO and set up
4624 * the CCB bus address for reselection,
4625 * and count it for this LUN.
4626 * Toggle reselect path to tagged.
4628 if (lp->busy_itlq < SYM_CONF_MAX_TASK) {
4629 tag = lp->cb_tags[lp->ia_tag];
4630 if (++lp->ia_tag == SYM_CONF_MAX_TASK)
4633 #ifndef SYM_OPT_HANDLE_DEVICE_QUEUEING
4634 lp->itlq_tbl[tag] = cpu_to_scr(cp->ccb_ba);
4636 cpu_to_scr(SCRIPTA_BA(np, resel_tag));
4638 #ifdef SYM_OPT_LIMIT_COMMAND_REORDERING
4639 cp->tags_si = lp->tags_si;
4640 ++lp->tags_sum[cp->tags_si];
4648 * This command will not be tagged.
4649 * If we already have either a tagged or untagged
4650 * one, refuse to overlap this untagged one.
4654 * Debugging purpose.
4656 #ifndef SYM_OPT_HANDLE_DEVICE_QUEUEING
4657 if (lp->busy_itl != 0 || lp->busy_itlq != 0)
4661 * Count this nexus for this LUN.
4662 * Set up the CCB bus address for reselection.
4663 * Toggle reselect path to untagged.
4666 #ifndef SYM_OPT_HANDLE_DEVICE_QUEUEING
4667 if (lp->busy_itl == 1) {
4668 lp->head.itl_task_sa = cpu_to_scr(cp->ccb_ba);
4670 cpu_to_scr(SCRIPTA_BA(np, resel_no_tag));
4678 * Put the CCB into the busy queue.
4680 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq);
4681 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
4683 sym_remque(&cp->link2_ccbq);
4684 sym_insque_tail(&cp->link2_ccbq, &lp->waiting_ccbq);
4689 cp->odd_byte_adjustment = 0;
4691 cp->order = tag_order;
4695 if (DEBUG_FLAGS & DEBUG_TAGS) {
4696 sym_print_addr(cmd, "ccb @%p using tag %d.\n", cp, tag);
4702 sym_insque_head(&cp->link_ccbq, &np->free_ccbq);
4707 * Release one control block
4709 void sym_free_ccb (struct sym_hcb *np, struct sym_ccb *cp)
4711 struct sym_tcb *tp = &np->target[cp->target];
4712 struct sym_lcb *lp = sym_lp(tp, cp->lun);
4714 if (DEBUG_FLAGS & DEBUG_TAGS) {
4715 sym_print_addr(cp->cmd, "ccb @%p freeing tag %d.\n",
4724 * If tagged, release the tag, set the relect path
4726 if (cp->tag != NO_TAG) {
4727 #ifdef SYM_OPT_LIMIT_COMMAND_REORDERING
4728 --lp->tags_sum[cp->tags_si];
4731 * Free the tag value.
4733 lp->cb_tags[lp->if_tag] = cp->tag;
4734 if (++lp->if_tag == SYM_CONF_MAX_TASK)
4737 * Make the reselect path invalid,
4738 * and uncount this CCB.
4740 lp->itlq_tbl[cp->tag] = cpu_to_scr(np->bad_itlq_ba);
4742 } else { /* Untagged */
4744 * Make the reselect path invalid,
4745 * and uncount this CCB.
4747 lp->head.itl_task_sa = cpu_to_scr(np->bad_itl_ba);
4751 * If no JOB active, make the LUN reselect path invalid.
4753 if (lp->busy_itlq == 0 && lp->busy_itl == 0)
4755 cpu_to_scr(SCRIPTB_BA(np, resel_bad_lun));
4759 * We donnot queue more than 1 ccb per target
4760 * with negotiation at any time. If this ccb was
4761 * used for negotiation, clear this info in the tcb.
4763 if (cp == tp->nego_cp)
4766 #ifdef SYM_CONF_IARB_SUPPORT
4768 * If we just complete the last queued CCB,
4769 * clear this info that is no longer relevant.
4771 if (cp == np->last_cp)
4776 * Make this CCB available.
4779 cp->host_status = HS_IDLE;
4780 sym_remque(&cp->link_ccbq);
4781 sym_insque_head(&cp->link_ccbq, &np->free_ccbq);
4783 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
4785 sym_remque(&cp->link2_ccbq);
4786 sym_insque_tail(&cp->link2_ccbq, &np->dummy_ccbq);
4788 if (cp->tag != NO_TAG)
4791 --lp->started_no_tag;
4799 * Allocate a CCB from memory and initialize its fixed part.
4801 static struct sym_ccb *sym_alloc_ccb(struct sym_hcb *np)
4803 struct sym_ccb *cp = NULL;
4807 * Prevent from allocating more CCBs than we can
4808 * queue to the controller.
4810 if (np->actccbs >= SYM_CONF_MAX_START)
4814 * Allocate memory for this CCB.
4816 cp = sym_calloc_dma(sizeof(struct sym_ccb), "CCB");
4826 * Compute the bus address of this ccb.
4828 cp->ccb_ba = vtobus(cp);
4831 * Insert this ccb into the hashed list.
4833 hcode = CCB_HASH_CODE(cp->ccb_ba);
4834 cp->link_ccbh = np->ccbh[hcode];
4835 np->ccbh[hcode] = cp;
4838 * Initialyze the start and restart actions.
4840 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA(np, idle));
4841 cp->phys.head.go.restart = cpu_to_scr(SCRIPTB_BA(np, bad_i_t_l));
4844 * Initilialyze some other fields.
4846 cp->phys.smsg_ext.addr = cpu_to_scr(HCB_BA(np, msgin[2]));
4849 * Chain into free ccb queue.
4851 sym_insque_head(&cp->link_ccbq, &np->free_ccbq);
4854 * Chain into optionnal lists.
4856 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
4857 sym_insque_head(&cp->link2_ccbq, &np->dummy_ccbq);
4862 sym_mfree_dma(cp, sizeof(*cp), "CCB");
4867 * Look up a CCB from a DSA value.
4869 static struct sym_ccb *sym_ccb_from_dsa(struct sym_hcb *np, u32 dsa)
4874 hcode = CCB_HASH_CODE(dsa);
4875 cp = np->ccbh[hcode];
4877 if (cp->ccb_ba == dsa)
4886 * Target control block initialisation.
4887 * Nothing important to do at the moment.
4889 static void sym_init_tcb (struct sym_hcb *np, u_char tn)
4891 #if 0 /* Hmmm... this checking looks paranoid. */
4893 * Check some alignments required by the chip.
4895 assert (((offsetof(struct sym_reg, nc_sxfer) ^
4896 offsetof(struct sym_tcb, head.sval)) &3) == 0);
4897 assert (((offsetof(struct sym_reg, nc_scntl3) ^
4898 offsetof(struct sym_tcb, head.wval)) &3) == 0);
4903 * Lun control block allocation and initialization.
4905 struct sym_lcb *sym_alloc_lcb (struct sym_hcb *np, u_char tn, u_char ln)
4907 struct sym_tcb *tp = &np->target[tn];
4908 struct sym_lcb *lp = NULL;
4911 * Initialize the target control block if not yet.
4913 sym_init_tcb (np, tn);
4916 * Allocate the LCB bus address array.
4917 * Compute the bus address of this table.
4919 if (ln && !tp->luntbl) {
4922 tp->luntbl = sym_calloc_dma(256, "LUNTBL");
4925 for (i = 0 ; i < 64 ; i++)
4926 tp->luntbl[i] = cpu_to_scr(vtobus(&np->badlun_sa));
4927 tp->head.luntbl_sa = cpu_to_scr(vtobus(tp->luntbl));
4931 * Allocate the table of pointers for LUN(s) > 0, if needed.
4933 if (ln && !tp->lunmp) {
4934 tp->lunmp = kcalloc(SYM_CONF_MAX_LUN, sizeof(struct sym_lcb *),
4942 * Make it available to the chip.
4944 lp = sym_calloc_dma(sizeof(struct sym_lcb), "LCB");
4949 tp->luntbl[ln] = cpu_to_scr(vtobus(lp));
4953 tp->head.lun0_sa = cpu_to_scr(vtobus(lp));
4957 * Let the itl task point to error handling.
4959 lp->head.itl_task_sa = cpu_to_scr(np->bad_itl_ba);
4962 * Set the reselect pattern to our default. :)
4964 lp->head.resel_sa = cpu_to_scr(SCRIPTB_BA(np, resel_bad_lun));
4967 * Set user capabilities.
4969 lp->user_flags = tp->usrflags & (SYM_DISC_ENABLED | SYM_TAGS_ENABLED);
4971 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
4973 * Initialize device queueing.
4975 sym_que_init(&lp->waiting_ccbq);
4976 sym_que_init(&lp->started_ccbq);
4977 lp->started_max = SYM_CONF_MAX_TASK;
4978 lp->started_limit = SYM_CONF_MAX_TASK;
4986 * Allocate LCB resources for tagged command queuing.
4988 static void sym_alloc_lcb_tags (struct sym_hcb *np, u_char tn, u_char ln)
4990 struct sym_tcb *tp = &np->target[tn];
4991 struct sym_lcb *lp = sym_lp(tp, ln);
4995 * Allocate the task table and and the tag allocation
4996 * circular buffer. We want both or none.
4998 lp->itlq_tbl = sym_calloc_dma(SYM_CONF_MAX_TASK*4, "ITLQ_TBL");
5001 lp->cb_tags = kcalloc(SYM_CONF_MAX_TASK, 1, GFP_ATOMIC);
5003 sym_mfree_dma(lp->itlq_tbl, SYM_CONF_MAX_TASK*4, "ITLQ_TBL");
5004 lp->itlq_tbl = NULL;
5009 * Initialize the task table with invalid entries.
5011 for (i = 0 ; i < SYM_CONF_MAX_TASK ; i++)
5012 lp->itlq_tbl[i] = cpu_to_scr(np->notask_ba);
5015 * Fill up the tag buffer with tag numbers.
5017 for (i = 0 ; i < SYM_CONF_MAX_TASK ; i++)
5021 * Make the task table available to SCRIPTS,
5022 * And accept tagged commands now.
5024 lp->head.itlq_tbl_sa = cpu_to_scr(vtobus(lp->itlq_tbl));
5032 * Queue a SCSI IO to the controller.
5034 int sym_queue_scsiio(struct sym_hcb *np, struct scsi_cmnd *cmd, struct sym_ccb *cp)
5036 struct scsi_device *sdev = cmd->device;
5044 * Keep track of the IO in our CCB.
5049 * Retrieve the target descriptor.
5051 tp = &np->target[cp->target];
5054 * Retrieve the lun descriptor.
5056 lp = sym_lp(tp, sdev->lun);
5058 can_disconnect = (cp->tag != NO_TAG) ||
5059 (lp && (lp->curr_flags & SYM_DISC_ENABLED));
5061 msgptr = cp->scsi_smsg;
5063 msgptr[msglen++] = IDENTIFY(can_disconnect, sdev->lun);
5066 * Build the tag message if present.
5068 if (cp->tag != NO_TAG) {
5069 u_char order = cp->order;
5077 order = M_SIMPLE_TAG;
5079 #ifdef SYM_OPT_LIMIT_COMMAND_REORDERING
5081 * Avoid too much reordering of SCSI commands.
5082 * The algorithm tries to prevent completion of any
5083 * tagged command from being delayed against more
5084 * than 3 times the max number of queued commands.
5086 if (lp && lp->tags_since > 3*SYM_CONF_MAX_TAG) {
5087 lp->tags_si = !(lp->tags_si);
5088 if (lp->tags_sum[lp->tags_si]) {
5089 order = M_ORDERED_TAG;
5090 if ((DEBUG_FLAGS & DEBUG_TAGS)||sym_verbose>1) {
5092 "ordered tag forced.\n");
5098 msgptr[msglen++] = order;
5101 * For less than 128 tags, actual tags are numbered
5102 * 1,3,5,..2*MAXTAGS+1,since we may have to deal
5103 * with devices that have problems with #TAG 0 or too
5104 * great #TAG numbers. For more tags (up to 256),
5105 * we use directly our tag number.
5107 #if SYM_CONF_MAX_TASK > (512/4)
5108 msgptr[msglen++] = cp->tag;
5110 msgptr[msglen++] = (cp->tag << 1) + 1;
5115 * Build a negotiation message if needed.
5116 * (nego_status is filled by sym_prepare_nego())
5118 cp->nego_status = 0;
5119 if (tp->tgoal.check_nego && !tp->nego_cp && lp) {
5120 msglen += sym_prepare_nego(np, cp, msgptr + msglen);
5126 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA(np, select));
5127 cp->phys.head.go.restart = cpu_to_scr(SCRIPTA_BA(np, resel_dsa));
5132 cp->phys.select.sel_id = cp->target;
5133 cp->phys.select.sel_scntl3 = tp->head.wval;
5134 cp->phys.select.sel_sxfer = tp->head.sval;
5135 cp->phys.select.sel_scntl4 = tp->head.uval;
5140 cp->phys.smsg.addr = CCB_BA(cp, scsi_smsg);
5141 cp->phys.smsg.size = cpu_to_scr(msglen);
5146 cp->host_xflags = 0;
5147 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY;
5148 cp->ssss_status = S_ILLEGAL;
5149 cp->xerr_status = 0;
5151 cp->extra_bytes = 0;
5154 * extreme data pointer.
5155 * shall be positive, so -1 is lower than lowest.:)
5161 * Build the CDB and DATA descriptor block
5164 return sym_setup_data_and_start(np, cmd, cp);
5168 * Reset a SCSI target (all LUNs of this target).
5170 int sym_reset_scsi_target(struct sym_hcb *np, int target)
5174 if (target == np->myaddr || (u_int)target >= SYM_CONF_MAX_TARGET)
5177 tp = &np->target[target];
5180 np->istat_sem = SEM;
5181 OUTB(np, nc_istat, SIGP|SEM);
5189 static int sym_abort_ccb(struct sym_hcb *np, struct sym_ccb *cp, int timed_out)
5192 * Check that the IO is active.
5194 if (!cp || !cp->host_status || cp->host_status == HS_WAIT)
5198 * If a previous abort didn't succeed in time,
5199 * perform a BUS reset.
5202 sym_reset_scsi_bus(np, 1);
5207 * Mark the CCB for abort and allow time for.
5209 cp->to_abort = timed_out ? 2 : 1;
5212 * Tell the SCRIPTS processor to stop and synchronize with us.
5214 np->istat_sem = SEM;
5215 OUTB(np, nc_istat, SIGP|SEM);
5219 int sym_abort_scsiio(struct sym_hcb *np, struct scsi_cmnd *cmd, int timed_out)
5225 * Look up our CCB control block.
5228 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
5229 struct sym_ccb *cp2 = sym_que_entry(qp, struct sym_ccb, link_ccbq);
5230 if (cp2->cmd == cmd) {
5236 return sym_abort_ccb(np, cp, timed_out);
5240 * Complete execution of a SCSI command with extended
5241 * error, SCSI status error, or having been auto-sensed.
5243 * The SCRIPTS processor is not running there, so we
5244 * can safely access IO registers and remove JOBs from
5246 * SCRATCHA is assumed to have been loaded with STARTPOS
5247 * before the SCRIPTS called the C code.
5249 void sym_complete_error(struct sym_hcb *np, struct sym_ccb *cp)
5251 struct scsi_device *sdev;
5252 struct scsi_cmnd *cmd;
5259 * Paranoid check. :)
5261 if (!cp || !cp->cmd)
5266 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_RESULT)) {
5267 dev_info(&sdev->sdev_gendev, "CCB=%p STAT=%x/%x/%x\n", cp,
5268 cp->host_status, cp->ssss_status, cp->host_flags);
5272 * Get target and lun pointers.
5274 tp = &np->target[cp->target];
5275 lp = sym_lp(tp, sdev->lun);
5278 * Check for extended errors.
5280 if (cp->xerr_status) {
5282 sym_print_xerr(cmd, cp->xerr_status);
5283 if (cp->host_status == HS_COMPLETE)
5284 cp->host_status = HS_COMP_ERR;
5288 * Calculate the residual.
5290 resid = sym_compute_residual(np, cp);
5292 if (!SYM_SETUP_RESIDUAL_SUPPORT) {/* If user does not want residuals */
5293 resid = 0; /* throw them away. :) */
5298 printf("XXXX RESID= %d - 0x%x\n", resid, resid);
5302 * Dequeue all queued CCBs for that device
5303 * not yet started by SCRIPTS.
5305 i = (INL(np, nc_scratcha) - np->squeue_ba) / 4;
5306 i = sym_dequeue_from_squeue(np, i, cp->target, sdev->lun, -1);
5309 * Restart the SCRIPTS processor.
5311 OUTL_DSP(np, SCRIPTA_BA(np, start));
5313 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
5314 if (cp->host_status == HS_COMPLETE &&
5315 cp->ssss_status == S_QUEUE_FULL) {
5316 if (!lp || lp->started_tags - i < 2)
5319 * Decrease queue depth as needed.
5321 lp->started_max = lp->started_tags - i - 1;
5324 if (sym_verbose >= 2) {
5325 sym_print_addr(cmd, " queue depth is now %d\n",
5332 cp->host_status = HS_BUSY;
5333 cp->ssss_status = S_ILLEGAL;
5336 * Let's requeue it to device.
5338 sym_set_cam_status(cmd, DID_SOFT_ERROR);
5344 * Build result in CAM ccb.
5346 sym_set_cam_result_error(np, cp, resid);
5348 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
5352 * Add this one to the COMP queue.
5354 sym_remque(&cp->link_ccbq);
5355 sym_insque_head(&cp->link_ccbq, &np->comp_ccbq);
5358 * Complete all those commands with either error
5359 * or requeue condition.
5361 sym_flush_comp_queue(np, 0);
5363 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
5365 * Donnot start more than 1 command after an error.
5367 sym_start_next_ccbs(np, lp, 1);
5372 * Complete execution of a successful SCSI command.
5374 * Only successful commands go to the DONE queue,
5375 * since we need to have the SCRIPTS processor
5376 * stopped on any error condition.
5377 * The SCRIPTS processor is running while we are
5378 * completing successful commands.
5380 void sym_complete_ok (struct sym_hcb *np, struct sym_ccb *cp)
5384 struct scsi_cmnd *cmd;
5388 * Paranoid check. :)
5390 if (!cp || !cp->cmd)
5392 assert (cp->host_status == HS_COMPLETE);
5400 * Get target and lun pointers.
5402 tp = &np->target[cp->target];
5403 lp = sym_lp(tp, cp->lun);
5406 * If all data have been transferred, given than no
5407 * extended error did occur, there is no residual.
5410 if (cp->phys.head.lastp != cp->goalp)
5411 resid = sym_compute_residual(np, cp);
5414 * Wrong transfer residuals may be worse than just always
5415 * returning zero. User can disable this feature in
5416 * sym53c8xx.h. Residual support is enabled by default.
5418 if (!SYM_SETUP_RESIDUAL_SUPPORT)
5422 printf("XXXX RESID= %d - 0x%x\n", resid, resid);
5426 * Build result in CAM ccb.
5428 sym_set_cam_result_ok(cp, cmd, resid);
5430 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
5432 * If max number of started ccbs had been reduced,
5433 * increase it if 200 good status received.
5435 if (lp && lp->started_max < lp->started_limit) {
5437 if (lp->num_sgood >= 200) {
5440 if (sym_verbose >= 2) {
5441 sym_print_addr(cmd, " queue depth is now %d\n",
5451 sym_free_ccb (np, cp);
5453 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
5455 * Requeue a couple of awaiting scsi commands.
5457 if (!sym_que_empty(&lp->waiting_ccbq))
5458 sym_start_next_ccbs(np, lp, 2);
5461 * Complete the command.
5463 sym_xpt_done(np, cmd);
5467 * Soft-attach the controller.
5469 int sym_hcb_attach(struct Scsi_Host *shost, struct sym_fw *fw, struct sym_nvram *nvram)
5471 struct sym_hcb *np = sym_get_hcb(shost);
5475 * Get some info about the firmware.
5477 np->scripta_sz = fw->a_size;
5478 np->scriptb_sz = fw->b_size;
5479 np->scriptz_sz = fw->z_size;
5480 np->fw_setup = fw->setup;
5481 np->fw_patch = fw->patch;
5482 np->fw_name = fw->name;
5485 * Save setting of some IO registers, so we will
5486 * be able to probe specific implementations.
5488 sym_save_initial_setting (np);
5491 * Reset the chip now, since it has been reported
5492 * that SCSI clock calibration may not work properly
5493 * if the chip is currently active.
5498 * Prepare controller and devices settings, according
5499 * to chip features, user set-up and driver set-up.
5501 sym_prepare_setting(shost, np, nvram);
5504 * Check the PCI clock frequency.
5505 * Must be performed after prepare_setting since it destroys
5506 * STEST1 that is used to probe for the clock doubler.
5508 i = sym_getpciclock(np);
5509 if (i > 37000 && !(np->features & FE_66MHZ))
5510 printf("%s: PCI BUS clock seems too high: %u KHz.\n",
5514 * Allocate the start queue.
5516 np->squeue = sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"SQUEUE");
5519 np->squeue_ba = vtobus(np->squeue);
5522 * Allocate the done queue.
5524 np->dqueue = sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"DQUEUE");
5527 np->dqueue_ba = vtobus(np->dqueue);
5530 * Allocate the target bus address array.
5532 np->targtbl = sym_calloc_dma(256, "TARGTBL");
5535 np->targtbl_ba = vtobus(np->targtbl);
5538 * Allocate SCRIPTS areas.
5540 np->scripta0 = sym_calloc_dma(np->scripta_sz, "SCRIPTA0");
5541 np->scriptb0 = sym_calloc_dma(np->scriptb_sz, "SCRIPTB0");
5542 np->scriptz0 = sym_calloc_dma(np->scriptz_sz, "SCRIPTZ0");
5543 if (!np->scripta0 || !np->scriptb0 || !np->scriptz0)
5547 * Allocate the array of lists of CCBs hashed by DSA.
5549 np->ccbh = kcalloc(sizeof(struct sym_ccb **), CCB_HASH_SIZE, GFP_KERNEL);
5554 * Initialyze the CCB free and busy queues.
5556 sym_que_init(&np->free_ccbq);
5557 sym_que_init(&np->busy_ccbq);
5558 sym_que_init(&np->comp_ccbq);
5561 * Initialization for optional handling
5562 * of device queueing.
5564 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
5565 sym_que_init(&np->dummy_ccbq);
5568 * Allocate some CCB. We need at least ONE.
5570 if (!sym_alloc_ccb(np))
5574 * Calculate BUS addresses where we are going
5575 * to load the SCRIPTS.
5577 np->scripta_ba = vtobus(np->scripta0);
5578 np->scriptb_ba = vtobus(np->scriptb0);
5579 np->scriptz_ba = vtobus(np->scriptz0);
5582 np->scripta_ba = np->ram_ba;
5583 if (np->features & FE_RAM8K) {
5585 np->scriptb_ba = np->scripta_ba + 4096;
5586 #if 0 /* May get useful for 64 BIT PCI addressing */
5587 np->scr_ram_seg = cpu_to_scr(np->scripta_ba >> 32);
5595 * Copy scripts to controller instance.
5597 memcpy(np->scripta0, fw->a_base, np->scripta_sz);
5598 memcpy(np->scriptb0, fw->b_base, np->scriptb_sz);
5599 memcpy(np->scriptz0, fw->z_base, np->scriptz_sz);
5602 * Setup variable parts in scripts and compute
5603 * scripts bus addresses used from the C code.
5605 np->fw_setup(np, fw);
5608 * Bind SCRIPTS with physical addresses usable by the
5609 * SCRIPTS processor (as seen from the BUS = BUS addresses).
5611 sym_fw_bind_script(np, (u32 *) np->scripta0, np->scripta_sz);
5612 sym_fw_bind_script(np, (u32 *) np->scriptb0, np->scriptb_sz);
5613 sym_fw_bind_script(np, (u32 *) np->scriptz0, np->scriptz_sz);
5615 #ifdef SYM_CONF_IARB_SUPPORT
5617 * If user wants IARB to be set when we win arbitration
5618 * and have other jobs, compute the max number of consecutive
5619 * settings of IARB hints before we leave devices a chance to
5620 * arbitrate for reselection.
5622 #ifdef SYM_SETUP_IARB_MAX
5623 np->iarb_max = SYM_SETUP_IARB_MAX;
5630 * Prepare the idle and invalid task actions.
5632 np->idletask.start = cpu_to_scr(SCRIPTA_BA(np, idle));
5633 np->idletask.restart = cpu_to_scr(SCRIPTB_BA(np, bad_i_t_l));
5634 np->idletask_ba = vtobus(&np->idletask);
5636 np->notask.start = cpu_to_scr(SCRIPTA_BA(np, idle));
5637 np->notask.restart = cpu_to_scr(SCRIPTB_BA(np, bad_i_t_l));
5638 np->notask_ba = vtobus(&np->notask);
5640 np->bad_itl.start = cpu_to_scr(SCRIPTA_BA(np, idle));
5641 np->bad_itl.restart = cpu_to_scr(SCRIPTB_BA(np, bad_i_t_l));
5642 np->bad_itl_ba = vtobus(&np->bad_itl);
5644 np->bad_itlq.start = cpu_to_scr(SCRIPTA_BA(np, idle));
5645 np->bad_itlq.restart = cpu_to_scr(SCRIPTB_BA(np,bad_i_t_l_q));
5646 np->bad_itlq_ba = vtobus(&np->bad_itlq);
5649 * Allocate and prepare the lun JUMP table that is used
5650 * for a target prior the probing of devices (bad lun table).
5651 * A private table will be allocated for the target on the
5652 * first INQUIRY response received.
5654 np->badluntbl = sym_calloc_dma(256, "BADLUNTBL");
5658 np->badlun_sa = cpu_to_scr(SCRIPTB_BA(np, resel_bad_lun));
5659 for (i = 0 ; i < 64 ; i++) /* 64 luns/target, no less */
5660 np->badluntbl[i] = cpu_to_scr(vtobus(&np->badlun_sa));
5663 * Prepare the bus address array that contains the bus
5664 * address of each target control block.
5665 * For now, assume all logical units are wrong. :)
5667 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) {
5668 np->targtbl[i] = cpu_to_scr(vtobus(&np->target[i]));
5669 np->target[i].head.luntbl_sa =
5670 cpu_to_scr(vtobus(np->badluntbl));
5671 np->target[i].head.lun0_sa =
5672 cpu_to_scr(vtobus(&np->badlun_sa));
5676 * Now check the cache handling of the pci chipset.
5678 if (sym_snooptest (np)) {
5679 printf("%s: CACHE INCORRECTLY CONFIGURED.\n", sym_name(np));
5684 * Sigh! we are done.
5693 * Free everything that has been allocated for this device.
5695 void sym_hcb_free(struct sym_hcb *np)
5703 sym_mfree_dma(np->scriptz0, np->scriptz_sz, "SCRIPTZ0");
5705 sym_mfree_dma(np->scriptb0, np->scriptb_sz, "SCRIPTB0");
5707 sym_mfree_dma(np->scripta0, np->scripta_sz, "SCRIPTA0");
5709 sym_mfree_dma(np->squeue, sizeof(u32)*(MAX_QUEUE*2), "SQUEUE");
5711 sym_mfree_dma(np->dqueue, sizeof(u32)*(MAX_QUEUE*2), "DQUEUE");
5714 while ((qp = sym_remque_head(&np->free_ccbq)) != 0) {
5715 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
5716 sym_mfree_dma(cp, sizeof(*cp), "CCB");
5722 sym_mfree_dma(np->badluntbl, 256,"BADLUNTBL");
5724 for (target = 0; target < SYM_CONF_MAX_TARGET ; target++) {
5725 tp = &np->target[target];
5726 #if SYM_CONF_MAX_LUN > 1
5731 sym_mfree_dma(np->targtbl, 256, "TARGTBL");
projects / linux-2.6 / blob