1 #ifndef _PARISC_PGTABLE_H
2 #define _PARISC_PGTABLE_H
4 #include <asm-generic/4level-fixup.h>
6 #include <linux/config.h>
7 #include <asm/fixmap.h>
11 * we simulate an x86-style page table for the linux mm code
14 #include <linux/spinlock.h>
15 #include <linux/mm.h> /* for vm_area_struct */
16 #include <asm/processor.h>
17 #include <asm/cache.h>
18 #include <asm/bitops.h>
21 * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
22 * memory. For the return value to be meaningful, ADDR must be >=
23 * PAGE_OFFSET. This operation can be relatively expensive (e.g.,
24 * require a hash-, or multi-level tree-lookup or something of that
25 * sort) but it guarantees to return TRUE only if accessing the page
26 * at that address does not cause an error. Note that there may be
27 * addresses for which kern_addr_valid() returns FALSE even though an
28 * access would not cause an error (e.g., this is typically true for
29 * memory mapped I/O regions.
31 * XXX Need to implement this for parisc.
33 #define kern_addr_valid(addr) (1)
35 /* Certain architectures need to do special things when PTEs
36 * within a page table are directly modified. Thus, the following
37 * hook is made available.
39 #define set_pte(pteptr, pteval) \
41 *(pteptr) = (pteval); \
43 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
45 #endif /* !__ASSEMBLY__ */
47 #define pte_ERROR(e) \
48 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
49 #define pmd_ERROR(e) \
50 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, (unsigned long)pmd_val(e))
51 #define pgd_ERROR(e) \
52 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, (unsigned long)pgd_val(e))
54 /* Note: If you change ISTACK_SIZE, you need to change the corresponding
55 * values in vmlinux.lds and vmlinux64.lds (init_istack section). Also,
56 * the "order" and size need to agree.
59 #define ISTACK_SIZE 32768 /* Interrupt Stack Size */
60 #define ISTACK_ORDER 3
62 /* This is the size of the initially mapped kernel memory (i.e. currently
63 * 0 to 1<<23 == 8MB */
65 #define KERNEL_INITIAL_ORDER 24
67 #define KERNEL_INITIAL_ORDER 23
69 #define KERNEL_INITIAL_SIZE (1 << KERNEL_INITIAL_ORDER)
73 #define PGD_ORDER 1 /* Number of pages per pgd */
74 #define PMD_ORDER 1 /* Number of pages per pmd */
75 #define PGD_ALLOC_ORDER 2 /* first pgd contains pmd */
78 #define PGD_ORDER 1 /* Number of pages per pgd */
79 #define PGD_ALLOC_ORDER PGD_ORDER
82 /* Definitions for 3rd level (we use PLD here for Page Lower directory
83 * because PTE_SHIFT is used lower down to mean shift that has to be
84 * done to get usable bits out of the PTE) */
85 #define PLD_SHIFT PAGE_SHIFT
86 #define PLD_SIZE PAGE_SIZE
87 #define BITS_PER_PTE (PAGE_SHIFT - BITS_PER_PTE_ENTRY)
88 #define PTRS_PER_PTE (1UL << BITS_PER_PTE)
90 /* Definitions for 2nd level */
91 #define pgtable_cache_init() do { } while (0)
93 #define PMD_SHIFT (PLD_SHIFT + BITS_PER_PTE)
94 #define PMD_SIZE (1UL << PMD_SHIFT)
95 #define PMD_MASK (~(PMD_SIZE-1))
97 #define BITS_PER_PMD (PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY)
99 #define BITS_PER_PMD 0
101 #define PTRS_PER_PMD (1UL << BITS_PER_PMD)
103 /* Definitions for 1st level */
104 #define PGDIR_SHIFT (PMD_SHIFT + BITS_PER_PMD)
105 #define BITS_PER_PGD (PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY)
106 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
107 #define PGDIR_MASK (~(PGDIR_SIZE-1))
108 #define PTRS_PER_PGD (1UL << BITS_PER_PGD)
109 #define USER_PTRS_PER_PGD PTRS_PER_PGD
111 #define MAX_ADDRBITS (PGDIR_SHIFT + BITS_PER_PGD)
112 #define MAX_ADDRESS (1UL << MAX_ADDRBITS)
114 #define SPACEID_SHIFT (MAX_ADDRBITS - 32)
116 /* This calculates the number of initial pages we need for the initial
118 #define PT_INITIAL (1 << (KERNEL_INITIAL_ORDER - PMD_SHIFT))
121 * pgd entries used up by user/kernel:
124 #define FIRST_USER_ADDRESS 0
127 extern void *vmalloc_start;
128 #define PCXL_DMA_MAP_SIZE (8*1024*1024)
129 #define VMALLOC_START ((unsigned long)vmalloc_start)
130 /* this is a fixmap remnant, see fixmap.h */
131 #define VMALLOC_END (KERNEL_MAP_END)
134 /* NB: The tlb miss handlers make certain assumptions about the order */
135 /* of the following bits, so be careful (One example, bits 25-31 */
136 /* are moved together in one instruction). */
138 #define _PAGE_READ_BIT 31 /* (0x001) read access allowed */
139 #define _PAGE_WRITE_BIT 30 /* (0x002) write access allowed */
140 #define _PAGE_EXEC_BIT 29 /* (0x004) execute access allowed */
141 #define _PAGE_GATEWAY_BIT 28 /* (0x008) privilege promotion allowed */
142 #define _PAGE_DMB_BIT 27 /* (0x010) Data Memory Break enable (B bit) */
143 #define _PAGE_DIRTY_BIT 26 /* (0x020) Page Dirty (D bit) */
144 #define _PAGE_FILE_BIT _PAGE_DIRTY_BIT /* overload this bit */
145 #define _PAGE_REFTRAP_BIT 25 /* (0x040) Page Ref. Trap enable (T bit) */
146 #define _PAGE_NO_CACHE_BIT 24 /* (0x080) Uncached Page (U bit) */
147 #define _PAGE_ACCESSED_BIT 23 /* (0x100) Software: Page Accessed */
148 #define _PAGE_PRESENT_BIT 22 /* (0x200) Software: translation valid */
149 #define _PAGE_FLUSH_BIT 21 /* (0x400) Software: translation valid */
150 /* for cache flushing only */
151 #define _PAGE_USER_BIT 20 /* (0x800) Software: User accessible page */
153 /* N.B. The bits are defined in terms of a 32 bit word above, so the */
154 /* following macro is ok for both 32 and 64 bit. */
156 #define xlate_pabit(x) (31 - x)
158 /* this defines the shift to the usable bits in the PTE it is set so
159 * that the valid bits _PAGE_PRESENT_BIT and _PAGE_USER_BIT are set
161 #define PTE_SHIFT xlate_pabit(_PAGE_USER_BIT)
163 /* this is how many bits may be used by the file functions */
164 #define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_SHIFT)
166 #define pte_to_pgoff(pte) (pte_val(pte) >> PTE_SHIFT)
167 #define pgoff_to_pte(off) ((pte_t) { ((off) << PTE_SHIFT) | _PAGE_FILE })
169 #define _PAGE_READ (1 << xlate_pabit(_PAGE_READ_BIT))
170 #define _PAGE_WRITE (1 << xlate_pabit(_PAGE_WRITE_BIT))
171 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
172 #define _PAGE_EXEC (1 << xlate_pabit(_PAGE_EXEC_BIT))
173 #define _PAGE_GATEWAY (1 << xlate_pabit(_PAGE_GATEWAY_BIT))
174 #define _PAGE_DMB (1 << xlate_pabit(_PAGE_DMB_BIT))
175 #define _PAGE_DIRTY (1 << xlate_pabit(_PAGE_DIRTY_BIT))
176 #define _PAGE_REFTRAP (1 << xlate_pabit(_PAGE_REFTRAP_BIT))
177 #define _PAGE_NO_CACHE (1 << xlate_pabit(_PAGE_NO_CACHE_BIT))
178 #define _PAGE_ACCESSED (1 << xlate_pabit(_PAGE_ACCESSED_BIT))
179 #define _PAGE_PRESENT (1 << xlate_pabit(_PAGE_PRESENT_BIT))
180 #define _PAGE_FLUSH (1 << xlate_pabit(_PAGE_FLUSH_BIT))
181 #define _PAGE_USER (1 << xlate_pabit(_PAGE_USER_BIT))
182 #define _PAGE_FILE (1 << xlate_pabit(_PAGE_FILE_BIT))
184 #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED)
185 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
186 #define _PAGE_KERNEL (_PAGE_PRESENT | _PAGE_EXEC | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED)
188 /* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds
189 * are page-aligned, we don't care about the PAGE_OFFSET bits, except
190 * for a few meta-information bits, so we shift the address to be
191 * able to effectively address 40-bits of physical address space. */
192 #define _PxD_PRESENT_BIT 31
193 #define _PxD_ATTACHED_BIT 30
194 #define _PxD_VALID_BIT 29
196 #define PxD_FLAG_PRESENT (1 << xlate_pabit(_PxD_PRESENT_BIT))
197 #define PxD_FLAG_ATTACHED (1 << xlate_pabit(_PxD_ATTACHED_BIT))
198 #define PxD_FLAG_VALID (1 << xlate_pabit(_PxD_VALID_BIT))
199 #define PxD_FLAG_MASK (0xf)
200 #define PxD_FLAG_SHIFT (4)
201 #define PxD_VALUE_SHIFT (8)
205 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
206 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_ACCESSED)
207 /* Others seem to make this executable, I don't know if that's correct
208 or not. The stack is mapped this way though so this is necessary
209 in the short term - dhd@linuxcare.com, 2000-08-08 */
210 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_ACCESSED)
211 #define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITE | _PAGE_ACCESSED)
212 #define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_EXEC |_PAGE_ACCESSED)
213 #define PAGE_COPY PAGE_EXECREAD
214 #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC |_PAGE_ACCESSED)
215 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
216 #define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE)
217 #define PAGE_KERNEL_UNC __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE)
218 #define PAGE_GATEWAY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_GATEWAY| _PAGE_READ)
219 #define PAGE_FLUSH __pgprot(_PAGE_FLUSH)
223 * We could have an execute only page using "gateway - promote to priv
224 * level 3", but that is kind of silly. So, the way things are defined
225 * now, we must always have read permission for pages with execute
226 * permission. For the fun of it we'll go ahead and support write only
231 #define __P000 PAGE_NONE
232 #define __P001 PAGE_READONLY
233 #define __P010 __P000 /* copy on write */
234 #define __P011 __P001 /* copy on write */
235 #define __P100 PAGE_EXECREAD
236 #define __P101 PAGE_EXECREAD
237 #define __P110 __P100 /* copy on write */
238 #define __P111 __P101 /* copy on write */
240 #define __S000 PAGE_NONE
241 #define __S001 PAGE_READONLY
242 #define __S010 PAGE_WRITEONLY
243 #define __S011 PAGE_SHARED
244 #define __S100 PAGE_EXECREAD
245 #define __S101 PAGE_EXECREAD
246 #define __S110 PAGE_RWX
247 #define __S111 PAGE_RWX
249 extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */
251 /* initial page tables for 0-8MB for kernel */
255 /* zero page used for uninitialized stuff */
257 extern unsigned long *empty_zero_page;
260 * ZERO_PAGE is a global shared page that is always zero: used
261 * for zero-mapped memory areas etc..
264 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
266 #define pte_none(x) ((pte_val(x) == 0) || (pte_val(x) & _PAGE_FLUSH))
267 #define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
268 #define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0)
270 #define pmd_flag(x) (pmd_val(x) & PxD_FLAG_MASK)
271 #define pmd_address(x) ((unsigned long)(pmd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
272 #define pgd_flag(x) (pgd_val(x) & PxD_FLAG_MASK)
273 #define pgd_address(x) ((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
276 /* The first entry of the permanent pmd is not there if it contains
277 * the gateway marker */
278 #define pmd_none(x) (!pmd_val(x) || pmd_flag(x) == PxD_FLAG_ATTACHED)
280 #define pmd_none(x) (!pmd_val(x))
282 #define pmd_bad(x) (!(pmd_flag(x) & PxD_FLAG_VALID))
283 #define pmd_present(x) (pmd_flag(x) & PxD_FLAG_PRESENT)
284 static inline void pmd_clear(pmd_t *pmd) {
286 if (pmd_flag(*pmd) & PxD_FLAG_ATTACHED)
287 /* This is the entry pointing to the permanent pmd
288 * attached to the pgd; cannot clear it */
289 __pmd_val_set(*pmd, PxD_FLAG_ATTACHED);
292 __pmd_val_set(*pmd, 0);
298 #define pgd_page(pgd) ((unsigned long) __va(pgd_address(pgd)))
300 /* For 64 bit we have three level tables */
302 #define pgd_none(x) (!pgd_val(x))
303 #define pgd_bad(x) (!(pgd_flag(x) & PxD_FLAG_VALID))
304 #define pgd_present(x) (pgd_flag(x) & PxD_FLAG_PRESENT)
305 static inline void pgd_clear(pgd_t *pgd) {
307 if(pgd_flag(*pgd) & PxD_FLAG_ATTACHED)
308 /* This is the permanent pmd attached to the pgd; cannot
312 __pgd_val_set(*pgd, 0);
316 * The "pgd_xxx()" functions here are trivial for a folded two-level
317 * setup: the pgd is never bad, and a pmd always exists (as it's folded
318 * into the pgd entry)
320 extern inline int pgd_none(pgd_t pgd) { return 0; }
321 extern inline int pgd_bad(pgd_t pgd) { return 0; }
322 extern inline int pgd_present(pgd_t pgd) { return 1; }
323 extern inline void pgd_clear(pgd_t * pgdp) { }
327 * The following only work if pte_present() is true.
328 * Undefined behaviour if not..
330 extern inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; }
331 extern inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
332 extern inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
333 extern inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
334 extern inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
335 extern inline int pte_user(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
337 extern inline pte_t pte_rdprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_READ; return pte; }
338 extern inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
339 extern inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
340 extern inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_WRITE; return pte; }
341 extern inline pte_t pte_mkread(pte_t pte) { pte_val(pte) |= _PAGE_READ; return pte; }
342 extern inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; }
343 extern inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
344 extern inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return pte; }
347 * Conversion functions: convert a page and protection to a page entry,
348 * and a page entry and page directory to the page they refer to.
350 #define __mk_pte(addr,pgprot) \
354 pte_val(__pte) = ((addr)+pgprot_val(pgprot)); \
359 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
361 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
364 pte_val(pte) = (pfn << PAGE_SHIFT) | pgprot_val(pgprot);
368 /* This takes a physical page address that is used by the remapping functions */
369 #define mk_pte_phys(physpage, pgprot) \
370 ({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; })
372 extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
373 { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
375 /* Permanent address of a page. On parisc we don't have highmem. */
377 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
379 #define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
381 #define pmd_page_kernel(pmd) ((unsigned long) __va(pmd_address(pmd)))
383 #define __pmd_page(pmd) ((unsigned long) __va(pmd_address(pmd)))
384 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
386 #define pgd_index(address) ((address) >> PGDIR_SHIFT)
388 /* to find an entry in a page-table-directory */
389 #define pgd_offset(mm, address) \
390 ((mm)->pgd + ((address) >> PGDIR_SHIFT))
392 /* to find an entry in a kernel page-table-directory */
393 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
395 /* Find an entry in the second-level page table.. */
398 #define pmd_offset(dir,address) \
399 ((pmd_t *) pgd_page(*(dir)) + (((address)>>PMD_SHIFT) & (PTRS_PER_PMD-1)))
401 #define pmd_offset(dir,addr) ((pmd_t *) dir)
404 /* Find an entry in the third-level page table.. */
405 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
406 #define pte_offset_kernel(pmd, address) \
407 ((pte_t *) pmd_page_kernel(*(pmd)) + pte_index(address))
408 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
409 #define pte_offset_map_nested(pmd, address) pte_offset_kernel(pmd, address)
410 #define pte_unmap(pte) do { } while (0)
411 #define pte_unmap_nested(pte) do { } while (0)
413 #define pte_unmap(pte) do { } while (0)
414 #define pte_unmap_nested(pte) do { } while (0)
416 extern void paging_init (void);
418 /* Used for deferring calls to flush_dcache_page() */
420 #define PG_dcache_dirty PG_arch_1
422 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
424 /* Encode and de-code a swap entry */
426 #define __swp_type(x) ((x).val & 0x1f)
427 #define __swp_offset(x) ( (((x).val >> 6) & 0x7) | \
428 (((x).val >> 8) & ~0x7) )
429 #define __swp_entry(type, offset) ((swp_entry_t) { (type) | \
430 ((offset & 0x7) << 6) | \
431 ((offset & ~0x7) << 8) })
432 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
433 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
435 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
438 if (!pte_young(*ptep))
440 return test_and_clear_bit(xlate_pabit(_PAGE_ACCESSED_BIT), &pte_val(*ptep));
445 set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
450 static inline int ptep_test_and_clear_dirty(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
453 if (!pte_dirty(*ptep))
455 return test_and_clear_bit(xlate_pabit(_PAGE_DIRTY_BIT), &pte_val(*ptep));
460 set_pte_at(vma->vm_mm, addr, ptep, pte_mkclean(pte));
465 extern spinlock_t pa_dbit_lock;
468 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
473 spin_lock(&pa_dbit_lock);
474 pte = old_pte = *ptep;
475 pte_val(pte) &= ~_PAGE_PRESENT;
476 pte_val(pte) |= _PAGE_FLUSH;
477 set_pte_at(mm,addr,ptep,pte);
478 spin_unlock(&pa_dbit_lock);
483 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
486 unsigned long new, old;
489 old = pte_val(*ptep);
490 new = pte_val(pte_wrprotect(__pte (old)));
491 } while (cmpxchg((unsigned long *) ptep, old, new) != old);
493 pte_t old_pte = *ptep;
494 set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
498 #define pte_same(A,B) (pte_val(A) == pte_val(B))
500 #endif /* !__ASSEMBLY__ */
502 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
503 remap_pfn_range(vma, vaddr, pfn, size, prot)
505 #define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE)
507 #define MK_IOSPACE_PFN(space, pfn) (pfn)
508 #define GET_IOSPACE(pfn) 0
509 #define GET_PFN(pfn) (pfn)
511 /* We provide our own get_unmapped_area to provide cache coherency */
513 #define HAVE_ARCH_UNMAPPED_AREA
515 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
516 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
517 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
518 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
519 #define __HAVE_ARCH_PTE_SAME
520 #include <asm-generic/pgtable.h>
522 #endif /* _PARISC_PGTABLE_H */