2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003, 04, 07 Ralf Baechle <ralf@linux-mips.org>
7 * Copyright (C) MIPS Technologies, Inc.
8 * written by Ralf Baechle <ralf@linux-mips.org>
10 #ifndef _ASM_HAZARDS_H
11 #define _ASM_HAZARDS_H
14 #define ASMMACRO(name, code...) .macro name; code; .endm
17 #include <asm/cpu-features.h>
19 #define ASMMACRO(name, code...) \
20 __asm__(".macro " #name "; " #code "; .endm"); \
22 static inline void name(void) \
24 __asm__ __volatile__ (#name); \
28 * MIPS R2 instruction hazard barrier. Needs to be called as a subroutine.
30 extern void mips_ihb(void);
45 #if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_CAVIUM_OCTEON)
48 * MIPSR2 defines ehb for hazard avoidance
51 ASMMACRO(mtc0_tlbw_hazard,
54 ASMMACRO(tlbw_use_hazard,
57 ASMMACRO(tlb_probe_hazard,
60 ASMMACRO(irq_enable_hazard,
63 ASMMACRO(irq_disable_hazard,
66 ASMMACRO(back_to_back_c0_hazard,
70 * gcc has a tradition of misscompiling the previous construct using the
71 * address of a label as argument to inline assembler. Gas otoh has the
72 * annoying difference between la and dla which are only usable for 32-bit
73 * rsp. 64-bit code, so can't be used without conditional compilation.
74 * The alterantive is switching the assembler to 64-bit code which happens
75 * to work right even for 32-bit code ...
77 #define instruction_hazard() \
81 __asm__ __volatile__( \
90 #elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MACH_ALCHEMY)
93 * These are slightly complicated by the fact that we guarantee R1 kernels to
94 * run fine on R2 processors.
96 ASMMACRO(mtc0_tlbw_hazard,
99 ASMMACRO(tlbw_use_hazard,
100 _ssnop; _ssnop; _ssnop; _ehb
102 ASMMACRO(tlb_probe_hazard,
103 _ssnop; _ssnop; _ssnop; _ehb
105 ASMMACRO(irq_enable_hazard,
106 _ssnop; _ssnop; _ssnop; _ehb
108 ASMMACRO(irq_disable_hazard,
109 _ssnop; _ssnop; _ssnop; _ehb
111 ASMMACRO(back_to_back_c0_hazard,
112 _ssnop; _ssnop; _ssnop; _ehb
115 * gcc has a tradition of misscompiling the previous construct using the
116 * address of a label as argument to inline assembler. Gas otoh has the
117 * annoying difference between la and dla which are only usable for 32-bit
118 * rsp. 64-bit code, so can't be used without conditional compilation.
119 * The alterantive is switching the assembler to 64-bit code which happens
120 * to work right even for 32-bit code ...
122 #define __instruction_hazard() \
126 __asm__ __volatile__( \
127 " .set mips64r2 \n" \
135 #define instruction_hazard() \
137 if (cpu_has_mips_r2) \
138 __instruction_hazard(); \
141 #elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
142 defined(CONFIG_CPU_R5500) || defined(CONFIG_MACH_ALCHEMY)
145 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
148 ASMMACRO(mtc0_tlbw_hazard,
150 ASMMACRO(tlbw_use_hazard,
152 ASMMACRO(tlb_probe_hazard,
154 ASMMACRO(irq_enable_hazard,
156 ASMMACRO(irq_disable_hazard,
158 ASMMACRO(back_to_back_c0_hazard,
160 #define instruction_hazard() do { } while (0)
162 #elif defined(CONFIG_CPU_RM9000)
165 * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
166 * use of the JTLB for instructions should not occur for 4 cpu cycles and use
167 * for data translations should not occur for 3 cpu cycles.
170 ASMMACRO(mtc0_tlbw_hazard,
171 _ssnop; _ssnop; _ssnop; _ssnop
173 ASMMACRO(tlbw_use_hazard,
174 _ssnop; _ssnop; _ssnop; _ssnop
176 ASMMACRO(tlb_probe_hazard,
177 _ssnop; _ssnop; _ssnop; _ssnop
179 ASMMACRO(irq_enable_hazard,
181 ASMMACRO(irq_disable_hazard,
183 ASMMACRO(back_to_back_c0_hazard,
185 #define instruction_hazard() do { } while (0)
187 #elif defined(CONFIG_CPU_SB1)
190 * Mostly like R4000 for historic reasons
192 ASMMACRO(mtc0_tlbw_hazard,
194 ASMMACRO(tlbw_use_hazard,
196 ASMMACRO(tlb_probe_hazard,
198 ASMMACRO(irq_enable_hazard,
200 ASMMACRO(irq_disable_hazard,
201 _ssnop; _ssnop; _ssnop
203 ASMMACRO(back_to_back_c0_hazard,
205 #define instruction_hazard() do { } while (0)
210 * Finally the catchall case for all other processors including R4000, R4400,
211 * R4600, R4700, R5000, RM7000, NEC VR41xx etc.
213 * The taken branch will result in a two cycle penalty for the two killed
214 * instructions on R4000 / R4400. Other processors only have a single cycle
215 * hazard so this is nice trick to have an optimal code for a range of
218 ASMMACRO(mtc0_tlbw_hazard,
221 ASMMACRO(tlbw_use_hazard,
224 ASMMACRO(tlb_probe_hazard,
227 ASMMACRO(irq_enable_hazard,
228 _ssnop; _ssnop; _ssnop;
230 ASMMACRO(irq_disable_hazard,
233 ASMMACRO(back_to_back_c0_hazard,
234 _ssnop; _ssnop; _ssnop;
236 #define instruction_hazard() do { } while (0)
243 #if defined(CONFIG_CPU_SB1)
244 ASMMACRO(enable_fpu_hazard,
253 ASMMACRO(disable_fpu_hazard,
256 #elif defined(CONFIG_CPU_MIPSR2)
257 ASMMACRO(enable_fpu_hazard,
260 ASMMACRO(disable_fpu_hazard,
264 ASMMACRO(enable_fpu_hazard,
267 ASMMACRO(disable_fpu_hazard,
272 #endif /* _ASM_HAZARDS_H */