git.oblomov.eu Git - linux-2.6/blob - arch/mips/sibyte/bcm1480/irq.c

   1 /*
   2  * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/linkage.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/mm.h>
  24 #include <linux/slab.h>
  25 #include <linux/kernel_stat.h>
  26
  27 #include <asm/errno.h>
  28 #include <asm/signal.h>
  29 #include <asm/system.h>
  30 #include <asm/ptrace.h>
  31 #include <asm/io.h>
  32
  33 #include <asm/sibyte/bcm1480_regs.h>
  34 #include <asm/sibyte/bcm1480_int.h>
  35 #include <asm/sibyte/bcm1480_scd.h>
  36
  37 #include <asm/sibyte/sb1250_uart.h>
  38 #include <asm/sibyte/sb1250.h>
  39
  40 /*
  41  * These are the routines that handle all the low level interrupt stuff.
  42  * Actions handled here are: initialization of the interrupt map, requesting of
  43  * interrupt lines by handlers, dispatching if interrupts to handlers, probing
  44  * for interrupt lines
  45  */
  46
  47
  48 #define shutdown_bcm1480_irq    disable_bcm1480_irq
  49 static void end_bcm1480_irq(unsigned int irq);
  50 static void enable_bcm1480_irq(unsigned int irq);
  51 static void disable_bcm1480_irq(unsigned int irq);
  52 static unsigned int startup_bcm1480_irq(unsigned int irq);
  53 static void ack_bcm1480_irq(unsigned int irq);
  54 #ifdef CONFIG_SMP
  55 static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask);
  56 #endif
  57
  58 #ifdef CONFIG_PCI
  59 extern unsigned long ht_eoi_space;
  60 #endif
  61
  62 #ifdef CONFIG_KGDB
  63 #include <asm/gdb-stub.h>
  64 extern void breakpoint(void);
  65 static int kgdb_irq;
  66 #ifdef CONFIG_GDB_CONSOLE
  67 extern void register_gdb_console(void);
  68 #endif
  69
  70 /* kgdb is on when configured.  Pass "nokgdb" kernel arg to turn it off */
  71 static int kgdb_flag = 1;
  72 static int __init nokgdb(char *str)
  73 {
  74         kgdb_flag = 0;
  75         return 1;
  76 }
  77 __setup("nokgdb", nokgdb);
  78
  79 /* Default to UART1 */
  80 int kgdb_port = 1;
  81 #ifdef CONFIG_SIBYTE_SB1250_DUART
  82 extern char sb1250_duart_present[];
  83 #endif
  84 #endif
  85
  86 static struct irq_chip bcm1480_irq_type = {
  87         .typename = "BCM1480-IMR",
  88         .startup = startup_bcm1480_irq,
  89         .shutdown = shutdown_bcm1480_irq,
  90         .enable = enable_bcm1480_irq,
  91         .disable = disable_bcm1480_irq,
  92         .ack = ack_bcm1480_irq,
  93         .end = end_bcm1480_irq,
  94 #ifdef CONFIG_SMP
  95         .set_affinity = bcm1480_set_affinity
  96 #endif
  97 };
  98
  99 /* Store the CPU id (not the logical number) */
 100 int bcm1480_irq_owner[BCM1480_NR_IRQS];
 101
 102 DEFINE_SPINLOCK(bcm1480_imr_lock);
 103
 104 void bcm1480_mask_irq(int cpu, int irq)
 105 {
 106         unsigned long flags;
 107         u64 cur_ints,hl_spacing;
 108
 109         spin_lock_irqsave(&bcm1480_imr_lock, flags);
 110         hl_spacing = 0;
 111         if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
 112                 hl_spacing = BCM1480_IMR_HL_SPACING;
 113                 irq -= BCM1480_NR_IRQS_HALF;
 114         }
 115         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
 116         cur_ints |= (((u64) 1) << irq);
 117         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
 118         spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
 119 }
 120
 121 void bcm1480_unmask_irq(int cpu, int irq)
 122 {
 123         unsigned long flags;
 124         u64 cur_ints,hl_spacing;
 125
 126         spin_lock_irqsave(&bcm1480_imr_lock, flags);
 127         hl_spacing = 0;
 128         if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
 129                 hl_spacing = BCM1480_IMR_HL_SPACING;
 130                 irq -= BCM1480_NR_IRQS_HALF;
 131         }
 132         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
 133         cur_ints &= ~(((u64) 1) << irq);
 134         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
 135         spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
 136 }
 137
 138 #ifdef CONFIG_SMP
 139 static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask)
 140 {
 141         int i = 0, old_cpu, cpu, int_on, k;
 142         u64 cur_ints;
 143         struct irq_desc *desc = irq_desc + irq;
 144         unsigned long flags;
 145         unsigned int irq_dirty;
 146
 147         i = first_cpu(mask);
 148         if (next_cpu(i, mask) <= NR_CPUS) {
 149                 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
 150                 return;
 151         }
 152
 153         /* Convert logical CPU to physical CPU */
 154         cpu = cpu_logical_map(i);
 155
 156         /* Protect against other affinity changers and IMR manipulation */
 157         spin_lock_irqsave(&desc->lock, flags);
 158         spin_lock(&bcm1480_imr_lock);
 159
 160         /* Swizzle each CPU's IMR (but leave the IP selection alone) */
 161         old_cpu = bcm1480_irq_owner[irq];
 162         irq_dirty = irq;
 163         if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
 164                 irq_dirty -= BCM1480_NR_IRQS_HALF;
 165         }
 166
 167         for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */
 168                 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
 169                 int_on = !(cur_ints & (((u64) 1) << irq_dirty));
 170                 if (int_on) {
 171                         /* If it was on, mask it */
 172                         cur_ints |= (((u64) 1) << irq_dirty);
 173                         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
 174                 }
 175                 bcm1480_irq_owner[irq] = cpu;
 176                 if (int_on) {
 177                         /* unmask for the new CPU */
 178                         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
 179                         cur_ints &= ~(((u64) 1) << irq_dirty);
 180                         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
 181                 }
 182         }
 183         spin_unlock(&bcm1480_imr_lock);
 184         spin_unlock_irqrestore(&desc->lock, flags);
 185 }
 186 #endif
 187
 188
 189 /*****************************************************************************/
 190
 191 static unsigned int startup_bcm1480_irq(unsigned int irq)
 192 {
 193         bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
 194
 195         return 0;               /* never anything pending */
 196 }
 197
 198
 199 static void disable_bcm1480_irq(unsigned int irq)
 200 {
 201         bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
 202 }
 203
 204 static void enable_bcm1480_irq(unsigned int irq)
 205 {
 206         bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
 207 }
 208
 209
 210 static void ack_bcm1480_irq(unsigned int irq)
 211 {
 212         u64 pending;
 213         unsigned int irq_dirty;
 214         int k;
 215
 216         /*
 217          * If the interrupt was an HT interrupt, now is the time to
 218          * clear it.  NOTE: we assume the HT bridge was set up to
 219          * deliver the interrupts to all CPUs (which makes affinity
 220          * changing easier for us)
 221          */
 222         irq_dirty = irq;
 223         if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
 224                 irq_dirty -= BCM1480_NR_IRQS_HALF;
 225         }
 226         for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */
 227                 pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq],
 228                                                 R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING))));
 229                 pending &= ((u64)1 << (irq_dirty));
 230                 if (pending) {
 231 #ifdef CONFIG_SMP
 232                         int i;
 233                         for (i=0; i<NR_CPUS; i++) {
 234                                 /*
 235                                  * Clear for all CPUs so an affinity switch
 236                                  * doesn't find an old status
 237                                  */
 238                                 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i),
 239                                                                 R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
 240                         }
 241 #else
 242                         __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
 243 #endif
 244
 245                         /*
 246                          * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
 247                          * Pass 2, the LDT world may be edge-triggered, but
 248                          * this EOI shouldn't hurt.  If they are
 249                          * level-sensitive, the EOI is required.
 250                          */
 251 #ifdef CONFIG_PCI
 252                         if (ht_eoi_space)
 253                                 *(uint32_t *)(ht_eoi_space+(irq<<16)+(7<<2)) = 0;
 254 #endif
 255                 }
 256         }
 257         bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
 258 }
 259
 260
 261 static void end_bcm1480_irq(unsigned int irq)
 262 {
 263         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
 264                 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
 265         }
 266 }
 267
 268
 269 void __init init_bcm1480_irqs(void)
 270 {
 271         int i;
 272
 273         for (i = 0; i < NR_IRQS; i++) {
 274                 irq_desc[i].status = IRQ_DISABLED;
 275                 irq_desc[i].action = 0;
 276                 irq_desc[i].depth = 1;
 277                 if (i < BCM1480_NR_IRQS) {
 278                         irq_desc[i].chip = &bcm1480_irq_type;
 279                         bcm1480_irq_owner[i] = 0;
 280                 } else {
 281                         irq_desc[i].chip = &no_irq_chip;
 282                 }
 283         }
 284 }
 285
 286
 287 static irqreturn_t bcm1480_dummy_handler(int irq, void *dev_id,
 288         struct pt_regs *regs)
 289 {
 290         return IRQ_NONE;
 291 }
 292
 293 static struct irqaction bcm1480_dummy_action = {
 294         .handler = bcm1480_dummy_handler,
 295         .flags   = 0,
 296         .mask    = CPU_MASK_NONE,
 297         .name    = "bcm1480-private",
 298         .next    = NULL,
 299         .dev_id  = 0
 300 };
 301
 302 int bcm1480_steal_irq(int irq)
 303 {
 304         struct irq_desc *desc = irq_desc + irq;
 305         unsigned long flags;
 306         int retval = 0;
 307
 308         if (irq >= BCM1480_NR_IRQS)
 309                 return -EINVAL;
 310
 311         spin_lock_irqsave(&desc->lock,flags);
 312         /* Don't allow sharing at all for these */
 313         if (desc->action != NULL)
 314                 retval = -EBUSY;
 315         else {
 316                 desc->action = &bcm1480_dummy_action;
 317                 desc->depth = 0;
 318         }
 319         spin_unlock_irqrestore(&desc->lock,flags);
 320         return 0;
 321 }
 322
 323 /*
 324  *  init_IRQ is called early in the boot sequence from init/main.c.  It
 325  *  is responsible for setting up the interrupt mapper and installing the
 326  *  handler that will be responsible for dispatching interrupts to the
 327  *  "right" place.
 328  */
 329 /*
 330  * For now, map all interrupts to IP[2].  We could save
 331  * some cycles by parceling out system interrupts to different
 332  * IP lines, but keep it simple for bringup.  We'll also direct
 333  * all interrupts to a single CPU; we should probably route
 334  * PCI and LDT to one cpu and everything else to the other
 335  * to balance the load a bit.
 336  *
 337  * On the second cpu, everything is set to IP5, which is
 338  * ignored, EXCEPT the mailbox interrupt.  That one is
 339  * set to IP[2] so it is handled.  This is needed so we
 340  * can do cross-cpu function calls, as requred by SMP
 341  */
 342
 343 #define IMR_IP2_VAL     K_BCM1480_INT_MAP_I0
 344 #define IMR_IP3_VAL     K_BCM1480_INT_MAP_I1
 345 #define IMR_IP4_VAL     K_BCM1480_INT_MAP_I2
 346 #define IMR_IP5_VAL     K_BCM1480_INT_MAP_I3
 347 #define IMR_IP6_VAL     K_BCM1480_INT_MAP_I4
 348
 349 void __init arch_init_irq(void)
 350 {
 351
 352         unsigned int i, cpu;
 353         u64 tmp;
 354         unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
 355                 STATUSF_IP1 | STATUSF_IP0;
 356
 357         /* Default everything to IP2 */
 358         /* Start with _high registers which has no bit 0 interrupt source */
 359         for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) {    /* was I0 */
 360                 for (cpu = 0; cpu < 4; cpu++) {
 361                         __raw_writeq(IMR_IP2_VAL,
 362                                      IOADDR(A_BCM1480_IMR_REGISTER(cpu,
 363                                                                    R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3)));
 364                 }
 365         }
 366
 367         /* Now do _low registers */
 368         for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) {
 369                 for (cpu = 0; cpu < 4; cpu++) {
 370                         __raw_writeq(IMR_IP2_VAL,
 371                                      IOADDR(A_BCM1480_IMR_REGISTER(cpu,
 372                                                                    R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3)));
 373                 }
 374         }
 375
 376         init_bcm1480_irqs();
 377
 378         /*
 379          * Map the high 16 bits of mailbox_0 registers to IP[3], for
 380          * inter-cpu messages
 381          */
 382         /* Was I1 */
 383         for (cpu = 0; cpu < 4; cpu++) {
 384                 __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
 385                                                  (K_BCM1480_INT_MBOX_0_0 << 3)));
 386         }
 387
 388
 389         /* Clear the mailboxes.  The firmware may leave them dirty */
 390         for (cpu = 0; cpu < 4; cpu++) {
 391                 __raw_writeq(0xffffffffffffffffULL,
 392                              IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU)));
 393                 __raw_writeq(0xffffffffffffffffULL,
 394                              IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU)));
 395         }
 396
 397
 398         /* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */
 399         tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0));
 400         for (cpu = 0; cpu < 4; cpu++) {
 401                 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H)));
 402         }
 403         tmp = ~((u64) 0);
 404         for (cpu = 0; cpu < 4; cpu++) {
 405                 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L)));
 406         }
 407
 408         bcm1480_steal_irq(K_BCM1480_INT_MBOX_0_0);
 409
 410         /*
 411          * Note that the timer interrupts are also mapped, but this is
 412          * done in bcm1480_time_init().  Also, the profiling driver
 413          * does its own management of IP7.
 414          */
 415
 416 #ifdef CONFIG_KGDB
 417         imask |= STATUSF_IP6;
 418 #endif
 419         /* Enable necessary IPs, disable the rest */
 420         change_c0_status(ST0_IM, imask);
 421
 422 #ifdef CONFIG_KGDB
 423         if (kgdb_flag) {
 424                 kgdb_irq = K_BCM1480_INT_UART_0 + kgdb_port;
 425
 426 #ifdef CONFIG_SIBYTE_SB1250_DUART
 427                 sb1250_duart_present[kgdb_port] = 0;
 428 #endif
 429                 /* Setup uart 1 settings, mapper */
 430                 /* QQQ FIXME */
 431                 __raw_writeq(M_DUART_IMR_BRK, IO_SPACE_BASE + A_DUART_IMRREG(kgdb_port));
 432
 433                 bcm1480_steal_irq(kgdb_irq);
 434                 __raw_writeq(IMR_IP6_VAL,
 435                              IO_SPACE_BASE + A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
 436                              (kgdb_irq<<3));
 437                 bcm1480_unmask_irq(0, kgdb_irq);
 438
 439 #ifdef CONFIG_GDB_CONSOLE
 440                 register_gdb_console();
 441 #endif
 442                 prom_printf("Waiting for GDB on UART port %d\n", kgdb_port);
 443                 set_debug_traps();
 444                 breakpoint();
 445         }
 446 #endif
 447 }
 448
 449 #ifdef CONFIG_KGDB
 450
 451 #include <linux/delay.h>
 452
 453 #define duart_out(reg, val)     csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
 454 #define duart_in(reg)           csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
 455
 456 void bcm1480_kgdb_interrupt(struct pt_regs *regs)
 457 {
 458         /*
 459          * Clear break-change status (allow some time for the remote
 460          * host to stop the break, since we would see another
 461          * interrupt on the end-of-break too)
 462          */
 463         kstat.irqs[smp_processor_id()][kgdb_irq]++;
 464         mdelay(500);
 465         duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
 466                                 M_DUART_RX_EN | M_DUART_TX_EN);
 467         set_async_breakpoint(&regs->cp0_epc);
 468 }
 469
 470 #endif  /* CONFIG_KGDB */
 471
 472 static inline int dclz(unsigned long long x)
 473 {
 474         int lz;
 475
 476         __asm__ (
 477         "       .set    push                                            \n"
 478         "       .set    mips64                                          \n"
 479         "       dclz    %0, %1                                          \n"
 480         "       .set    pop                                             \n"
 481         : "=r" (lz)
 482         : "r" (x));
 483
 484         return lz;
 485 }
 486
 487 extern void bcm1480_timer_interrupt(struct pt_regs *regs);
 488 extern void bcm1480_mailbox_interrupt(struct pt_regs *regs);
 489 extern void bcm1480_kgdb_interrupt(struct pt_regs *regs);
 490
 491 asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
 492 {
 493         unsigned int pending;
 494
 495 #ifdef CONFIG_SIBYTE_BCM1480_PROF
 496         /* Set compare to count to silence count/compare timer interrupts */
 497         write_c0_compare(read_c0_count());
 498 #endif
 499
 500         pending = read_c0_cause();
 501
 502 #ifdef CONFIG_SIBYTE_BCM1480_PROF
 503         if (pending & CAUSEF_IP7)       /* Cpu performance counter interrupt */
 504                 sbprof_cpu_intr(exception_epc(regs));
 505         else
 506 #endif
 507
 508         if (pending & CAUSEF_IP4)
 509                 bcm1480_timer_interrupt(regs);
 510
 511 #ifdef CONFIG_SMP
 512         else if (pending & CAUSEF_IP3)
 513                 bcm1480_mailbox_interrupt(regs);
 514 #endif
 515
 516 #ifdef CONFIG_KGDB
 517         else if (pending & CAUSEF_IP6)
 518                 bcm1480_kgdb_interrupt(regs);           /* KGDB (uart 1) */
 519 #endif
 520
 521         else if (pending & CAUSEF_IP2) {
 522                 unsigned long long mask_h, mask_l;
 523                 unsigned long base;
 524
 525                 /*
 526                  * Default...we've hit an IP[2] interrupt, which means we've
 527                  * got to check the 1480 interrupt registers to figure out what
 528                  * to do.  Need to detect which CPU we're on, now that
 529                  * smp_affinity is supported.
 530                  */
 531                 base = A_BCM1480_IMR_MAPPER(smp_processor_id());
 532                 mask_h = __raw_readq(
 533                         IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H));
 534                 mask_l = __raw_readq(
 535                         IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L));
 536
 537                 if (mask_h) {
 538                         if (mask_h ^ 1)
 539                                 do_IRQ(63 - dclz(mask_h), regs);
 540                         else
 541                                 do_IRQ(127 - dclz(mask_l), regs);
 542                 }
 543         }
 544 }