Merge master.kernel.org:/pub/scm/linux/kernel/git/gregkh/pci-2.6
[linux-2.6] / drivers / char / ipmi / ipmi_smic_sm.c
1 /*
2  * ipmi_smic_sm.c
3  *
4  * The state-machine driver for an IPMI SMIC driver
5  *
6  * It started as a copy of Corey Minyard's driver for the KSC interface
7  * and the kernel patch "mmcdev-patch-245" by HP
8  *
9  * modified by: Hannes Schulz <schulz@schwaar.com>
10  *              ipmi@schwaar.com
11  *
12  *
13  * Corey Minyard's driver for the KSC interface has the following
14  * copyright notice:
15  *   Copyright 2002 MontaVista Software Inc.
16  *
17  * the kernel patch "mmcdev-patch-245" by HP has the following
18  * copyright notice:
19  * (c) Copyright 2001 Grant Grundler (c) Copyright
20  * 2001 Hewlett-Packard Company
21  *
22  *
23  *  This program is free software; you can redistribute it and/or modify it
24  *  under the terms of the GNU General Public License as published by the
25  *  Free Software Foundation; either version 2 of the License, or (at your
26  *  option) any later version.
27  *
28  *
29  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
30  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
31  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
32  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
33  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
34  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
35  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
36  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
37  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
38  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39  *
40  *  You should have received a copy of the GNU General Public License along
41  *  with this program; if not, write to the Free Software Foundation, Inc.,
42  *  675 Mass Ave, Cambridge, MA 02139, USA.  */
43
44 #include <linux/kernel.h> /* For printk. */
45 #include <linux/string.h>
46 #include <linux/module.h>
47 #include <linux/moduleparam.h>
48 #include <linux/ipmi_msgdefs.h>         /* for completion codes */
49 #include "ipmi_si_sm.h"
50
51 /* smic_debug is a bit-field
52  *      SMIC_DEBUG_ENABLE -     turned on for now
53  *      SMIC_DEBUG_MSG -        commands and their responses
54  *      SMIC_DEBUG_STATES -     state machine
55 */
56 #define SMIC_DEBUG_STATES       4
57 #define SMIC_DEBUG_MSG          2
58 #define SMIC_DEBUG_ENABLE       1
59
60 static int smic_debug = 1;
61 module_param(smic_debug, int, 0644);
62 MODULE_PARM_DESC(smic_debug, "debug bitmask, 1=enable, 2=messages, 4=states");
63
64 enum smic_states {
65         SMIC_IDLE,
66         SMIC_START_OP,
67         SMIC_OP_OK,
68         SMIC_WRITE_START,
69         SMIC_WRITE_NEXT,
70         SMIC_WRITE_END,
71         SMIC_WRITE2READ,
72         SMIC_READ_START,
73         SMIC_READ_NEXT,
74         SMIC_READ_END,
75         SMIC_HOSED
76 };
77
78 #define MAX_SMIC_READ_SIZE 80
79 #define MAX_SMIC_WRITE_SIZE 80
80 #define SMIC_MAX_ERROR_RETRIES 3
81
82 /* Timeouts in microseconds. */
83 #define SMIC_RETRY_TIMEOUT 2000000
84
85 /* SMIC Flags Register Bits */
86 #define SMIC_RX_DATA_READY      0x80
87 #define SMIC_TX_DATA_READY      0x40
88 /*
89  * SMIC_SMI and SMIC_EVM_DATA_AVAIL are only used by
90  * a few systems, and then only by Systems Management
91  * Interrupts, not by the OS.  Always ignore these bits.
92  *
93  */
94 #define SMIC_SMI                0x10
95 #define SMIC_EVM_DATA_AVAIL     0x08
96 #define SMIC_SMS_DATA_AVAIL     0x04
97 #define SMIC_FLAG_BSY           0x01
98
99 /* SMIC Error Codes */
100 #define EC_NO_ERROR             0x00
101 #define EC_ABORTED              0x01
102 #define EC_ILLEGAL_CONTROL      0x02
103 #define EC_NO_RESPONSE          0x03
104 #define EC_ILLEGAL_COMMAND      0x04
105 #define EC_BUFFER_FULL          0x05
106
107 struct si_sm_data
108 {
109         enum smic_states state;
110         struct si_sm_io *io;
111         unsigned char    write_data[MAX_SMIC_WRITE_SIZE];
112         int              write_pos;
113         int              write_count;
114         int              orig_write_count;
115         unsigned char    read_data[MAX_SMIC_READ_SIZE];
116         int              read_pos;
117         int              truncated;
118         unsigned int     error_retries;
119         long             smic_timeout;
120 };
121
122 static unsigned int init_smic_data (struct si_sm_data *smic,
123                                     struct si_sm_io *io)
124 {
125         smic->state = SMIC_IDLE;
126         smic->io = io;
127         smic->write_pos = 0;
128         smic->write_count = 0;
129         smic->orig_write_count = 0;
130         smic->read_pos = 0;
131         smic->error_retries = 0;
132         smic->truncated = 0;
133         smic->smic_timeout = SMIC_RETRY_TIMEOUT;
134
135         /* We use 3 bytes of I/O. */
136         return 3;
137 }
138
139 static int start_smic_transaction(struct si_sm_data *smic,
140                                   unsigned char *data, unsigned int size)
141 {
142         unsigned int i;
143
144         if (size < 2)
145                 return IPMI_REQ_LEN_INVALID_ERR;
146         if (size > MAX_SMIC_WRITE_SIZE)
147                 return IPMI_REQ_LEN_EXCEEDED_ERR;
148
149         if ((smic->state != SMIC_IDLE) && (smic->state != SMIC_HOSED))
150                 return IPMI_NOT_IN_MY_STATE_ERR;
151
152         if (smic_debug & SMIC_DEBUG_MSG) {
153                 printk(KERN_INFO "start_smic_transaction -");
154                 for (i = 0; i < size; i ++) {
155                         printk (" %02x", (unsigned char) (data [i]));
156                 }
157                 printk ("\n");
158         }
159         smic->error_retries = 0;
160         memcpy(smic->write_data, data, size);
161         smic->write_count = size;
162         smic->orig_write_count = size;
163         smic->write_pos = 0;
164         smic->read_pos = 0;
165         smic->state = SMIC_START_OP;
166         smic->smic_timeout = SMIC_RETRY_TIMEOUT;
167         return 0;
168 }
169
170 static int smic_get_result(struct si_sm_data *smic,
171                            unsigned char *data, unsigned int length)
172 {
173         int i;
174
175         if (smic_debug & SMIC_DEBUG_MSG) {
176                 printk (KERN_INFO "smic_get result -");
177                 for (i = 0; i < smic->read_pos; i ++) {
178                         printk (" %02x", (smic->read_data [i]));
179                 }
180                 printk ("\n");
181         }
182         if (length < smic->read_pos) {
183                 smic->read_pos = length;
184                 smic->truncated = 1;
185         }
186         memcpy(data, smic->read_data, smic->read_pos);
187
188         if ((length >= 3) && (smic->read_pos < 3)) {
189                 data[2] = IPMI_ERR_UNSPECIFIED;
190                 smic->read_pos = 3;
191         }
192         if (smic->truncated) {
193                 data[2] = IPMI_ERR_MSG_TRUNCATED;
194                 smic->truncated = 0;
195         }
196         return smic->read_pos;
197 }
198
199 static inline unsigned char read_smic_flags(struct si_sm_data *smic)
200 {
201         return smic->io->inputb(smic->io, 2);
202 }
203
204 static inline unsigned char read_smic_status(struct si_sm_data *smic)
205 {
206         return smic->io->inputb(smic->io, 1);
207 }
208
209 static inline unsigned char read_smic_data(struct si_sm_data *smic)
210 {
211         return smic->io->inputb(smic->io, 0);
212 }
213
214 static inline void write_smic_flags(struct si_sm_data *smic,
215                                     unsigned char   flags)
216 {
217         smic->io->outputb(smic->io, 2, flags);
218 }
219
220 static inline void write_smic_control(struct si_sm_data *smic,
221                                       unsigned char   control)
222 {
223         smic->io->outputb(smic->io, 1, control);
224 }
225
226 static inline void write_si_sm_data (struct si_sm_data *smic,
227                                    unsigned char   data)
228 {
229         smic->io->outputb(smic->io, 0, data);
230 }
231
232 static inline void start_error_recovery(struct si_sm_data *smic, char *reason)
233 {
234         (smic->error_retries)++;
235         if (smic->error_retries > SMIC_MAX_ERROR_RETRIES) {
236                 if (smic_debug & SMIC_DEBUG_ENABLE) {
237                         printk(KERN_WARNING
238                                "ipmi_smic_drv: smic hosed: %s\n", reason);
239                 }
240                 smic->state = SMIC_HOSED;
241         } else {
242                 smic->write_count = smic->orig_write_count;
243                 smic->write_pos = 0;
244                 smic->read_pos = 0;
245                 smic->state = SMIC_START_OP;
246                 smic->smic_timeout = SMIC_RETRY_TIMEOUT;
247         }
248 }
249
250 static inline void write_next_byte(struct si_sm_data *smic)
251 {
252         write_si_sm_data(smic, smic->write_data[smic->write_pos]);
253         (smic->write_pos)++;
254         (smic->write_count)--;
255 }
256
257 static inline void read_next_byte (struct si_sm_data *smic)
258 {
259         if (smic->read_pos >= MAX_SMIC_READ_SIZE) {
260                 read_smic_data (smic);
261                 smic->truncated = 1;
262         } else {
263                 smic->read_data[smic->read_pos] = read_smic_data(smic);
264                 (smic->read_pos)++;
265         }
266 }
267
268 /*  SMIC Control/Status Code Components */
269 #define SMIC_GET_STATUS         0x00    /* Control form's name */
270 #define SMIC_READY              0x00    /* Status  form's name */
271 #define SMIC_WR_START           0x01    /* Unified Control/Status names... */
272 #define SMIC_WR_NEXT            0x02
273 #define SMIC_WR_END             0x03
274 #define SMIC_RD_START           0x04
275 #define SMIC_RD_NEXT            0x05
276 #define SMIC_RD_END             0x06
277 #define SMIC_CODE_MASK          0x0f
278
279 #define SMIC_CONTROL            0x00
280 #define SMIC_STATUS             0x80
281 #define SMIC_CS_MASK            0x80
282
283 #define SMIC_SMS                0x40
284 #define SMIC_SMM                0x60
285 #define SMIC_STREAM_MASK        0x60
286
287 /*  SMIC Control Codes */
288 #define SMIC_CC_SMS_GET_STATUS  (SMIC_CONTROL|SMIC_SMS|SMIC_GET_STATUS)
289 #define SMIC_CC_SMS_WR_START    (SMIC_CONTROL|SMIC_SMS|SMIC_WR_START)
290 #define SMIC_CC_SMS_WR_NEXT     (SMIC_CONTROL|SMIC_SMS|SMIC_WR_NEXT)
291 #define SMIC_CC_SMS_WR_END      (SMIC_CONTROL|SMIC_SMS|SMIC_WR_END)
292 #define SMIC_CC_SMS_RD_START    (SMIC_CONTROL|SMIC_SMS|SMIC_RD_START)
293 #define SMIC_CC_SMS_RD_NEXT     (SMIC_CONTROL|SMIC_SMS|SMIC_RD_NEXT)
294 #define SMIC_CC_SMS_RD_END      (SMIC_CONTROL|SMIC_SMS|SMIC_RD_END)
295
296 #define SMIC_CC_SMM_GET_STATUS  (SMIC_CONTROL|SMIC_SMM|SMIC_GET_STATUS)
297 #define SMIC_CC_SMM_WR_START    (SMIC_CONTROL|SMIC_SMM|SMIC_WR_START)
298 #define SMIC_CC_SMM_WR_NEXT     (SMIC_CONTROL|SMIC_SMM|SMIC_WR_NEXT)
299 #define SMIC_CC_SMM_WR_END      (SMIC_CONTROL|SMIC_SMM|SMIC_WR_END)
300 #define SMIC_CC_SMM_RD_START    (SMIC_CONTROL|SMIC_SMM|SMIC_RD_START)
301 #define SMIC_CC_SMM_RD_NEXT     (SMIC_CONTROL|SMIC_SMM|SMIC_RD_NEXT)
302 #define SMIC_CC_SMM_RD_END      (SMIC_CONTROL|SMIC_SMM|SMIC_RD_END)
303
304 /*  SMIC Status Codes */
305 #define SMIC_SC_SMS_READY       (SMIC_STATUS|SMIC_SMS|SMIC_READY)
306 #define SMIC_SC_SMS_WR_START    (SMIC_STATUS|SMIC_SMS|SMIC_WR_START)
307 #define SMIC_SC_SMS_WR_NEXT     (SMIC_STATUS|SMIC_SMS|SMIC_WR_NEXT)
308 #define SMIC_SC_SMS_WR_END      (SMIC_STATUS|SMIC_SMS|SMIC_WR_END)
309 #define SMIC_SC_SMS_RD_START    (SMIC_STATUS|SMIC_SMS|SMIC_RD_START)
310 #define SMIC_SC_SMS_RD_NEXT     (SMIC_STATUS|SMIC_SMS|SMIC_RD_NEXT)
311 #define SMIC_SC_SMS_RD_END      (SMIC_STATUS|SMIC_SMS|SMIC_RD_END)
312
313 #define SMIC_SC_SMM_READY       (SMIC_STATUS|SMIC_SMM|SMIC_READY)
314 #define SMIC_SC_SMM_WR_START    (SMIC_STATUS|SMIC_SMM|SMIC_WR_START)
315 #define SMIC_SC_SMM_WR_NEXT     (SMIC_STATUS|SMIC_SMM|SMIC_WR_NEXT)
316 #define SMIC_SC_SMM_WR_END      (SMIC_STATUS|SMIC_SMM|SMIC_WR_END)
317 #define SMIC_SC_SMM_RD_START    (SMIC_STATUS|SMIC_SMM|SMIC_RD_START)
318 #define SMIC_SC_SMM_RD_NEXT     (SMIC_STATUS|SMIC_SMM|SMIC_RD_NEXT)
319 #define SMIC_SC_SMM_RD_END      (SMIC_STATUS|SMIC_SMM|SMIC_RD_END)
320
321 /* these are the control/status codes we actually use
322         SMIC_CC_SMS_GET_STATUS  0x40
323         SMIC_CC_SMS_WR_START    0x41
324         SMIC_CC_SMS_WR_NEXT     0x42
325         SMIC_CC_SMS_WR_END      0x43
326         SMIC_CC_SMS_RD_START    0x44
327         SMIC_CC_SMS_RD_NEXT     0x45
328         SMIC_CC_SMS_RD_END      0x46
329
330         SMIC_SC_SMS_READY       0xC0
331         SMIC_SC_SMS_WR_START    0xC1
332         SMIC_SC_SMS_WR_NEXT     0xC2
333         SMIC_SC_SMS_WR_END      0xC3
334         SMIC_SC_SMS_RD_START    0xC4
335         SMIC_SC_SMS_RD_NEXT     0xC5
336         SMIC_SC_SMS_RD_END      0xC6
337 */
338
339 static enum si_sm_result smic_event (struct si_sm_data *smic, long time)
340 {
341         unsigned char status;
342         unsigned char flags;
343         unsigned char data;
344
345         if (smic->state == SMIC_HOSED) {
346                 init_smic_data(smic, smic->io);
347                 return SI_SM_HOSED;
348         }
349         if (smic->state != SMIC_IDLE) {
350                 if (smic_debug & SMIC_DEBUG_STATES) {
351                         printk(KERN_INFO
352                                "smic_event - smic->smic_timeout = %ld,"
353                                " time = %ld\n",
354                                smic->smic_timeout, time);
355                 }
356 /* FIXME: smic_event is sometimes called with time > SMIC_RETRY_TIMEOUT */
357                 if (time < SMIC_RETRY_TIMEOUT) {
358                         smic->smic_timeout -= time;
359                         if (smic->smic_timeout < 0) {
360                                 start_error_recovery(smic, "smic timed out.");
361                                 return SI_SM_CALL_WITH_DELAY;
362                         }
363                 }
364         }
365         flags = read_smic_flags(smic);
366         if (flags & SMIC_FLAG_BSY)
367                 return SI_SM_CALL_WITH_DELAY;
368
369         status = read_smic_status (smic);
370         if (smic_debug & SMIC_DEBUG_STATES)
371                 printk(KERN_INFO
372                        "smic_event - state = %d, flags = 0x%02x,"
373                        " status = 0x%02x\n",
374                        smic->state, flags, status);
375
376         switch (smic->state) {
377         case SMIC_IDLE:
378                 /* in IDLE we check for available messages */
379                 if (flags & SMIC_SMS_DATA_AVAIL)
380                 {
381                         return SI_SM_ATTN;
382                 }
383                 return SI_SM_IDLE;
384
385         case SMIC_START_OP:
386                 /* sanity check whether smic is really idle */
387                 write_smic_control(smic, SMIC_CC_SMS_GET_STATUS);
388                 write_smic_flags(smic, flags | SMIC_FLAG_BSY);
389                 smic->state = SMIC_OP_OK;
390                 break;
391
392         case SMIC_OP_OK:
393                 if (status != SMIC_SC_SMS_READY) {
394                                 /* this should not happen */
395                         start_error_recovery(smic,
396                                              "state = SMIC_OP_OK,"
397                                              " status != SMIC_SC_SMS_READY");
398                         return SI_SM_CALL_WITH_DELAY;
399                 }
400                 /* OK so far; smic is idle let us start ... */
401                 write_smic_control(smic, SMIC_CC_SMS_WR_START);
402                 write_next_byte(smic);
403                 write_smic_flags(smic, flags | SMIC_FLAG_BSY);
404                 smic->state = SMIC_WRITE_START;
405                 break;
406
407         case SMIC_WRITE_START:
408                 if (status != SMIC_SC_SMS_WR_START) {
409                         start_error_recovery(smic,
410                                              "state = SMIC_WRITE_START, "
411                                              "status != SMIC_SC_SMS_WR_START");
412                         return SI_SM_CALL_WITH_DELAY;
413                 }
414                 /* we must not issue WR_(NEXT|END) unless
415                    TX_DATA_READY is set */
416                 if (flags & SMIC_TX_DATA_READY) {
417                         if (smic->write_count == 1) {
418                                 /* last byte */
419                                 write_smic_control(smic, SMIC_CC_SMS_WR_END);
420                                 smic->state = SMIC_WRITE_END;
421                         } else {
422                                 write_smic_control(smic, SMIC_CC_SMS_WR_NEXT);
423                                 smic->state = SMIC_WRITE_NEXT;
424                         }
425                         write_next_byte(smic);
426                         write_smic_flags(smic, flags | SMIC_FLAG_BSY);
427                 }
428                 else {
429                         return SI_SM_CALL_WITH_DELAY;
430                 }
431                 break;
432
433         case SMIC_WRITE_NEXT:
434                 if (status != SMIC_SC_SMS_WR_NEXT) {
435                         start_error_recovery(smic,
436                                              "state = SMIC_WRITE_NEXT, "
437                                              "status != SMIC_SC_SMS_WR_NEXT");
438                         return SI_SM_CALL_WITH_DELAY;
439                 }
440                 /* this is the same code as in SMIC_WRITE_START */
441                 if (flags & SMIC_TX_DATA_READY) {
442                         if (smic->write_count == 1) {
443                                 write_smic_control(smic, SMIC_CC_SMS_WR_END);
444                                 smic->state = SMIC_WRITE_END;
445                         }
446                         else {
447                                 write_smic_control(smic, SMIC_CC_SMS_WR_NEXT);
448                                 smic->state = SMIC_WRITE_NEXT;
449                         }
450                         write_next_byte(smic);
451                         write_smic_flags(smic, flags | SMIC_FLAG_BSY);
452                 }
453                 else {
454                         return SI_SM_CALL_WITH_DELAY;
455                 }
456                 break;
457
458         case SMIC_WRITE_END:
459                 if (status != SMIC_SC_SMS_WR_END) {
460                         start_error_recovery (smic,
461                                               "state = SMIC_WRITE_END, "
462                                               "status != SMIC_SC_SMS_WR_END");
463                         return SI_SM_CALL_WITH_DELAY;
464                 }
465                 /* data register holds an error code */
466                 data = read_smic_data(smic);
467                 if (data != 0) {
468                         if (smic_debug & SMIC_DEBUG_ENABLE) {
469                                 printk(KERN_INFO
470                                        "SMIC_WRITE_END: data = %02x\n", data);
471                         }
472                         start_error_recovery(smic,
473                                              "state = SMIC_WRITE_END, "
474                                              "data != SUCCESS");
475                         return SI_SM_CALL_WITH_DELAY;
476                 } else {
477                         smic->state = SMIC_WRITE2READ;
478                 }
479                 break;
480
481         case SMIC_WRITE2READ:
482                 /* we must wait for RX_DATA_READY to be set before we
483                    can continue */
484                 if (flags & SMIC_RX_DATA_READY) {
485                         write_smic_control(smic, SMIC_CC_SMS_RD_START);
486                         write_smic_flags(smic, flags | SMIC_FLAG_BSY);
487                         smic->state = SMIC_READ_START;
488                 } else {
489                         return SI_SM_CALL_WITH_DELAY;
490                 }
491                 break;
492
493         case SMIC_READ_START:
494                 if (status != SMIC_SC_SMS_RD_START) {
495                         start_error_recovery(smic,
496                                              "state = SMIC_READ_START, "
497                                              "status != SMIC_SC_SMS_RD_START");
498                         return SI_SM_CALL_WITH_DELAY;
499                 }
500                 if (flags & SMIC_RX_DATA_READY) {
501                         read_next_byte(smic);
502                         write_smic_control(smic, SMIC_CC_SMS_RD_NEXT);
503                         write_smic_flags(smic, flags | SMIC_FLAG_BSY);
504                         smic->state = SMIC_READ_NEXT;
505                 } else {
506                         return SI_SM_CALL_WITH_DELAY;
507                 }
508                 break;
509
510         case SMIC_READ_NEXT:
511                 switch (status) {
512                 /* smic tells us that this is the last byte to be read
513                    --> clean up */
514                 case SMIC_SC_SMS_RD_END:
515                         read_next_byte(smic);
516                         write_smic_control(smic, SMIC_CC_SMS_RD_END);
517                         write_smic_flags(smic, flags | SMIC_FLAG_BSY);
518                         smic->state = SMIC_READ_END;
519                         break;
520                 case SMIC_SC_SMS_RD_NEXT:
521                         if (flags & SMIC_RX_DATA_READY) {
522                                 read_next_byte(smic);
523                                 write_smic_control(smic, SMIC_CC_SMS_RD_NEXT);
524                                 write_smic_flags(smic, flags | SMIC_FLAG_BSY);
525                                 smic->state = SMIC_READ_NEXT;
526                         } else {
527                                 return SI_SM_CALL_WITH_DELAY;
528                         }
529                         break;
530                 default:
531                         start_error_recovery(
532                                 smic,
533                                 "state = SMIC_READ_NEXT, "
534                                 "status != SMIC_SC_SMS_RD_(NEXT|END)");
535                         return SI_SM_CALL_WITH_DELAY;
536                 }
537                 break;
538
539         case SMIC_READ_END:
540                 if (status != SMIC_SC_SMS_READY) {
541                         start_error_recovery(smic,
542                                              "state = SMIC_READ_END, "
543                                              "status != SMIC_SC_SMS_READY");
544                         return SI_SM_CALL_WITH_DELAY;
545                 }
546                 data = read_smic_data(smic);
547                 /* data register holds an error code */
548                 if (data != 0) {
549                         if (smic_debug & SMIC_DEBUG_ENABLE) {
550                                 printk(KERN_INFO
551                                        "SMIC_READ_END: data = %02x\n", data);
552                         }
553                         start_error_recovery(smic,
554                                              "state = SMIC_READ_END, "
555                                              "data != SUCCESS");
556                         return SI_SM_CALL_WITH_DELAY;
557                 } else {
558                         smic->state = SMIC_IDLE;
559                         return SI_SM_TRANSACTION_COMPLETE;
560                 }
561
562         case SMIC_HOSED:
563                 init_smic_data(smic, smic->io);
564                 return SI_SM_HOSED;
565
566         default:
567                 if (smic_debug & SMIC_DEBUG_ENABLE) {
568                         printk(KERN_WARNING "smic->state = %d\n", smic->state);
569                         start_error_recovery(smic, "state = UNKNOWN");
570                         return SI_SM_CALL_WITH_DELAY;
571                 }
572         }
573         smic->smic_timeout = SMIC_RETRY_TIMEOUT;
574         return SI_SM_CALL_WITHOUT_DELAY;
575 }
576
577 static int smic_detect(struct si_sm_data *smic)
578 {
579         /* It's impossible for the SMIC fnags register to be all 1's,
580            (assuming a properly functioning, self-initialized BMC)
581            but that's what you get from reading a bogus address, so we
582            test that first. */
583         if (read_smic_flags(smic) == 0xff)
584                 return 1;
585
586         return 0;
587 }
588
589 static void smic_cleanup(struct si_sm_data *kcs)
590 {
591 }
592
593 static int smic_size(void)
594 {
595         return sizeof(struct si_sm_data);
596 }
597
598 struct si_sm_handlers smic_smi_handlers =
599 {
600         .init_data         = init_smic_data,
601         .start_transaction = start_smic_transaction,
602         .get_result        = smic_get_result,
603         .event             = smic_event,
604         .detect            = smic_detect,
605         .cleanup           = smic_cleanup,
606         .size              = smic_size,
607 };