git.oblomov.eu Git - linux-2.6/blob - drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G-2 10/100 Network Connection
  31  * 82562GT 10/100 Network Connection
  32  * 82562GT-2 10/100 Network Connection
  33  * 82562V 10/100 Network Connection
  34  * 82562V-2 10/100 Network Connection
  35  * 82566DC-2 Gigabit Network Connection
  36  * 82566DC Gigabit Network Connection
  37  * 82566DM-2 Gigabit Network Connection
  38  * 82566DM Gigabit Network Connection
  39  * 82566MC Gigabit Network Connection
  40  * 82566MM Gigabit Network Connection
  41  * 82567LM Gigabit Network Connection
  42  * 82567LF Gigabit Network Connection
  43  * 82567LM-2 Gigabit Network Connection
  44  * 82567LF-2 Gigabit Network Connection
  45  * 82567V-2 Gigabit Network Connection
  46  * 82562GT-3 10/100 Network Connection
  47  */
  48
  49 #include <linux/netdevice.h>
  50 #include <linux/ethtool.h>
  51 #include <linux/delay.h>
  52 #include <linux/pci.h>
  53
  54 #include "e1000.h"
  55
  56 #define ICH_FLASH_GFPREG                0x0000
  57 #define ICH_FLASH_HSFSTS                0x0004
  58 #define ICH_FLASH_HSFCTL                0x0006
  59 #define ICH_FLASH_FADDR                 0x0008
  60 #define ICH_FLASH_FDATA0                0x0010
  61
  62 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  63 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  64 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  65 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  66 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  67
  68 #define ICH_CYCLE_READ                  0
  69 #define ICH_CYCLE_WRITE                 2
  70 #define ICH_CYCLE_ERASE                 3
  71
  72 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  73 #define FLASH_SECTOR_ADDR_SHIFT         12
  74
  75 #define ICH_FLASH_SEG_SIZE_256          256
  76 #define ICH_FLASH_SEG_SIZE_4K           4096
  77 #define ICH_FLASH_SEG_SIZE_8K           8192
  78 #define ICH_FLASH_SEG_SIZE_64K          65536
  79
  80
  81 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  82
  83 #define E1000_ICH_MNG_IAMT_MODE         0x2
  84
  85 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  86                                  (ID_LED_DEF1_OFF2 <<  8) | \
  87                                  (ID_LED_DEF1_ON2  <<  4) | \
  88                                  (ID_LED_DEF1_DEF2))
  89
  90 #define E1000_ICH_NVM_SIG_WORD          0x13
  91 #define E1000_ICH_NVM_SIG_MASK          0xC000
  92
  93 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
  94
  95 #define E1000_FEXTNVM_SW_CONFIG         1
  96 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
  97
  98 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
  99
 100 #define E1000_ICH_RAR_ENTRIES           7
 101
 102 #define PHY_PAGE_SHIFT 5
 103 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 104                            ((reg) & MAX_PHY_REG_ADDRESS))
 105 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 106 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 107
 108 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 109 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 110 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 111
 112 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 113 /* Offset 04h HSFSTS */
 114 union ich8_hws_flash_status {
 115         struct ich8_hsfsts {
 116                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 117                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 118                 u16 dael       :1; /* bit 2 Direct Access error Log */
 119                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 120                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 121                 u16 reserved1  :2; /* bit 13:6 Reserved */
 122                 u16 reserved2  :6; /* bit 13:6 Reserved */
 123                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 124                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 125         } hsf_status;
 126         u16 regval;
 127 };
 128
 129 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 130 /* Offset 06h FLCTL */
 131 union ich8_hws_flash_ctrl {
 132         struct ich8_hsflctl {
 133                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 134                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 135                 u16 reserved   :5;   /* 7:3 Reserved  */
 136                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 137                 u16 flockdn    :6;   /* 15:10 Reserved */
 138         } hsf_ctrl;
 139         u16 regval;
 140 };
 141
 142 /* ICH Flash Region Access Permissions */
 143 union ich8_hws_flash_regacc {
 144         struct ich8_flracc {
 145                 u32 grra      :8; /* 0:7 GbE region Read Access */
 146                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 147                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 148                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 149         } hsf_flregacc;
 150         u16 regval;
 151 };
 152
 153 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 154 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 155 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 156 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
 157 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 158 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 159                                                 u32 offset, u8 byte);
 160 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 161                                          u16 *data);
 162 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 163                                          u8 size, u16 *data);
 164 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 165 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 166
 167 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 168 {
 169         return readw(hw->flash_address + reg);
 170 }
 171
 172 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 173 {
 174         return readl(hw->flash_address + reg);
 175 }
 176
 177 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 178 {
 179         writew(val, hw->flash_address + reg);
 180 }
 181
 182 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 183 {
 184         writel(val, hw->flash_address + reg);
 185 }
 186
 187 #define er16flash(reg)          __er16flash(hw, (reg))
 188 #define er32flash(reg)          __er32flash(hw, (reg))
 189 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 190 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 191
 192 /**
 193  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 194  *  @hw: pointer to the HW structure
 195  *
 196  *  Initialize family-specific PHY parameters and function pointers.
 197  **/
 198 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 199 {
 200         struct e1000_phy_info *phy = &hw->phy;
 201         s32 ret_val;
 202         u16 i = 0;
 203
 204         phy->addr                       = 1;
 205         phy->reset_delay_us             = 100;
 206
 207         /*
 208          * We may need to do this twice - once for IGP and if that fails,
 209          * we'll set BM func pointers and try again
 210          */
 211         ret_val = e1000e_determine_phy_address(hw);
 212         if (ret_val) {
 213                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
 214                 hw->phy.ops.read_phy_reg  = e1000e_read_phy_reg_bm;
 215                 ret_val = e1000e_determine_phy_address(hw);
 216                 if (ret_val)
 217                         return ret_val;
 218         }
 219
 220         phy->id = 0;
 221         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 222                (i++ < 100)) {
 223                 msleep(1);
 224                 ret_val = e1000e_get_phy_id(hw);
 225                 if (ret_val)
 226                         return ret_val;
 227         }
 228
 229         /* Verify phy id */
 230         switch (phy->id) {
 231         case IGP03E1000_E_PHY_ID:
 232                 phy->type = e1000_phy_igp_3;
 233                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 234                 break;
 235         case IFE_E_PHY_ID:
 236         case IFE_PLUS_E_PHY_ID:
 237         case IFE_C_E_PHY_ID:
 238                 phy->type = e1000_phy_ife;
 239                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 240                 break;
 241         case BME1000_E_PHY_ID:
 242                 phy->type = e1000_phy_bm;
 243                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 244                 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
 245                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
 246                 hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
 247                 break;
 248         default:
 249                 return -E1000_ERR_PHY;
 250                 break;
 251         }
 252
 253         return 0;
 254 }
 255
 256 /**
 257  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 258  *  @hw: pointer to the HW structure
 259  *
 260  *  Initialize family-specific NVM parameters and function
 261  *  pointers.
 262  **/
 263 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 264 {
 265         struct e1000_nvm_info *nvm = &hw->nvm;
 266         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 267         u32 gfpreg;
 268         u32 sector_base_addr;
 269         u32 sector_end_addr;
 270         u16 i;
 271
 272         /* Can't read flash registers if the register set isn't mapped. */
 273         if (!hw->flash_address) {
 274                 hw_dbg(hw, "ERROR: Flash registers not mapped\n");
 275                 return -E1000_ERR_CONFIG;
 276         }
 277
 278         nvm->type = e1000_nvm_flash_sw;
 279
 280         gfpreg = er32flash(ICH_FLASH_GFPREG);
 281
 282         /*
 283          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 284          * Add 1 to sector_end_addr since this sector is included in
 285          * the overall size.
 286          */
 287         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 288         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 289
 290         /* flash_base_addr is byte-aligned */
 291         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 292
 293         /*
 294          * find total size of the NVM, then cut in half since the total
 295          * size represents two separate NVM banks.
 296          */
 297         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 298                                 << FLASH_SECTOR_ADDR_SHIFT;
 299         nvm->flash_bank_size /= 2;
 300         /* Adjust to word count */
 301         nvm->flash_bank_size /= sizeof(u16);
 302
 303         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 304
 305         /* Clear shadow ram */
 306         for (i = 0; i < nvm->word_size; i++) {
 307                 dev_spec->shadow_ram[i].modified = 0;
 308                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 309         }
 310
 311         return 0;
 312 }
 313
 314 /**
 315  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 316  *  @hw: pointer to the HW structure
 317  *
 318  *  Initialize family-specific MAC parameters and function
 319  *  pointers.
 320  **/
 321 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 322 {
 323         struct e1000_hw *hw = &adapter->hw;
 324         struct e1000_mac_info *mac = &hw->mac;
 325
 326         /* Set media type function pointer */
 327         hw->phy.media_type = e1000_media_type_copper;
 328
 329         /* Set mta register count */
 330         mac->mta_reg_count = 32;
 331         /* Set rar entry count */
 332         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 333         if (mac->type == e1000_ich8lan)
 334                 mac->rar_entry_count--;
 335         /* Set if manageability features are enabled. */
 336         mac->arc_subsystem_valid = 1;
 337
 338         /* Enable PCS Lock-loss workaround for ICH8 */
 339         if (mac->type == e1000_ich8lan)
 340                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
 341
 342         return 0;
 343 }
 344
 345 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 346 {
 347         struct e1000_hw *hw = &adapter->hw;
 348         s32 rc;
 349
 350         rc = e1000_init_mac_params_ich8lan(adapter);
 351         if (rc)
 352                 return rc;
 353
 354         rc = e1000_init_nvm_params_ich8lan(hw);
 355         if (rc)
 356                 return rc;
 357
 358         rc = e1000_init_phy_params_ich8lan(hw);
 359         if (rc)
 360                 return rc;
 361
 362         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 363             (adapter->hw.phy.type == e1000_phy_igp_3))
 364                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 365
 366         return 0;
 367 }
 368
 369 /**
 370  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 371  *  @hw: pointer to the HW structure
 372  *
 373  *  Acquires the software control flag for performing NVM and PHY
 374  *  operations.  This is a function pointer entry point only called by
 375  *  read/write routines for the PHY and NVM parts.
 376  **/
 377 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 378 {
 379         u32 extcnf_ctrl;
 380         u32 timeout = PHY_CFG_TIMEOUT;
 381
 382         while (timeout) {
 383                 extcnf_ctrl = er32(EXTCNF_CTRL);
 384                 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 385                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 386
 387                 extcnf_ctrl = er32(EXTCNF_CTRL);
 388                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 389                         break;
 390                 mdelay(1);
 391                 timeout--;
 392         }
 393
 394         if (!timeout) {
 395                 hw_dbg(hw, "FW or HW has locked the resource for too long.\n");
 396                 return -E1000_ERR_CONFIG;
 397         }
 398
 399         return 0;
 400 }
 401
 402 /**
 403  *  e1000_release_swflag_ich8lan - Release software control flag
 404  *  @hw: pointer to the HW structure
 405  *
 406  *  Releases the software control flag for performing NVM and PHY operations.
 407  *  This is a function pointer entry point only called by read/write
 408  *  routines for the PHY and NVM parts.
 409  **/
 410 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 411 {
 412         u32 extcnf_ctrl;
 413
 414         extcnf_ctrl = er32(EXTCNF_CTRL);
 415         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 416         ew32(EXTCNF_CTRL, extcnf_ctrl);
 417 }
 418
 419 /**
 420  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 421  *  @hw: pointer to the HW structure
 422  *
 423  *  Checks if firmware is blocking the reset of the PHY.
 424  *  This is a function pointer entry point only called by
 425  *  reset routines.
 426  **/
 427 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 428 {
 429         u32 fwsm;
 430
 431         fwsm = er32(FWSM);
 432
 433         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 434 }
 435
 436 /**
 437  *  e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
 438  *  @hw: pointer to the HW structure
 439  *
 440  *  Forces the speed and duplex settings of the PHY.
 441  *  This is a function pointer entry point only called by
 442  *  PHY setup routines.
 443  **/
 444 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
 445 {
 446         struct e1000_phy_info *phy = &hw->phy;
 447         s32 ret_val;
 448         u16 data;
 449         bool link;
 450
 451         if (phy->type != e1000_phy_ife) {
 452                 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
 453                 return ret_val;
 454         }
 455
 456         ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
 457         if (ret_val)
 458                 return ret_val;
 459
 460         e1000e_phy_force_speed_duplex_setup(hw, &data);
 461
 462         ret_val = e1e_wphy(hw, PHY_CONTROL, data);
 463         if (ret_val)
 464                 return ret_val;
 465
 466         /* Disable MDI-X support for 10/100 */
 467         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
 468         if (ret_val)
 469                 return ret_val;
 470
 471         data &= ~IFE_PMC_AUTO_MDIX;
 472         data &= ~IFE_PMC_FORCE_MDIX;
 473
 474         ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
 475         if (ret_val)
 476                 return ret_val;
 477
 478         hw_dbg(hw, "IFE PMC: %X\n", data);
 479
 480         udelay(1);
 481
 482         if (phy->autoneg_wait_to_complete) {
 483                 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
 484
 485                 ret_val = e1000e_phy_has_link_generic(hw,
 486                                                      PHY_FORCE_LIMIT,
 487                                                      100000,
 488                                                      &link);
 489                 if (ret_val)
 490                         return ret_val;
 491
 492                 if (!link)
 493                         hw_dbg(hw, "Link taking longer than expected.\n");
 494
 495                 /* Try once more */
 496                 ret_val = e1000e_phy_has_link_generic(hw,
 497                                                      PHY_FORCE_LIMIT,
 498                                                      100000,
 499                                                      &link);
 500                 if (ret_val)
 501                         return ret_val;
 502         }
 503
 504         return 0;
 505 }
 506
 507 /**
 508  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
 509  *  @hw: pointer to the HW structure
 510  *
 511  *  Resets the PHY
 512  *  This is a function pointer entry point called by drivers
 513  *  or other shared routines.
 514  **/
 515 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
 516 {
 517         struct e1000_phy_info *phy = &hw->phy;
 518         u32 i;
 519         u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
 520         s32 ret_val;
 521         u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
 522         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 523
 524         ret_val = e1000e_phy_hw_reset_generic(hw);
 525         if (ret_val)
 526                 return ret_val;
 527
 528         /*
 529          * Initialize the PHY from the NVM on ICH platforms.  This
 530          * is needed due to an issue where the NVM configuration is
 531          * not properly autoloaded after power transitions.
 532          * Therefore, after each PHY reset, we will load the
 533          * configuration data out of the NVM manually.
 534          */
 535         if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
 536                 struct e1000_adapter *adapter = hw->adapter;
 537
 538                 /* Check if SW needs configure the PHY */
 539                 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
 540                     (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M))
 541                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 542                 else
 543                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
 544
 545                 data = er32(FEXTNVM);
 546                 if (!(data & sw_cfg_mask))
 547                         return 0;
 548
 549                 /* Wait for basic configuration completes before proceeding*/
 550                 do {
 551                         data = er32(STATUS);
 552                         data &= E1000_STATUS_LAN_INIT_DONE;
 553                         udelay(100);
 554                 } while ((!data) && --loop);
 555
 556                 /*
 557                  * If basic configuration is incomplete before the above loop
 558                  * count reaches 0, loading the configuration from NVM will
 559                  * leave the PHY in a bad state possibly resulting in no link.
 560                  */
 561                 if (loop == 0) {
 562                         hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
 563                 }
 564
 565                 /* Clear the Init Done bit for the next init event */
 566                 data = er32(STATUS);
 567                 data &= ~E1000_STATUS_LAN_INIT_DONE;
 568                 ew32(STATUS, data);
 569
 570                 /*
 571                  * Make sure HW does not configure LCD from PHY
 572                  * extended configuration before SW configuration
 573                  */
 574                 data = er32(EXTCNF_CTRL);
 575                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
 576                         return 0;
 577
 578                 cnf_size = er32(EXTCNF_SIZE);
 579                 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
 580                 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
 581                 if (!cnf_size)
 582                         return 0;
 583
 584                 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
 585                 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
 586
 587                 /* Configure LCD from extended configuration region. */
 588
 589                 /* cnf_base_addr is in DWORD */
 590                 word_addr = (u16)(cnf_base_addr << 1);
 591
 592                 for (i = 0; i < cnf_size; i++) {
 593                         ret_val = e1000_read_nvm(hw,
 594                                                 (word_addr + i * 2),
 595                                                 1,
 596                                                 &reg_data);
 597                         if (ret_val)
 598                                 return ret_val;
 599
 600                         ret_val = e1000_read_nvm(hw,
 601                                                 (word_addr + i * 2 + 1),
 602                                                 1,
 603                                                 &reg_addr);
 604                         if (ret_val)
 605                                 return ret_val;
 606
 607                         /* Save off the PHY page for future writes. */
 608                         if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
 609                                 phy_page = reg_data;
 610                                 continue;
 611                         }
 612
 613                         reg_addr |= phy_page;
 614
 615                         ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
 616                         if (ret_val)
 617                                 return ret_val;
 618                 }
 619         }
 620
 621         return 0;
 622 }
 623
 624 /**
 625  *  e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
 626  *  @hw: pointer to the HW structure
 627  *
 628  *  Populates "phy" structure with various feature states.
 629  *  This function is only called by other family-specific
 630  *  routines.
 631  **/
 632 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
 633 {
 634         struct e1000_phy_info *phy = &hw->phy;
 635         s32 ret_val;
 636         u16 data;
 637         bool link;
 638
 639         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 640         if (ret_val)
 641                 return ret_val;
 642
 643         if (!link) {
 644                 hw_dbg(hw, "Phy info is only valid if link is up\n");
 645                 return -E1000_ERR_CONFIG;
 646         }
 647
 648         ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
 649         if (ret_val)
 650                 return ret_val;
 651         phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
 652
 653         if (phy->polarity_correction) {
 654                 ret_val = e1000_check_polarity_ife_ich8lan(hw);
 655                 if (ret_val)
 656                         return ret_val;
 657         } else {
 658                 /* Polarity is forced */
 659                 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
 660                                       ? e1000_rev_polarity_reversed
 661                                       : e1000_rev_polarity_normal;
 662         }
 663
 664         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
 665         if (ret_val)
 666                 return ret_val;
 667
 668         phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
 669
 670         /* The following parameters are undefined for 10/100 operation. */
 671         phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
 672         phy->local_rx = e1000_1000t_rx_status_undefined;
 673         phy->remote_rx = e1000_1000t_rx_status_undefined;
 674
 675         return 0;
 676 }
 677
 678 /**
 679  *  e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
 680  *  @hw: pointer to the HW structure
 681  *
 682  *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
 683  *  This is a function pointer entry point called by drivers
 684  *  or other shared routines.
 685  **/
 686 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
 687 {
 688         switch (hw->phy.type) {
 689         case e1000_phy_ife:
 690                 return e1000_get_phy_info_ife_ich8lan(hw);
 691                 break;
 692         case e1000_phy_igp_3:
 693         case e1000_phy_bm:
 694                 return e1000e_get_phy_info_igp(hw);
 695                 break;
 696         default:
 697                 break;
 698         }
 699
 700         return -E1000_ERR_PHY_TYPE;
 701 }
 702
 703 /**
 704  *  e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
 705  *  @hw: pointer to the HW structure
 706  *
 707  *  Polarity is determined on the polarity reversal feature being enabled.
 708  *  This function is only called by other family-specific
 709  *  routines.
 710  **/
 711 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
 712 {
 713         struct e1000_phy_info *phy = &hw->phy;
 714         s32 ret_val;
 715         u16 phy_data, offset, mask;
 716
 717         /*
 718          * Polarity is determined based on the reversal feature being enabled.
 719          */
 720         if (phy->polarity_correction) {
 721                 offset  = IFE_PHY_EXTENDED_STATUS_CONTROL;
 722                 mask    = IFE_PESC_POLARITY_REVERSED;
 723         } else {
 724                 offset  = IFE_PHY_SPECIAL_CONTROL;
 725                 mask    = IFE_PSC_FORCE_POLARITY;
 726         }
 727
 728         ret_val = e1e_rphy(hw, offset, &phy_data);
 729
 730         if (!ret_val)
 731                 phy->cable_polarity = (phy_data & mask)
 732                                       ? e1000_rev_polarity_reversed
 733                                       : e1000_rev_polarity_normal;
 734
 735         return ret_val;
 736 }
 737
 738 /**
 739  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
 740  *  @hw: pointer to the HW structure
 741  *  @active: TRUE to enable LPLU, FALSE to disable
 742  *
 743  *  Sets the LPLU D0 state according to the active flag.  When
 744  *  activating LPLU this function also disables smart speed
 745  *  and vice versa.  LPLU will not be activated unless the
 746  *  device autonegotiation advertisement meets standards of
 747  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 748  *  This is a function pointer entry point only called by
 749  *  PHY setup routines.
 750  **/
 751 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
 752 {
 753         struct e1000_phy_info *phy = &hw->phy;
 754         u32 phy_ctrl;
 755         s32 ret_val = 0;
 756         u16 data;
 757
 758         if (phy->type == e1000_phy_ife)
 759                 return ret_val;
 760
 761         phy_ctrl = er32(PHY_CTRL);
 762
 763         if (active) {
 764                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
 765                 ew32(PHY_CTRL, phy_ctrl);
 766
 767                 /*
 768                  * Call gig speed drop workaround on LPLU before accessing
 769                  * any PHY registers
 770                  */
 771                 if ((hw->mac.type == e1000_ich8lan) &&
 772                     (hw->phy.type == e1000_phy_igp_3))
 773                         e1000e_gig_downshift_workaround_ich8lan(hw);
 774
 775                 /* When LPLU is enabled, we should disable SmartSpeed */
 776                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 777                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 778                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 779                 if (ret_val)
 780                         return ret_val;
 781         } else {
 782                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
 783                 ew32(PHY_CTRL, phy_ctrl);
 784
 785                 /*
 786                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 787                  * during Dx states where the power conservation is most
 788                  * important.  During driver activity we should enable
 789                  * SmartSpeed, so performance is maintained.
 790                  */
 791                 if (phy->smart_speed == e1000_smart_speed_on) {
 792                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 793                                            &data);
 794                         if (ret_val)
 795                                 return ret_val;
 796
 797                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 798                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 799                                            data);
 800                         if (ret_val)
 801                                 return ret_val;
 802                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 803                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 804                                            &data);
 805                         if (ret_val)
 806                                 return ret_val;
 807
 808                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 809                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 810                                            data);
 811                         if (ret_val)
 812                                 return ret_val;
 813                 }
 814         }
 815
 816         return 0;
 817 }
 818
 819 /**
 820  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
 821  *  @hw: pointer to the HW structure
 822  *  @active: TRUE to enable LPLU, FALSE to disable
 823  *
 824  *  Sets the LPLU D3 state according to the active flag.  When
 825  *  activating LPLU this function also disables smart speed
 826  *  and vice versa.  LPLU will not be activated unless the
 827  *  device autonegotiation advertisement meets standards of
 828  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 829  *  This is a function pointer entry point only called by
 830  *  PHY setup routines.
 831  **/
 832 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
 833 {
 834         struct e1000_phy_info *phy = &hw->phy;
 835         u32 phy_ctrl;
 836         s32 ret_val;
 837         u16 data;
 838
 839         phy_ctrl = er32(PHY_CTRL);
 840
 841         if (!active) {
 842                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
 843                 ew32(PHY_CTRL, phy_ctrl);
 844                 /*
 845                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 846                  * during Dx states where the power conservation is most
 847                  * important.  During driver activity we should enable
 848                  * SmartSpeed, so performance is maintained.
 849                  */
 850                 if (phy->smart_speed == e1000_smart_speed_on) {
 851                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 852                                            &data);
 853                         if (ret_val)
 854                                 return ret_val;
 855
 856                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 857                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 858                                            data);
 859                         if (ret_val)
 860                                 return ret_val;
 861                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 862                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 863                                            &data);
 864                         if (ret_val)
 865                                 return ret_val;
 866
 867                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 868                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 869                                            data);
 870                         if (ret_val)
 871                                 return ret_val;
 872                 }
 873         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 874                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 875                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 876                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
 877                 ew32(PHY_CTRL, phy_ctrl);
 878
 879                 /*
 880                  * Call gig speed drop workaround on LPLU before accessing
 881                  * any PHY registers
 882                  */
 883                 if ((hw->mac.type == e1000_ich8lan) &&
 884                     (hw->phy.type == e1000_phy_igp_3))
 885                         e1000e_gig_downshift_workaround_ich8lan(hw);
 886
 887                 /* When LPLU is enabled, we should disable SmartSpeed */
 888                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 889                 if (ret_val)
 890                         return ret_val;
 891
 892                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 893                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 894         }
 895
 896         return 0;
 897 }
 898
 899 /**
 900  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
 901  *  @hw: pointer to the HW structure
 902  *  @offset: The offset (in bytes) of the word(s) to read.
 903  *  @words: Size of data to read in words
 904  *  @data: Pointer to the word(s) to read at offset.
 905  *
 906  *  Reads a word(s) from the NVM using the flash access registers.
 907  **/
 908 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
 909                                   u16 *data)
 910 {
 911         struct e1000_nvm_info *nvm = &hw->nvm;
 912         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 913         u32 act_offset;
 914         s32 ret_val;
 915         u16 i, word;
 916
 917         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
 918             (words == 0)) {
 919                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
 920                 return -E1000_ERR_NVM;
 921         }
 922
 923         ret_val = e1000_acquire_swflag_ich8lan(hw);
 924         if (ret_val)
 925                 return ret_val;
 926
 927         /* Start with the bank offset, then add the relative offset. */
 928         act_offset = (er32(EECD) & E1000_EECD_SEC1VAL)
 929                      ? nvm->flash_bank_size
 930                      : 0;
 931         act_offset += offset;
 932
 933         for (i = 0; i < words; i++) {
 934                 if ((dev_spec->shadow_ram) &&
 935                     (dev_spec->shadow_ram[offset+i].modified)) {
 936                         data[i] = dev_spec->shadow_ram[offset+i].value;
 937                 } else {
 938                         ret_val = e1000_read_flash_word_ich8lan(hw,
 939                                                                 act_offset + i,
 940                                                                 &word);
 941                         if (ret_val)
 942                                 break;
 943                         data[i] = word;
 944                 }
 945         }
 946
 947         e1000_release_swflag_ich8lan(hw);
 948
 949         return ret_val;
 950 }
 951
 952 /**
 953  *  e1000_flash_cycle_init_ich8lan - Initialize flash
 954  *  @hw: pointer to the HW structure
 955  *
 956  *  This function does initial flash setup so that a new read/write/erase cycle
 957  *  can be started.
 958  **/
 959 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
 960 {
 961         union ich8_hws_flash_status hsfsts;
 962         s32 ret_val = -E1000_ERR_NVM;
 963         s32 i = 0;
 964
 965         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
 966
 967         /* Check if the flash descriptor is valid */
 968         if (hsfsts.hsf_status.fldesvalid == 0) {
 969                 hw_dbg(hw, "Flash descriptor invalid.  "
 970                          "SW Sequencing must be used.");
 971                 return -E1000_ERR_NVM;
 972         }
 973
 974         /* Clear FCERR and DAEL in hw status by writing 1 */
 975         hsfsts.hsf_status.flcerr = 1;
 976         hsfsts.hsf_status.dael = 1;
 977
 978         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
 979
 980         /*
 981          * Either we should have a hardware SPI cycle in progress
 982          * bit to check against, in order to start a new cycle or
 983          * FDONE bit should be changed in the hardware so that it
 984          * is 1 after hardware reset, which can then be used as an
 985          * indication whether a cycle is in progress or has been
 986          * completed.
 987          */
 988
 989         if (hsfsts.hsf_status.flcinprog == 0) {
 990                 /*
 991                  * There is no cycle running at present,
 992                  * so we can start a cycle
 993                  * Begin by setting Flash Cycle Done.
 994                  */
 995                 hsfsts.hsf_status.flcdone = 1;
 996                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
 997                 ret_val = 0;
 998         } else {
 999                 /*
1000                  * otherwise poll for sometime so the current
1001                  * cycle has a chance to end before giving up.
1002                  */
1003                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1004                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1005                         if (hsfsts.hsf_status.flcinprog == 0) {
1006                                 ret_val = 0;
1007                                 break;
1008                         }
1009                         udelay(1);
1010                 }
1011                 if (ret_val == 0) {
1012                         /*
1013                          * Successful in waiting for previous cycle to timeout,
1014                          * now set the Flash Cycle Done.
1015                          */
1016                         hsfsts.hsf_status.flcdone = 1;
1017                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1018                 } else {
1019                         hw_dbg(hw, "Flash controller busy, cannot get access");
1020                 }
1021         }
1022
1023         return ret_val;
1024 }
1025
1026 /**
1027  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1028  *  @hw: pointer to the HW structure
1029  *  @timeout: maximum time to wait for completion
1030  *
1031  *  This function starts a flash cycle and waits for its completion.
1032  **/
1033 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1034 {
1035         union ich8_hws_flash_ctrl hsflctl;
1036         union ich8_hws_flash_status hsfsts;
1037         s32 ret_val = -E1000_ERR_NVM;
1038         u32 i = 0;
1039
1040         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1041         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1042         hsflctl.hsf_ctrl.flcgo = 1;
1043         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1044
1045         /* wait till FDONE bit is set to 1 */
1046         do {
1047                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1048                 if (hsfsts.hsf_status.flcdone == 1)
1049                         break;
1050                 udelay(1);
1051         } while (i++ < timeout);
1052
1053         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1054                 return 0;
1055
1056         return ret_val;
1057 }
1058
1059 /**
1060  *  e1000_read_flash_word_ich8lan - Read word from flash
1061  *  @hw: pointer to the HW structure
1062  *  @offset: offset to data location
1063  *  @data: pointer to the location for storing the data
1064  *
1065  *  Reads the flash word at offset into data.  Offset is converted
1066  *  to bytes before read.
1067  **/
1068 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1069                                          u16 *data)
1070 {
1071         /* Must convert offset into bytes. */
1072         offset <<= 1;
1073
1074         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1075 }
1076
1077 /**
1078  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
1079  *  @hw: pointer to the HW structure
1080  *  @offset: The offset (in bytes) of the byte or word to read.
1081  *  @size: Size of data to read, 1=byte 2=word
1082  *  @data: Pointer to the word to store the value read.
1083  *
1084  *  Reads a byte or word from the NVM using the flash access registers.
1085  **/
1086 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1087                                          u8 size, u16 *data)
1088 {
1089         union ich8_hws_flash_status hsfsts;
1090         union ich8_hws_flash_ctrl hsflctl;
1091         u32 flash_linear_addr;
1092         u32 flash_data = 0;
1093         s32 ret_val = -E1000_ERR_NVM;
1094         u8 count = 0;
1095
1096         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1097                 return -E1000_ERR_NVM;
1098
1099         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1100                             hw->nvm.flash_base_addr;
1101
1102         do {
1103                 udelay(1);
1104                 /* Steps */
1105                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1106                 if (ret_val != 0)
1107                         break;
1108
1109                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1110                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1111                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1112                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1113                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1114
1115                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1116
1117                 ret_val = e1000_flash_cycle_ich8lan(hw,
1118                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
1119
1120                 /*
1121                  * Check if FCERR is set to 1, if set to 1, clear it
1122                  * and try the whole sequence a few more times, else
1123                  * read in (shift in) the Flash Data0, the order is
1124                  * least significant byte first msb to lsb
1125                  */
1126                 if (ret_val == 0) {
1127                         flash_data = er32flash(ICH_FLASH_FDATA0);
1128                         if (size == 1) {
1129                                 *data = (u8)(flash_data & 0x000000FF);
1130                         } else if (size == 2) {
1131                                 *data = (u16)(flash_data & 0x0000FFFF);
1132                         }
1133                         break;
1134                 } else {
1135                         /*
1136                          * If we've gotten here, then things are probably
1137                          * completely hosed, but if the error condition is
1138                          * detected, it won't hurt to give it another try...
1139                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1140                          */
1141                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1142                         if (hsfsts.hsf_status.flcerr == 1) {
1143                                 /* Repeat for some time before giving up. */
1144                                 continue;
1145                         } else if (hsfsts.hsf_status.flcdone == 0) {
1146                                 hw_dbg(hw, "Timeout error - flash cycle "
1147                                          "did not complete.");
1148                                 break;
1149                         }
1150                 }
1151         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1152
1153         return ret_val;
1154 }
1155
1156 /**
1157  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
1158  *  @hw: pointer to the HW structure
1159  *  @offset: The offset (in bytes) of the word(s) to write.
1160  *  @words: Size of data to write in words
1161  *  @data: Pointer to the word(s) to write at offset.
1162  *
1163  *  Writes a byte or word to the NVM using the flash access registers.
1164  **/
1165 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1166                                    u16 *data)
1167 {
1168         struct e1000_nvm_info *nvm = &hw->nvm;
1169         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1170         s32 ret_val;
1171         u16 i;
1172
1173         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1174             (words == 0)) {
1175                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1176                 return -E1000_ERR_NVM;
1177         }
1178
1179         ret_val = e1000_acquire_swflag_ich8lan(hw);
1180         if (ret_val)
1181                 return ret_val;
1182
1183         for (i = 0; i < words; i++) {
1184                 dev_spec->shadow_ram[offset+i].modified = 1;
1185                 dev_spec->shadow_ram[offset+i].value = data[i];
1186         }
1187
1188         e1000_release_swflag_ich8lan(hw);
1189
1190         return 0;
1191 }
1192
1193 /**
1194  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1195  *  @hw: pointer to the HW structure
1196  *
1197  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
1198  *  which writes the checksum to the shadow ram.  The changes in the shadow
1199  *  ram are then committed to the EEPROM by processing each bank at a time
1200  *  checking for the modified bit and writing only the pending changes.
1201  *  After a successful commit, the shadow ram is cleared and is ready for
1202  *  future writes.
1203  **/
1204 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1205 {
1206         struct e1000_nvm_info *nvm = &hw->nvm;
1207         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1208         u32 i, act_offset, new_bank_offset, old_bank_offset;
1209         s32 ret_val;
1210         u16 data;
1211
1212         ret_val = e1000e_update_nvm_checksum_generic(hw);
1213         if (ret_val)
1214                 return ret_val;
1215
1216         if (nvm->type != e1000_nvm_flash_sw)
1217                 return ret_val;
1218
1219         ret_val = e1000_acquire_swflag_ich8lan(hw);
1220         if (ret_val)
1221                 return ret_val;
1222
1223         /*
1224          * We're writing to the opposite bank so if we're on bank 1,
1225          * write to bank 0 etc.  We also need to erase the segment that
1226          * is going to be written
1227          */
1228         if (!(er32(EECD) & E1000_EECD_SEC1VAL)) {
1229                 new_bank_offset = nvm->flash_bank_size;
1230                 old_bank_offset = 0;
1231                 e1000_erase_flash_bank_ich8lan(hw, 1);
1232         } else {
1233                 old_bank_offset = nvm->flash_bank_size;
1234                 new_bank_offset = 0;
1235                 e1000_erase_flash_bank_ich8lan(hw, 0);
1236         }
1237
1238         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1239                 /*
1240                  * Determine whether to write the value stored
1241                  * in the other NVM bank or a modified value stored
1242                  * in the shadow RAM
1243                  */
1244                 if (dev_spec->shadow_ram[i].modified) {
1245                         data = dev_spec->shadow_ram[i].value;
1246                 } else {
1247                         e1000_read_flash_word_ich8lan(hw,
1248                                                       i + old_bank_offset,
1249                                                       &data);
1250                 }
1251
1252                 /*
1253                  * If the word is 0x13, then make sure the signature bits
1254                  * (15:14) are 11b until the commit has completed.
1255                  * This will allow us to write 10b which indicates the
1256                  * signature is valid.  We want to do this after the write
1257                  * has completed so that we don't mark the segment valid
1258                  * while the write is still in progress
1259                  */
1260                 if (i == E1000_ICH_NVM_SIG_WORD)
1261                         data |= E1000_ICH_NVM_SIG_MASK;
1262
1263                 /* Convert offset to bytes. */
1264                 act_offset = (i + new_bank_offset) << 1;
1265
1266                 udelay(100);
1267                 /* Write the bytes to the new bank. */
1268                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1269                                                                act_offset,
1270                                                                (u8)data);
1271                 if (ret_val)
1272                         break;
1273
1274                 udelay(100);
1275                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1276                                                           act_offset + 1,
1277                                                           (u8)(data >> 8));
1278                 if (ret_val)
1279                         break;
1280         }
1281
1282         /*
1283          * Don't bother writing the segment valid bits if sector
1284          * programming failed.
1285          */
1286         if (ret_val) {
1287                 hw_dbg(hw, "Flash commit failed.\n");
1288                 e1000_release_swflag_ich8lan(hw);
1289                 return ret_val;
1290         }
1291
1292         /*
1293          * Finally validate the new segment by setting bit 15:14
1294          * to 10b in word 0x13 , this can be done without an
1295          * erase as well since these bits are 11 to start with
1296          * and we need to change bit 14 to 0b
1297          */
1298         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1299         e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1300         data &= 0xBFFF;
1301         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1302                                                        act_offset * 2 + 1,
1303                                                        (u8)(data >> 8));
1304         if (ret_val) {
1305                 e1000_release_swflag_ich8lan(hw);
1306                 return ret_val;
1307         }
1308
1309         /*
1310          * And invalidate the previously valid segment by setting
1311          * its signature word (0x13) high_byte to 0b. This can be
1312          * done without an erase because flash erase sets all bits
1313          * to 1's. We can write 1's to 0's without an erase
1314          */
1315         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1316         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1317         if (ret_val) {
1318                 e1000_release_swflag_ich8lan(hw);
1319                 return ret_val;
1320         }
1321
1322         /* Great!  Everything worked, we can now clear the cached entries. */
1323         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1324                 dev_spec->shadow_ram[i].modified = 0;
1325                 dev_spec->shadow_ram[i].value = 0xFFFF;
1326         }
1327
1328         e1000_release_swflag_ich8lan(hw);
1329
1330         /*
1331          * Reload the EEPROM, or else modifications will not appear
1332          * until after the next adapter reset.
1333          */
1334         e1000e_reload_nvm(hw);
1335         msleep(10);
1336
1337         return ret_val;
1338 }
1339
1340 /**
1341  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1342  *  @hw: pointer to the HW structure
1343  *
1344  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1345  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
1346  *  calculated, in which case we need to calculate the checksum and set bit 6.
1347  **/
1348 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1349 {
1350         s32 ret_val;
1351         u16 data;
1352
1353         /*
1354          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
1355          * needs to be fixed.  This bit is an indication that the NVM
1356          * was prepared by OEM software and did not calculate the
1357          * checksum...a likely scenario.
1358          */
1359         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1360         if (ret_val)
1361                 return ret_val;
1362
1363         if ((data & 0x40) == 0) {
1364                 data |= 0x40;
1365                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
1366                 if (ret_val)
1367                         return ret_val;
1368                 ret_val = e1000e_update_nvm_checksum(hw);
1369                 if (ret_val)
1370                         return ret_val;
1371         }
1372
1373         return e1000e_validate_nvm_checksum_generic(hw);
1374 }
1375
1376 /**
1377  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1378  *  @hw: pointer to the HW structure
1379  *  @offset: The offset (in bytes) of the byte/word to read.
1380  *  @size: Size of data to read, 1=byte 2=word
1381  *  @data: The byte(s) to write to the NVM.
1382  *
1383  *  Writes one/two bytes to the NVM using the flash access registers.
1384  **/
1385 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1386                                           u8 size, u16 data)
1387 {
1388         union ich8_hws_flash_status hsfsts;
1389         union ich8_hws_flash_ctrl hsflctl;
1390         u32 flash_linear_addr;
1391         u32 flash_data = 0;
1392         s32 ret_val;
1393         u8 count = 0;
1394
1395         if (size < 1 || size > 2 || data > size * 0xff ||
1396             offset > ICH_FLASH_LINEAR_ADDR_MASK)
1397                 return -E1000_ERR_NVM;
1398
1399         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1400                             hw->nvm.flash_base_addr;
1401
1402         do {
1403                 udelay(1);
1404                 /* Steps */
1405                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1406                 if (ret_val)
1407                         break;
1408
1409                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1410                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1411                 hsflctl.hsf_ctrl.fldbcount = size -1;
1412                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
1413                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1414
1415                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1416
1417                 if (size == 1)
1418                         flash_data = (u32)data & 0x00FF;
1419                 else
1420                         flash_data = (u32)data;
1421
1422                 ew32flash(ICH_FLASH_FDATA0, flash_data);
1423
1424                 /*
1425                  * check if FCERR is set to 1 , if set to 1, clear it
1426                  * and try the whole sequence a few more times else done
1427                  */
1428                 ret_val = e1000_flash_cycle_ich8lan(hw,
1429                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1430                 if (!ret_val)
1431                         break;
1432
1433                 /*
1434                  * If we're here, then things are most likely
1435                  * completely hosed, but if the error condition
1436                  * is detected, it won't hurt to give it another
1437                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1438                  */
1439                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1440                 if (hsfsts.hsf_status.flcerr == 1)
1441                         /* Repeat for some time before giving up. */
1442                         continue;
1443                 if (hsfsts.hsf_status.flcdone == 0) {
1444                         hw_dbg(hw, "Timeout error - flash cycle "
1445                                  "did not complete.");
1446                         break;
1447                 }
1448         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1449
1450         return ret_val;
1451 }
1452
1453 /**
1454  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1455  *  @hw: pointer to the HW structure
1456  *  @offset: The index of the byte to read.
1457  *  @data: The byte to write to the NVM.
1458  *
1459  *  Writes a single byte to the NVM using the flash access registers.
1460  **/
1461 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1462                                           u8 data)
1463 {
1464         u16 word = (u16)data;
1465
1466         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1467 }
1468
1469 /**
1470  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1471  *  @hw: pointer to the HW structure
1472  *  @offset: The offset of the byte to write.
1473  *  @byte: The byte to write to the NVM.
1474  *
1475  *  Writes a single byte to the NVM using the flash access registers.
1476  *  Goes through a retry algorithm before giving up.
1477  **/
1478 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
1479                                                 u32 offset, u8 byte)
1480 {
1481         s32 ret_val;
1482         u16 program_retries;
1483
1484         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1485         if (!ret_val)
1486                 return ret_val;
1487
1488         for (program_retries = 0; program_retries < 100; program_retries++) {
1489                 hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
1490                 udelay(100);
1491                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1492                 if (!ret_val)
1493                         break;
1494         }
1495         if (program_retries == 100)
1496                 return -E1000_ERR_NVM;
1497
1498         return 0;
1499 }
1500
1501 /**
1502  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1503  *  @hw: pointer to the HW structure
1504  *  @bank: 0 for first bank, 1 for second bank, etc.
1505  *
1506  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1507  *  bank N is 4096 * N + flash_reg_addr.
1508  **/
1509 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1510 {
1511         struct e1000_nvm_info *nvm = &hw->nvm;
1512         union ich8_hws_flash_status hsfsts;
1513         union ich8_hws_flash_ctrl hsflctl;
1514         u32 flash_linear_addr;
1515         /* bank size is in 16bit words - adjust to bytes */
1516         u32 flash_bank_size = nvm->flash_bank_size * 2;
1517         s32 ret_val;
1518         s32 count = 0;
1519         s32 iteration;
1520         s32 sector_size;
1521         s32 j;
1522
1523         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1524
1525         /*
1526          * Determine HW Sector size: Read BERASE bits of hw flash status
1527          * register
1528          * 00: The Hw sector is 256 bytes, hence we need to erase 16
1529          *     consecutive sectors.  The start index for the nth Hw sector
1530          *     can be calculated as = bank * 4096 + n * 256
1531          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1532          *     The start index for the nth Hw sector can be calculated
1533          *     as = bank * 4096
1534          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1535          *     (ich9 only, otherwise error condition)
1536          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
1537          */
1538         switch (hsfsts.hsf_status.berasesz) {
1539         case 0:
1540                 /* Hw sector size 256 */
1541                 sector_size = ICH_FLASH_SEG_SIZE_256;
1542                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
1543                 break;
1544         case 1:
1545                 sector_size = ICH_FLASH_SEG_SIZE_4K;
1546                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K;
1547                 break;
1548         case 2:
1549                 if (hw->mac.type == e1000_ich9lan) {
1550                         sector_size = ICH_FLASH_SEG_SIZE_8K;
1551                         iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K;
1552                 } else {
1553                         return -E1000_ERR_NVM;
1554                 }
1555                 break;
1556         case 3:
1557                 sector_size = ICH_FLASH_SEG_SIZE_64K;
1558                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K;
1559                 break;
1560         default:
1561                 return -E1000_ERR_NVM;
1562         }
1563
1564         /* Start with the base address, then add the sector offset. */
1565         flash_linear_addr = hw->nvm.flash_base_addr;
1566         flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
1567
1568         for (j = 0; j < iteration ; j++) {
1569                 do {
1570                         /* Steps */
1571                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
1572                         if (ret_val)
1573                                 return ret_val;
1574
1575                         /*
1576                          * Write a value 11 (block Erase) in Flash
1577                          * Cycle field in hw flash control
1578                          */
1579                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1580                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
1581                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1582
1583                         /*
1584                          * Write the last 24 bits of an index within the
1585                          * block into Flash Linear address field in Flash
1586                          * Address.
1587                          */
1588                         flash_linear_addr += (j * sector_size);
1589                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1590
1591                         ret_val = e1000_flash_cycle_ich8lan(hw,
1592                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
1593                         if (ret_val == 0)
1594                                 break;
1595
1596                         /*
1597                          * Check if FCERR is set to 1.  If 1,
1598                          * clear it and try the whole sequence
1599                          * a few more times else Done
1600                          */
1601                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1602                         if (hsfsts.hsf_status.flcerr == 1)
1603                                 /* repeat for some time before giving up */
1604                                 continue;
1605                         else if (hsfsts.hsf_status.flcdone == 0)
1606                                 return ret_val;
1607                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
1608         }
1609
1610         return 0;
1611 }
1612
1613 /**
1614  *  e1000_valid_led_default_ich8lan - Set the default LED settings
1615  *  @hw: pointer to the HW structure
1616  *  @data: Pointer to the LED settings
1617  *
1618  *  Reads the LED default settings from the NVM to data.  If the NVM LED
1619  *  settings is all 0's or F's, set the LED default to a valid LED default
1620  *  setting.
1621  **/
1622 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
1623 {
1624         s32 ret_val;
1625
1626         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1627         if (ret_val) {
1628                 hw_dbg(hw, "NVM Read Error\n");
1629                 return ret_val;
1630         }
1631
1632         if (*data == ID_LED_RESERVED_0000 ||
1633             *data == ID_LED_RESERVED_FFFF)
1634                 *data = ID_LED_DEFAULT_ICH8LAN;
1635
1636         return 0;
1637 }
1638
1639 /**
1640  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1641  *  @hw: pointer to the HW structure
1642  *
1643  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1644  *  register, so the the bus width is hard coded.
1645  **/
1646 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
1647 {
1648         struct e1000_bus_info *bus = &hw->bus;
1649         s32 ret_val;
1650
1651         ret_val = e1000e_get_bus_info_pcie(hw);
1652
1653         /*
1654          * ICH devices are "PCI Express"-ish.  They have
1655          * a configuration space, but do not contain
1656          * PCI Express Capability registers, so bus width
1657          * must be hardcoded.
1658          */
1659         if (bus->width == e1000_bus_width_unknown)
1660                 bus->width = e1000_bus_width_pcie_x1;
1661
1662         return ret_val;
1663 }
1664
1665 /**
1666  *  e1000_reset_hw_ich8lan - Reset the hardware
1667  *  @hw: pointer to the HW structure
1668  *
1669  *  Does a full reset of the hardware which includes a reset of the PHY and
1670  *  MAC.
1671  **/
1672 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
1673 {
1674         u32 ctrl, icr, kab;
1675         s32 ret_val;
1676
1677         /*
1678          * Prevent the PCI-E bus from sticking if there is no TLP connection
1679          * on the last TLP read/write transaction when MAC is reset.
1680          */
1681         ret_val = e1000e_disable_pcie_master(hw);
1682         if (ret_val) {
1683                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
1684         }
1685
1686         hw_dbg(hw, "Masking off all interrupts\n");
1687         ew32(IMC, 0xffffffff);
1688
1689         /*
1690          * Disable the Transmit and Receive units.  Then delay to allow
1691          * any pending transactions to complete before we hit the MAC
1692          * with the global reset.
1693          */
1694         ew32(RCTL, 0);
1695         ew32(TCTL, E1000_TCTL_PSP);
1696         e1e_flush();
1697
1698         msleep(10);
1699
1700         /* Workaround for ICH8 bit corruption issue in FIFO memory */
1701         if (hw->mac.type == e1000_ich8lan) {
1702                 /* Set Tx and Rx buffer allocation to 8k apiece. */
1703                 ew32(PBA, E1000_PBA_8K);
1704                 /* Set Packet Buffer Size to 16k. */
1705                 ew32(PBS, E1000_PBS_16K);
1706         }
1707
1708         ctrl = er32(CTRL);
1709
1710         if (!e1000_check_reset_block(hw)) {
1711                 /*
1712                  * PHY HW reset requires MAC CORE reset at the same
1713                  * time to make sure the interface between MAC and the
1714                  * external PHY is reset.
1715                  */
1716                 ctrl |= E1000_CTRL_PHY_RST;
1717         }
1718         ret_val = e1000_acquire_swflag_ich8lan(hw);
1719         hw_dbg(hw, "Issuing a global reset to ich8lan");
1720         ew32(CTRL, (ctrl | E1000_CTRL_RST));
1721         msleep(20);
1722
1723         ret_val = e1000e_get_auto_rd_done(hw);
1724         if (ret_val) {
1725                 /*
1726                  * When auto config read does not complete, do not
1727                  * return with an error. This can happen in situations
1728                  * where there is no eeprom and prevents getting link.
1729                  */
1730                 hw_dbg(hw, "Auto Read Done did not complete\n");
1731         }
1732
1733         ew32(IMC, 0xffffffff);
1734         icr = er32(ICR);
1735
1736         kab = er32(KABGTXD);
1737         kab |= E1000_KABGTXD_BGSQLBIAS;
1738         ew32(KABGTXD, kab);
1739
1740         return ret_val;
1741 }
1742
1743 /**
1744  *  e1000_init_hw_ich8lan - Initialize the hardware
1745  *  @hw: pointer to the HW structure
1746  *
1747  *  Prepares the hardware for transmit and receive by doing the following:
1748  *   - initialize hardware bits
1749  *   - initialize LED identification
1750  *   - setup receive address registers
1751  *   - setup flow control
1752  *   - setup transmit descriptors
1753  *   - clear statistics
1754  **/
1755 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
1756 {
1757         struct e1000_mac_info *mac = &hw->mac;
1758         u32 ctrl_ext, txdctl, snoop;
1759         s32 ret_val;
1760         u16 i;
1761
1762         e1000_initialize_hw_bits_ich8lan(hw);
1763
1764         /* Initialize identification LED */
1765         ret_val = e1000e_id_led_init(hw);
1766         if (ret_val) {
1767                 hw_dbg(hw, "Error initializing identification LED\n");
1768                 return ret_val;
1769         }
1770
1771         /* Setup the receive address. */
1772         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
1773
1774         /* Zero out the Multicast HASH table */
1775         hw_dbg(hw, "Zeroing the MTA\n");
1776         for (i = 0; i < mac->mta_reg_count; i++)
1777                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1778
1779         /* Setup link and flow control */
1780         ret_val = e1000_setup_link_ich8lan(hw);
1781
1782         /* Set the transmit descriptor write-back policy for both queues */
1783         txdctl = er32(TXDCTL(0));
1784         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
1785                  E1000_TXDCTL_FULL_TX_DESC_WB;
1786         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
1787                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
1788         ew32(TXDCTL(0), txdctl);
1789         txdctl = er32(TXDCTL(1));
1790         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
1791                  E1000_TXDCTL_FULL_TX_DESC_WB;
1792         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
1793                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
1794         ew32(TXDCTL(1), txdctl);
1795
1796         /*
1797          * ICH8 has opposite polarity of no_snoop bits.
1798          * By default, we should use snoop behavior.
1799          */
1800         if (mac->type == e1000_ich8lan)
1801                 snoop = PCIE_ICH8_SNOOP_ALL;
1802         else
1803                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
1804         e1000e_set_pcie_no_snoop(hw, snoop);
1805
1806         ctrl_ext = er32(CTRL_EXT);
1807         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1808         ew32(CTRL_EXT, ctrl_ext);
1809
1810         /*
1811          * Clear all of the statistics registers (clear on read).  It is
1812          * important that we do this after we have tried to establish link
1813          * because the symbol error count will increment wildly if there
1814          * is no link.
1815          */
1816         e1000_clear_hw_cntrs_ich8lan(hw);
1817
1818         return 0;
1819 }
1820 /**
1821  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
1822  *  @hw: pointer to the HW structure
1823  *
1824  *  Sets/Clears required hardware bits necessary for correctly setting up the
1825  *  hardware for transmit and receive.
1826  **/
1827 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
1828 {
1829         u32 reg;
1830
1831         /* Extended Device Control */
1832         reg = er32(CTRL_EXT);
1833         reg |= (1 << 22);
1834         ew32(CTRL_EXT, reg);
1835
1836         /* Transmit Descriptor Control 0 */
1837         reg = er32(TXDCTL(0));
1838         reg |= (1 << 22);
1839         ew32(TXDCTL(0), reg);
1840
1841         /* Transmit Descriptor Control 1 */
1842         reg = er32(TXDCTL(1));
1843         reg |= (1 << 22);
1844         ew32(TXDCTL(1), reg);
1845
1846         /* Transmit Arbitration Control 0 */
1847         reg = er32(TARC(0));
1848         if (hw->mac.type == e1000_ich8lan)
1849                 reg |= (1 << 28) | (1 << 29);
1850         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
1851         ew32(TARC(0), reg);
1852
1853         /* Transmit Arbitration Control 1 */
1854         reg = er32(TARC(1));
1855         if (er32(TCTL) & E1000_TCTL_MULR)
1856                 reg &= ~(1 << 28);
1857         else
1858                 reg |= (1 << 28);
1859         reg |= (1 << 24) | (1 << 26) | (1 << 30);
1860         ew32(TARC(1), reg);
1861
1862         /* Device Status */
1863         if (hw->mac.type == e1000_ich8lan) {
1864                 reg = er32(STATUS);
1865                 reg &= ~(1 << 31);
1866                 ew32(STATUS, reg);
1867         }
1868 }
1869
1870 /**
1871  *  e1000_setup_link_ich8lan - Setup flow control and link settings
1872  *  @hw: pointer to the HW structure
1873  *
1874  *  Determines which flow control settings to use, then configures flow
1875  *  control.  Calls the appropriate media-specific link configuration
1876  *  function.  Assuming the adapter has a valid link partner, a valid link
1877  *  should be established.  Assumes the hardware has previously been reset
1878  *  and the transmitter and receiver are not enabled.
1879  **/
1880 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
1881 {
1882         s32 ret_val;
1883
1884         if (e1000_check_reset_block(hw))
1885                 return 0;
1886
1887         /*
1888          * ICH parts do not have a word in the NVM to determine
1889          * the default flow control setting, so we explicitly
1890          * set it to full.
1891          */
1892         if (hw->fc.type == e1000_fc_default)
1893                 hw->fc.type = e1000_fc_full;
1894
1895         hw->fc.original_type = hw->fc.type;
1896
1897         hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", hw->fc.type);
1898
1899         /* Continue to configure the copper link. */
1900         ret_val = e1000_setup_copper_link_ich8lan(hw);
1901         if (ret_val)
1902                 return ret_val;
1903
1904         ew32(FCTTV, hw->fc.pause_time);
1905
1906         return e1000e_set_fc_watermarks(hw);
1907 }
1908
1909 /**
1910  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
1911  *  @hw: pointer to the HW structure
1912  *
1913  *  Configures the kumeran interface to the PHY to wait the appropriate time
1914  *  when polling the PHY, then call the generic setup_copper_link to finish
1915  *  configuring the copper link.
1916  **/
1917 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
1918 {
1919         u32 ctrl;
1920         s32 ret_val;
1921         u16 reg_data;
1922
1923         ctrl = er32(CTRL);
1924         ctrl |= E1000_CTRL_SLU;
1925         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1926         ew32(CTRL, ctrl);
1927
1928         /*
1929          * Set the mac to wait the maximum time between each iteration
1930          * and increase the max iterations when polling the phy;
1931          * this fixes erroneous timeouts at 10Mbps.
1932          */
1933         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1934         if (ret_val)
1935                 return ret_val;
1936         ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1937         if (ret_val)
1938                 return ret_val;
1939         reg_data |= 0x3F;
1940         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1941         if (ret_val)
1942                 return ret_val;
1943
1944         if (hw->phy.type == e1000_phy_igp_3) {
1945                 ret_val = e1000e_copper_link_setup_igp(hw);
1946                 if (ret_val)
1947                         return ret_val;
1948         } else if (hw->phy.type == e1000_phy_bm) {
1949                 ret_val = e1000e_copper_link_setup_m88(hw);
1950                 if (ret_val)
1951                         return ret_val;
1952         }
1953
1954         if (hw->phy.type == e1000_phy_ife) {
1955                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
1956                 if (ret_val)
1957                         return ret_val;
1958
1959                 reg_data &= ~IFE_PMC_AUTO_MDIX;
1960
1961                 switch (hw->phy.mdix) {
1962                 case 1:
1963                         reg_data &= ~IFE_PMC_FORCE_MDIX;
1964                         break;
1965                 case 2:
1966                         reg_data |= IFE_PMC_FORCE_MDIX;
1967                         break;
1968                 case 0:
1969                 default:
1970                         reg_data |= IFE_PMC_AUTO_MDIX;
1971                         break;
1972                 }
1973                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
1974                 if (ret_val)
1975                         return ret_val;
1976         }
1977         return e1000e_setup_copper_link(hw);
1978 }
1979
1980 /**
1981  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
1982  *  @hw: pointer to the HW structure
1983  *  @speed: pointer to store current link speed
1984  *  @duplex: pointer to store the current link duplex
1985  *
1986  *  Calls the generic get_speed_and_duplex to retrieve the current link
1987  *  information and then calls the Kumeran lock loss workaround for links at
1988  *  gigabit speeds.
1989  **/
1990 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
1991                                           u16 *duplex)
1992 {
1993         s32 ret_val;
1994
1995         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
1996         if (ret_val)
1997                 return ret_val;
1998
1999         if ((hw->mac.type == e1000_ich8lan) &&
2000             (hw->phy.type == e1000_phy_igp_3) &&
2001             (*speed == SPEED_1000)) {
2002                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2003         }
2004
2005         return ret_val;
2006 }
2007
2008 /**
2009  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2010  *  @hw: pointer to the HW structure
2011  *
2012  *  Work-around for 82566 Kumeran PCS lock loss:
2013  *  On link status change (i.e. PCI reset, speed change) and link is up and
2014  *  speed is gigabit-
2015  *    0) if workaround is optionally disabled do nothing
2016  *    1) wait 1ms for Kumeran link to come up
2017  *    2) check Kumeran Diagnostic register PCS lock loss bit
2018  *    3) if not set the link is locked (all is good), otherwise...
2019  *    4) reset the PHY
2020  *    5) repeat up to 10 times
2021  *  Note: this is only called for IGP3 copper when speed is 1gb.
2022  **/
2023 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2024 {
2025         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2026         u32 phy_ctrl;
2027         s32 ret_val;
2028         u16 i, data;
2029         bool link;
2030
2031         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2032                 return 0;
2033
2034         /*
2035          * Make sure link is up before proceeding.  If not just return.
2036          * Attempting this while link is negotiating fouled up link
2037          * stability
2038          */
2039         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2040         if (!link)
2041                 return 0;
2042
2043         for (i = 0; i < 10; i++) {
2044                 /* read once to clear */
2045                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2046                 if (ret_val)
2047                         return ret_val;
2048                 /* and again to get new status */
2049                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2050                 if (ret_val)
2051                         return ret_val;
2052
2053                 /* check for PCS lock */
2054                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2055                         return 0;
2056
2057                 /* Issue PHY reset */
2058                 e1000_phy_hw_reset(hw);
2059                 mdelay(5);
2060         }
2061         /* Disable GigE link negotiation */
2062         phy_ctrl = er32(PHY_CTRL);
2063         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2064                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2065         ew32(PHY_CTRL, phy_ctrl);
2066
2067         /*
2068          * Call gig speed drop workaround on Gig disable before accessing
2069          * any PHY registers
2070          */
2071         e1000e_gig_downshift_workaround_ich8lan(hw);
2072
2073         /* unable to acquire PCS lock */
2074         return -E1000_ERR_PHY;
2075 }
2076
2077 /**
2078  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2079  *  @hw: pointer to the HW structure
2080  *  @state: boolean value used to set the current Kumeran workaround state
2081  *
2082  *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
2083  *  /disabled - FALSE).
2084  **/
2085 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2086                                                  bool state)
2087 {
2088         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2089
2090         if (hw->mac.type != e1000_ich8lan) {
2091                 hw_dbg(hw, "Workaround applies to ICH8 only.\n");
2092                 return;
2093         }
2094
2095         dev_spec->kmrn_lock_loss_workaround_enabled = state;
2096 }
2097
2098 /**
2099  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2100  *  @hw: pointer to the HW structure
2101  *
2102  *  Workaround for 82566 power-down on D3 entry:
2103  *    1) disable gigabit link
2104  *    2) write VR power-down enable
2105  *    3) read it back
2106  *  Continue if successful, else issue LCD reset and repeat
2107  **/
2108 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2109 {
2110         u32 reg;
2111         u16 data;
2112         u8  retry = 0;
2113
2114         if (hw->phy.type != e1000_phy_igp_3)
2115                 return;
2116
2117         /* Try the workaround twice (if needed) */
2118         do {
2119                 /* Disable link */
2120                 reg = er32(PHY_CTRL);
2121                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2122                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2123                 ew32(PHY_CTRL, reg);
2124
2125                 /*
2126                  * Call gig speed drop workaround on Gig disable before
2127                  * accessing any PHY registers
2128                  */
2129                 if (hw->mac.type == e1000_ich8lan)
2130                         e1000e_gig_downshift_workaround_ich8lan(hw);
2131
2132                 /* Write VR power-down enable */
2133                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2134                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2135                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2136
2137                 /* Read it back and test */
2138                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2139                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2140                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2141                         break;
2142
2143                 /* Issue PHY reset and repeat at most one more time */
2144                 reg = er32(CTRL);
2145                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
2146                 retry++;
2147         } while (retry);
2148 }
2149
2150 /**
2151  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2152  *  @hw: pointer to the HW structure
2153  *
2154  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2155  *  LPLU, Gig disable, MDIC PHY reset):
2156  *    1) Set Kumeran Near-end loopback
2157  *    2) Clear Kumeran Near-end loopback
2158  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
2159  **/
2160 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2161 {
2162         s32 ret_val;
2163         u16 reg_data;
2164
2165         if ((hw->mac.type != e1000_ich8lan) ||
2166             (hw->phy.type != e1000_phy_igp_3))
2167                 return;
2168
2169         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2170                                       &reg_data);
2171         if (ret_val)
2172                 return;
2173         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
2174         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2175                                        reg_data);
2176         if (ret_val)
2177                 return;
2178         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
2179         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2180                                        reg_data);
2181 }
2182
2183 /**
2184  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
2185  *  @hw: pointer to the HW structure
2186  *
2187  *  During S0 to Sx transition, it is possible the link remains at gig
2188  *  instead of negotiating to a lower speed.  Before going to Sx, set
2189  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2190  *  to a lower speed.
2191  *
2192  *  Should only be called for ICH9 devices.
2193  **/
2194 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2195 {
2196         u32 phy_ctrl;
2197
2198         if (hw->mac.type == e1000_ich9lan) {
2199                 phy_ctrl = er32(PHY_CTRL);
2200                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2201                             E1000_PHY_CTRL_GBE_DISABLE;
2202                 ew32(PHY_CTRL, phy_ctrl);
2203         }
2204
2205         return;
2206 }
2207
2208 /**
2209  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
2210  *  @hw: pointer to the HW structure
2211  *
2212  *  Return the LED back to the default configuration.
2213  **/
2214 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2215 {
2216         if (hw->phy.type == e1000_phy_ife)
2217                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
2218
2219         ew32(LEDCTL, hw->mac.ledctl_default);
2220         return 0;
2221 }
2222
2223 /**
2224  *  e1000_led_on_ich8lan - Turn LEDs on
2225  *  @hw: pointer to the HW structure
2226  *
2227  *  Turn on the LEDs.
2228  **/
2229 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2230 {
2231         if (hw->phy.type == e1000_phy_ife)
2232                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2233                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2234
2235         ew32(LEDCTL, hw->mac.ledctl_mode2);
2236         return 0;
2237 }
2238
2239 /**
2240  *  e1000_led_off_ich8lan - Turn LEDs off
2241  *  @hw: pointer to the HW structure
2242  *
2243  *  Turn off the LEDs.
2244  **/
2245 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2246 {
2247         if (hw->phy.type == e1000_phy_ife)
2248                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2249                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2250
2251         ew32(LEDCTL, hw->mac.ledctl_mode1);
2252         return 0;
2253 }
2254
2255 /**
2256  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2257  *  @hw: pointer to the HW structure
2258  *
2259  *  Clears hardware counters specific to the silicon family and calls
2260  *  clear_hw_cntrs_generic to clear all general purpose counters.
2261  **/
2262 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2263 {
2264         u32 temp;
2265
2266         e1000e_clear_hw_cntrs_base(hw);
2267
2268         temp = er32(ALGNERRC);
2269         temp = er32(RXERRC);
2270         temp = er32(TNCRS);
2271         temp = er32(CEXTERR);
2272         temp = er32(TSCTC);
2273         temp = er32(TSCTFC);
2274
2275         temp = er32(MGTPRC);
2276         temp = er32(MGTPDC);
2277         temp = er32(MGTPTC);
2278
2279         temp = er32(IAC);
2280         temp = er32(ICRXOC);
2281
2282 }
2283
2284 static struct e1000_mac_operations ich8_mac_ops = {
2285         .mng_mode_enab          = E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT,
2286         .check_for_link         = e1000e_check_for_copper_link,
2287         .cleanup_led            = e1000_cleanup_led_ich8lan,
2288         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
2289         .get_bus_info           = e1000_get_bus_info_ich8lan,
2290         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
2291         .led_on                 = e1000_led_on_ich8lan,
2292         .led_off                = e1000_led_off_ich8lan,
2293         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
2294         .reset_hw               = e1000_reset_hw_ich8lan,
2295         .init_hw                = e1000_init_hw_ich8lan,
2296         .setup_link             = e1000_setup_link_ich8lan,
2297         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
2298 };
2299
2300 static struct e1000_phy_operations ich8_phy_ops = {
2301         .acquire_phy            = e1000_acquire_swflag_ich8lan,
2302         .check_reset_block      = e1000_check_reset_block_ich8lan,
2303         .commit_phy             = NULL,
2304         .force_speed_duplex     = e1000_phy_force_speed_duplex_ich8lan,
2305         .get_cfg_done           = e1000e_get_cfg_done,
2306         .get_cable_length       = e1000e_get_cable_length_igp_2,
2307         .get_phy_info           = e1000_get_phy_info_ich8lan,
2308         .read_phy_reg           = e1000e_read_phy_reg_igp,
2309         .release_phy            = e1000_release_swflag_ich8lan,
2310         .reset_phy              = e1000_phy_hw_reset_ich8lan,
2311         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
2312         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
2313         .write_phy_reg          = e1000e_write_phy_reg_igp,
2314 };
2315
2316 static struct e1000_nvm_operations ich8_nvm_ops = {
2317         .acquire_nvm            = e1000_acquire_swflag_ich8lan,
2318         .read_nvm               = e1000_read_nvm_ich8lan,
2319         .release_nvm            = e1000_release_swflag_ich8lan,
2320         .update_nvm             = e1000_update_nvm_checksum_ich8lan,
2321         .valid_led_default      = e1000_valid_led_default_ich8lan,
2322         .validate_nvm           = e1000_validate_nvm_checksum_ich8lan,
2323         .write_nvm              = e1000_write_nvm_ich8lan,
2324 };
2325
2326 struct e1000_info e1000_ich8_info = {
2327         .mac                    = e1000_ich8lan,
2328         .flags                  = FLAG_HAS_WOL
2329                                   | FLAG_IS_ICH
2330                                   | FLAG_RX_CSUM_ENABLED
2331                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2332                                   | FLAG_HAS_AMT
2333                                   | FLAG_HAS_FLASH
2334                                   | FLAG_APME_IN_WUC,
2335         .pba                    = 8,
2336         .get_variants           = e1000_get_variants_ich8lan,
2337         .mac_ops                = &ich8_mac_ops,
2338         .phy_ops                = &ich8_phy_ops,
2339         .nvm_ops                = &ich8_nvm_ops,
2340 };
2341
2342 struct e1000_info e1000_ich9_info = {
2343         .mac                    = e1000_ich9lan,
2344         .flags                  = FLAG_HAS_JUMBO_FRAMES
2345                                   | FLAG_IS_ICH
2346                                   | FLAG_HAS_WOL
2347                                   | FLAG_RX_CSUM_ENABLED
2348                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2349                                   | FLAG_HAS_AMT
2350                                   | FLAG_HAS_ERT
2351                                   | FLAG_HAS_FLASH
2352                                   | FLAG_APME_IN_WUC,
2353         .pba                    = 10,
2354         .get_variants           = e1000_get_variants_ich8lan,
2355         .mac_ops                = &ich8_mac_ops,
2356         .phy_ops                = &ich8_phy_ops,
2357         .nvm_ops                = &ich8_nvm_ops,
2358 };
2359