1 /* -*- c-basic-offset: 8 -*-
3 * fw-ohci.c - Driver for OHCI 1394 boards
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/pci.h>
26 #include <linux/delay.h>
27 #include <linux/poll.h>
28 #include <linux/dma-mapping.h>
30 #include <asm/uaccess.h>
31 #include <asm/semaphore.h>
33 #include "fw-transaction.h"
36 #define descriptor_output_more 0
37 #define descriptor_output_last (1 << 12)
38 #define descriptor_input_more (2 << 12)
39 #define descriptor_input_last (3 << 12)
40 #define descriptor_status (1 << 11)
41 #define descriptor_key_immediate (2 << 8)
42 #define descriptor_ping (1 << 7)
43 #define descriptor_yy (1 << 6)
44 #define descriptor_no_irq (0 << 4)
45 #define descriptor_irq_error (1 << 4)
46 #define descriptor_irq_always (3 << 4)
47 #define descriptor_branch_always (3 << 2)
48 #define descriptor_wait (3 << 0)
54 __le32 branch_address;
56 __le16 transfer_status;
57 } __attribute__((aligned(16)));
59 struct db_descriptor {
62 __le16 second_req_count;
63 __le16 first_req_count;
64 __le32 branch_address;
65 __le16 second_res_count;
66 __le16 first_res_count;
71 } __attribute__((aligned(16)));
73 #define control_set(regs) (regs)
74 #define control_clear(regs) ((regs) + 4)
75 #define command_ptr(regs) ((regs) + 12)
76 #define context_match(regs) ((regs) + 16)
79 struct descriptor descriptor;
80 struct ar_buffer *next;
86 struct ar_buffer *current_buffer;
87 struct ar_buffer *last_buffer;
90 struct tasklet_struct tasklet;
95 typedef int (*descriptor_callback_t)(struct context *ctx,
97 struct descriptor *last);
102 struct descriptor *buffer;
103 dma_addr_t buffer_bus;
105 struct descriptor *head_descriptor;
106 struct descriptor *tail_descriptor;
107 struct descriptor *tail_descriptor_last;
108 struct descriptor *prev_descriptor;
110 descriptor_callback_t callback;
112 struct tasklet_struct tasklet;
118 struct fw_ohci *ohci;
119 dma_addr_t descriptor_bus;
120 dma_addr_t buffer_bus;
121 struct fw_packet *current_packet;
123 struct list_head list;
126 struct descriptor more;
128 struct descriptor last;
133 struct tasklet_struct tasklet;
136 #define it_header_sy(v) ((v) << 0)
137 #define it_header_tcode(v) ((v) << 4)
138 #define it_header_channel(v) ((v) << 8)
139 #define it_header_tag(v) ((v) << 14)
140 #define it_header_speed(v) ((v) << 16)
141 #define it_header_data_length(v) ((v) << 16)
144 struct fw_iso_context base;
145 struct context context;
147 size_t header_length;
150 #define CONFIG_ROM_SIZE 1024
156 __iomem char *registers;
157 dma_addr_t self_id_bus;
159 struct tasklet_struct bus_reset_tasklet;
162 int request_generation;
164 /* Spinlock for accessing fw_ohci data. Never call out of
165 * this driver with this lock held. */
167 u32 self_id_buffer[512];
169 /* Config rom buffers */
171 dma_addr_t config_rom_bus;
172 __be32 *next_config_rom;
173 dma_addr_t next_config_rom_bus;
176 struct ar_context ar_request_ctx;
177 struct ar_context ar_response_ctx;
178 struct at_context at_request_ctx;
179 struct at_context at_response_ctx;
182 struct iso_context *it_context_list;
184 struct iso_context *ir_context_list;
187 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
189 return container_of(card, struct fw_ohci, card);
192 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
193 #define IR_CONTEXT_BUFFER_FILL 0x80000000
194 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
195 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
196 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
197 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
199 #define CONTEXT_RUN 0x8000
200 #define CONTEXT_WAKE 0x1000
201 #define CONTEXT_DEAD 0x0800
202 #define CONTEXT_ACTIVE 0x0400
204 #define OHCI1394_MAX_AT_REQ_RETRIES 0x2
205 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
206 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
208 #define FW_OHCI_MAJOR 240
209 #define OHCI1394_REGISTER_SIZE 0x800
210 #define OHCI_LOOP_COUNT 500
211 #define OHCI1394_PCI_HCI_Control 0x40
212 #define SELF_ID_BUF_SIZE 0x800
213 #define OHCI_TCODE_PHY_PACKET 0x0e
214 #define OHCI_VERSION_1_1 0x010010
216 static char ohci_driver_name[] = KBUILD_MODNAME;
218 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
220 writel(data, ohci->registers + offset);
223 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
225 return readl(ohci->registers + offset);
228 static inline void flush_writes(const struct fw_ohci *ohci)
230 /* Do a dummy read to flush writes. */
231 reg_read(ohci, OHCI1394_Version);
235 ohci_update_phy_reg(struct fw_card *card, int addr,
236 int clear_bits, int set_bits)
238 struct fw_ohci *ohci = fw_ohci(card);
241 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
243 val = reg_read(ohci, OHCI1394_PhyControl);
244 if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
245 fw_error("failed to set phy reg bits.\n");
249 old = OHCI1394_PhyControl_ReadData(val);
250 old = (old & ~clear_bits) | set_bits;
251 reg_write(ohci, OHCI1394_PhyControl,
252 OHCI1394_PhyControl_Write(addr, old));
257 static int ar_context_add_page(struct ar_context *ctx)
259 struct device *dev = ctx->ohci->card.device;
260 struct ar_buffer *ab;
264 ab = (struct ar_buffer *) __get_free_page(GFP_ATOMIC);
268 ab_bus = dma_map_single(dev, ab, PAGE_SIZE, DMA_BIDIRECTIONAL);
269 if (dma_mapping_error(ab_bus)) {
270 free_page((unsigned long) ab);
274 memset(&ab->descriptor, 0, sizeof ab->descriptor);
275 ab->descriptor.control = cpu_to_le16(descriptor_input_more |
277 descriptor_branch_always);
278 offset = offsetof(struct ar_buffer, data);
279 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
280 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
281 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
282 ab->descriptor.branch_address = 0;
284 dma_sync_single_for_device(dev, ab_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
286 ctx->last_buffer->descriptor.branch_address = ab_bus | 1;
287 ctx->last_buffer->next = ab;
288 ctx->last_buffer = ab;
290 reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_WAKE);
291 flush_writes(ctx->ohci);
296 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
298 struct fw_ohci *ohci = ctx->ohci;
300 u32 status, length, tcode;
302 p.header[0] = le32_to_cpu(buffer[0]);
303 p.header[1] = le32_to_cpu(buffer[1]);
304 p.header[2] = le32_to_cpu(buffer[2]);
306 tcode = (p.header[0] >> 4) & 0x0f;
308 case TCODE_WRITE_QUADLET_REQUEST:
309 case TCODE_READ_QUADLET_RESPONSE:
310 p.header[3] = (__force __u32) buffer[3];
311 p.header_length = 16;
312 p.payload_length = 0;
315 case TCODE_READ_BLOCK_REQUEST :
316 p.header[3] = le32_to_cpu(buffer[3]);
317 p.header_length = 16;
318 p.payload_length = 0;
321 case TCODE_WRITE_BLOCK_REQUEST:
322 case TCODE_READ_BLOCK_RESPONSE:
323 case TCODE_LOCK_REQUEST:
324 case TCODE_LOCK_RESPONSE:
325 p.header[3] = le32_to_cpu(buffer[3]);
326 p.header_length = 16;
327 p.payload_length = p.header[3] >> 16;
330 case TCODE_WRITE_RESPONSE:
331 case TCODE_READ_QUADLET_REQUEST:
332 case OHCI_TCODE_PHY_PACKET:
333 p.header_length = 12;
334 p.payload_length = 0;
338 p.payload = (void *) buffer + p.header_length;
340 /* FIXME: What to do about evt_* errors? */
341 length = (p.header_length + p.payload_length + 3) / 4;
342 status = le32_to_cpu(buffer[length]);
344 p.ack = ((status >> 16) & 0x1f) - 16;
345 p.speed = (status >> 21) & 0x7;
346 p.timestamp = status & 0xffff;
347 p.generation = ohci->request_generation;
349 /* The OHCI bus reset handler synthesizes a phy packet with
350 * the new generation number when a bus reset happens (see
351 * section 8.4.2.3). This helps us determine when a request
352 * was received and make sure we send the response in the same
353 * generation. We only need this for requests; for responses
354 * we use the unique tlabel for finding the matching
357 if (p.ack + 16 == 0x09)
358 ohci->request_generation = (buffer[2] >> 16) & 0xff;
359 else if (ctx == &ohci->ar_request_ctx)
360 fw_core_handle_request(&ohci->card, &p);
362 fw_core_handle_response(&ohci->card, &p);
364 return buffer + length + 1;
367 static void ar_context_tasklet(unsigned long data)
369 struct ar_context *ctx = (struct ar_context *)data;
370 struct fw_ohci *ohci = ctx->ohci;
371 struct ar_buffer *ab;
372 struct descriptor *d;
375 ab = ctx->current_buffer;
378 if (d->res_count == 0) {
379 size_t size, rest, offset;
381 /* This descriptor is finished and we may have a
382 * packet split across this and the next buffer. We
383 * reuse the page for reassembling the split packet. */
385 offset = offsetof(struct ar_buffer, data);
386 dma_unmap_single(ohci->card.device,
387 ab->descriptor.data_address - offset,
388 PAGE_SIZE, DMA_BIDIRECTIONAL);
393 size = buffer + PAGE_SIZE - ctx->pointer;
394 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
395 memmove(buffer, ctx->pointer, size);
396 memcpy(buffer + size, ab->data, rest);
397 ctx->current_buffer = ab;
398 ctx->pointer = (void *) ab->data + rest;
399 end = buffer + size + rest;
402 buffer = handle_ar_packet(ctx, buffer);
404 free_page((unsigned long)buffer);
405 ar_context_add_page(ctx);
407 buffer = ctx->pointer;
409 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
412 buffer = handle_ar_packet(ctx, buffer);
417 ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
423 ctx->last_buffer = &ab;
424 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
426 ar_context_add_page(ctx);
427 ar_context_add_page(ctx);
428 ctx->current_buffer = ab.next;
429 ctx->pointer = ctx->current_buffer->data;
431 reg_write(ctx->ohci, command_ptr(ctx->regs), ab.descriptor.branch_address);
432 reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_RUN);
433 flush_writes(ctx->ohci);
438 static void context_tasklet(unsigned long data)
440 struct context *ctx = (struct context *) data;
441 struct fw_ohci *ohci = ctx->ohci;
442 struct descriptor *d, *last;
446 dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus,
447 ctx->buffer_size, DMA_TO_DEVICE);
449 d = ctx->tail_descriptor;
450 last = ctx->tail_descriptor_last;
452 while (last->branch_address != 0) {
453 address = le32_to_cpu(last->branch_address);
455 d = ctx->buffer + (address - ctx->buffer_bus) / sizeof *d;
456 last = (z == 2) ? d : d + z - 1;
458 if (!ctx->callback(ctx, d, last))
461 ctx->tail_descriptor = d;
462 ctx->tail_descriptor_last = last;
467 context_init(struct context *ctx, struct fw_ohci *ohci,
468 size_t buffer_size, u32 regs,
469 descriptor_callback_t callback)
473 ctx->buffer_size = buffer_size;
474 ctx->buffer = kmalloc(buffer_size, GFP_KERNEL);
475 if (ctx->buffer == NULL)
478 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
479 ctx->callback = callback;
482 dma_map_single(ohci->card.device, ctx->buffer,
483 buffer_size, DMA_TO_DEVICE);
484 if (dma_mapping_error(ctx->buffer_bus)) {
489 ctx->head_descriptor = ctx->buffer;
490 ctx->prev_descriptor = ctx->buffer;
491 ctx->tail_descriptor = ctx->buffer;
492 ctx->tail_descriptor_last = ctx->buffer;
494 /* We put a dummy descriptor in the buffer that has a NULL
495 * branch address and looks like it's been sent. That way we
496 * have a descriptor to append DMA programs to. Also, the
497 * ring buffer invariant is that it always has at least one
498 * element so that head == tail means buffer full. */
500 memset(ctx->head_descriptor, 0, sizeof *ctx->head_descriptor);
501 ctx->head_descriptor->control = cpu_to_le16(descriptor_output_last);
502 ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011);
503 ctx->head_descriptor++;
509 context_release(struct context *ctx)
511 struct fw_card *card = &ctx->ohci->card;
513 dma_unmap_single(card->device, ctx->buffer_bus,
514 ctx->buffer_size, DMA_TO_DEVICE);
518 static struct descriptor *
519 context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
521 struct descriptor *d, *tail, *end;
523 d = ctx->head_descriptor;
524 tail = ctx->tail_descriptor;
525 end = ctx->buffer + ctx->buffer_size / sizeof(struct descriptor);
529 } else if (d > tail && d + z <= end) {
531 } else if (d > tail && ctx->buffer + z <= tail) {
539 memset(d, 0, z * sizeof *d);
540 *d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d;
545 static void context_run(struct context *ctx, u32 extra)
547 struct fw_ohci *ohci = ctx->ohci;
549 reg_write(ohci, command_ptr(ctx->regs),
550 le32_to_cpu(ctx->tail_descriptor_last->branch_address));
551 reg_write(ohci, control_clear(ctx->regs), ~0);
552 reg_write(ohci, control_set(ctx->regs), CONTEXT_RUN | extra);
556 static void context_append(struct context *ctx,
557 struct descriptor *d, int z, int extra)
561 d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d;
563 ctx->head_descriptor = d + z + extra;
564 ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z);
565 ctx->prev_descriptor = z == 2 ? d : d + z - 1;
567 dma_sync_single_for_device(ctx->ohci->card.device, ctx->buffer_bus,
568 ctx->buffer_size, DMA_TO_DEVICE);
570 reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_WAKE);
571 flush_writes(ctx->ohci);
574 static void context_stop(struct context *ctx)
579 reg_write(ctx->ohci, control_clear(ctx->regs), CONTEXT_RUN);
580 flush_writes(ctx->ohci);
582 for (i = 0; i < 10; i++) {
583 reg = reg_read(ctx->ohci, control_set(ctx->regs));
584 if ((reg & CONTEXT_ACTIVE) == 0)
587 fw_notify("context_stop: still active (0x%08x)\n", reg);
593 do_packet_callbacks(struct fw_ohci *ohci, struct list_head *list)
595 struct fw_packet *p, *next;
597 list_for_each_entry_safe(p, next, list, link)
598 p->callback(p, &ohci->card, p->ack);
602 complete_transmission(struct fw_packet *packet,
603 int ack, struct list_head *list)
605 list_move_tail(&packet->link, list);
609 /* This function prepares the first packet in the context queue for
610 * transmission. Must always be called with the ochi->lock held to
611 * ensure proper generation handling and locking around packet queue
614 at_context_setup_packet(struct at_context *ctx, struct list_head *list)
616 struct fw_packet *packet;
617 struct fw_ohci *ohci = ctx->ohci;
620 packet = fw_packet(ctx->list.next);
622 memset(&ctx->d, 0, sizeof ctx->d);
623 if (packet->payload_length > 0) {
624 packet->payload_bus = dma_map_single(ohci->card.device,
626 packet->payload_length,
628 if (dma_mapping_error(packet->payload_bus)) {
629 complete_transmission(packet, RCODE_SEND_ERROR, list);
633 ctx->d.more.control =
634 cpu_to_le16(descriptor_output_more |
635 descriptor_key_immediate);
636 ctx->d.more.req_count = cpu_to_le16(packet->header_length);
637 ctx->d.more.res_count = cpu_to_le16(packet->timestamp);
638 ctx->d.last.control =
639 cpu_to_le16(descriptor_output_last |
640 descriptor_irq_always |
641 descriptor_branch_always);
642 ctx->d.last.req_count = cpu_to_le16(packet->payload_length);
643 ctx->d.last.data_address = cpu_to_le32(packet->payload_bus);
646 ctx->d.more.control =
647 cpu_to_le16(descriptor_output_last |
648 descriptor_key_immediate |
649 descriptor_irq_always |
650 descriptor_branch_always);
651 ctx->d.more.req_count = cpu_to_le16(packet->header_length);
652 ctx->d.more.res_count = cpu_to_le16(packet->timestamp);
656 /* The DMA format for asyncronous link packets is different
657 * from the IEEE1394 layout, so shift the fields around
658 * accordingly. If header_length is 8, it's a PHY packet, to
659 * which we need to prepend an extra quadlet. */
660 if (packet->header_length > 8) {
661 ctx->d.header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
662 (packet->speed << 16));
663 ctx->d.header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
664 (packet->header[0] & 0xffff0000));
665 ctx->d.header[2] = cpu_to_le32(packet->header[2]);
667 tcode = (packet->header[0] >> 4) & 0x0f;
668 if (TCODE_IS_BLOCK_PACKET(tcode))
669 ctx->d.header[3] = cpu_to_le32(packet->header[3]);
671 ctx->d.header[3] = packet->header[3];
674 cpu_to_le32((OHCI1394_phy_tcode << 4) |
675 (packet->speed << 16));
676 ctx->d.header[1] = cpu_to_le32(packet->header[0]);
677 ctx->d.header[2] = cpu_to_le32(packet->header[1]);
678 ctx->d.more.req_count = cpu_to_le16(12);
681 /* FIXME: Document how the locking works. */
682 if (ohci->generation == packet->generation) {
683 reg_write(ctx->ohci, command_ptr(ctx->regs),
684 ctx->descriptor_bus | z);
685 reg_write(ctx->ohci, control_set(ctx->regs),
686 CONTEXT_RUN | CONTEXT_WAKE);
687 ctx->current_packet = packet;
689 /* We dont return error codes from this function; all
690 * transmission errors are reported through the
692 complete_transmission(packet, RCODE_GENERATION, list);
696 static void at_context_stop(struct at_context *ctx)
700 reg_write(ctx->ohci, control_clear(ctx->regs), CONTEXT_RUN);
702 reg = reg_read(ctx->ohci, control_set(ctx->regs));
703 if (reg & CONTEXT_ACTIVE)
704 fw_notify("Tried to stop context, but it is still active "
708 static void at_context_tasklet(unsigned long data)
710 struct at_context *ctx = (struct at_context *)data;
711 struct fw_ohci *ohci = ctx->ohci;
712 struct fw_packet *packet;
717 spin_lock_irqsave(&ohci->lock, flags);
719 packet = fw_packet(ctx->list.next);
721 at_context_stop(ctx);
723 /* If the head of the list isn't the packet that just got
724 * transmitted, the packet got cancelled before we finished
725 * transmitting it. */
726 if (ctx->current_packet != packet)
729 if (packet->payload_length > 0) {
730 dma_unmap_single(ohci->card.device, packet->payload_bus,
731 packet->payload_length, DMA_TO_DEVICE);
732 evt = le16_to_cpu(ctx->d.last.transfer_status) & 0x1f;
733 packet->timestamp = le16_to_cpu(ctx->d.last.res_count);
736 evt = le16_to_cpu(ctx->d.more.transfer_status) & 0x1f;
737 packet->timestamp = le16_to_cpu(ctx->d.more.res_count);
742 case OHCI1394_evt_timeout:
743 /* Async response transmit timed out. */
744 complete_transmission(packet, RCODE_CANCELLED, &list);
747 case OHCI1394_evt_flushed:
748 /* The packet was flushed should give same
749 * error as when we try to use a stale
750 * generation count. */
751 complete_transmission(packet,
752 RCODE_GENERATION, &list);
755 case OHCI1394_evt_missing_ack:
756 /* Using a valid (current) generation count,
757 * but the node is not on the bus or not
759 complete_transmission(packet, RCODE_NO_ACK, &list);
763 complete_transmission(packet, RCODE_SEND_ERROR, &list);
767 complete_transmission(packet, evt - 16, &list);
770 /* If more packets are queued, set up the next one. */
771 if (!list_empty(&ctx->list))
772 at_context_setup_packet(ctx, &list);
774 spin_unlock_irqrestore(&ohci->lock, flags);
776 do_packet_callbacks(ohci, &list);
780 at_context_init(struct at_context *ctx, struct fw_ohci *ohci, u32 regs)
782 INIT_LIST_HEAD(&ctx->list);
784 ctx->descriptor_bus =
785 dma_map_single(ohci->card.device, &ctx->d,
786 sizeof ctx->d, DMA_TO_DEVICE);
787 if (dma_mapping_error(ctx->descriptor_bus))
793 tasklet_init(&ctx->tasklet, at_context_tasklet, (unsigned long)ctx);
798 #define header_get_destination(q) (((q) >> 16) & 0xffff)
799 #define header_get_tcode(q) (((q) >> 4) & 0x0f)
800 #define header_get_offset_high(q) (((q) >> 0) & 0xffff)
801 #define header_get_data_length(q) (((q) >> 16) & 0xffff)
802 #define header_get_extended_tcode(q) (((q) >> 0) & 0xffff)
805 handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
807 struct fw_packet response;
808 int tcode, length, i;
810 tcode = header_get_tcode(packet->header[0]);
811 if (TCODE_IS_BLOCK_PACKET(tcode))
812 length = header_get_data_length(packet->header[3]);
816 i = csr - CSR_CONFIG_ROM;
817 if (i + length > CONFIG_ROM_SIZE) {
818 fw_fill_response(&response, packet->header,
819 RCODE_ADDRESS_ERROR, NULL, 0);
820 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
821 fw_fill_response(&response, packet->header,
822 RCODE_TYPE_ERROR, NULL, 0);
824 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
825 (void *) ohci->config_rom + i, length);
828 fw_core_handle_response(&ohci->card, &response);
832 handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
834 struct fw_packet response;
835 int tcode, length, ext_tcode, sel;
836 __be32 *payload, lock_old;
837 u32 lock_arg, lock_data;
839 tcode = header_get_tcode(packet->header[0]);
840 length = header_get_data_length(packet->header[3]);
841 payload = packet->payload;
842 ext_tcode = header_get_extended_tcode(packet->header[3]);
844 if (tcode == TCODE_LOCK_REQUEST &&
845 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
846 lock_arg = be32_to_cpu(payload[0]);
847 lock_data = be32_to_cpu(payload[1]);
848 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
852 fw_fill_response(&response, packet->header,
853 RCODE_TYPE_ERROR, NULL, 0);
857 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
858 reg_write(ohci, OHCI1394_CSRData, lock_data);
859 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
860 reg_write(ohci, OHCI1394_CSRControl, sel);
862 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
863 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
865 fw_notify("swap not done yet\n");
867 fw_fill_response(&response, packet->header,
868 RCODE_COMPLETE, &lock_old, sizeof lock_old);
870 fw_core_handle_response(&ohci->card, &response);
874 handle_local_request(struct at_context *ctx, struct fw_packet *packet)
879 packet->ack = ACK_PENDING;
880 packet->callback(packet, &ctx->ohci->card, packet->ack);
883 ((unsigned long long)
884 header_get_offset_high(packet->header[1]) << 32) |
886 csr = offset - CSR_REGISTER_BASE;
888 /* Handle config rom reads. */
889 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
890 handle_local_rom(ctx->ohci, packet, csr);
892 case CSR_BUS_MANAGER_ID:
893 case CSR_BANDWIDTH_AVAILABLE:
894 case CSR_CHANNELS_AVAILABLE_HI:
895 case CSR_CHANNELS_AVAILABLE_LO:
896 handle_local_lock(ctx->ohci, packet, csr);
899 if (ctx == &ctx->ohci->at_request_ctx)
900 fw_core_handle_request(&ctx->ohci->card, packet);
902 fw_core_handle_response(&ctx->ohci->card, packet);
908 at_context_transmit(struct at_context *ctx, struct fw_packet *packet)
913 spin_lock_irqsave(&ctx->ohci->lock, flags);
915 if (header_get_destination(packet->header[0]) == ctx->ohci->node_id &&
916 ctx->ohci->generation == packet->generation) {
917 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
918 handle_local_request(ctx, packet);
922 list_add_tail(&packet->link, &ctx->list);
923 if (ctx->list.next == &packet->link)
924 at_context_setup_packet(ctx, &list);
926 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
928 do_packet_callbacks(ctx->ohci, &list);
931 static void bus_reset_tasklet(unsigned long data)
933 struct fw_ohci *ohci = (struct fw_ohci *)data;
934 int self_id_count, i, j, reg;
935 int generation, new_generation;
938 reg = reg_read(ohci, OHCI1394_NodeID);
939 if (!(reg & OHCI1394_NodeID_idValid)) {
940 fw_error("node ID not valid, new bus reset in progress\n");
943 ohci->node_id = reg & 0xffff;
945 /* The count in the SelfIDCount register is the number of
946 * bytes in the self ID receive buffer. Since we also receive
947 * the inverted quadlets and a header quadlet, we shift one
948 * bit extra to get the actual number of self IDs. */
950 self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff;
951 generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
953 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
954 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1])
955 fw_error("inconsistent self IDs\n");
956 ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]);
959 /* Check the consistency of the self IDs we just read. The
960 * problem we face is that a new bus reset can start while we
961 * read out the self IDs from the DMA buffer. If this happens,
962 * the DMA buffer will be overwritten with new self IDs and we
963 * will read out inconsistent data. The OHCI specification
964 * (section 11.2) recommends a technique similar to
965 * linux/seqlock.h, where we remember the generation of the
966 * self IDs in the buffer before reading them out and compare
967 * it to the current generation after reading them out. If
968 * the two generations match we know we have a consistent set
971 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
972 if (new_generation != generation) {
973 fw_notify("recursive bus reset detected, "
974 "discarding self ids\n");
978 /* FIXME: Document how the locking works. */
979 spin_lock_irqsave(&ohci->lock, flags);
981 ohci->generation = generation;
982 at_context_stop(&ohci->at_request_ctx);
983 at_context_stop(&ohci->at_response_ctx);
984 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
986 /* This next bit is unrelated to the AT context stuff but we
987 * have to do it under the spinlock also. If a new config rom
988 * was set up before this reset, the old one is now no longer
989 * in use and we can free it. Update the config rom pointers
990 * to point to the current config rom and clear the
991 * next_config_rom pointer so a new udpate can take place. */
993 if (ohci->next_config_rom != NULL) {
994 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
995 ohci->config_rom, ohci->config_rom_bus);
996 ohci->config_rom = ohci->next_config_rom;
997 ohci->config_rom_bus = ohci->next_config_rom_bus;
998 ohci->next_config_rom = NULL;
1000 /* Restore config_rom image and manually update
1001 * config_rom registers. Writing the header quadlet
1002 * will indicate that the config rom is ready, so we
1004 reg_write(ohci, OHCI1394_BusOptions,
1005 be32_to_cpu(ohci->config_rom[2]));
1006 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
1007 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
1010 spin_unlock_irqrestore(&ohci->lock, flags);
1012 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1013 self_id_count, ohci->self_id_buffer);
1016 static irqreturn_t irq_handler(int irq, void *data)
1018 struct fw_ohci *ohci = data;
1019 u32 event, iso_event;
1022 event = reg_read(ohci, OHCI1394_IntEventClear);
1027 reg_write(ohci, OHCI1394_IntEventClear, event);
1029 if (event & OHCI1394_selfIDComplete)
1030 tasklet_schedule(&ohci->bus_reset_tasklet);
1032 if (event & OHCI1394_RQPkt)
1033 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1035 if (event & OHCI1394_RSPkt)
1036 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1038 if (event & OHCI1394_reqTxComplete)
1039 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1041 if (event & OHCI1394_respTxComplete)
1042 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1044 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1045 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1048 i = ffs(iso_event) - 1;
1049 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1050 iso_event &= ~(1 << i);
1053 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1054 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1057 i = ffs(iso_event) - 1;
1058 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1059 iso_event &= ~(1 << i);
1065 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1067 struct fw_ohci *ohci = fw_ohci(card);
1068 struct pci_dev *dev = to_pci_dev(card->device);
1070 /* When the link is not yet enabled, the atomic config rom
1071 * update mechanism described below in ohci_set_config_rom()
1072 * is not active. We have to update ConfigRomHeader and
1073 * BusOptions manually, and the write to ConfigROMmap takes
1074 * effect immediately. We tie this to the enabling of the
1075 * link, so we have a valid config rom before enabling - the
1076 * OHCI requires that ConfigROMhdr and BusOptions have valid
1077 * values before enabling.
1079 * However, when the ConfigROMmap is written, some controllers
1080 * always read back quadlets 0 and 2 from the config rom to
1081 * the ConfigRomHeader and BusOptions registers on bus reset.
1082 * They shouldn't do that in this initial case where the link
1083 * isn't enabled. This means we have to use the same
1084 * workaround here, setting the bus header to 0 and then write
1085 * the right values in the bus reset tasklet.
1088 ohci->next_config_rom =
1089 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1090 &ohci->next_config_rom_bus, GFP_KERNEL);
1091 if (ohci->next_config_rom == NULL)
1094 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1095 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1097 ohci->next_header = config_rom[0];
1098 ohci->next_config_rom[0] = 0;
1099 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1100 reg_write(ohci, OHCI1394_BusOptions, config_rom[2]);
1101 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1103 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1105 if (request_irq(dev->irq, irq_handler,
1106 SA_SHIRQ, ohci_driver_name, ohci)) {
1107 fw_error("Failed to allocate shared interrupt %d.\n",
1109 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1110 ohci->config_rom, ohci->config_rom_bus);
1114 reg_write(ohci, OHCI1394_HCControlSet,
1115 OHCI1394_HCControl_linkEnable |
1116 OHCI1394_HCControl_BIBimageValid);
1119 /* We are ready to go, initiate bus reset to finish the
1120 * initialization. */
1122 fw_core_initiate_bus_reset(&ohci->card, 1);
1128 ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1130 struct fw_ohci *ohci;
1131 unsigned long flags;
1133 __be32 *next_config_rom;
1134 dma_addr_t next_config_rom_bus;
1136 ohci = fw_ohci(card);
1138 /* When the OHCI controller is enabled, the config rom update
1139 * mechanism is a bit tricky, but easy enough to use. See
1140 * section 5.5.6 in the OHCI specification.
1142 * The OHCI controller caches the new config rom address in a
1143 * shadow register (ConfigROMmapNext) and needs a bus reset
1144 * for the changes to take place. When the bus reset is
1145 * detected, the controller loads the new values for the
1146 * ConfigRomHeader and BusOptions registers from the specified
1147 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1148 * shadow register. All automatically and atomically.
1150 * Now, there's a twist to this story. The automatic load of
1151 * ConfigRomHeader and BusOptions doesn't honor the
1152 * noByteSwapData bit, so with a be32 config rom, the
1153 * controller will load be32 values in to these registers
1154 * during the atomic update, even on litte endian
1155 * architectures. The workaround we use is to put a 0 in the
1156 * header quadlet; 0 is endian agnostic and means that the
1157 * config rom isn't ready yet. In the bus reset tasklet we
1158 * then set up the real values for the two registers.
1160 * We use ohci->lock to avoid racing with the code that sets
1161 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1165 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1166 &next_config_rom_bus, GFP_KERNEL);
1167 if (next_config_rom == NULL)
1170 spin_lock_irqsave(&ohci->lock, flags);
1172 if (ohci->next_config_rom == NULL) {
1173 ohci->next_config_rom = next_config_rom;
1174 ohci->next_config_rom_bus = next_config_rom_bus;
1176 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1177 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1180 ohci->next_header = config_rom[0];
1181 ohci->next_config_rom[0] = 0;
1183 reg_write(ohci, OHCI1394_ConfigROMmap,
1184 ohci->next_config_rom_bus);
1186 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1187 next_config_rom, next_config_rom_bus);
1191 spin_unlock_irqrestore(&ohci->lock, flags);
1193 /* Now initiate a bus reset to have the changes take
1194 * effect. We clean up the old config rom memory and DMA
1195 * mappings in the bus reset tasklet, since the OHCI
1196 * controller could need to access it before the bus reset
1199 fw_core_initiate_bus_reset(&ohci->card, 1);
1204 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1206 struct fw_ohci *ohci = fw_ohci(card);
1208 at_context_transmit(&ohci->at_request_ctx, packet);
1211 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1213 struct fw_ohci *ohci = fw_ohci(card);
1215 at_context_transmit(&ohci->at_response_ctx, packet);
1218 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1220 struct fw_ohci *ohci = fw_ohci(card);
1222 unsigned long flags;
1224 spin_lock_irqsave(&ohci->lock, flags);
1226 if (packet->ack == 0) {
1227 fw_notify("cancelling packet %p (header[0]=%08x)\n",
1228 packet, packet->header[0]);
1230 complete_transmission(packet, RCODE_CANCELLED, &list);
1233 spin_unlock_irqrestore(&ohci->lock, flags);
1235 do_packet_callbacks(ohci, &list);
1237 /* Return success if we actually cancelled something. */
1238 return list_empty(&list) ? -ENOENT : 0;
1242 ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1244 struct fw_ohci *ohci = fw_ohci(card);
1245 unsigned long flags;
1248 /* FIXME: Make sure this bitmask is cleared when we clear the busReset
1249 * interrupt bit. Clear physReqResourceAllBuses on bus reset. */
1251 spin_lock_irqsave(&ohci->lock, flags);
1253 if (ohci->generation != generation) {
1258 /* NOTE, if the node ID contains a non-local bus ID, physical DMA is
1259 * enabled for _all_ nodes on remote buses. */
1261 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1263 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1265 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1269 spin_unlock_irqrestore(&ohci->lock, flags);
1273 static int handle_ir_bufferfill_packet(struct context *context,
1274 struct descriptor *d,
1275 struct descriptor *last)
1277 struct iso_context *ctx =
1278 container_of(context, struct iso_context, context);
1280 if (d->res_count > 0)
1283 if (le16_to_cpu(last->control) & descriptor_irq_always)
1284 ctx->base.callback(&ctx->base,
1285 le16_to_cpu(last->res_count),
1286 0, NULL, ctx->base.callback_data);
1291 static int handle_ir_dualbuffer_packet(struct context *context,
1292 struct descriptor *d,
1293 struct descriptor *last)
1295 struct iso_context *ctx =
1296 container_of(context, struct iso_context, context);
1297 struct db_descriptor *db = (struct db_descriptor *) d;
1298 size_t header_length;
1300 if (db->first_res_count > 0 && db->second_res_count > 0)
1301 /* This descriptor isn't done yet, stop iteration. */
1304 header_length = db->first_req_count - db->first_res_count;
1305 if (ctx->header_length + header_length <= PAGE_SIZE)
1306 memcpy(ctx->header + ctx->header_length, db + 1, header_length);
1307 ctx->header_length += header_length;
1309 if (le16_to_cpu(db->control) & descriptor_irq_always) {
1310 ctx->base.callback(&ctx->base, 0,
1311 ctx->header_length, ctx->header,
1312 ctx->base.callback_data);
1313 ctx->header_length = 0;
1319 #define ISO_BUFFER_SIZE (64 * 1024)
1321 static int handle_it_packet(struct context *context,
1322 struct descriptor *d,
1323 struct descriptor *last)
1325 struct iso_context *ctx =
1326 container_of(context, struct iso_context, context);
1328 if (last->transfer_status == 0)
1329 /* This descriptor isn't done yet, stop iteration. */
1332 if (le16_to_cpu(last->control) & descriptor_irq_always)
1333 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1334 0, NULL, ctx->base.callback_data);
1339 static struct fw_iso_context *
1340 ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
1342 struct fw_ohci *ohci = fw_ohci(card);
1343 struct iso_context *ctx, *list;
1344 descriptor_callback_t callback;
1346 unsigned long flags;
1347 int index, retval = -ENOMEM;
1349 if (type == FW_ISO_CONTEXT_TRANSMIT) {
1350 mask = &ohci->it_context_mask;
1351 list = ohci->it_context_list;
1352 callback = handle_it_packet;
1354 mask = &ohci->ir_context_mask;
1355 list = ohci->ir_context_list;
1356 if (header_size > 0)
1357 callback = handle_ir_dualbuffer_packet;
1359 callback = handle_ir_bufferfill_packet;
1362 if (callback == handle_ir_dualbuffer_packet &&
1363 ohci->version < OHCI_VERSION_1_1)
1364 return ERR_PTR(-EINVAL);
1366 spin_lock_irqsave(&ohci->lock, flags);
1367 index = ffs(*mask) - 1;
1369 *mask &= ~(1 << index);
1370 spin_unlock_irqrestore(&ohci->lock, flags);
1373 return ERR_PTR(-EBUSY);
1375 if (type == FW_ISO_CONTEXT_TRANSMIT)
1376 regs = OHCI1394_IsoXmitContextBase(index);
1378 regs = OHCI1394_IsoRcvContextBase(index);
1381 memset(ctx, 0, sizeof *ctx);
1382 ctx->header_length = 0;
1383 ctx->header = (void *) __get_free_page(GFP_KERNEL);
1384 if (ctx->header == NULL)
1387 retval = context_init(&ctx->context, ohci, ISO_BUFFER_SIZE,
1390 goto out_with_header;
1395 free_page((unsigned long)ctx->header);
1397 spin_lock_irqsave(&ohci->lock, flags);
1398 *mask |= 1 << index;
1399 spin_unlock_irqrestore(&ohci->lock, flags);
1401 return ERR_PTR(retval);
1404 static int ohci_start_iso(struct fw_iso_context *base, s32 cycle)
1406 struct iso_context *ctx = container_of(base, struct iso_context, base);
1407 struct fw_ohci *ohci = ctx->context.ohci;
1408 u32 cycle_match = 0, mode;
1411 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1412 index = ctx - ohci->it_context_list;
1414 cycle_match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1415 (cycle & 0x7fff) << 16;
1417 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1418 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1419 context_run(&ctx->context, cycle_match);
1421 index = ctx - ohci->ir_context_list;
1423 if (ctx->base.header_size > 0)
1424 mode = IR_CONTEXT_DUAL_BUFFER_MODE;
1426 mode = IR_CONTEXT_BUFFER_FILL;
1427 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1428 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
1429 reg_write(ohci, context_match(ctx->context.regs),
1430 0xf0000000 | ctx->base.channel);
1431 context_run(&ctx->context, mode);
1437 static int ohci_stop_iso(struct fw_iso_context *base)
1439 struct fw_ohci *ohci = fw_ohci(base->card);
1440 struct iso_context *ctx = container_of(base, struct iso_context, base);
1443 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1444 index = ctx - ohci->it_context_list;
1445 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1447 index = ctx - ohci->ir_context_list;
1448 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1451 context_stop(&ctx->context);
1456 static void ohci_free_iso_context(struct fw_iso_context *base)
1458 struct fw_ohci *ohci = fw_ohci(base->card);
1459 struct iso_context *ctx = container_of(base, struct iso_context, base);
1460 unsigned long flags;
1463 ohci_stop_iso(base);
1464 context_release(&ctx->context);
1465 free_page((unsigned long)ctx->header);
1467 spin_lock_irqsave(&ohci->lock, flags);
1469 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1470 index = ctx - ohci->it_context_list;
1471 ohci->it_context_mask |= 1 << index;
1473 index = ctx - ohci->ir_context_list;
1474 ohci->ir_context_mask |= 1 << index;
1477 spin_unlock_irqrestore(&ohci->lock, flags);
1481 ohci_queue_iso_transmit(struct fw_iso_context *base,
1482 struct fw_iso_packet *packet,
1483 struct fw_iso_buffer *buffer,
1484 unsigned long payload)
1486 struct iso_context *ctx = container_of(base, struct iso_context, base);
1487 struct descriptor *d, *last, *pd;
1488 struct fw_iso_packet *p;
1490 dma_addr_t d_bus, page_bus;
1491 u32 z, header_z, payload_z, irq;
1492 u32 payload_index, payload_end_index, next_page_index;
1493 int page, end_page, i, length, offset;
1495 /* FIXME: Cycle lost behavior should be configurable: lose
1496 * packet, retransmit or terminate.. */
1499 payload_index = payload;
1505 if (p->header_length > 0)
1508 /* Determine the first page the payload isn't contained in. */
1509 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
1510 if (p->payload_length > 0)
1511 payload_z = end_page - (payload_index >> PAGE_SHIFT);
1517 /* Get header size in number of descriptors. */
1518 header_z = DIV_ROUND_UP(p->header_length, sizeof *d);
1520 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
1525 d[0].control = cpu_to_le16(descriptor_key_immediate);
1526 d[0].req_count = cpu_to_le16(8);
1528 header = (__le32 *) &d[1];
1529 header[0] = cpu_to_le32(it_header_sy(p->sy) |
1530 it_header_tag(p->tag) |
1531 it_header_tcode(TCODE_STREAM_DATA) |
1532 it_header_channel(ctx->base.channel) |
1533 it_header_speed(ctx->base.speed));
1535 cpu_to_le32(it_header_data_length(p->header_length +
1536 p->payload_length));
1539 if (p->header_length > 0) {
1540 d[2].req_count = cpu_to_le16(p->header_length);
1541 d[2].data_address = cpu_to_le32(d_bus + z * sizeof *d);
1542 memcpy(&d[z], p->header, p->header_length);
1545 pd = d + z - payload_z;
1546 payload_end_index = payload_index + p->payload_length;
1547 for (i = 0; i < payload_z; i++) {
1548 page = payload_index >> PAGE_SHIFT;
1549 offset = payload_index & ~PAGE_MASK;
1550 next_page_index = (page + 1) << PAGE_SHIFT;
1552 min(next_page_index, payload_end_index) - payload_index;
1553 pd[i].req_count = cpu_to_le16(length);
1555 page_bus = page_private(buffer->pages[page]);
1556 pd[i].data_address = cpu_to_le32(page_bus + offset);
1558 payload_index += length;
1562 irq = descriptor_irq_always;
1564 irq = descriptor_no_irq;
1566 last = z == 2 ? d : d + z - 1;
1567 last->control |= cpu_to_le16(descriptor_output_last |
1569 descriptor_branch_always |
1572 context_append(&ctx->context, d, z, header_z);
1578 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
1579 struct fw_iso_packet *packet,
1580 struct fw_iso_buffer *buffer,
1581 unsigned long payload)
1583 struct iso_context *ctx = container_of(base, struct iso_context, base);
1584 struct db_descriptor *db = NULL;
1585 struct descriptor *d;
1586 struct fw_iso_packet *p;
1587 dma_addr_t d_bus, page_bus;
1588 u32 z, header_z, length, rest;
1591 /* FIXME: Cycle lost behavior should be configurable: lose
1592 * packet, retransmit or terminate.. */
1597 /* Get header size in number of descriptors. */
1598 header_z = DIV_ROUND_UP(p->header_length, sizeof *d);
1599 page = payload >> PAGE_SHIFT;
1600 offset = payload & ~PAGE_MASK;
1601 rest = p->payload_length;
1603 /* FIXME: OHCI 1.0 doesn't support dual buffer receive */
1604 /* FIXME: handle descriptor_wait */
1605 /* FIXME: make packet-per-buffer/dual-buffer a context option */
1607 d = context_get_descriptors(&ctx->context,
1608 z + header_z, &d_bus);
1612 db = (struct db_descriptor *) d;
1613 db->control = cpu_to_le16(descriptor_status |
1614 descriptor_branch_always);
1615 db->first_size = cpu_to_le16(ctx->base.header_size);
1616 db->first_req_count = cpu_to_le16(p->header_length);
1617 db->first_res_count = db->first_req_count;
1618 db->first_buffer = cpu_to_le32(d_bus + sizeof *db);
1620 if (offset + rest < PAGE_SIZE)
1623 length = PAGE_SIZE - offset;
1625 db->second_req_count = cpu_to_le16(length);
1626 db->second_res_count = db->second_req_count;
1627 page_bus = page_private(buffer->pages[page]);
1628 db->second_buffer = cpu_to_le32(page_bus + offset);
1630 if (p->interrupt && length == rest)
1631 db->control |= cpu_to_le16(descriptor_irq_always);
1633 context_append(&ctx->context, d, z, header_z);
1634 offset = (offset + length) & ~PAGE_MASK;
1643 ohci_queue_iso_receive_bufferfill(struct fw_iso_context *base,
1644 struct fw_iso_packet *packet,
1645 struct fw_iso_buffer *buffer,
1646 unsigned long payload)
1648 struct iso_context *ctx = container_of(base, struct iso_context, base);
1649 struct descriptor *d = NULL;
1650 dma_addr_t d_bus, page_bus;
1654 page = payload >> PAGE_SHIFT;
1655 offset = payload & ~PAGE_MASK;
1656 rest = packet->payload_length;
1659 d = context_get_descriptors(&ctx->context, 1, &d_bus);
1663 d->control = cpu_to_le16(descriptor_input_more |
1665 descriptor_branch_always);
1667 if (offset + rest < PAGE_SIZE)
1670 length = PAGE_SIZE - offset;
1672 page_bus = page_private(buffer->pages[page]);
1673 d->data_address = cpu_to_le32(page_bus + offset);
1674 d->req_count = cpu_to_le16(length);
1675 d->res_count = cpu_to_le16(length);
1677 if (packet->interrupt && length == rest)
1678 d->control |= cpu_to_le16(descriptor_irq_always);
1680 context_append(&ctx->context, d, 1, 0);
1682 offset = (offset + length) & ~PAGE_MASK;
1691 ohci_queue_iso(struct fw_iso_context *base,
1692 struct fw_iso_packet *packet,
1693 struct fw_iso_buffer *buffer,
1694 unsigned long payload)
1696 struct iso_context *ctx = container_of(base, struct iso_context, base);
1698 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
1699 return ohci_queue_iso_transmit(base, packet, buffer, payload);
1700 else if (base->header_size == 0)
1701 return ohci_queue_iso_receive_bufferfill(base, packet,
1703 else if (ctx->context.ohci->version >= OHCI_VERSION_1_1)
1704 return ohci_queue_iso_receive_dualbuffer(base, packet,
1707 /* FIXME: Implement fallback for OHCI 1.0 controllers. */
1711 static const struct fw_card_driver ohci_driver = {
1712 .name = ohci_driver_name,
1713 .enable = ohci_enable,
1714 .update_phy_reg = ohci_update_phy_reg,
1715 .set_config_rom = ohci_set_config_rom,
1716 .send_request = ohci_send_request,
1717 .send_response = ohci_send_response,
1718 .cancel_packet = ohci_cancel_packet,
1719 .enable_phys_dma = ohci_enable_phys_dma,
1721 .allocate_iso_context = ohci_allocate_iso_context,
1722 .free_iso_context = ohci_free_iso_context,
1723 .queue_iso = ohci_queue_iso,
1724 .start_iso = ohci_start_iso,
1725 .stop_iso = ohci_stop_iso,
1728 static int software_reset(struct fw_ohci *ohci)
1732 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1734 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1735 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1736 OHCI1394_HCControl_softReset) == 0)
1744 /* ---------- pci subsystem interface ---------- */
1754 static int cleanup(struct fw_ohci *ohci, int stage, int code)
1756 struct pci_dev *dev = to_pci_dev(ohci->card.device);
1759 case CLEANUP_SELF_ID:
1760 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
1761 ohci->self_id_cpu, ohci->self_id_bus);
1762 case CLEANUP_REGISTERS:
1763 kfree(ohci->it_context_list);
1764 kfree(ohci->ir_context_list);
1765 pci_iounmap(dev, ohci->registers);
1767 pci_release_region(dev, 0);
1768 case CLEANUP_DISABLE:
1769 pci_disable_device(dev);
1770 case CLEANUP_PUT_CARD:
1771 fw_card_put(&ohci->card);
1777 static int __devinit
1778 pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
1780 struct fw_ohci *ohci;
1781 u32 bus_options, max_receive, link_speed;
1786 ohci = kzalloc(sizeof *ohci, GFP_KERNEL);
1788 fw_error("Could not malloc fw_ohci data.\n");
1792 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
1794 if (pci_enable_device(dev)) {
1795 fw_error("Failed to enable OHCI hardware.\n");
1796 return cleanup(ohci, CLEANUP_PUT_CARD, -ENODEV);
1799 pci_set_master(dev);
1800 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
1801 pci_set_drvdata(dev, ohci);
1803 spin_lock_init(&ohci->lock);
1805 tasklet_init(&ohci->bus_reset_tasklet,
1806 bus_reset_tasklet, (unsigned long)ohci);
1808 if (pci_request_region(dev, 0, ohci_driver_name)) {
1809 fw_error("MMIO resource unavailable\n");
1810 return cleanup(ohci, CLEANUP_DISABLE, -EBUSY);
1813 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
1814 if (ohci->registers == NULL) {
1815 fw_error("Failed to remap registers\n");
1816 return cleanup(ohci, CLEANUP_IOMEM, -ENXIO);
1819 if (software_reset(ohci)) {
1820 fw_error("Failed to reset ohci card.\n");
1821 return cleanup(ohci, CLEANUP_REGISTERS, -EBUSY);
1824 /* Now enable LPS, which we need in order to start accessing
1825 * most of the registers. In fact, on some cards (ALI M5251),
1826 * accessing registers in the SClk domain without LPS enabled
1827 * will lock up the machine. Wait 50msec to make sure we have
1828 * full link enabled. */
1829 reg_write(ohci, OHCI1394_HCControlSet,
1830 OHCI1394_HCControl_LPS |
1831 OHCI1394_HCControl_postedWriteEnable);
1835 reg_write(ohci, OHCI1394_HCControlClear,
1836 OHCI1394_HCControl_noByteSwapData);
1838 reg_write(ohci, OHCI1394_LinkControlSet,
1839 OHCI1394_LinkControl_rcvSelfID |
1840 OHCI1394_LinkControl_cycleTimerEnable |
1841 OHCI1394_LinkControl_cycleMaster);
1843 ar_context_init(&ohci->ar_request_ctx, ohci,
1844 OHCI1394_AsReqRcvContextControlSet);
1846 ar_context_init(&ohci->ar_response_ctx, ohci,
1847 OHCI1394_AsRspRcvContextControlSet);
1849 at_context_init(&ohci->at_request_ctx, ohci,
1850 OHCI1394_AsReqTrContextControlSet);
1852 at_context_init(&ohci->at_response_ctx, ohci,
1853 OHCI1394_AsRspTrContextControlSet);
1855 reg_write(ohci, OHCI1394_ATRetries,
1856 OHCI1394_MAX_AT_REQ_RETRIES |
1857 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1858 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1860 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
1861 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
1862 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
1863 size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
1864 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
1866 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
1867 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
1868 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
1869 size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
1870 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
1872 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
1873 fw_error("Out of memory for it/ir contexts.\n");
1874 return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM);
1877 /* self-id dma buffer allocation */
1878 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
1882 if (ohci->self_id_cpu == NULL) {
1883 fw_error("Out of memory for self ID buffer.\n");
1884 return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM);
1887 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1888 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1889 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1890 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1891 reg_write(ohci, OHCI1394_IntMaskSet,
1892 OHCI1394_selfIDComplete |
1893 OHCI1394_RQPkt | OHCI1394_RSPkt |
1894 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1895 OHCI1394_isochRx | OHCI1394_isochTx |
1896 OHCI1394_masterIntEnable);
1898 bus_options = reg_read(ohci, OHCI1394_BusOptions);
1899 max_receive = (bus_options >> 12) & 0xf;
1900 link_speed = bus_options & 0x7;
1901 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
1902 reg_read(ohci, OHCI1394_GUIDLo);
1904 error_code = fw_card_add(&ohci->card, max_receive, link_speed, guid);
1906 return cleanup(ohci, CLEANUP_SELF_ID, error_code);
1908 ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
1909 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
1910 dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff);
1915 static void pci_remove(struct pci_dev *dev)
1917 struct fw_ohci *ohci;
1919 ohci = pci_get_drvdata(dev);
1920 reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_masterIntEnable);
1921 fw_core_remove_card(&ohci->card);
1923 /* FIXME: Fail all pending packets here, now that the upper
1924 * layers can't queue any more. */
1926 software_reset(ohci);
1927 free_irq(dev->irq, ohci);
1928 cleanup(ohci, CLEANUP_SELF_ID, 0);
1930 fw_notify("Removed fw-ohci device.\n");
1933 static struct pci_device_id pci_table[] = {
1934 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
1938 MODULE_DEVICE_TABLE(pci, pci_table);
1940 static struct pci_driver fw_ohci_pci_driver = {
1941 .name = ohci_driver_name,
1942 .id_table = pci_table,
1944 .remove = pci_remove,
1947 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
1948 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
1949 MODULE_LICENSE("GPL");
1951 static int __init fw_ohci_init(void)
1953 return pci_register_driver(&fw_ohci_pci_driver);
1956 static void __exit fw_ohci_cleanup(void)
1958 pci_unregister_driver(&fw_ohci_pci_driver);
1961 module_init(fw_ohci_init);
1962 module_exit(fw_ohci_cleanup);