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   1 /*
   2  * MPC8540 ADS Device Tree Source
   3  *
   4  * Copyright 2006 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12
  13 / {
  14         model = "MPC8540ADS";
  15         compatible = "MPC8540ADS", "MPC85xxADS";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         aliases {
  20                 ethernet0 = &enet0;
  21                 ethernet1 = &enet1;
  22                 ethernet2 = &enet2;
  23                 serial0 = &serial0;
  24                 serial1 = &serial1;
  25                 pci0 = &pci0;
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 PowerPC,8540@0 {
  33                         device_type = "cpu";
  34                         reg = <0>;
  35                         d-cache-line-size = <20>;       // 32 bytes
  36                         i-cache-line-size = <20>;       // 32 bytes
  37                         d-cache-size = <8000>;          // L1, 32K
  38                         i-cache-size = <8000>;          // L1, 32K
  39                         timebase-frequency = <0>;       //  33 MHz, from uboot
  40                         bus-frequency = <0>;    // 166 MHz
  41                         clock-frequency = <0>;  // 825 MHz, from uboot
  42                 };
  43         };
  44
  45         memory {
  46                 device_type = "memory";
  47                 reg = <00000000 08000000>;      // 128M at 0x0
  48         };
  49
  50         soc8540@e0000000 {
  51                 #address-cells = <1>;
  52                 #size-cells = <1>;
  53                 device_type = "soc";
  54                 ranges = <0 e0000000 00100000>;
  55                 reg = <e0000000 00100000>;      // CCSRBAR 1M
  56                 bus-frequency = <0>;
  57
  58                 memory-controller@2000 {
  59                         compatible = "fsl,8540-memory-controller";
  60                         reg = <2000 1000>;
  61                         interrupt-parent = <&mpic>;
  62                         interrupts = <12 2>;
  63                 };
  64
  65                 l2-cache-controller@20000 {
  66                         compatible = "fsl,8540-l2-cache-controller";
  67                         reg = <20000 1000>;
  68                         cache-line-size = <20>; // 32 bytes
  69                         cache-size = <40000>;   // L2, 256K
  70                         interrupt-parent = <&mpic>;
  71                         interrupts = <10 2>;
  72                 };
  73
  74                 i2c@3000 {
  75                         #address-cells = <1>;
  76                         #size-cells = <0>;
  77                         cell-index = <0>;
  78                         compatible = "fsl-i2c";
  79                         reg = <3000 100>;
  80                         interrupts = <2b 2>;
  81                         interrupt-parent = <&mpic>;
  82                         dfsrr;
  83                 };
  84
  85                 mdio@24520 {
  86                         #address-cells = <1>;
  87                         #size-cells = <0>;
  88                         compatible = "fsl,gianfar-mdio";
  89                         reg = <24520 20>;
  90
  91                         phy0: ethernet-phy@0 {
  92                                 interrupt-parent = <&mpic>;
  93                                 interrupts = <5 1>;
  94                                 reg = <0>;
  95                                 device_type = "ethernet-phy";
  96                         };
  97                         phy1: ethernet-phy@1 {
  98                                 interrupt-parent = <&mpic>;
  99                                 interrupts = <5 1>;
 100                                 reg = <1>;
 101                                 device_type = "ethernet-phy";
 102                         };
 103                         phy3: ethernet-phy@3 {
 104                                 interrupt-parent = <&mpic>;
 105                                 interrupts = <7 1>;
 106                                 reg = <3>;
 107                                 device_type = "ethernet-phy";
 108                         };
 109                 };
 110
 111                 enet0: ethernet@24000 {
 112                         cell-index = <0>;
 113                         device_type = "network";
 114                         model = "TSEC";
 115                         compatible = "gianfar";
 116                         reg = <24000 1000>;
 117                         local-mac-address = [ 00 00 00 00 00 00 ];
 118                         interrupts = <1d 2 1e 2 22 2>;
 119                         interrupt-parent = <&mpic>;
 120                         phy-handle = <&phy0>;
 121                 };
 122
 123                 enet1: ethernet@25000 {
 124                         cell-index = <1>;
 125                         device_type = "network";
 126                         model = "TSEC";
 127                         compatible = "gianfar";
 128                         reg = <25000 1000>;
 129                         local-mac-address = [ 00 00 00 00 00 00 ];
 130                         interrupts = <23 2 24 2 28 2>;
 131                         interrupt-parent = <&mpic>;
 132                         phy-handle = <&phy1>;
 133                 };
 134
 135                 enet2: ethernet@26000 {
 136                         cell-index = <2>;
 137                         device_type = "network";
 138                         model = "FEC";
 139                         compatible = "gianfar";
 140                         reg = <26000 1000>;
 141                         local-mac-address = [ 00 00 00 00 00 00 ];
 142                         interrupts = <29 2>;
 143                         interrupt-parent = <&mpic>;
 144                         phy-handle = <&phy3>;
 145                 };
 146
 147                 serial0: serial@4500 {
 148                         cell-index = <0>;
 149                         device_type = "serial";
 150                         compatible = "ns16550";
 151                         reg = <4500 100>;       // reg base, size
 152                         clock-frequency = <0>;  // should we fill in in uboot?
 153                         interrupts = <2a 2>;
 154                         interrupt-parent = <&mpic>;
 155                 };
 156
 157                 serial1: serial@4600 {
 158                         cell-index = <1>;
 159                         device_type = "serial";
 160                         compatible = "ns16550";
 161                         reg = <4600 100>;       // reg base, size
 162                         clock-frequency = <0>;  // should we fill in in uboot?
 163                         interrupts = <2a 2>;
 164                         interrupt-parent = <&mpic>;
 165                 };
 166                 mpic: pic@40000 {
 167                         clock-frequency = <0>;
 168                         interrupt-controller;
 169                         #address-cells = <0>;
 170                         #interrupt-cells = <2>;
 171                         reg = <40000 40000>;
 172                         compatible = "chrp,open-pic";
 173                         device_type = "open-pic";
 174                         big-endian;
 175                 };
 176         };
 177
 178         pci0: pci@e0008000 {
 179                 cell-index = <0>;
 180                 interrupt-map-mask = <f800 0 0 7>;
 181                 interrupt-map = <
 182
 183                         /* IDSEL 0x02 */
 184                         1000 0 0 1 &mpic 1 1
 185                         1000 0 0 2 &mpic 2 1
 186                         1000 0 0 3 &mpic 3 1
 187                         1000 0 0 4 &mpic 4 1
 188
 189                         /* IDSEL 0x03 */
 190                         1800 0 0 1 &mpic 4 1
 191                         1800 0 0 2 &mpic 1 1
 192                         1800 0 0 3 &mpic 2 1
 193                         1800 0 0 4 &mpic 3 1
 194
 195                         /* IDSEL 0x04 */
 196                         2000 0 0 1 &mpic 3 1
 197                         2000 0 0 2 &mpic 4 1
 198                         2000 0 0 3 &mpic 1 1
 199                         2000 0 0 4 &mpic 2 1
 200
 201                         /* IDSEL 0x05 */
 202                         2800 0 0 1 &mpic 2 1
 203                         2800 0 0 2 &mpic 3 1
 204                         2800 0 0 3 &mpic 4 1
 205                         2800 0 0 4 &mpic 1 1
 206
 207                         /* IDSEL 0x0c */
 208                         6000 0 0 1 &mpic 1 1
 209                         6000 0 0 2 &mpic 2 1
 210                         6000 0 0 3 &mpic 3 1
 211                         6000 0 0 4 &mpic 4 1
 212
 213                         /* IDSEL 0x0d */
 214                         6800 0 0 1 &mpic 4 1
 215                         6800 0 0 2 &mpic 1 1
 216                         6800 0 0 3 &mpic 2 1
 217                         6800 0 0 4 &mpic 3 1
 218
 219                         /* IDSEL 0x0e */
 220                         7000 0 0 1 &mpic 3 1
 221                         7000 0 0 2 &mpic 4 1
 222                         7000 0 0 3 &mpic 1 1
 223                         7000 0 0 4 &mpic 2 1
 224
 225                         /* IDSEL 0x0f */
 226                         7800 0 0 1 &mpic 2 1
 227                         7800 0 0 2 &mpic 3 1
 228                         7800 0 0 3 &mpic 4 1
 229                         7800 0 0 4 &mpic 1 1
 230
 231                         /* IDSEL 0x12 */
 232                         9000 0 0 1 &mpic 1 1
 233                         9000 0 0 2 &mpic 2 1
 234                         9000 0 0 3 &mpic 3 1
 235                         9000 0 0 4 &mpic 4 1
 236
 237                         /* IDSEL 0x13 */
 238                         9800 0 0 1 &mpic 4 1
 239                         9800 0 0 2 &mpic 1 1
 240                         9800 0 0 3 &mpic 2 1
 241                         9800 0 0 4 &mpic 3 1
 242
 243                         /* IDSEL 0x14 */
 244                         a000 0 0 1 &mpic 3 1
 245                         a000 0 0 2 &mpic 4 1
 246                         a000 0 0 3 &mpic 1 1
 247                         a000 0 0 4 &mpic 2 1
 248
 249                         /* IDSEL 0x15 */
 250                         a800 0 0 1 &mpic 2 1
 251                         a800 0 0 2 &mpic 3 1
 252                         a800 0 0 3 &mpic 4 1
 253                         a800 0 0 4 &mpic 1 1>;
 254                 interrupt-parent = <&mpic>;
 255                 interrupts = <18 2>;
 256                 bus-range = <0 0>;
 257                 ranges = <02000000 0 80000000 80000000 0 20000000
 258                           01000000 0 00000000 e2000000 0 00100000>;
 259                 clock-frequency = <3f940aa>;
 260                 #interrupt-cells = <1>;
 261                 #size-cells = <2>;
 262                 #address-cells = <3>;
 263                 reg = <e0008000 1000>;
 264                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
 265                 device_type = "pci";
 266         };
 267 };