[POWERPC] Enable RTC for Ebony and Walnut (v2)
[linux-2.6] / arch / powerpc / boot / dts / mpc8555cds.dts
1 /*
2  * MPC8555 CDS Device Tree Source
3  *
4  * Copyright 2006 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12
13 / {
14         model = "MPC8555CDS";
15         compatible = "MPC8555CDS", "MPC85xxCDS";
16         #address-cells = <1>;
17         #size-cells = <1>;
18
19         aliases {
20                 ethernet0 = &enet0;
21                 ethernet1 = &enet1;
22                 serial0 = &serial0;
23                 serial1 = &serial1;
24                 pci0 = &pci0;
25                 pci1 = &pci1;
26         };
27
28         cpus {
29                 #address-cells = <1>;
30                 #size-cells = <0>;
31
32                 PowerPC,8555@0 {
33                         device_type = "cpu";
34                         reg = <0>;
35                         d-cache-line-size = <20>;       // 32 bytes
36                         i-cache-line-size = <20>;       // 32 bytes
37                         d-cache-size = <8000>;          // L1, 32K
38                         i-cache-size = <8000>;          // L1, 32K
39                         timebase-frequency = <0>;       //  33 MHz, from uboot
40                         bus-frequency = <0>;    // 166 MHz
41                         clock-frequency = <0>;  // 825 MHz, from uboot
42                 };
43         };
44
45         memory {
46                 device_type = "memory";
47                 reg = <00000000 08000000>;      // 128M at 0x0
48         };
49
50         soc8555@e0000000 {
51                 #address-cells = <1>;
52                 #size-cells = <1>;
53                 device_type = "soc";
54                 ranges = <0 e0000000 00100000>;
55                 reg = <e0000000 00001000>;      // CCSRBAR 1M
56                 bus-frequency = <0>;
57
58                 memory-controller@2000 {
59                         compatible = "fsl,8555-memory-controller";
60                         reg = <2000 1000>;
61                         interrupt-parent = <&mpic>;
62                         interrupts = <12 2>;
63                 };
64
65                 l2-cache-controller@20000 {
66                         compatible = "fsl,8555-l2-cache-controller";
67                         reg = <20000 1000>;
68                         cache-line-size = <20>; // 32 bytes
69                         cache-size = <40000>;   // L2, 256K
70                         interrupt-parent = <&mpic>;
71                         interrupts = <10 2>;
72                 };
73
74                 i2c@3000 {
75                         #address-cells = <1>;
76                         #size-cells = <0>;
77                         cell-index = <0>;
78                         compatible = "fsl-i2c";
79                         reg = <3000 100>;
80                         interrupts = <2b 2>;
81                         interrupt-parent = <&mpic>;
82                         dfsrr;
83                 };
84
85                 mdio@24520 {
86                         #address-cells = <1>;
87                         #size-cells = <0>;
88                         compatible = "fsl,gianfar-mdio";
89                         reg = <24520 20>;
90
91                         phy0: ethernet-phy@0 {
92                                 interrupt-parent = <&mpic>;
93                                 interrupts = <5 1>;
94                                 reg = <0>;
95                                 device_type = "ethernet-phy";
96                         };
97                         phy1: ethernet-phy@1 {
98                                 interrupt-parent = <&mpic>;
99                                 interrupts = <5 1>;
100                                 reg = <1>;
101                                 device_type = "ethernet-phy";
102                         };
103                 };
104
105                 enet0: ethernet@24000 {
106                         cell-index = <0>;
107                         device_type = "network";
108                         model = "TSEC";
109                         compatible = "gianfar";
110                         reg = <24000 1000>;
111                         local-mac-address = [ 00 00 00 00 00 00 ];
112                         interrupts = <1d 2 1e 2 22 2>;
113                         interrupt-parent = <&mpic>;
114                         phy-handle = <&phy0>;
115                 };
116
117                 enet1: ethernet@25000 {
118                         cell-index = <1>;
119                         device_type = "network";
120                         model = "TSEC";
121                         compatible = "gianfar";
122                         reg = <25000 1000>;
123                         local-mac-address = [ 00 00 00 00 00 00 ];
124                         interrupts = <23 2 24 2 28 2>;
125                         interrupt-parent = <&mpic>;
126                         phy-handle = <&phy1>;
127                 };
128
129                 serial0: serial@4500 {
130                         cell-index = <0>;
131                         device_type = "serial";
132                         compatible = "ns16550";
133                         reg = <4500 100>;       // reg base, size
134                         clock-frequency = <0>;  // should we fill in in uboot?
135                         interrupts = <2a 2>;
136                         interrupt-parent = <&mpic>;
137                 };
138
139                 serial1: serial@4600 {
140                         cell-index = <1>;
141                         device_type = "serial";
142                         compatible = "ns16550";
143                         reg = <4600 100>;       // reg base, size
144                         clock-frequency = <0>;  // should we fill in in uboot?
145                         interrupts = <2a 2>;
146                         interrupt-parent = <&mpic>;
147                 };
148
149                 mpic: pic@40000 {
150                         clock-frequency = <0>;
151                         interrupt-controller;
152                         #address-cells = <0>;
153                         #interrupt-cells = <2>;
154                         reg = <40000 40000>;
155                         compatible = "chrp,open-pic";
156                         device_type = "open-pic";
157                         big-endian;
158                 };
159
160                 cpm@919c0 {
161                         #address-cells = <1>;
162                         #size-cells = <1>;
163                         compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
164                         reg = <919c0 30>;
165                         ranges;
166
167                         muram@80000 {
168                                 #address-cells = <1>;
169                                 #size-cells = <1>;
170                                 ranges = <0 80000 10000>;
171
172                                 data@0 {
173                                         compatible = "fsl,cpm-muram-data";
174                                         reg = <0 2000 9000 1000>;
175                                 };
176                         };
177
178                         brg@919f0 {
179                                 compatible = "fsl,mpc8555-brg",
180                                              "fsl,cpm2-brg",
181                                              "fsl,cpm-brg";
182                                 reg = <919f0 10 915f0 10>;
183                         };
184
185                         cpmpic: pic@90c00 {
186                                 interrupt-controller;
187                                 #address-cells = <0>;
188                                 #interrupt-cells = <2>;
189                                 interrupts = <2e 2>;
190                                 interrupt-parent = <&mpic>;
191                                 reg = <90c00 80>;
192                                 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
193                         };
194                 };
195         };
196
197         pci0: pci@e0008000 {
198                 cell-index = <0>;
199                 interrupt-map-mask = <1f800 0 0 7>;
200                 interrupt-map = <
201
202                         /* IDSEL 0x10 */
203                         08000 0 0 1 &mpic 0 1
204                         08000 0 0 2 &mpic 1 1
205                         08000 0 0 3 &mpic 2 1
206                         08000 0 0 4 &mpic 3 1
207
208                         /* IDSEL 0x11 */
209                         08800 0 0 1 &mpic 0 1
210                         08800 0 0 2 &mpic 1 1
211                         08800 0 0 3 &mpic 2 1
212                         08800 0 0 4 &mpic 3 1
213
214                         /* IDSEL 0x12 (Slot 1) */
215                         09000 0 0 1 &mpic 0 1
216                         09000 0 0 2 &mpic 1 1
217                         09000 0 0 3 &mpic 2 1
218                         09000 0 0 4 &mpic 3 1
219
220                         /* IDSEL 0x13 (Slot 2) */
221                         09800 0 0 1 &mpic 1 1
222                         09800 0 0 2 &mpic 2 1
223                         09800 0 0 3 &mpic 3 1
224                         09800 0 0 4 &mpic 0 1
225
226                         /* IDSEL 0x14 (Slot 3) */
227                         0a000 0 0 1 &mpic 2 1
228                         0a000 0 0 2 &mpic 3 1
229                         0a000 0 0 3 &mpic 0 1
230                         0a000 0 0 4 &mpic 1 1
231
232                         /* IDSEL 0x15 (Slot 4) */
233                         0a800 0 0 1 &mpic 3 1
234                         0a800 0 0 2 &mpic 0 1
235                         0a800 0 0 3 &mpic 1 1
236                         0a800 0 0 4 &mpic 2 1
237
238                         /* Bus 1 (Tundra Bridge) */
239                         /* IDSEL 0x12 (ISA bridge) */
240                         19000 0 0 1 &mpic 0 1
241                         19000 0 0 2 &mpic 1 1
242                         19000 0 0 3 &mpic 2 1
243                         19000 0 0 4 &mpic 3 1>;
244                 interrupt-parent = <&mpic>;
245                 interrupts = <18 2>;
246                 bus-range = <0 0>;
247                 ranges = <02000000 0 80000000 80000000 0 20000000
248                           01000000 0 00000000 e2000000 0 00100000>;
249                 clock-frequency = <3f940aa>;
250                 #interrupt-cells = <1>;
251                 #size-cells = <2>;
252                 #address-cells = <3>;
253                 reg = <e0008000 1000>;
254                 compatible = "fsl,mpc8540-pci";
255                 device_type = "pci";
256
257                 i8259@19000 {
258                         interrupt-controller;
259                         device_type = "interrupt-controller";
260                         reg = <19000 0 0 0 1>;
261                         #address-cells = <0>;
262                         #interrupt-cells = <2>;
263                         compatible = "chrp,iic";
264                         interrupts = <1>;
265                         interrupt-parent = <&pci0>;
266                 };
267         };
268
269         pci1: pci@e0009000 {
270                 cell-index = <1>;
271                 interrupt-map-mask = <f800 0 0 7>;
272                 interrupt-map = <
273
274                         /* IDSEL 0x15 */
275                         a800 0 0 1 &mpic b 1
276                         a800 0 0 2 &mpic b 1
277                         a800 0 0 3 &mpic b 1
278                         a800 0 0 4 &mpic b 1>;
279                 interrupt-parent = <&mpic>;
280                 interrupts = <19 2>;
281                 bus-range = <0 0>;
282                 ranges = <02000000 0 a0000000 a0000000 0 20000000
283                           01000000 0 00000000 e3000000 0 00100000>;
284                 clock-frequency = <3f940aa>;
285                 #interrupt-cells = <1>;
286                 #size-cells = <2>;
287                 #address-cells = <3>;
288                 reg = <e0009000 1000>;
289                 compatible = "fsl,mpc8540-pci";
290                 device_type = "pci";
291         };
292 };