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   1 /*
   2  * drivers/net/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  *
  12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
  13  * Copyright (c) 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through platform_device.  Structures which
  29  *  define the configuration needed by the board are defined in a
  30  *  board structure in arch/ppc/platforms (though I do not
  31  *  discount the possibility that other architectures could one
  32  *  day be supported.
  33  *
  34  *  The Gianfar Ethernet Controller uses a ring of buffer
  35  *  descriptors.  The beginning is indicated by a register
  36  *  pointing to the physical address of the start of the ring.
  37  *  The end is determined by a "wrap" bit being set in the
  38  *  last descriptor of the ring.
  39  *
  40  *  When a packet is received, the RXF bit in the
  41  *  IEVENT register is set, triggering an interrupt when the
  42  *  corresponding bit in the IMASK register is also set (if
  43  *  interrupt coalescing is active, then the interrupt may not
  44  *  happen immediately, but will wait until either a set number
  45  *  of frames or amount of time have passed).  In NAPI, the
  46  *  interrupt handler will signal there is work to be done, and
  47  *  exit. This method will start at the last known empty
  48  *  descriptor, and process every subsequent descriptor until there
  49  *  are none left with data (NAPI will stop after a set number of
  50  *  packets to give time to other tasks, but will eventually
  51  *  process all the packets).  The data arrives inside a
  52  *  pre-allocated skb, and so after the skb is passed up to the
  53  *  stack, a new skb must be allocated, and the address field in
  54  *  the buffer descriptor must be updated to indicate this new
  55  *  skb.
  56  *
  57  *  When the kernel requests that a packet be transmitted, the
  58  *  driver starts where it left off last time, and points the
  59  *  descriptor at the buffer which was passed in.  The driver
  60  *  then informs the DMA engine that there are packets ready to
  61  *  be transmitted.  Once the controller is finished transmitting
  62  *  the packet, an interrupt may be triggered (under the same
  63  *  conditions as for reception, but depending on the TXF bit).
  64  *  The driver then cleans up the buffer.
  65  */
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/init.h>
  74 #include <linux/delay.h>
  75 #include <linux/netdevice.h>
  76 #include <linux/etherdevice.h>
  77 #include <linux/skbuff.h>
  78 #include <linux/if_vlan.h>
  79 #include <linux/spinlock.h>
  80 #include <linux/mm.h>
  81 #include <linux/platform_device.h>
  82 #include <linux/ip.h>
  83 #include <linux/tcp.h>
  84 #include <linux/udp.h>
  85 #include <linux/in.h>
  86
  87 #include <asm/io.h>
  88 #include <asm/irq.h>
  89 #include <asm/uaccess.h>
  90 #include <linux/module.h>
  91 #include <linux/dma-mapping.h>
  92 #include <linux/crc32.h>
  93 #include <linux/mii.h>
  94 #include <linux/phy.h>
  95
  96 #include "gianfar.h"
  97 #include "gianfar_mii.h"
  98
  99 #define TX_TIMEOUT      (1*HZ)
 100 #undef BRIEF_GFAR_ERRORS
 101 #undef VERBOSE_GFAR_ERRORS
 102
 103 const char gfar_driver_name[] = "Gianfar Ethernet";
 104 const char gfar_driver_version[] = "1.3";
 105
 106 static int gfar_enet_open(struct net_device *dev);
 107 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 108 static void gfar_reset_task(struct work_struct *work);
 109 static void gfar_timeout(struct net_device *dev);
 110 static int gfar_close(struct net_device *dev);
 111 struct sk_buff *gfar_new_skb(struct net_device *dev);
 112 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
 113                 struct sk_buff *skb);
 114 static int gfar_set_mac_address(struct net_device *dev);
 115 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 116 static irqreturn_t gfar_error(int irq, void *dev_id);
 117 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 118 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 119 static void adjust_link(struct net_device *dev);
 120 static void init_registers(struct net_device *dev);
 121 static int init_phy(struct net_device *dev);
 122 static int gfar_probe(struct platform_device *pdev);
 123 static int gfar_remove(struct platform_device *pdev);
 124 static void free_skb_resources(struct gfar_private *priv);
 125 static void gfar_set_multi(struct net_device *dev);
 126 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 127 static void gfar_configure_serdes(struct net_device *dev);
 128 static int gfar_poll(struct napi_struct *napi, int budget);
 129 #ifdef CONFIG_NET_POLL_CONTROLLER
 130 static void gfar_netpoll(struct net_device *dev);
 131 #endif
 132 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
 133 static int gfar_clean_tx_ring(struct net_device *dev);
 134 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
 135 static void gfar_vlan_rx_register(struct net_device *netdev,
 136                                 struct vlan_group *grp);
 137 void gfar_halt(struct net_device *dev);
 138 static void gfar_halt_nodisable(struct net_device *dev);
 139 void gfar_start(struct net_device *dev);
 140 static void gfar_clear_exact_match(struct net_device *dev);
 141 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
 142
 143 extern const struct ethtool_ops gfar_ethtool_ops;
 144
 145 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 146 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 147 MODULE_LICENSE("GPL");
 148
 149 /* Returns 1 if incoming frames use an FCB */
 150 static inline int gfar_uses_fcb(struct gfar_private *priv)
 151 {
 152         return (priv->vlan_enable || priv->rx_csum_enable);
 153 }
 154
 155 /* Set up the ethernet device structure, private data,
 156  * and anything else we need before we start */
 157 static int gfar_probe(struct platform_device *pdev)
 158 {
 159         u32 tempval;
 160         struct net_device *dev = NULL;
 161         struct gfar_private *priv = NULL;
 162         struct gianfar_platform_data *einfo;
 163         struct resource *r;
 164         int err = 0, irq;
 165         DECLARE_MAC_BUF(mac);
 166
 167         einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
 168
 169         if (NULL == einfo) {
 170                 printk(KERN_ERR "gfar %d: Missing additional data!\n",
 171                        pdev->id);
 172
 173                 return -ENODEV;
 174         }
 175
 176         /* Create an ethernet device instance */
 177         dev = alloc_etherdev(sizeof (*priv));
 178
 179         if (NULL == dev)
 180                 return -ENOMEM;
 181
 182         priv = netdev_priv(dev);
 183         priv->dev = dev;
 184
 185         /* Set the info in the priv to the current info */
 186         priv->einfo = einfo;
 187
 188         /* fill out IRQ fields */
 189         if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 190                 irq = platform_get_irq_byname(pdev, "tx");
 191                 if (irq < 0)
 192                         goto regs_fail;
 193                 priv->interruptTransmit = irq;
 194
 195                 irq = platform_get_irq_byname(pdev, "rx");
 196                 if (irq < 0)
 197                         goto regs_fail;
 198                 priv->interruptReceive = irq;
 199
 200                 irq = platform_get_irq_byname(pdev, "error");
 201                 if (irq < 0)
 202                         goto regs_fail;
 203                 priv->interruptError = irq;
 204         } else {
 205                 irq = platform_get_irq(pdev, 0);
 206                 if (irq < 0)
 207                         goto regs_fail;
 208                 priv->interruptTransmit = irq;
 209         }
 210
 211         /* get a pointer to the register memory */
 212         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 213         priv->regs = ioremap(r->start, sizeof (struct gfar));
 214
 215         if (NULL == priv->regs) {
 216                 err = -ENOMEM;
 217                 goto regs_fail;
 218         }
 219
 220         spin_lock_init(&priv->txlock);
 221         spin_lock_init(&priv->rxlock);
 222         spin_lock_init(&priv->bflock);
 223         INIT_WORK(&priv->reset_task, gfar_reset_task);
 224
 225         platform_set_drvdata(pdev, dev);
 226
 227         /* Stop the DMA engine now, in case it was running before */
 228         /* (The firmware could have used it, and left it running). */
 229         /* To do this, we write Graceful Receive Stop and Graceful */
 230         /* Transmit Stop, and then wait until the corresponding bits */
 231         /* in IEVENT indicate the stops have completed. */
 232         tempval = gfar_read(&priv->regs->dmactrl);
 233         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 234         gfar_write(&priv->regs->dmactrl, tempval);
 235
 236         tempval = gfar_read(&priv->regs->dmactrl);
 237         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 238         gfar_write(&priv->regs->dmactrl, tempval);
 239
 240         while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
 241                 cpu_relax();
 242
 243         /* Reset MAC layer */
 244         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
 245
 246         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
 247         gfar_write(&priv->regs->maccfg1, tempval);
 248
 249         /* Initialize MACCFG2. */
 250         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
 251
 252         /* Initialize ECNTRL */
 253         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
 254
 255         /* Copy the station address into the dev structure, */
 256         memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
 257
 258         /* Set the dev->base_addr to the gfar reg region */
 259         dev->base_addr = (unsigned long) (priv->regs);
 260
 261         SET_NETDEV_DEV(dev, &pdev->dev);
 262
 263         /* Fill in the dev structure */
 264         dev->open = gfar_enet_open;
 265         dev->hard_start_xmit = gfar_start_xmit;
 266         dev->tx_timeout = gfar_timeout;
 267         dev->watchdog_timeo = TX_TIMEOUT;
 268         netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
 269 #ifdef CONFIG_NET_POLL_CONTROLLER
 270         dev->poll_controller = gfar_netpoll;
 271 #endif
 272         dev->stop = gfar_close;
 273         dev->change_mtu = gfar_change_mtu;
 274         dev->mtu = 1500;
 275         dev->set_multicast_list = gfar_set_multi;
 276
 277         dev->ethtool_ops = &gfar_ethtool_ops;
 278
 279         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
 280                 priv->rx_csum_enable = 1;
 281                 dev->features |= NETIF_F_IP_CSUM;
 282         } else
 283                 priv->rx_csum_enable = 0;
 284
 285         priv->vlgrp = NULL;
 286
 287         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
 288                 dev->vlan_rx_register = gfar_vlan_rx_register;
 289
 290                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
 291
 292                 priv->vlan_enable = 1;
 293         }
 294
 295         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
 296                 priv->extended_hash = 1;
 297                 priv->hash_width = 9;
 298
 299                 priv->hash_regs[0] = &priv->regs->igaddr0;
 300                 priv->hash_regs[1] = &priv->regs->igaddr1;
 301                 priv->hash_regs[2] = &priv->regs->igaddr2;
 302                 priv->hash_regs[3] = &priv->regs->igaddr3;
 303                 priv->hash_regs[4] = &priv->regs->igaddr4;
 304                 priv->hash_regs[5] = &priv->regs->igaddr5;
 305                 priv->hash_regs[6] = &priv->regs->igaddr6;
 306                 priv->hash_regs[7] = &priv->regs->igaddr7;
 307                 priv->hash_regs[8] = &priv->regs->gaddr0;
 308                 priv->hash_regs[9] = &priv->regs->gaddr1;
 309                 priv->hash_regs[10] = &priv->regs->gaddr2;
 310                 priv->hash_regs[11] = &priv->regs->gaddr3;
 311                 priv->hash_regs[12] = &priv->regs->gaddr4;
 312                 priv->hash_regs[13] = &priv->regs->gaddr5;
 313                 priv->hash_regs[14] = &priv->regs->gaddr6;
 314                 priv->hash_regs[15] = &priv->regs->gaddr7;
 315
 316         } else {
 317                 priv->extended_hash = 0;
 318                 priv->hash_width = 8;
 319
 320                 priv->hash_regs[0] = &priv->regs->gaddr0;
 321                 priv->hash_regs[1] = &priv->regs->gaddr1;
 322                 priv->hash_regs[2] = &priv->regs->gaddr2;
 323                 priv->hash_regs[3] = &priv->regs->gaddr3;
 324                 priv->hash_regs[4] = &priv->regs->gaddr4;
 325                 priv->hash_regs[5] = &priv->regs->gaddr5;
 326                 priv->hash_regs[6] = &priv->regs->gaddr6;
 327                 priv->hash_regs[7] = &priv->regs->gaddr7;
 328         }
 329
 330         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
 331                 priv->padding = DEFAULT_PADDING;
 332         else
 333                 priv->padding = 0;
 334
 335         if (dev->features & NETIF_F_IP_CSUM)
 336                 dev->hard_header_len += GMAC_FCB_LEN;
 337
 338         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
 339         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
 340         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
 341
 342         priv->txcoalescing = DEFAULT_TX_COALESCE;
 343         priv->txcount = DEFAULT_TXCOUNT;
 344         priv->txtime = DEFAULT_TXTIME;
 345         priv->rxcoalescing = DEFAULT_RX_COALESCE;
 346         priv->rxcount = DEFAULT_RXCOUNT;
 347         priv->rxtime = DEFAULT_RXTIME;
 348
 349         /* Enable most messages by default */
 350         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
 351
 352         /* Carrier starts down, phylib will bring it up */
 353         netif_carrier_off(dev);
 354
 355         err = register_netdev(dev);
 356
 357         if (err) {
 358                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
 359                                 dev->name);
 360                 goto register_fail;
 361         }
 362
 363         /* Create all the sysfs files */
 364         gfar_init_sysfs(dev);
 365
 366         /* Print out the device info */
 367         printk(KERN_INFO DEVICE_NAME "%s\n",
 368                dev->name, print_mac(mac, dev->dev_addr));
 369
 370         /* Even more device info helps when determining which kernel */
 371         /* provided which set of benchmarks. */
 372         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
 373         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
 374                dev->name, priv->rx_ring_size, priv->tx_ring_size);
 375
 376         return 0;
 377
 378 register_fail:
 379         iounmap(priv->regs);
 380 regs_fail:
 381         free_netdev(dev);
 382         return err;
 383 }
 384
 385 static int gfar_remove(struct platform_device *pdev)
 386 {
 387         struct net_device *dev = platform_get_drvdata(pdev);
 388         struct gfar_private *priv = netdev_priv(dev);
 389
 390         platform_set_drvdata(pdev, NULL);
 391
 392         iounmap(priv->regs);
 393         free_netdev(dev);
 394
 395         return 0;
 396 }
 397
 398 #ifdef CONFIG_PM
 399 static int gfar_suspend(struct platform_device *pdev, pm_message_t state)
 400 {
 401         struct net_device *dev = platform_get_drvdata(pdev);
 402         struct gfar_private *priv = netdev_priv(dev);
 403         unsigned long flags;
 404         u32 tempval;
 405
 406         int magic_packet = priv->wol_en &&
 407                 (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 408
 409         netif_device_detach(dev);
 410
 411         if (netif_running(dev)) {
 412                 spin_lock_irqsave(&priv->txlock, flags);
 413                 spin_lock(&priv->rxlock);
 414
 415                 gfar_halt_nodisable(dev);
 416
 417                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
 418                 tempval = gfar_read(&priv->regs->maccfg1);
 419
 420                 tempval &= ~MACCFG1_TX_EN;
 421
 422                 if (!magic_packet)
 423                         tempval &= ~MACCFG1_RX_EN;
 424
 425                 gfar_write(&priv->regs->maccfg1, tempval);
 426
 427                 spin_unlock(&priv->rxlock);
 428                 spin_unlock_irqrestore(&priv->txlock, flags);
 429
 430                 napi_disable(&priv->napi);
 431
 432                 if (magic_packet) {
 433                         /* Enable interrupt on Magic Packet */
 434                         gfar_write(&priv->regs->imask, IMASK_MAG);
 435
 436                         /* Enable Magic Packet mode */
 437                         tempval = gfar_read(&priv->regs->maccfg2);
 438                         tempval |= MACCFG2_MPEN;
 439                         gfar_write(&priv->regs->maccfg2, tempval);
 440                 } else {
 441                         phy_stop(priv->phydev);
 442                 }
 443         }
 444
 445         return 0;
 446 }
 447
 448 static int gfar_resume(struct platform_device *pdev)
 449 {
 450         struct net_device *dev = platform_get_drvdata(pdev);
 451         struct gfar_private *priv = netdev_priv(dev);
 452         unsigned long flags;
 453         u32 tempval;
 454         int magic_packet = priv->wol_en &&
 455                 (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 456
 457         if (!netif_running(dev)) {
 458                 netif_device_attach(dev);
 459                 return 0;
 460         }
 461
 462         if (!magic_packet && priv->phydev)
 463                 phy_start(priv->phydev);
 464
 465         /* Disable Magic Packet mode, in case something
 466          * else woke us up.
 467          */
 468
 469         spin_lock_irqsave(&priv->txlock, flags);
 470         spin_lock(&priv->rxlock);
 471
 472         tempval = gfar_read(&priv->regs->maccfg2);
 473         tempval &= ~MACCFG2_MPEN;
 474         gfar_write(&priv->regs->maccfg2, tempval);
 475
 476         gfar_start(dev);
 477
 478         spin_unlock(&priv->rxlock);
 479         spin_unlock_irqrestore(&priv->txlock, flags);
 480
 481         netif_device_attach(dev);
 482
 483         napi_enable(&priv->napi);
 484
 485         return 0;
 486 }
 487 #else
 488 #define gfar_suspend NULL
 489 #define gfar_resume NULL
 490 #endif
 491
 492 /* Reads the controller's registers to determine what interface
 493  * connects it to the PHY.
 494  */
 495 static phy_interface_t gfar_get_interface(struct net_device *dev)
 496 {
 497         struct gfar_private *priv = netdev_priv(dev);
 498         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
 499
 500         if (ecntrl & ECNTRL_SGMII_MODE)
 501                 return PHY_INTERFACE_MODE_SGMII;
 502
 503         if (ecntrl & ECNTRL_TBI_MODE) {
 504                 if (ecntrl & ECNTRL_REDUCED_MODE)
 505                         return PHY_INTERFACE_MODE_RTBI;
 506                 else
 507                         return PHY_INTERFACE_MODE_TBI;
 508         }
 509
 510         if (ecntrl & ECNTRL_REDUCED_MODE) {
 511                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
 512                         return PHY_INTERFACE_MODE_RMII;
 513                 else {
 514                         phy_interface_t interface = priv->einfo->interface;
 515
 516                         /*
 517                          * This isn't autodetected right now, so it must
 518                          * be set by the device tree or platform code.
 519                          */
 520                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
 521                                 return PHY_INTERFACE_MODE_RGMII_ID;
 522
 523                         return PHY_INTERFACE_MODE_RGMII;
 524                 }
 525         }
 526
 527         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
 528                 return PHY_INTERFACE_MODE_GMII;
 529
 530         return PHY_INTERFACE_MODE_MII;
 531 }
 532
 533
 534 /* Initializes driver's PHY state, and attaches to the PHY.
 535  * Returns 0 on success.
 536  */
 537 static int init_phy(struct net_device *dev)
 538 {
 539         struct gfar_private *priv = netdev_priv(dev);
 540         uint gigabit_support =
 541                 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
 542                 SUPPORTED_1000baseT_Full : 0;
 543         struct phy_device *phydev;
 544         char phy_id[BUS_ID_SIZE];
 545         phy_interface_t interface;
 546
 547         priv->oldlink = 0;
 548         priv->oldspeed = 0;
 549         priv->oldduplex = -1;
 550
 551         snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
 552
 553         interface = gfar_get_interface(dev);
 554
 555         phydev = phy_connect(dev, phy_id, &adjust_link, 0, interface);
 556
 557         if (interface == PHY_INTERFACE_MODE_SGMII)
 558                 gfar_configure_serdes(dev);
 559
 560         if (IS_ERR(phydev)) {
 561                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
 562                 return PTR_ERR(phydev);
 563         }
 564
 565         /* Remove any features not supported by the controller */
 566         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
 567         phydev->advertising = phydev->supported;
 568
 569         priv->phydev = phydev;
 570
 571         return 0;
 572 }
 573
 574 /*
 575  * Initialize TBI PHY interface for communicating with the
 576  * SERDES lynx PHY on the chip.  We communicate with this PHY
 577  * through the MDIO bus on each controller, treating it as a
 578  * "normal" PHY at the address found in the TBIPA register.  We assume
 579  * that the TBIPA register is valid.  Either the MDIO bus code will set
 580  * it to a value that doesn't conflict with other PHYs on the bus, or the
 581  * value doesn't matter, as there are no other PHYs on the bus.
 582  */
 583 static void gfar_configure_serdes(struct net_device *dev)
 584 {
 585         struct gfar_private *priv = netdev_priv(dev);
 586         struct gfar_mii __iomem *regs =
 587                         (void __iomem *)&priv->regs->gfar_mii_regs;
 588         int tbipa = gfar_read(&priv->regs->tbipa);
 589
 590         /* Single clk mode, mii mode off(for serdes communication) */
 591         gfar_local_mdio_write(regs, tbipa, MII_TBICON, TBICON_CLK_SELECT);
 592
 593         gfar_local_mdio_write(regs, tbipa, MII_ADVERTISE,
 594                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
 595                         ADVERTISE_1000XPSE_ASYM);
 596
 597         gfar_local_mdio_write(regs, tbipa, MII_BMCR, BMCR_ANENABLE |
 598                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
 599 }
 600
 601 static void init_registers(struct net_device *dev)
 602 {
 603         struct gfar_private *priv = netdev_priv(dev);
 604
 605         /* Clear IEVENT */
 606         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
 607
 608         /* Initialize IMASK */
 609         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
 610
 611         /* Init hash registers to zero */
 612         gfar_write(&priv->regs->igaddr0, 0);
 613         gfar_write(&priv->regs->igaddr1, 0);
 614         gfar_write(&priv->regs->igaddr2, 0);
 615         gfar_write(&priv->regs->igaddr3, 0);
 616         gfar_write(&priv->regs->igaddr4, 0);
 617         gfar_write(&priv->regs->igaddr5, 0);
 618         gfar_write(&priv->regs->igaddr6, 0);
 619         gfar_write(&priv->regs->igaddr7, 0);
 620
 621         gfar_write(&priv->regs->gaddr0, 0);
 622         gfar_write(&priv->regs->gaddr1, 0);
 623         gfar_write(&priv->regs->gaddr2, 0);
 624         gfar_write(&priv->regs->gaddr3, 0);
 625         gfar_write(&priv->regs->gaddr4, 0);
 626         gfar_write(&priv->regs->gaddr5, 0);
 627         gfar_write(&priv->regs->gaddr6, 0);
 628         gfar_write(&priv->regs->gaddr7, 0);
 629
 630         /* Zero out the rmon mib registers if it has them */
 631         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
 632                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
 633
 634                 /* Mask off the CAM interrupts */
 635                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
 636                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
 637         }
 638
 639         /* Initialize the max receive buffer length */
 640         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
 641
 642         /* Initialize the Minimum Frame Length Register */
 643         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
 644 }
 645
 646
 647 /* Halt the receive and transmit queues */
 648 static void gfar_halt_nodisable(struct net_device *dev)
 649 {
 650         struct gfar_private *priv = netdev_priv(dev);
 651         struct gfar __iomem *regs = priv->regs;
 652         u32 tempval;
 653
 654         /* Mask all interrupts */
 655         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 656
 657         /* Clear all interrupts */
 658         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 659
 660         /* Stop the DMA, and wait for it to stop */
 661         tempval = gfar_read(&priv->regs->dmactrl);
 662         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
 663             != (DMACTRL_GRS | DMACTRL_GTS)) {
 664                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 665                 gfar_write(&priv->regs->dmactrl, tempval);
 666
 667                 while (!(gfar_read(&priv->regs->ievent) &
 668                          (IEVENT_GRSC | IEVENT_GTSC)))
 669                         cpu_relax();
 670         }
 671 }
 672
 673 /* Halt the receive and transmit queues */
 674 void gfar_halt(struct net_device *dev)
 675 {
 676         struct gfar_private *priv = netdev_priv(dev);
 677         struct gfar __iomem *regs = priv->regs;
 678         u32 tempval;
 679
 680         gfar_halt_nodisable(dev);
 681
 682         /* Disable Rx and Tx */
 683         tempval = gfar_read(&regs->maccfg1);
 684         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
 685         gfar_write(&regs->maccfg1, tempval);
 686 }
 687
 688 void stop_gfar(struct net_device *dev)
 689 {
 690         struct gfar_private *priv = netdev_priv(dev);
 691         struct gfar __iomem *regs = priv->regs;
 692         unsigned long flags;
 693
 694         phy_stop(priv->phydev);
 695
 696         /* Lock it down */
 697         spin_lock_irqsave(&priv->txlock, flags);
 698         spin_lock(&priv->rxlock);
 699
 700         gfar_halt(dev);
 701
 702         spin_unlock(&priv->rxlock);
 703         spin_unlock_irqrestore(&priv->txlock, flags);
 704
 705         /* Free the IRQs */
 706         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 707                 free_irq(priv->interruptError, dev);
 708                 free_irq(priv->interruptTransmit, dev);
 709                 free_irq(priv->interruptReceive, dev);
 710         } else {
 711                 free_irq(priv->interruptTransmit, dev);
 712         }
 713
 714         free_skb_resources(priv);
 715
 716         dma_free_coherent(&dev->dev,
 717                         sizeof(struct txbd8)*priv->tx_ring_size
 718                         + sizeof(struct rxbd8)*priv->rx_ring_size,
 719                         priv->tx_bd_base,
 720                         gfar_read(&regs->tbase0));
 721 }
 722
 723 /* If there are any tx skbs or rx skbs still around, free them.
 724  * Then free tx_skbuff and rx_skbuff */
 725 static void free_skb_resources(struct gfar_private *priv)
 726 {
 727         struct rxbd8 *rxbdp;
 728         struct txbd8 *txbdp;
 729         int i;
 730
 731         /* Go through all the buffer descriptors and free their data buffers */
 732         txbdp = priv->tx_bd_base;
 733
 734         for (i = 0; i < priv->tx_ring_size; i++) {
 735
 736                 if (priv->tx_skbuff[i]) {
 737                         dma_unmap_single(&priv->dev->dev, txbdp->bufPtr,
 738                                         txbdp->length,
 739                                         DMA_TO_DEVICE);
 740                         dev_kfree_skb_any(priv->tx_skbuff[i]);
 741                         priv->tx_skbuff[i] = NULL;
 742                 }
 743
 744                 txbdp++;
 745         }
 746
 747         kfree(priv->tx_skbuff);
 748
 749         rxbdp = priv->rx_bd_base;
 750
 751         /* rx_skbuff is not guaranteed to be allocated, so only
 752          * free it and its contents if it is allocated */
 753         if(priv->rx_skbuff != NULL) {
 754                 for (i = 0; i < priv->rx_ring_size; i++) {
 755                         if (priv->rx_skbuff[i]) {
 756                                 dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr,
 757                                                 priv->rx_buffer_size,
 758                                                 DMA_FROM_DEVICE);
 759
 760                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
 761                                 priv->rx_skbuff[i] = NULL;
 762                         }
 763
 764                         rxbdp->status = 0;
 765                         rxbdp->length = 0;
 766                         rxbdp->bufPtr = 0;
 767
 768                         rxbdp++;
 769                 }
 770
 771                 kfree(priv->rx_skbuff);
 772         }
 773 }
 774
 775 void gfar_start(struct net_device *dev)
 776 {
 777         struct gfar_private *priv = netdev_priv(dev);
 778         struct gfar __iomem *regs = priv->regs;
 779         u32 tempval;
 780
 781         /* Enable Rx and Tx in MACCFG1 */
 782         tempval = gfar_read(&regs->maccfg1);
 783         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 784         gfar_write(&regs->maccfg1, tempval);
 785
 786         /* Initialize DMACTRL to have WWR and WOP */
 787         tempval = gfar_read(&priv->regs->dmactrl);
 788         tempval |= DMACTRL_INIT_SETTINGS;
 789         gfar_write(&priv->regs->dmactrl, tempval);
 790
 791         /* Make sure we aren't stopped */
 792         tempval = gfar_read(&priv->regs->dmactrl);
 793         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 794         gfar_write(&priv->regs->dmactrl, tempval);
 795
 796         /* Clear THLT/RHLT, so that the DMA starts polling now */
 797         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
 798         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
 799
 800         /* Unmask the interrupts we look for */
 801         gfar_write(&regs->imask, IMASK_DEFAULT);
 802 }
 803
 804 /* Bring the controller up and running */
 805 int startup_gfar(struct net_device *dev)
 806 {
 807         struct txbd8 *txbdp;
 808         struct rxbd8 *rxbdp;
 809         dma_addr_t addr = 0;
 810         unsigned long vaddr;
 811         int i;
 812         struct gfar_private *priv = netdev_priv(dev);
 813         struct gfar __iomem *regs = priv->regs;
 814         int err = 0;
 815         u32 rctrl = 0;
 816         u32 attrs = 0;
 817
 818         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 819
 820         /* Allocate memory for the buffer descriptors */
 821         vaddr = (unsigned long) dma_alloc_coherent(&dev->dev,
 822                         sizeof (struct txbd8) * priv->tx_ring_size +
 823                         sizeof (struct rxbd8) * priv->rx_ring_size,
 824                         &addr, GFP_KERNEL);
 825
 826         if (vaddr == 0) {
 827                 if (netif_msg_ifup(priv))
 828                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
 829                                         dev->name);
 830                 return -ENOMEM;
 831         }
 832
 833         priv->tx_bd_base = (struct txbd8 *) vaddr;
 834
 835         /* enet DMA only understands physical addresses */
 836         gfar_write(&regs->tbase0, addr);
 837
 838         /* Start the rx descriptor ring where the tx ring leaves off */
 839         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
 840         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
 841         priv->rx_bd_base = (struct rxbd8 *) vaddr;
 842         gfar_write(&regs->rbase0, addr);
 843
 844         /* Setup the skbuff rings */
 845         priv->tx_skbuff =
 846             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
 847                                         priv->tx_ring_size, GFP_KERNEL);
 848
 849         if (NULL == priv->tx_skbuff) {
 850                 if (netif_msg_ifup(priv))
 851                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
 852                                         dev->name);
 853                 err = -ENOMEM;
 854                 goto tx_skb_fail;
 855         }
 856
 857         for (i = 0; i < priv->tx_ring_size; i++)
 858                 priv->tx_skbuff[i] = NULL;
 859
 860         priv->rx_skbuff =
 861             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
 862                                         priv->rx_ring_size, GFP_KERNEL);
 863
 864         if (NULL == priv->rx_skbuff) {
 865                 if (netif_msg_ifup(priv))
 866                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
 867                                         dev->name);
 868                 err = -ENOMEM;
 869                 goto rx_skb_fail;
 870         }
 871
 872         for (i = 0; i < priv->rx_ring_size; i++)
 873                 priv->rx_skbuff[i] = NULL;
 874
 875         /* Initialize some variables in our dev structure */
 876         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
 877         priv->cur_rx = priv->rx_bd_base;
 878         priv->skb_curtx = priv->skb_dirtytx = 0;
 879         priv->skb_currx = 0;
 880
 881         /* Initialize Transmit Descriptor Ring */
 882         txbdp = priv->tx_bd_base;
 883         for (i = 0; i < priv->tx_ring_size; i++) {
 884                 txbdp->status = 0;
 885                 txbdp->length = 0;
 886                 txbdp->bufPtr = 0;
 887                 txbdp++;
 888         }
 889
 890         /* Set the last descriptor in the ring to indicate wrap */
 891         txbdp--;
 892         txbdp->status |= TXBD_WRAP;
 893
 894         rxbdp = priv->rx_bd_base;
 895         for (i = 0; i < priv->rx_ring_size; i++) {
 896                 struct sk_buff *skb;
 897
 898                 skb = gfar_new_skb(dev);
 899
 900                 if (!skb) {
 901                         printk(KERN_ERR "%s: Can't allocate RX buffers\n",
 902                                         dev->name);
 903
 904                         goto err_rxalloc_fail;
 905                 }
 906
 907                 priv->rx_skbuff[i] = skb;
 908
 909                 gfar_new_rxbdp(dev, rxbdp, skb);
 910
 911                 rxbdp++;
 912         }
 913
 914         /* Set the last descriptor in the ring to wrap */
 915         rxbdp--;
 916         rxbdp->status |= RXBD_WRAP;
 917
 918         /* If the device has multiple interrupts, register for
 919          * them.  Otherwise, only register for the one */
 920         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 921                 /* Install our interrupt handlers for Error,
 922                  * Transmit, and Receive */
 923                 if (request_irq(priv->interruptError, gfar_error,
 924                                 0, "enet_error", dev) < 0) {
 925                         if (netif_msg_intr(priv))
 926                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 927                                         dev->name, priv->interruptError);
 928
 929                         err = -1;
 930                         goto err_irq_fail;
 931                 }
 932
 933                 if (request_irq(priv->interruptTransmit, gfar_transmit,
 934                                 0, "enet_tx", dev) < 0) {
 935                         if (netif_msg_intr(priv))
 936                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 937                                         dev->name, priv->interruptTransmit);
 938
 939                         err = -1;
 940
 941                         goto tx_irq_fail;
 942                 }
 943
 944                 if (request_irq(priv->interruptReceive, gfar_receive,
 945                                 0, "enet_rx", dev) < 0) {
 946                         if (netif_msg_intr(priv))
 947                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
 948                                                 dev->name, priv->interruptReceive);
 949
 950                         err = -1;
 951                         goto rx_irq_fail;
 952                 }
 953         } else {
 954                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
 955                                 0, "gfar_interrupt", dev) < 0) {
 956                         if (netif_msg_intr(priv))
 957                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 958                                         dev->name, priv->interruptError);
 959
 960                         err = -1;
 961                         goto err_irq_fail;
 962                 }
 963         }
 964
 965         phy_start(priv->phydev);
 966
 967         /* Configure the coalescing support */
 968         if (priv->txcoalescing)
 969                 gfar_write(&regs->txic,
 970                            mk_ic_value(priv->txcount, priv->txtime));
 971         else
 972                 gfar_write(&regs->txic, 0);
 973
 974         if (priv->rxcoalescing)
 975                 gfar_write(&regs->rxic,
 976                            mk_ic_value(priv->rxcount, priv->rxtime));
 977         else
 978                 gfar_write(&regs->rxic, 0);
 979
 980         if (priv->rx_csum_enable)
 981                 rctrl |= RCTRL_CHECKSUMMING;
 982
 983         if (priv->extended_hash) {
 984                 rctrl |= RCTRL_EXTHASH;
 985
 986                 gfar_clear_exact_match(dev);
 987                 rctrl |= RCTRL_EMEN;
 988         }
 989
 990         if (priv->vlan_enable)
 991                 rctrl |= RCTRL_VLAN;
 992
 993         if (priv->padding) {
 994                 rctrl &= ~RCTRL_PAL_MASK;
 995                 rctrl |= RCTRL_PADDING(priv->padding);
 996         }
 997
 998         /* Init rctrl based on our settings */
 999         gfar_write(&priv->regs->rctrl, rctrl);
1000
1001         if (dev->features & NETIF_F_IP_CSUM)
1002                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1003
1004         /* Set the extraction length and index */
1005         attrs = ATTRELI_EL(priv->rx_stash_size) |
1006                 ATTRELI_EI(priv->rx_stash_index);
1007
1008         gfar_write(&priv->regs->attreli, attrs);
1009
1010         /* Start with defaults, and add stashing or locking
1011          * depending on the approprate variables */
1012         attrs = ATTR_INIT_SETTINGS;
1013
1014         if (priv->bd_stash_en)
1015                 attrs |= ATTR_BDSTASH;
1016
1017         if (priv->rx_stash_size != 0)
1018                 attrs |= ATTR_BUFSTASH;
1019
1020         gfar_write(&priv->regs->attr, attrs);
1021
1022         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1023         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1024         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1025
1026         /* Start the controller */
1027         gfar_start(dev);
1028
1029         return 0;
1030
1031 rx_irq_fail:
1032         free_irq(priv->interruptTransmit, dev);
1033 tx_irq_fail:
1034         free_irq(priv->interruptError, dev);
1035 err_irq_fail:
1036 err_rxalloc_fail:
1037 rx_skb_fail:
1038         free_skb_resources(priv);
1039 tx_skb_fail:
1040         dma_free_coherent(&dev->dev,
1041                         sizeof(struct txbd8)*priv->tx_ring_size
1042                         + sizeof(struct rxbd8)*priv->rx_ring_size,
1043                         priv->tx_bd_base,
1044                         gfar_read(&regs->tbase0));
1045
1046         return err;
1047 }
1048
1049 /* Called when something needs to use the ethernet device */
1050 /* Returns 0 for success. */
1051 static int gfar_enet_open(struct net_device *dev)
1052 {
1053         struct gfar_private *priv = netdev_priv(dev);
1054         int err;
1055
1056         napi_enable(&priv->napi);
1057
1058         /* Initialize a bunch of registers */
1059         init_registers(dev);
1060
1061         gfar_set_mac_address(dev);
1062
1063         err = init_phy(dev);
1064
1065         if(err) {
1066                 napi_disable(&priv->napi);
1067                 return err;
1068         }
1069
1070         err = startup_gfar(dev);
1071         if (err) {
1072                 napi_disable(&priv->napi);
1073                 return err;
1074         }
1075
1076         netif_start_queue(dev);
1077
1078         return err;
1079 }
1080
1081 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
1082 {
1083         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
1084
1085         memset(fcb, 0, GMAC_FCB_LEN);
1086
1087         return fcb;
1088 }
1089
1090 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1091 {
1092         u8 flags = 0;
1093
1094         /* If we're here, it's a IP packet with a TCP or UDP
1095          * payload.  We set it to checksum, using a pseudo-header
1096          * we provide
1097          */
1098         flags = TXFCB_DEFAULT;
1099
1100         /* Tell the controller what the protocol is */
1101         /* And provide the already calculated phcs */
1102         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1103                 flags |= TXFCB_UDP;
1104                 fcb->phcs = udp_hdr(skb)->check;
1105         } else
1106                 fcb->phcs = tcp_hdr(skb)->check;
1107
1108         /* l3os is the distance between the start of the
1109          * frame (skb->data) and the start of the IP hdr.
1110          * l4os is the distance between the start of the
1111          * l3 hdr and the l4 hdr */
1112         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1113         fcb->l4os = skb_network_header_len(skb);
1114
1115         fcb->flags = flags;
1116 }
1117
1118 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1119 {
1120         fcb->flags |= TXFCB_VLN;
1121         fcb->vlctl = vlan_tx_tag_get(skb);
1122 }
1123
1124 /* This is called by the kernel when a frame is ready for transmission. */
1125 /* It is pointed to by the dev->hard_start_xmit function pointer */
1126 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1127 {
1128         struct gfar_private *priv = netdev_priv(dev);
1129         struct txfcb *fcb = NULL;
1130         struct txbd8 *txbdp;
1131         u16 status;
1132         unsigned long flags;
1133
1134         /* Update transmit stats */
1135         dev->stats.tx_bytes += skb->len;
1136
1137         /* Lock priv now */
1138         spin_lock_irqsave(&priv->txlock, flags);
1139
1140         /* Point at the first free tx descriptor */
1141         txbdp = priv->cur_tx;
1142
1143         /* Clear all but the WRAP status flags */
1144         status = txbdp->status & TXBD_WRAP;
1145
1146         /* Set up checksumming */
1147         if (likely((dev->features & NETIF_F_IP_CSUM)
1148                         && (CHECKSUM_PARTIAL == skb->ip_summed))) {
1149                 fcb = gfar_add_fcb(skb, txbdp);
1150                 status |= TXBD_TOE;
1151                 gfar_tx_checksum(skb, fcb);
1152         }
1153
1154         if (priv->vlan_enable &&
1155                         unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
1156                 if (unlikely(NULL == fcb)) {
1157                         fcb = gfar_add_fcb(skb, txbdp);
1158                         status |= TXBD_TOE;
1159                 }
1160
1161                 gfar_tx_vlan(skb, fcb);
1162         }
1163
1164         /* Set buffer length and pointer */
1165         txbdp->length = skb->len;
1166         txbdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1167                         skb->len, DMA_TO_DEVICE);
1168
1169         /* Save the skb pointer so we can free it later */
1170         priv->tx_skbuff[priv->skb_curtx] = skb;
1171
1172         /* Update the current skb pointer (wrapping if this was the last) */
1173         priv->skb_curtx =
1174             (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1175
1176         /* Flag the BD as interrupt-causing */
1177         status |= TXBD_INTERRUPT;
1178
1179         /* Flag the BD as ready to go, last in frame, and  */
1180         /* in need of CRC */
1181         status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
1182
1183         dev->trans_start = jiffies;
1184
1185         /* The powerpc-specific eieio() is used, as wmb() has too strong
1186          * semantics (it requires synchronization between cacheable and
1187          * uncacheable mappings, which eieio doesn't provide and which we
1188          * don't need), thus requiring a more expensive sync instruction.  At
1189          * some point, the set of architecture-independent barrier functions
1190          * should be expanded to include weaker barriers.
1191          */
1192
1193         eieio();
1194         txbdp->status = status;
1195
1196         /* If this was the last BD in the ring, the next one */
1197         /* is at the beginning of the ring */
1198         if (txbdp->status & TXBD_WRAP)
1199                 txbdp = priv->tx_bd_base;
1200         else
1201                 txbdp++;
1202
1203         /* If the next BD still needs to be cleaned up, then the bds
1204            are full.  We need to tell the kernel to stop sending us stuff. */
1205         if (txbdp == priv->dirty_tx) {
1206                 netif_stop_queue(dev);
1207
1208                 dev->stats.tx_fifo_errors++;
1209         }
1210
1211         /* Update the current txbd to the next one */
1212         priv->cur_tx = txbdp;
1213
1214         /* Tell the DMA to go go go */
1215         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1216
1217         /* Unlock priv */
1218         spin_unlock_irqrestore(&priv->txlock, flags);
1219
1220         return 0;
1221 }
1222
1223 /* Stops the kernel queue, and halts the controller */
1224 static int gfar_close(struct net_device *dev)
1225 {
1226         struct gfar_private *priv = netdev_priv(dev);
1227
1228         napi_disable(&priv->napi);
1229
1230         cancel_work_sync(&priv->reset_task);
1231         stop_gfar(dev);
1232
1233         /* Disconnect from the PHY */
1234         phy_disconnect(priv->phydev);
1235         priv->phydev = NULL;
1236
1237         netif_stop_queue(dev);
1238
1239         return 0;
1240 }
1241
1242 /* Changes the mac address if the controller is not running. */
1243 static int gfar_set_mac_address(struct net_device *dev)
1244 {
1245         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1246
1247         return 0;
1248 }
1249
1250
1251 /* Enables and disables VLAN insertion/extraction */
1252 static void gfar_vlan_rx_register(struct net_device *dev,
1253                 struct vlan_group *grp)
1254 {
1255         struct gfar_private *priv = netdev_priv(dev);
1256         unsigned long flags;
1257         u32 tempval;
1258
1259         spin_lock_irqsave(&priv->rxlock, flags);
1260
1261         priv->vlgrp = grp;
1262
1263         if (grp) {
1264                 /* Enable VLAN tag insertion */
1265                 tempval = gfar_read(&priv->regs->tctrl);
1266                 tempval |= TCTRL_VLINS;
1267
1268                 gfar_write(&priv->regs->tctrl, tempval);
1269
1270                 /* Enable VLAN tag extraction */
1271                 tempval = gfar_read(&priv->regs->rctrl);
1272                 tempval |= RCTRL_VLEX;
1273                 gfar_write(&priv->regs->rctrl, tempval);
1274         } else {
1275                 /* Disable VLAN tag insertion */
1276                 tempval = gfar_read(&priv->regs->tctrl);
1277                 tempval &= ~TCTRL_VLINS;
1278                 gfar_write(&priv->regs->tctrl, tempval);
1279
1280                 /* Disable VLAN tag extraction */
1281                 tempval = gfar_read(&priv->regs->rctrl);
1282                 tempval &= ~RCTRL_VLEX;
1283                 gfar_write(&priv->regs->rctrl, tempval);
1284         }
1285
1286         spin_unlock_irqrestore(&priv->rxlock, flags);
1287 }
1288
1289 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1290 {
1291         int tempsize, tempval;
1292         struct gfar_private *priv = netdev_priv(dev);
1293         int oldsize = priv->rx_buffer_size;
1294         int frame_size = new_mtu + ETH_HLEN;
1295
1296         if (priv->vlan_enable)
1297                 frame_size += VLAN_HLEN;
1298
1299         if (gfar_uses_fcb(priv))
1300                 frame_size += GMAC_FCB_LEN;
1301
1302         frame_size += priv->padding;
1303
1304         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1305                 if (netif_msg_drv(priv))
1306                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1307                                         dev->name);
1308                 return -EINVAL;
1309         }
1310
1311         tempsize =
1312             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1313             INCREMENTAL_BUFFER_SIZE;
1314
1315         /* Only stop and start the controller if it isn't already
1316          * stopped, and we changed something */
1317         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1318                 stop_gfar(dev);
1319
1320         priv->rx_buffer_size = tempsize;
1321
1322         dev->mtu = new_mtu;
1323
1324         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1325         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1326
1327         /* If the mtu is larger than the max size for standard
1328          * ethernet frames (ie, a jumbo frame), then set maccfg2
1329          * to allow huge frames, and to check the length */
1330         tempval = gfar_read(&priv->regs->maccfg2);
1331
1332         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1333                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1334         else
1335                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1336
1337         gfar_write(&priv->regs->maccfg2, tempval);
1338
1339         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1340                 startup_gfar(dev);
1341
1342         return 0;
1343 }
1344
1345 /* gfar_reset_task gets scheduled when a packet has not been
1346  * transmitted after a set amount of time.
1347  * For now, assume that clearing out all the structures, and
1348  * starting over will fix the problem.
1349  */
1350 static void gfar_reset_task(struct work_struct *work)
1351 {
1352         struct gfar_private *priv = container_of(work, struct gfar_private,
1353                         reset_task);
1354         struct net_device *dev = priv->dev;
1355
1356         if (dev->flags & IFF_UP) {
1357                 stop_gfar(dev);
1358                 startup_gfar(dev);
1359         }
1360
1361         netif_tx_schedule_all(dev);
1362 }
1363
1364 static void gfar_timeout(struct net_device *dev)
1365 {
1366         struct gfar_private *priv = netdev_priv(dev);
1367
1368         dev->stats.tx_errors++;
1369         schedule_work(&priv->reset_task);
1370 }
1371
1372 /* Interrupt Handler for Transmit complete */
1373 static int gfar_clean_tx_ring(struct net_device *dev)
1374 {
1375         struct txbd8 *bdp;
1376         struct gfar_private *priv = netdev_priv(dev);
1377         int howmany = 0;
1378
1379         bdp = priv->dirty_tx;
1380         while ((bdp->status & TXBD_READY) == 0) {
1381                 /* If dirty_tx and cur_tx are the same, then either the */
1382                 /* ring is empty or full now (it could only be full in the beginning, */
1383                 /* obviously).  If it is empty, we are done. */
1384                 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1385                         break;
1386
1387                 howmany++;
1388
1389                 /* Deferred means some collisions occurred during transmit, */
1390                 /* but we eventually sent the packet. */
1391                 if (bdp->status & TXBD_DEF)
1392                         dev->stats.collisions++;
1393
1394                 /* Free the sk buffer associated with this TxBD */
1395                 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1396
1397                 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1398                 priv->skb_dirtytx =
1399                     (priv->skb_dirtytx +
1400                      1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1401
1402                 /* Clean BD length for empty detection */
1403                 bdp->length = 0;
1404
1405                 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1406                 if (bdp->status & TXBD_WRAP)
1407                         bdp = priv->tx_bd_base;
1408                 else
1409                         bdp++;
1410
1411                 /* Move dirty_tx to be the next bd */
1412                 priv->dirty_tx = bdp;
1413
1414                 /* We freed a buffer, so now we can restart transmission */
1415                 if (netif_queue_stopped(dev))
1416                         netif_wake_queue(dev);
1417         } /* while ((bdp->status & TXBD_READY) == 0) */
1418
1419         dev->stats.tx_packets += howmany;
1420
1421         return howmany;
1422 }
1423
1424 /* Interrupt Handler for Transmit complete */
1425 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1426 {
1427         struct net_device *dev = (struct net_device *) dev_id;
1428         struct gfar_private *priv = netdev_priv(dev);
1429
1430         /* Clear IEVENT */
1431         gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1432
1433         /* Lock priv */
1434         spin_lock(&priv->txlock);
1435
1436         gfar_clean_tx_ring(dev);
1437
1438         /* If we are coalescing the interrupts, reset the timer */
1439         /* Otherwise, clear it */
1440         if (likely(priv->txcoalescing)) {
1441                 gfar_write(&priv->regs->txic, 0);
1442                 gfar_write(&priv->regs->txic,
1443                            mk_ic_value(priv->txcount, priv->txtime));
1444         }
1445
1446         spin_unlock(&priv->txlock);
1447
1448         return IRQ_HANDLED;
1449 }
1450
1451 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1452                 struct sk_buff *skb)
1453 {
1454         struct gfar_private *priv = netdev_priv(dev);
1455         u32 * status_len = (u32 *)bdp;
1456         u16 flags;
1457
1458         bdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1459                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1460
1461         flags = RXBD_EMPTY | RXBD_INTERRUPT;
1462
1463         if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1464                 flags |= RXBD_WRAP;
1465
1466         eieio();
1467
1468         *status_len = (u32)flags << 16;
1469 }
1470
1471
1472 struct sk_buff * gfar_new_skb(struct net_device *dev)
1473 {
1474         unsigned int alignamount;
1475         struct gfar_private *priv = netdev_priv(dev);
1476         struct sk_buff *skb = NULL;
1477
1478         /* We have to allocate the skb, so keep trying till we succeed */
1479         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
1480
1481         if (!skb)
1482                 return NULL;
1483
1484         alignamount = RXBUF_ALIGNMENT -
1485                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1486
1487         /* We need the data buffer to be aligned properly.  We will reserve
1488          * as many bytes as needed to align the data properly
1489          */
1490         skb_reserve(skb, alignamount);
1491
1492         return skb;
1493 }
1494
1495 static inline void count_errors(unsigned short status, struct net_device *dev)
1496 {
1497         struct gfar_private *priv = netdev_priv(dev);
1498         struct net_device_stats *stats = &dev->stats;
1499         struct gfar_extra_stats *estats = &priv->extra_stats;
1500
1501         /* If the packet was truncated, none of the other errors
1502          * matter */
1503         if (status & RXBD_TRUNCATED) {
1504                 stats->rx_length_errors++;
1505
1506                 estats->rx_trunc++;
1507
1508                 return;
1509         }
1510         /* Count the errors, if there were any */
1511         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1512                 stats->rx_length_errors++;
1513
1514                 if (status & RXBD_LARGE)
1515                         estats->rx_large++;
1516                 else
1517                         estats->rx_short++;
1518         }
1519         if (status & RXBD_NONOCTET) {
1520                 stats->rx_frame_errors++;
1521                 estats->rx_nonoctet++;
1522         }
1523         if (status & RXBD_CRCERR) {
1524                 estats->rx_crcerr++;
1525                 stats->rx_crc_errors++;
1526         }
1527         if (status & RXBD_OVERRUN) {
1528                 estats->rx_overrun++;
1529                 stats->rx_crc_errors++;
1530         }
1531 }
1532
1533 irqreturn_t gfar_receive(int irq, void *dev_id)
1534 {
1535         struct net_device *dev = (struct net_device *) dev_id;
1536         struct gfar_private *priv = netdev_priv(dev);
1537         u32 tempval;
1538
1539         /* support NAPI */
1540         /* Clear IEVENT, so interrupts aren't called again
1541          * because of the packets that have already arrived */
1542         gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1543
1544         if (netif_rx_schedule_prep(dev, &priv->napi)) {
1545                 tempval = gfar_read(&priv->regs->imask);
1546                 tempval &= IMASK_RTX_DISABLED;
1547                 gfar_write(&priv->regs->imask, tempval);
1548
1549                 __netif_rx_schedule(dev, &priv->napi);
1550         } else {
1551                 if (netif_msg_rx_err(priv))
1552                         printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1553                                 dev->name, gfar_read(&priv->regs->ievent),
1554                                 gfar_read(&priv->regs->imask));
1555         }
1556
1557         return IRQ_HANDLED;
1558 }
1559
1560 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1561 {
1562         /* If valid headers were found, and valid sums
1563          * were verified, then we tell the kernel that no
1564          * checksumming is necessary.  Otherwise, it is */
1565         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1566                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1567         else
1568                 skb->ip_summed = CHECKSUM_NONE;
1569 }
1570
1571
1572 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1573 {
1574         struct rxfcb *fcb = (struct rxfcb *)skb->data;
1575
1576         /* Remove the FCB from the skb */
1577         skb_pull(skb, GMAC_FCB_LEN);
1578
1579         return fcb;
1580 }
1581
1582 /* gfar_process_frame() -- handle one incoming packet if skb
1583  * isn't NULL.  */
1584 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1585                 int length)
1586 {
1587         struct gfar_private *priv = netdev_priv(dev);
1588         struct rxfcb *fcb = NULL;
1589
1590         if (NULL == skb) {
1591                 if (netif_msg_rx_err(priv))
1592                         printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1593                 dev->stats.rx_dropped++;
1594                 priv->extra_stats.rx_skbmissing++;
1595         } else {
1596                 int ret;
1597
1598                 /* Prep the skb for the packet */
1599                 skb_put(skb, length);
1600
1601                 /* Grab the FCB if there is one */
1602                 if (gfar_uses_fcb(priv))
1603                         fcb = gfar_get_fcb(skb);
1604
1605                 /* Remove the padded bytes, if there are any */
1606                 if (priv->padding)
1607                         skb_pull(skb, priv->padding);
1608
1609                 if (priv->rx_csum_enable)
1610                         gfar_rx_checksum(skb, fcb);
1611
1612                 /* Tell the skb what kind of packet this is */
1613                 skb->protocol = eth_type_trans(skb, dev);
1614
1615                 /* Send the packet up the stack */
1616                 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) {
1617                         ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp,
1618                                                        fcb->vlctl);
1619                 } else
1620                         ret = netif_receive_skb(skb);
1621
1622                 if (NET_RX_DROP == ret)
1623                         priv->extra_stats.kernel_dropped++;
1624         }
1625
1626         return 0;
1627 }
1628
1629 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1630  *   until the budget/quota has been reached. Returns the number
1631  *   of frames handled
1632  */
1633 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1634 {
1635         struct rxbd8 *bdp;
1636         struct sk_buff *skb;
1637         u16 pkt_len;
1638         int howmany = 0;
1639         struct gfar_private *priv = netdev_priv(dev);
1640
1641         /* Get the first full descriptor */
1642         bdp = priv->cur_rx;
1643
1644         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1645                 struct sk_buff *newskb;
1646                 rmb();
1647
1648                 /* Add another skb for the future */
1649                 newskb = gfar_new_skb(dev);
1650
1651                 skb = priv->rx_skbuff[priv->skb_currx];
1652
1653                 /* We drop the frame if we failed to allocate a new buffer */
1654                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1655                                  bdp->status & RXBD_ERR)) {
1656                         count_errors(bdp->status, dev);
1657
1658                         if (unlikely(!newskb))
1659                                 newskb = skb;
1660
1661                         if (skb) {
1662                                 dma_unmap_single(&priv->dev->dev,
1663                                                 bdp->bufPtr,
1664                                                 priv->rx_buffer_size,
1665                                                 DMA_FROM_DEVICE);
1666
1667                                 dev_kfree_skb_any(skb);
1668                         }
1669                 } else {
1670                         /* Increment the number of packets */
1671                         dev->stats.rx_packets++;
1672                         howmany++;
1673
1674                         /* Remove the FCS from the packet length */
1675                         pkt_len = bdp->length - 4;
1676
1677                         gfar_process_frame(dev, skb, pkt_len);
1678
1679                         dev->stats.rx_bytes += pkt_len;
1680                 }
1681
1682                 dev->last_rx = jiffies;
1683
1684                 priv->rx_skbuff[priv->skb_currx] = newskb;
1685
1686                 /* Setup the new bdp */
1687                 gfar_new_rxbdp(dev, bdp, newskb);
1688
1689                 /* Update to the next pointer */
1690                 if (bdp->status & RXBD_WRAP)
1691                         bdp = priv->rx_bd_base;
1692                 else
1693                         bdp++;
1694
1695                 /* update to point at the next skb */
1696                 priv->skb_currx =
1697                     (priv->skb_currx + 1) &
1698                     RX_RING_MOD_MASK(priv->rx_ring_size);
1699         }
1700
1701         /* Update the current rxbd pointer to be the next one */
1702         priv->cur_rx = bdp;
1703
1704         return howmany;
1705 }
1706
1707 static int gfar_poll(struct napi_struct *napi, int budget)
1708 {
1709         struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1710         struct net_device *dev = priv->dev;
1711         int howmany;
1712         unsigned long flags;
1713
1714         /* If we fail to get the lock, don't bother with the TX BDs */
1715         if (spin_trylock_irqsave(&priv->txlock, flags)) {
1716                 gfar_clean_tx_ring(dev);
1717                 spin_unlock_irqrestore(&priv->txlock, flags);
1718         }
1719
1720         howmany = gfar_clean_rx_ring(dev, budget);
1721
1722         if (howmany < budget) {
1723                 netif_rx_complete(dev, napi);
1724
1725                 /* Clear the halt bit in RSTAT */
1726                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1727
1728                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1729
1730                 /* If we are coalescing interrupts, update the timer */
1731                 /* Otherwise, clear it */
1732                 if (likely(priv->rxcoalescing)) {
1733                         gfar_write(&priv->regs->rxic, 0);
1734                         gfar_write(&priv->regs->rxic,
1735                                    mk_ic_value(priv->rxcount, priv->rxtime));
1736                 }
1737         }
1738
1739         return howmany;
1740 }
1741
1742 #ifdef CONFIG_NET_POLL_CONTROLLER
1743 /*
1744  * Polling 'interrupt' - used by things like netconsole to send skbs
1745  * without having to re-enable interrupts. It's not called while
1746  * the interrupt routine is executing.
1747  */
1748 static void gfar_netpoll(struct net_device *dev)
1749 {
1750         struct gfar_private *priv = netdev_priv(dev);
1751
1752         /* If the device has multiple interrupts, run tx/rx */
1753         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1754                 disable_irq(priv->interruptTransmit);
1755                 disable_irq(priv->interruptReceive);
1756                 disable_irq(priv->interruptError);
1757                 gfar_interrupt(priv->interruptTransmit, dev);
1758                 enable_irq(priv->interruptError);
1759                 enable_irq(priv->interruptReceive);
1760                 enable_irq(priv->interruptTransmit);
1761         } else {
1762                 disable_irq(priv->interruptTransmit);
1763                 gfar_interrupt(priv->interruptTransmit, dev);
1764                 enable_irq(priv->interruptTransmit);
1765         }
1766 }
1767 #endif
1768
1769 /* The interrupt handler for devices with one interrupt */
1770 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1771 {
1772         struct net_device *dev = dev_id;
1773         struct gfar_private *priv = netdev_priv(dev);
1774
1775         /* Save ievent for future reference */
1776         u32 events = gfar_read(&priv->regs->ievent);
1777
1778         /* Check for reception */
1779         if (events & IEVENT_RX_MASK)
1780                 gfar_receive(irq, dev_id);
1781
1782         /* Check for transmit completion */
1783         if (events & IEVENT_TX_MASK)
1784                 gfar_transmit(irq, dev_id);
1785
1786         /* Check for errors */
1787         if (events & IEVENT_ERR_MASK)
1788                 gfar_error(irq, dev_id);
1789
1790         return IRQ_HANDLED;
1791 }
1792
1793 /* Called every time the controller might need to be made
1794  * aware of new link state.  The PHY code conveys this
1795  * information through variables in the phydev structure, and this
1796  * function converts those variables into the appropriate
1797  * register values, and can bring down the device if needed.
1798  */
1799 static void adjust_link(struct net_device *dev)
1800 {
1801         struct gfar_private *priv = netdev_priv(dev);
1802         struct gfar __iomem *regs = priv->regs;
1803         unsigned long flags;
1804         struct phy_device *phydev = priv->phydev;
1805         int new_state = 0;
1806
1807         spin_lock_irqsave(&priv->txlock, flags);
1808         if (phydev->link) {
1809                 u32 tempval = gfar_read(&regs->maccfg2);
1810                 u32 ecntrl = gfar_read(&regs->ecntrl);
1811
1812                 /* Now we make sure that we can be in full duplex mode.
1813                  * If not, we operate in half-duplex mode. */
1814                 if (phydev->duplex != priv->oldduplex) {
1815                         new_state = 1;
1816                         if (!(phydev->duplex))
1817                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1818                         else
1819                                 tempval |= MACCFG2_FULL_DUPLEX;
1820
1821                         priv->oldduplex = phydev->duplex;
1822                 }
1823
1824                 if (phydev->speed != priv->oldspeed) {
1825                         new_state = 1;
1826                         switch (phydev->speed) {
1827                         case 1000:
1828                                 tempval =
1829                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1830                                 break;
1831                         case 100:
1832                         case 10:
1833                                 tempval =
1834                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1835
1836                                 /* Reduced mode distinguishes
1837                                  * between 10 and 100 */
1838                                 if (phydev->speed == SPEED_100)
1839                                         ecntrl |= ECNTRL_R100;
1840                                 else
1841                                         ecntrl &= ~(ECNTRL_R100);
1842                                 break;
1843                         default:
1844                                 if (netif_msg_link(priv))
1845                                         printk(KERN_WARNING
1846                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
1847                                                 dev->name, phydev->speed);
1848                                 break;
1849                         }
1850
1851                         priv->oldspeed = phydev->speed;
1852                 }
1853
1854                 gfar_write(&regs->maccfg2, tempval);
1855                 gfar_write(&regs->ecntrl, ecntrl);
1856
1857                 if (!priv->oldlink) {
1858                         new_state = 1;
1859                         priv->oldlink = 1;
1860                 }
1861         } else if (priv->oldlink) {
1862                 new_state = 1;
1863                 priv->oldlink = 0;
1864                 priv->oldspeed = 0;
1865                 priv->oldduplex = -1;
1866         }
1867
1868         if (new_state && netif_msg_link(priv))
1869                 phy_print_status(phydev);
1870
1871         spin_unlock_irqrestore(&priv->txlock, flags);
1872 }
1873
1874 /* Update the hash table based on the current list of multicast
1875  * addresses we subscribe to.  Also, change the promiscuity of
1876  * the device based on the flags (this function is called
1877  * whenever dev->flags is changed */
1878 static void gfar_set_multi(struct net_device *dev)
1879 {
1880         struct dev_mc_list *mc_ptr;
1881         struct gfar_private *priv = netdev_priv(dev);
1882         struct gfar __iomem *regs = priv->regs;
1883         u32 tempval;
1884
1885         if(dev->flags & IFF_PROMISC) {
1886                 /* Set RCTRL to PROM */
1887                 tempval = gfar_read(&regs->rctrl);
1888                 tempval |= RCTRL_PROM;
1889                 gfar_write(&regs->rctrl, tempval);
1890         } else {
1891                 /* Set RCTRL to not PROM */
1892                 tempval = gfar_read(&regs->rctrl);
1893                 tempval &= ~(RCTRL_PROM);
1894                 gfar_write(&regs->rctrl, tempval);
1895         }
1896
1897         if(dev->flags & IFF_ALLMULTI) {
1898                 /* Set the hash to rx all multicast frames */
1899                 gfar_write(&regs->igaddr0, 0xffffffff);
1900                 gfar_write(&regs->igaddr1, 0xffffffff);
1901                 gfar_write(&regs->igaddr2, 0xffffffff);
1902                 gfar_write(&regs->igaddr3, 0xffffffff);
1903                 gfar_write(&regs->igaddr4, 0xffffffff);
1904                 gfar_write(&regs->igaddr5, 0xffffffff);
1905                 gfar_write(&regs->igaddr6, 0xffffffff);
1906                 gfar_write(&regs->igaddr7, 0xffffffff);
1907                 gfar_write(&regs->gaddr0, 0xffffffff);
1908                 gfar_write(&regs->gaddr1, 0xffffffff);
1909                 gfar_write(&regs->gaddr2, 0xffffffff);
1910                 gfar_write(&regs->gaddr3, 0xffffffff);
1911                 gfar_write(&regs->gaddr4, 0xffffffff);
1912                 gfar_write(&regs->gaddr5, 0xffffffff);
1913                 gfar_write(&regs->gaddr6, 0xffffffff);
1914                 gfar_write(&regs->gaddr7, 0xffffffff);
1915         } else {
1916                 int em_num;
1917                 int idx;
1918
1919                 /* zero out the hash */
1920                 gfar_write(&regs->igaddr0, 0x0);
1921                 gfar_write(&regs->igaddr1, 0x0);
1922                 gfar_write(&regs->igaddr2, 0x0);
1923                 gfar_write(&regs->igaddr3, 0x0);
1924                 gfar_write(&regs->igaddr4, 0x0);
1925                 gfar_write(&regs->igaddr5, 0x0);
1926                 gfar_write(&regs->igaddr6, 0x0);
1927                 gfar_write(&regs->igaddr7, 0x0);
1928                 gfar_write(&regs->gaddr0, 0x0);
1929                 gfar_write(&regs->gaddr1, 0x0);
1930                 gfar_write(&regs->gaddr2, 0x0);
1931                 gfar_write(&regs->gaddr3, 0x0);
1932                 gfar_write(&regs->gaddr4, 0x0);
1933                 gfar_write(&regs->gaddr5, 0x0);
1934                 gfar_write(&regs->gaddr6, 0x0);
1935                 gfar_write(&regs->gaddr7, 0x0);
1936
1937                 /* If we have extended hash tables, we need to
1938                  * clear the exact match registers to prepare for
1939                  * setting them */
1940                 if (priv->extended_hash) {
1941                         em_num = GFAR_EM_NUM + 1;
1942                         gfar_clear_exact_match(dev);
1943                         idx = 1;
1944                 } else {
1945                         idx = 0;
1946                         em_num = 0;
1947                 }
1948
1949                 if(dev->mc_count == 0)
1950                         return;
1951
1952                 /* Parse the list, and set the appropriate bits */
1953                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1954                         if (idx < em_num) {
1955                                 gfar_set_mac_for_addr(dev, idx,
1956                                                 mc_ptr->dmi_addr);
1957                                 idx++;
1958                         } else
1959                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1960                 }
1961         }
1962
1963         return;
1964 }
1965
1966
1967 /* Clears each of the exact match registers to zero, so they
1968  * don't interfere with normal reception */
1969 static void gfar_clear_exact_match(struct net_device *dev)
1970 {
1971         int idx;
1972         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
1973
1974         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
1975                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
1976 }
1977
1978 /* Set the appropriate hash bit for the given addr */
1979 /* The algorithm works like so:
1980  * 1) Take the Destination Address (ie the multicast address), and
1981  * do a CRC on it (little endian), and reverse the bits of the
1982  * result.
1983  * 2) Use the 8 most significant bits as a hash into a 256-entry
1984  * table.  The table is controlled through 8 32-bit registers:
1985  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
1986  * gaddr7.  This means that the 3 most significant bits in the
1987  * hash index which gaddr register to use, and the 5 other bits
1988  * indicate which bit (assuming an IBM numbering scheme, which
1989  * for PowerPC (tm) is usually the case) in the register holds
1990  * the entry. */
1991 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
1992 {
1993         u32 tempval;
1994         struct gfar_private *priv = netdev_priv(dev);
1995         u32 result = ether_crc(MAC_ADDR_LEN, addr);
1996         int width = priv->hash_width;
1997         u8 whichbit = (result >> (32 - width)) & 0x1f;
1998         u8 whichreg = result >> (32 - width + 5);
1999         u32 value = (1 << (31-whichbit));
2000
2001         tempval = gfar_read(priv->hash_regs[whichreg]);
2002         tempval |= value;
2003         gfar_write(priv->hash_regs[whichreg], tempval);
2004
2005         return;
2006 }
2007
2008
2009 /* There are multiple MAC Address register pairs on some controllers
2010  * This function sets the numth pair to a given address
2011  */
2012 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2013 {
2014         struct gfar_private *priv = netdev_priv(dev);
2015         int idx;
2016         char tmpbuf[MAC_ADDR_LEN];
2017         u32 tempval;
2018         u32 __iomem *macptr = &priv->regs->macstnaddr1;
2019
2020         macptr += num*2;
2021
2022         /* Now copy it into the mac registers backwards, cuz */
2023         /* little endian is silly */
2024         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2025                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2026
2027         gfar_write(macptr, *((u32 *) (tmpbuf)));
2028
2029         tempval = *((u32 *) (tmpbuf + 4));
2030
2031         gfar_write(macptr+1, tempval);
2032 }
2033
2034 /* GFAR error interrupt handler */
2035 static irqreturn_t gfar_error(int irq, void *dev_id)
2036 {
2037         struct net_device *dev = dev_id;
2038         struct gfar_private *priv = netdev_priv(dev);
2039
2040         /* Save ievent for future reference */
2041         u32 events = gfar_read(&priv->regs->ievent);
2042
2043         /* Clear IEVENT */
2044         gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2045
2046         /* Magic Packet is not an error. */
2047         if ((priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2048             (events & IEVENT_MAG))
2049                 events &= ~IEVENT_MAG;
2050
2051         /* Hmm... */
2052         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2053                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2054                        dev->name, events, gfar_read(&priv->regs->imask));
2055
2056         /* Update the error counters */
2057         if (events & IEVENT_TXE) {
2058                 dev->stats.tx_errors++;
2059
2060                 if (events & IEVENT_LC)
2061                         dev->stats.tx_window_errors++;
2062                 if (events & IEVENT_CRL)
2063                         dev->stats.tx_aborted_errors++;
2064                 if (events & IEVENT_XFUN) {
2065                         if (netif_msg_tx_err(priv))
2066                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2067                                        "packet dropped.\n", dev->name);
2068                         dev->stats.tx_dropped++;
2069                         priv->extra_stats.tx_underrun++;
2070
2071                         /* Reactivate the Tx Queues */
2072                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2073                 }
2074                 if (netif_msg_tx_err(priv))
2075                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2076         }
2077         if (events & IEVENT_BSY) {
2078                 dev->stats.rx_errors++;
2079                 priv->extra_stats.rx_bsy++;
2080
2081                 gfar_receive(irq, dev_id);
2082
2083                 if (netif_msg_rx_err(priv))
2084                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2085                                dev->name, gfar_read(&priv->regs->rstat));
2086         }
2087         if (events & IEVENT_BABR) {
2088                 dev->stats.rx_errors++;
2089                 priv->extra_stats.rx_babr++;
2090
2091                 if (netif_msg_rx_err(priv))
2092                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2093         }
2094         if (events & IEVENT_EBERR) {
2095                 priv->extra_stats.eberr++;
2096                 if (netif_msg_rx_err(priv))
2097                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
2098         }
2099         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2100                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2101
2102         if (events & IEVENT_BABT) {
2103                 priv->extra_stats.tx_babt++;
2104                 if (netif_msg_tx_err(priv))
2105                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2106         }
2107         return IRQ_HANDLED;
2108 }
2109
2110 /* work with hotplug and coldplug */
2111 MODULE_ALIAS("platform:fsl-gianfar");
2112
2113 /* Structure for a device driver */
2114 static struct platform_driver gfar_driver = {
2115         .probe = gfar_probe,
2116         .remove = gfar_remove,
2117         .suspend = gfar_suspend,
2118         .resume = gfar_resume,
2119         .driver = {
2120                 .name = "fsl-gianfar",
2121                 .owner = THIS_MODULE,
2122         },
2123 };
2124
2125 static int __init gfar_init(void)
2126 {
2127         int err = gfar_mdio_init();
2128
2129         if (err)
2130                 return err;
2131
2132         err = platform_driver_register(&gfar_driver);
2133
2134         if (err)
2135                 gfar_mdio_exit();
2136
2137         return err;
2138 }
2139
2140 static void __exit gfar_exit(void)
2141 {
2142         platform_driver_unregister(&gfar_driver);
2143         gfar_mdio_exit();
2144 }
2145
2146 module_init(gfar_init);
2147 module_exit(gfar_exit);
2148